ETOX NOR flash memory device and preparation method thereof

Abstract

The present application provides an ETOX NOR flash memory device and a preparation method thereof. In the preparation method, a cap layer is formed on a control gate material layer, and then a first deep trench and a second deep trench are formed. A sacrificial oxide layer is filled in the first deep trench and the second deep trench, and the sacrificial oxide layer is planarized. Then, the sacrificial oxide layer in the first deep trench is etched and an ion implantation process is performed to form a source line ion implantation region. Then, a source line material layer is filled in the first deep trench. The present application uses a sacrificial oxide layer to fill the first deep trench, thereby avoiding the situation in which residual photoresist on the sidewall of the deep trench in a traditional SAS process subsequently adversely affects device performance, thereby improving device performance and facilitating further miniaturization and integration of storage units.

Description

Technical Field

[0001] The present application relates to the field of semiconductor manufacturing technology, and in particular to an ETOX NOR flash memory device and a preparation method thereof. Background Art

[0002] The source line area of ​​the current mainstream ETOX NOR flash memory device (flash) architecture adopts a SAS (Self-Aligned Source) structure. By etching the shallow trench isolation structure (STI) in the substrate between the control gates and performing ion implantation, a source line ion implantation region is formed in the substrate, and a source line polysilicon material layer is formed on the substrate surface next to the source line ion implantation region. The doped ions in the source line ion implantation region are conductive, connecting the source line ion implantation region and the source line polysilicon material layer in series, thereby forming a serpentine source line in the substrate and on the substrate surface.

[0003] As the size of storage cells continues to shrink, SAS structure-related processes are the main obstacle to further shrinking the size of storage cells. The main reasons are:

[0004] (1) In the lithography process of the SAS structure, deep trenches for preparing source lines, word lines, etc. are formed in the stacked floating gate, ONO dielectric layer and control gate. Before ion implantation is performed on the bottom of the source line deep trench, the wafer surface needs to be fully coated with a layer of photoresist. Therefore, all deep trenches are filled with photoresist. Then, the deep trench where the source line is located is opened through exposure, development and other processes to perform source line ion implantation on the substrate at the bottom of the deep trench. However, since the deep trench line width of the source line is small and the stacked floating gate, ONO dielectric layer and control gate of the storage unit are high, after the photoresist is filled into the deep trench, the SAS lithography process window is small, which is not conducive to the development of the photoresist and is prone to produce photoresist residues in the deep trench, thereby generating impurity residual defects that affect the electrical performance of the device;

[0005] (2) The etching process of the SAS structure will mistakenly etch the top corners of the control gate on both sides of the deep trench of the source line, making the top corners of the control gate rounded, which is not conducive to further thinning of the control gate;

[0006] (3) In the ion implantation process of the SAS structure, by etching the shallow trench isolation (STI) structure in the substrate between the control gates and implanting ions into the substrate, the lateral diffusion of the doped ions in the source line ion implantation region (source end) is twice that of the doped ions in the bit line ion implantation region (drain end), which shortens the effective channel of the memory cell and affects the electrical performance of the device. Summary of the Invention

[0007] The present application provides an ETOX NOR flash memory device and a preparation method thereof, which can solve at least one of the following problems: the mainstream source line SAS technology used in ETOX NOR flash memory devices causes residual photoresist in the deep trench of the source line, thereby affecting the electrical performance of the device; the etching step in the SAS technology easily mistakenly etches the top corners of the control gate on both sides of the deep trench of the source line; and the dopant ions in the source line ion implantation region severely diffuse laterally in the substrate, thereby shortening the effective channel of the storage unit.

[0008] On the one hand, an embodiment of the present application provides a method for preparing an ETOX NOR flash memory device, comprising:

[0009] A substrate is provided, the substrate comprising a storage area and a peripheral logic area, wherein a gate oxide layer, a floating gate material layer, an ONO dielectric layer, and a control gate material layer are formed on the substrate of the storage area, and a pad oxide layer and a control gate material layer are formed on the substrate of the peripheral logic area;

[0010] thinning the control gate material layer of the storage area to a certain thickness;

[0011] forming a capping layer, wherein the capping layer covers the control gate material layer of the storage region;

[0012] Etching the remaining thickness of the control gate material layer, the ONO dielectric layer, the floating gate material layer, and the gate oxide layer of the storage area to form a plurality of first deep trenches and a plurality of second deep trenches, wherein the first deep trenches and the second deep trenches are arranged in a staggered manner;

[0013] forming an anti-reflection layer, wherein the anti-reflection layer fills the first deep trench and covers the control gate material layer of the peripheral logic region;

[0014] Etching the control gate material layer and the pad oxide layer of the peripheral logic region to form a plurality of third deep trenches;

[0015] forming a first spacer material layer and a second spacer material layer, wherein the first spacer material layer covers the sidewalls and bottom walls of the first deep trench, the second deep trench, and the third deep trench, and the second spacer material layer covers the first spacer material layer;

[0016] forming a sacrificial oxide layer, wherein the sacrificial oxide layer covers the second spacer material layer and fills the first deep trench, the second deep trench, and the third deep trench;

[0017] planarizing the sacrificial oxide layer to the surface of the second spacer material layer;

[0018] Coating a photoresist layer on the flat surfaces of the sacrificial oxide layer and the second sidewall material layer;

[0019] By photolithography and etching processes, the sacrificial oxide layer in the first deep trench of the storage area and the second spacer material layer and the first spacer material layer on the bottom wall of the first deep trench are etched away;

[0020] forming a source line ion implantation region in the substrate at the bottom of the first deep trench by an ion implantation process;

[0021] forming a source line material layer, wherein the source line material layer fills the first deep trench;

[0022] Etching and removing the sacrificial oxide layer in the second deep trench of the storage area and the sacrificial oxide layer in the third deep trench of the peripheral logic area;

[0023] forming a third spacer material layer, wherein the third spacer material layer fills the second deep trench and the third deep trench;

[0024] Etching a portion of the third spacer material layer in the second deep trench, the second spacer material layer and the first spacer material layer on the bottom wall of the second deep trench to obtain a storage area spacer structure, and etching a portion of the third spacer material layer in the third deep trench, the second spacer material layer and the first spacer material layer on the bottom wall of the third deep trench to obtain a peripheral logic area spacer structure;

[0025] forming a bit line ion implantation region in the substrate at the bottom of the second deep trench and a source / drain region in the substrate at the bottom of the third deep trench by ion implantation processes respectively;

[0026] Forming a metal silicide layer on the surface of the bit line ion implantation region and the surface of the source line material layer in the storage area, and on the surface of the control gate material layer and the surface of the source / drain region in the peripheral logic area through a self-aligned metal silicide process; and

[0027] An interlayer insulating dielectric layer is formed, which fills the second deep trench and the third deep trench and covers the cap layer, the metal silicide layer on the top of the source line material layer and the metal silicide layer on the top of the control gate material layer of the peripheral logic area.

[0028] Optionally, in the method for preparing the ETOX NOR flash memory device, the step of etching away the sacrificial oxide layer in the first deep trench of the storage area and the second spacer material layer and the first spacer material layer on the bottom wall of the first deep trench by photolithography and etching processes includes:

[0029] defining an opening pattern on the photoresist layer at the top of the first deep trench through exposure and development processes;

[0030] etching and removing the sacrificial oxide layer in the first deep trench of the storage area through the opening pattern by a wet etching process; and

[0031] The second spacer material layer and the first spacer material layer on the bottom wall of the first deep trench are etched away by a wet etching process.

[0032] Optionally, in the method for manufacturing the ETOX NOR flash memory device, after forming a source line ion implantation region in the substrate at the bottom of the first deep trench by an ion implantation process and before forming the source line material layer, the method for manufacturing the ETOX NOR flash memory device further comprises:

[0033] The photoresist layer is removed by ashing.

[0034] Optionally, in the preparation method of the ETOX NOR flash memory device, while etching part of the third sidewall material layer in the second deep trench, the second sidewall material layer and the first sidewall material layer on the bottom wall of the second deep trench to obtain the storage area sidewall structure, and etching part of the third sidewall material layer in the third deep trench, the second sidewall material layer and the first sidewall material layer on the bottom wall of the third deep trench to obtain the peripheral logic area sidewall structure, the second sidewall material layer and the first sidewall material layer on the top of the cap layer of the storage area are etched, and the second sidewall material layer and the first sidewall material layer on the top of the control gate material layer of the peripheral logic area are etched.

[0035] Optionally, in the preparation method of the ETOX NOR flash memory device, the cap layer is made of silicon nitride; the first sidewall material layer is made of silicon dioxide; the second sidewall material layer is made of silicon nitride; and the third sidewall material layer is made of silicon dioxide.

[0036] Optionally, in the method for preparing the ETOX NOR flash memory device, after forming the interlayer insulating dielectric layer, the method for preparing the ETOX NOR flash memory device further comprises:

[0037] A first conductive plug, a second conductive plug, and a third conductive plug are formed, wherein the first conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the surface of the bit line ion implantation region, the second conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the top of the source line material layer, and the third conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the surface of the source / drain region.

[0038] Optionally, in the method for manufacturing the ETOX NOR flash memory device, after etching the control gate material layer and the pad oxide layer of the peripheral logic region to form a plurality of third deep trenches, and before forming the first spacer material layer and the second spacer material layer, the method for manufacturing the ETOX NOR flash memory device further comprises:

[0039] The anti-reflective layer is removed.

[0040] On the other hand, an embodiment of the present application further provides an ETOX NOR flash memory device, comprising:

[0041] A substrate comprising a storage area and a peripheral logic area, wherein a gate oxide layer, a floating gate material layer, an ONO dielectric layer, and a control gate material layer are formed on the substrate of the storage area, and a pad oxide layer and a control gate material layer are formed on the substrate of the peripheral logic area;

[0042] a capping layer, wherein the capping layer covers the control gate material layer of the storage area;

[0043] A first deep trench and a second deep trench, wherein the first deep trench and the second deep trench are located in the control gate material layer, the ONO dielectric layer, the floating gate material layer and the gate oxide layer of the storage area and are staggered;

[0044] a third deep trench, wherein the third deep trench is located in the control gate material layer and the liner oxide layer of the peripheral logic region;

[0045] a source line ion implantation region, the source line ion implantation region being located in the substrate at the bottom of the first deep trench;

[0046] a source line material layer, wherein the source line material layer fills the first deep trench;

[0047] a storage area sidewall structure, wherein the storage area sidewall structure covers a sidewall of the second deep trench;

[0048] a peripheral logic area sidewall structure, wherein the peripheral logic area sidewall structure covers the sidewall of the third deep trench;

[0049] a bit line ion implantation region, the bit line ion implantation region being located in the substrate at the bottom of the second deep trench;

[0050] a source / drain region, the source / drain region being located in the substrate at the bottom of the third deep trench;

[0051] a metal silicide layer, the metal silicide layer covering the surface of the bit line ion implantation region and the source line material layer of the storage region, and the surface of the control gate material layer and the source / drain region of the peripheral logic region; and

[0052] An interlayer insulating dielectric layer fills the second deep trench and the third deep trench and covers the cap layer, the metal silicide layer on top of the source line material layer, and the metal silicide layer on top of the control gate material layer of the peripheral logic area.

[0053] The technical solution of this application has at least the following advantages:

[0054] First, the present invention uses a sacrificial oxide layer to fill the first deep trench, etches away the sacrificial oxide layer in the first deep trench, and forms a source line ion implantation region in the substrate at the bottom of the first deep trench through an ion implantation process; then forms a source line material layer for filling the first deep trench. This avoids the situation in which residual photoresist on the sidewalls of the deep trench, which subsequently adversely affects device performance, during the preparation of serpentine source lines in a traditional SAS process. This improves device performance and facilitates further miniaturization and integration of memory cells.

[0055] Second, after forming the control gate material layer, the present application directly thins the control gate material layer in the storage area to a certain thickness, and then forms a cap layer on the thinned control gate material layer. In this way, in the subsequent etching process to form the first deep trench and the second deep trench, the presence of the cap layer can avoid accidental etching of the top corners of the control gate material layer, ensuring that the morphology and profile of the control gate material layer are intact. Because the process of thinning the control gate material layer is advanced, there is no need to thin the control gate material layer again later.

[0056] Third, the present application utilizes a source line material layer to connect the source line ion implantation areas of the storage area in series, eliminating the traditional etching and ion implantation process based on SAS technology. The source line ion implantation and word line ion implantation of the present application are symmetrical, which in disguise expands the effective channel of the storage unit and improves the device performance.

[0057] In addition, the preparation method of the ETOX NOR flash memory device provided in the present application can straighten the control gate in the integrated circuit layout, eliminating the elbow design in the traditional process, making OPC (optical proximity correction) simpler and improving the subsequent photolithography overlay accuracy; at the same time, all line width dimensions of the active area of ​​the storage area array (source line ion implantation area, word line ion implantation area, etc.) can be further reduced and maintained consistent, making OPC in this area simpler, and the subsequent CAA etching process is also simpler, thereby improving the subsequent photolithography overlay accuracy. BRIEF DESCRIPTION OF THE DRAWINGS

[0058] In order to more clearly illustrate the specific implementation methods of the present application or the technical solutions in the prior art, the following is a brief introduction to the drawings required for use in the specific implementation methods or the description of the prior art. Obviously, the drawings described below are some implementation methods of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0059] Figure 1-Figure 23 Schematic diagram of the semiconductor structure in each process step of preparing an ETOX NOR flash memory device according to an embodiment of the present invention;

[0060] The description of the accompanying drawings is as follows:

[0061] 10-substrate, 11-source line ion implantation region, 12-word line ion implantation region 1, 13-word line ion implantation region 2, 14-source / drain region, 21-gate oxide layer, 22-high voltage oxide layer, 23-low voltage oxide layer, 30-floating gate layer, 40-ONO dielectric layer, 50-control gate layer, 61-photoresist layer 1, 62-photoresist layer 2, 63-photoresist layer 3, 64-antireflective layer, 65-photoresist layer 4, 66-photoresist layer 5, 7 0-cap layer, 71-first deep trench, 72-second deep trench, 73-third deep trench, 81-first spacer material layer, 82-second spacer material layer, 83-third spacer material layer, 91-sacrificial oxide layer, 92-source line material layer, 93-metal silicide layer, 94-interlayer insulating dielectric layer, 95-first conductive plug, 96-second conductive plug, 98-third conductive plug, 97-fourth conductive plug, 99-fifth conductive plug. DETAILED DESCRIPTION

[0062] The following is a clear and complete description of the technical solutions in this application in conjunction with the accompanying drawings. Obviously, the embodiments described are part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making any creative efforts are within the scope of protection of this application.

[0063] In the description of this application, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings and are intended solely to facilitate the description of this application and simplify the description. They do not indicate or imply that the devices or components referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0064] In the description of this application, it should be noted that, unless otherwise expressly specified or limited, the terms "installed," "connected," and "connected" should be understood in a broad sense. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; they can refer to internal connections between two components; they can refer to wireless connections or wired connections. Those skilled in the art will understand the specific meanings of the above terms in this application based on the specific circumstances.

[0065] In addition, the technical features involved in the different embodiments of the present application described below can be combined with each other as long as they do not conflict with each other.

[0066] The present application embodiment provides a method for preparing an ETOX NOR flash memory device, referring to Figure 1-Figure 23 The preparation method of the ETOXNOR flash memory device includes:

[0067] First, refer to Figure 1 , Figure 1 This is a schematic diagram of a semiconductor structure after a control gate material layer is formed in an embodiment of the present application. A substrate 10 is provided, and the substrate 10 includes a storage area and a peripheral logic area, wherein a gate oxide layer 21, a floating gate material layer 30, an ONO dielectric layer 40 and a control gate material layer 50 are formed on the substrate of the storage area, and a pad oxide layer and a control gate material layer 50 are formed on the substrate of the peripheral logic area.

[0068] The peripheral logic region includes a high-voltage MOS device region and a low-voltage MOS device region, so the liner oxide layer of the high-voltage device region is the high-voltage oxide layer 22 ; the liner oxide layer of the low-voltage device region is the low-voltage oxide layer 23 .

[0069] Furthermore, the control gate material layer 50 of the peripheral logic region is subsequently used as the gate of the high-voltage MOS device and the gate of the low-voltage MOS device of the peripheral logic region.

[0070] Then, refer to Figure 2 , Figure 2 This is a schematic diagram of the semiconductor structure after the control gate material layer of the storage area is thinned to a certain thickness according to an embodiment of the present application. A photoresist layer 61 is coated on the control gate material layer 50 of the storage area and the control gate material layer 50 of the peripheral logic area. The control gate material layer 50 of the storage area is etched to a certain thickness using the photoresist layer 61 as a mask, thereby thinning the control gate material layer 50 of the storage area to a certain thickness.

[0071] Next, refer to Figure 3 , Figure 3 Schematic diagram of the semiconductor structure after forming a capping layer according to an embodiment of the present application, wherein a capping layer 70 is formed, and the capping layer 70 covers the control gate material layer 50 of the storage area and the control gate material layer 50 of the peripheral logic area.

[0072] In this embodiment, the capping layer 50 is made of silicon nitride.

[0073] Next, refer to Figure 4 , Figure 4 This is a schematic diagram of the semiconductor structure after the cap layer of the peripheral logic area is etched away in an embodiment of the present application. A second photoresist layer 62 is coated on the cap layer 70 of the storage area and the cap layer 70 of the peripheral logic area. The second photoresist layer 62 is used as a mask to etch away the cap layer 70 of the peripheral logic area.

[0074] For further reference, Figure 5 and Figure 6 , Figure 5 is a schematic diagram of the semiconductor structure after coating the third photoresist layer in an embodiment of the present application, Figure 6 This is a schematic diagram of the semiconductor structure after forming multiple first deep trenches and multiple second deep trenches in an embodiment of the present application. A photoresist layer 63 is coated on the cap layer 70 of the storage area and the control gate material layer 50 of the peripheral logic area, and the remaining thickness of the control gate material layer 50, the ONO dielectric layer 40, the floating gate material layer 30 and the gate oxide layer 21 of the storage area are etched to form multiple first deep trenches 71 and multiple second deep trenches 72. The first deep trenches 71 and the second deep trenches 72 are arranged in an alternating manner.

[0075] In the present application, after forming the control gate material layer, the control gate material layer of the storage area is directly thinned to a certain thickness, and then a cap layer is formed on the thinned control gate material layer. In this way, in the subsequent etching process to form the first deep trench and the second deep trench, the presence of the cap layer can avoid accidental etching of the top corners of the control gate material layer, thereby ensuring that the morphology and contour of the control gate material layer are intact. Since the process of thinning the control gate material layer is advanced, there is no need to thin the control gate material layer again later.

[0076] Next, refer to Figure 7 , Figure 7 Schematic diagram of the semiconductor structure after the anti-reflection layer is formed in an embodiment of the present application, wherein the anti-reflection layer 64 is formed, and the anti-reflection layer 64 fills the first deep trench 71 and covers the control gate material layer 50 of the peripheral logic region.

[0077] For further reference, Figure 8 and Figure 9 , Figure 8 Schematic diagram of the semiconductor structure after coating the photoresist layer 4 in the embodiment of the present application. Figure 9 This is a schematic diagram of the semiconductor structure after forming several third deep trenches in an embodiment of the present application. A photoresist layer 65 is coated on the anti-reflective layer 64, and the control gate material layer 50 and the high-voltage oxide layer 22 and the low-voltage oxide layer 23 of the peripheral logic area are etched to form several third deep trenches 73.

[0078] In this embodiment, after etching the control gate material layer 50 and the high-voltage oxide layer 22 and the low-voltage oxide layer 23 of the peripheral logic area to form a plurality of third deep trenches 73, and before forming the first spacer material layer 81 and the second spacer material layer 82, the preparation method of the ETOX NOR flash memory device may further include: removing the photoresist layer 65 and the anti-reflective layer 64.

[0079] Next, refer to Figure 10 , Figure 10 This is a schematic diagram of the semiconductor structure after the first spacer material layer and the second spacer material layer are formed in an embodiment of the present application, forming a first spacer material layer 81 and a second spacer material layer 82, wherein the first spacer material layer 81 covers the side walls and bottom walls of the first deep trench 71, the second deep trench 72 and the third deep trench 73, and the second spacer material layer 82 covers the first spacer material layer 81.

[0080] In this embodiment, the first spacer material layer 81 is made of silicon dioxide; the second spacer material layer 82 is made of silicon nitride.

[0081] For further reference, Figure 11 , Figure 11 This is a schematic diagram of the semiconductor structure after the sacrificial oxide layer is formed in an embodiment of the present application, forming a sacrificial oxide layer 91, which covers the second sidewall material layer 82 and fills the first deep trench 71, the second deep trench 72 and the third deep trench 73.

[0082] Next, refer to Figure 12 , Figure 12 1 is a schematic diagram of the semiconductor structure after the sacrificial oxide layer is planarized to the surface of the second spacer material layer according to an embodiment of the present application, wherein the sacrificial oxide layer 91 is planarized to the surface of the second spacer material layer 82 of the storage area.

[0083] Furthermore, a fifth photoresist layer 66 is coated on the flat surfaces of the sacrificial oxide layer 91 and the second spacer material layer 82 .

[0084] Next, the sacrificial oxide layer 91 in the first deep trench 71 of the storage area and the second spacer material layer 82 and the first spacer material layer 81 on the bottom wall of the first deep trench 71 are removed by photolithography and etching processes.

[0085] In this embodiment, the step of etching away the sacrificial oxide layer 91 in the first deep trench 71 of the storage area and the second spacer material layer 82 and the first spacer material layer 81 on the bottom wall of the first deep trench 71 by photolithography and etching processes may specifically include:

[0086] 1) Reference Figure 13 , Figure 13 FIG2 is a schematic diagram of a semiconductor structure after an opening pattern is defined on the photoresist layer 5 at the top of the first deep trench according to an embodiment of the present application. Through exposure and development processes, an opening pattern is defined on the photoresist layer 5 66 at the top of the first deep trench 71.

[0087] 2) Reference Figure 14 , Figure 14is a schematic diagram of the semiconductor structure after the sacrificial oxide layer in the first deep trench of the storage area is etched away according to an embodiment of the present application, wherein the sacrificial oxide layer 91 in the first deep trench 71 of the storage area is etched away by a wet etching process through the opening pattern; and

[0088] 3) Reference Figure 15 , Figure 15 This is a schematic diagram of the semiconductor structure after the second sidewall material layer and the first sidewall material layer on the bottom wall of the first deep trench are etched away in an embodiment of the present application. The second sidewall material layer 81 and the first sidewall material layer 82 on the bottom wall of the first deep trench 71 are etched away by a wet etching process.

[0089] For further reference, Figure 16 , Figure 16 Schematic diagram of the semiconductor structure after the source line ion implantation region is formed in an embodiment of the present application. The source line ion implantation region 11 is formed in the substrate 10 at the bottom of the first deep trench 71 through an ion implantation process.

[0090] In this embodiment, after forming the source line ion implantation region 11 in the substrate 10 at the bottom of the first deep trench 71 by an ion implantation process, and before forming the source line material layer 92, the preparation method of the ETOX NOR flash memory device may further include: removing the photoresist layer 5 66 by ashing.

[0091] Next, refer to Figure 17 and Figure 18 , Figure 17 is a schematic diagram of the semiconductor structure after forming the source line material layer in an embodiment of the present application, Figure 18 3 is a schematic diagram of the semiconductor structure after the source line material layer is polished beyond the upper surface of the sacrificial oxide layer according to an embodiment of the present application, forming a source line material layer 92, the source line material layer 92 filling the first deep trench 71 and covering the sacrificial oxide layer 91, and then the source line material layer 92 beyond the upper surface of the sacrificial oxide layer is polished using a CMP (chemical mechanical polishing) process, leaving only the source line material layer 92 in the first deep trench 71.

[0092] In the present application, a sacrificial oxide layer is used to fill the first deep trench, the sacrificial oxide layer in the first deep trench is etched away, and a source line ion implantation region is formed in the substrate at the bottom of the first deep trench through an ion implantation process; then a source line material layer is formed to fill the first deep trench, thereby avoiding the situation in which residual photoresist remains on the sidewall of the deep trench during the preparation of serpentine source lines in the traditional SAS process, which subsequently has an adverse effect on device performance, improves device performance, and is also conducive to further miniaturization and integration of storage units.

[0093] For further reference, Figure 19 , Figure 19This is a schematic diagram of the semiconductor structure after the sacrificial oxide layer in the second deep trench of the storage area and the sacrificial oxide layer in the third deep trench of the peripheral logic area are etched away in an embodiment of the present application, and the sacrificial oxide layer 91 in the second deep trench 72 of the storage area and the sacrificial oxide layer 91 in the third deep trench 73 of the peripheral logic area are etched away.

[0094] Next, a third spacer material layer 83 is formed, and the third spacer material layer 83 fills the second deep trench 72 and the third deep trench 73 .

[0095] In this embodiment, the third spacer material layer 83 is made of silicon dioxide.

[0096] For further reference, Figure 20 , Figure 20 It is a schematic diagram of the semiconductor structure after the storage area sidewall structure and the peripheral logic area sidewall structure are formed in an embodiment of the present application. Part of the third sidewall material layer 83 in the second deep trench 72, the second sidewall material layer 82 and the first sidewall material layer 81 on the bottom wall of the second deep trench 72 are etched to obtain the storage area sidewall structure, and part of the third sidewall material layer 83 in the third deep trench 73, the second sidewall material layer 82 and the first sidewall material layer 81 on the bottom wall of the third deep trench 73 are etched to obtain the peripheral logic area sidewall structure.

[0097] It is worth noting that while etching part of the third sidewall material layer 83 in the second deep trench 72, the second sidewall material layer 82 and the first sidewall material layer 81 on the bottom wall of the second deep trench 72 to obtain the storage area sidewall structure, and etching part of the third sidewall material layer 83 in the third deep trench 73, the second sidewall material layer 82 and the first sidewall material layer 81 on the bottom wall of the third deep trench 73 to obtain the peripheral logic area sidewall structure, the second sidewall material layer 82 and the first sidewall material layer 81 on the top of the cap layer 70 of the storage area are etched, and the second sidewall material layer 82 and the first sidewall material layer 81 on the top of the control gate material layer 50 of the peripheral logic area are etched.

[0098] Next, refer to Figure 21 , Figure 21 This is a schematic diagram of the semiconductor structure after the bit line ion implantation region and the source / drain region are formed in an embodiment of the present application. Through the ion implantation process, a bit line ion implantation region 12 and a bit line ion implantation region 2 13 are formed in the substrate 10 at the bottom of the second deep trench 72, and a source / drain region 14 is formed in the substrate at the bottom of the third deep trench 73.

[0099] For further reference, Figure 22 , Figure 22This is a schematic diagram of the semiconductor structure after the metal silicide layer is formed in an embodiment of the present application. Through a self-aligned metal silicide process, a metal silicide layer 93 is formed on the surface of the bit line ion implantation region 12 and the bit line ion implantation region 2 13 in the storage area, the surface of the source line material layer 92, and the surface of the control gate material layer 50 and the surface of the source / drain region 14 in the peripheral logic area.

[0100] Finally, reference Figure 23 , Figure 23 This is a schematic diagram of the semiconductor structure after the interlayer insulating dielectric layer is formed in an embodiment of the present application, forming an interlayer insulating dielectric layer 94, which fills the second deep trench 72 and the third deep trench 73 and covers the cap layer 70, the metal silicide layer 93 on the top of the source line material layer 92 and the metal silicide layer 93 on the top of the control gate material layer 50 of the peripheral logic area.

[0101] For further reference, Figure 23 After forming the interlayer insulating dielectric layer 94, the method for preparing the ETOX NOR flash memory device may further include: forming a first conductive plug 95, a second conductive plug 96, a third conductive plug 97, a fourth conductive plug 98, and a fifth conductive plug 99, wherein the first conductive plug 95 penetrates the interlayer insulating dielectric layer 94 and contacts the metal silicide layer on the surface of the bit line ion implantation region 12, the fourth conductive plug 98 penetrates the interlayer insulating dielectric layer 94 and contacts the metal silicide layer 93 on the surface of the bit line ion implantation region 2 13, the second conductive plug 96 penetrates the interlayer insulating dielectric layer 94 and contacts the metal silicide layer 93 on the top of the source line material layer 92, the third conductive plug 97 penetrates the interlayer insulating dielectric layer 94 and contacts the metal silicide layer 93 on the surface of the source / drain region 14; and the fifth conductive plug 99 penetrates the interlayer insulating dielectric layer 94 and contacts the metal silicide layer 93 on the top of the control gate material layer 50 of the peripheral logic region.

[0102] In this application, the source line ion implantation regions of the storage area are connected in series using a source line material layer, eliminating the traditional etching and ion implantation processes based on SAS technology. The symmetry of the source line ion implantation and word line ion implantation in this application indirectly expands the effective channel of the storage cell and improves device performance. In addition, the preparation method of the ETOX NOR flash memory device provided in this application can straighten the control gate in the integrated circuit layout, eliminating the elbow design used in traditional processes, making OPC (Optical Proximity Correction) simpler and improving the subsequent photolithography overlay accuracy. At the same time, all line width dimensions of the active area of ​​the storage array (source line ion implantation region, word line ion implantation region, etc.) can be further reduced and maintained consistent, simplifying OPC in this area, simplifying the subsequent CAA etching process, and improving the subsequent photolithography overlay accuracy.

[0103] Based on the same inventive concept, the present application also provides an ETOX NOR flash memory device, referring to Figure 23 , the ETOX NOR flash memory device comprises:

[0104] A substrate 10, comprising a memory area and a peripheral logic area, wherein a gate oxide layer 20, a floating gate material layer 30, an ONO dielectric layer 40, and a control gate material layer 50 are formed on the substrate 10 of the memory area, and a pad oxide layer and a control gate material layer 50 are formed on the substrate 10 of the peripheral logic area;

[0105] a capping layer 70 , wherein the capping layer 70 covers the control gate material layer 50 of the storage region;

[0106] A first deep trench 71 and a second deep trench 72, wherein the first deep trench 71 and the second deep trench 72 are located in the capping layer 70, the control gate material layer 50, the ONO dielectric layer 40, the floating gate material layer 30 and the gate oxide layer 20 of the storage area and are staggered;

[0107] A third deep trench 73, wherein the third deep trench 73 is located in the control gate material layer 50 and the liner oxide layer of the peripheral logic region;

[0108] a source line ion implantation region 11, wherein the source line ion implantation region 11 is located in the substrate at the bottom of the first deep trench 71;

[0109] a source line material layer 92 , wherein the source line material layer 92 fills the first deep trench 71 ;

[0110] a storage area sidewall structure, wherein the storage area sidewall structure covers the sidewall of the second deep trench 72;

[0111] a peripheral logic area sidewall structure, wherein the peripheral logic area sidewall structure covers the sidewall of the third deep trench 73;

[0112] The first bit line ion implantation region 12 and the second bit line ion implantation region 13 are located in the substrate at the bottom of the second deep trench 72;

[0113] a source / drain region 14 , the source / drain region 14 being located in the substrate 10 at the bottom of the third deep trench 73 ;

[0114] A metal silicide layer 93, the metal silicide layer 93 covering the surfaces of the bit line ion implantation region 12 and the bit line ion implantation region 2 13 of the storage region, the surface of the source line material layer 92, and the surface of the control gate material layer 50 and the surface of the source / drain region 14 of the peripheral logic region; and

[0115] An interlayer insulating dielectric layer 94 fills the second deep trench 72 and the third deep trench 73 and covers the cap layer 70, the metal silicide layer 93 on the top of the source line material layer 92 and the metal silicide layer 93 on the top of the control gate material layer 50 of the peripheral logic area.

[0116] Obviously, the above embodiments are merely examples for clarity of explanation and are not intended to limit the implementation methods. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all implementation methods here. Obvious variations or modifications arising therefrom remain within the scope of protection of this application.

Claims

1. A method for preparing an ETOX NOR flash memory device, characterized in that: include: A substrate is provided, the substrate comprising a storage area and a peripheral logic area, wherein a gate oxide layer, a floating gate material layer, an ONO dielectric layer, and a control gate material layer are formed on the substrate of the storage area, and a pad oxide layer and a control gate material layer are formed on the substrate of the peripheral logic area; thinning the control gate material layer of the storage area to a certain thickness; forming a capping layer, wherein the capping layer covers the control gate material layer of the storage region; Etching the remaining thickness of the control gate material layer, the ONO dielectric layer, the floating gate material layer, and the gate oxide layer of the storage area to form a plurality of first deep trenches and a plurality of second deep trenches, wherein the first deep trenches and the second deep trenches are arranged in a staggered manner; forming an anti-reflection layer, wherein the anti-reflection layer fills the first deep trench and covers the control gate material layer of the peripheral logic region; Etching the control gate material layer and the pad oxide layer of the peripheral logic region to form a plurality of third deep trenches; forming a first spacer material layer and a second spacer material layer, wherein the first spacer material layer covers the sidewalls and bottom walls of the first deep trench, the second deep trench, and the third deep trench, and the second spacer material layer covers the first spacer material layer; forming a sacrificial oxide layer, wherein the sacrificial oxide layer covers the second spacer material layer and fills the first deep trench, the second deep trench, and the third deep trench; planarizing the sacrificial oxide layer to the surface of the second spacer material layer; Coating a photoresist layer on the flat surfaces of the sacrificial oxide layer and the second sidewall material layer; By photolithography and etching processes, the sacrificial oxide layer in the first deep trench of the storage area and the second spacer material layer and the first spacer material layer on the bottom wall of the first deep trench are etched away; forming a source line ion implantation region in the substrate at the bottom of the first deep trench by an ion implantation process; forming a source line material layer, wherein the source line material layer fills the first deep trench; Etching and removing the sacrificial oxide layer in the second deep trench of the storage area and the sacrificial oxide layer in the third deep trench of the peripheral logic area; forming a third spacer material layer, wherein the third spacer material layer fills the second deep trench and the third deep trench; Etching a portion of the third spacer material layer in the second deep trench, the second spacer material layer and the first spacer material layer on the bottom wall of the second deep trench to obtain a storage area spacer structure, and etching a portion of the third spacer material layer in the third deep trench, the second spacer material layer and the first spacer material layer on the bottom wall of the third deep trench to obtain a peripheral logic area spacer structure; forming a bit line ion implantation region in the substrate at the bottom of the second deep trench and a source / drain region in the substrate at the bottom of the third deep trench by ion implantation processes respectively; Forming a metal silicide layer on the surface of the bit line ion implantation region and the surface of the source line material layer in the storage area, and on the surface of the control gate material layer and the surface of the source / drain region in the peripheral logic area through a self-aligned metal silicide process; and An interlayer insulating dielectric layer is formed, which fills the second deep trench and the third deep trench and covers the cap layer, the metal silicide layer on the top of the source line material layer and the metal silicide layer on the top of the control gate material layer of the peripheral logic area.

2. The method for preparing the ETOX NOR flash memory device according to claim 1, wherein: The step of etching and removing the sacrificial oxide layer in the first deep trench of the storage area and the second spacer material layer and the first spacer material layer on the bottom wall of the first deep trench by photolithography and etching processes comprises: defining an opening pattern on the photoresist layer at the top of the first deep trench through exposure and development processes; etching and removing the sacrificial oxide layer in the first deep trench of the storage area through the opening pattern by a wet etching process; and The second spacer material layer and the first spacer material layer on the bottom wall of the first deep trench are etched away by a wet etching process.

3. The method for preparing the ETOX NOR flash memory device according to claim 1, wherein: After forming a source line ion implantation region in the substrate at the bottom of the first deep trench by an ion implantation process and before forming a source line material layer, the method for preparing the ETOX NOR flash memory device further includes: The photoresist layer is removed by ashing.

4. The method for preparing the ETOX NOR flash memory device according to claim 1, wherein: While etching part of the third sidewall material layer in the second deep trench, the second sidewall material layer and the first sidewall material layer on the bottom wall of the second deep trench to obtain the storage area sidewall structure, and etching part of the third sidewall material layer in the third deep trench, the second sidewall material layer and the first sidewall material layer on the bottom wall of the third deep trench to obtain the peripheral logic area sidewall structure, the second sidewall material layer and the first sidewall material layer on the top of the cap layer of the storage area are etched, and the second sidewall material layer and the first sidewall material layer on the top of the control gate material layer of the peripheral logic area are etched.

5. The method for preparing the ETOX NOR flash memory device according to claim 1, wherein: The material of the capping layer is silicon nitride; the material of the first spacer material layer is silicon dioxide; the material of the second spacer material layer is silicon nitride; and the material of the third spacer material layer is silicon dioxide.

6. The method for preparing the ETOX NOR flash memory device according to claim 1, wherein: After forming the interlayer insulating dielectric layer, the method for preparing the ETOX NOR flash memory device further includes: A first conductive plug, a second conductive plug, and a third conductive plug are formed, wherein the first conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the surface of the bit line ion implantation region, the second conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the top of the source line material layer, and the third conductive plug penetrates the interlayer insulating dielectric layer and contacts the metal silicide layer on the surface of the source / drain region.

7. The method for preparing the ETOX NOR flash memory device according to claim 1, wherein: After etching the control gate material layer and the liner oxide layer of the peripheral logic region to form a plurality of third deep trenches, and before forming the first spacer material layer and the second spacer material layer, the method for preparing the ETOX NOR flash memory device further includes: The anti-reflective layer is removed.

8. An ETOX NOR flash memory device, characterized in that: include: A substrate comprising a storage area and a peripheral logic area, wherein a gate oxide layer, a floating gate material layer, an ONO dielectric layer, and a control gate material layer are formed on the substrate of the storage area, and a pad oxide layer and a control gate material layer are formed on the substrate of the peripheral logic area; a capping layer, wherein the capping layer covers the control gate material layer of the storage area; A first deep trench and a second deep trench, wherein the first deep trench and the second deep trench are located in the control gate material layer, the ONO dielectric layer, the floating gate material layer and the gate oxide layer of the storage area and are staggered; a third deep trench, wherein the third deep trench is located in the control gate material layer and the liner oxide layer of the peripheral logic region; a source line ion implantation region, the source line ion implantation region being located in the substrate at the bottom of the first deep trench; a source line material layer, wherein the source line material layer fills the first deep trench; a storage area sidewall structure, wherein the storage area sidewall structure covers a sidewall of the second deep trench; a peripheral logic area sidewall structure, wherein the peripheral logic area sidewall structure covers the sidewall of the third deep trench; a bit line ion implantation region, the bit line ion implantation region being located in the substrate at the bottom of the second deep trench; a source / drain region, the source / drain region being located in the substrate at the bottom of the third deep trench; a metal silicide layer, the metal silicide layer covering the surface of the bit line ion implantation region and the source line material layer of the storage region, and the surface of the control gate material layer and the source / drain region of the peripheral logic region; and An interlayer insulating dielectric layer fills the second deep trench and the third deep trench and covers the cap layer, the metal silicide layer on top of the source line material layer, and the metal silicide layer on top of the control gate material layer of the peripheral logic area.

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