A memory and a method of manufacturing the same

Abstract

The embodiment of the present application discloses a memory and a preparation method thereof. The memory comprises a plurality of memory cells, each of which comprises a charge storage region and a vertical transfer transistor located on the charge storage region. By controlling the doping concentration of the source end, the drain end and the channel region of the vertical transfer transistor, the interface between the source end and the channel region is prone to band-to-band tunneling, so as to realize lower subthreshold swing and larger on-state current, thereby improving the read-write speed. Further, a light doping concentration region including light doping and having a doping type opposite to that of the drain end is formed between the drain end and the channel region, so as to reduce the leakage current, reduce the refresh frequency and reduce the power consumption. The preparation method of the memory only needs simple doping concentration control, is compatible with the manufacturing of a CMOS image sensor, and can reduce the process manufacturing difficulty.

Description

Technical Field

[0001] This invention relates to the field of image sensor storage and processing, and more particularly to a memory and its fabrication method. Background Technology

[0002] As pixel array density increases in image sensors, the demands on image signal storage also rise. This results in caches occupying a very large area within image sensor chips and consuming significant energy during rapid read / write operations. To further improve the energy efficiency of cache systems, we previously proposed a process method using etching and epitaxial growth to fabricate high-density multi-value caches, effectively increasing signal storage density and reducing cache area. However, under traditional transistor designs, reading and writing large amounts of data still requires substantial energy.

[0003] like Figure 1 The diagram illustrates an example of an existing memory design. Existing vertical transfer transistors (Tx) rarely design the doping concentrations of the source (S), channel (CL), and drain (D). Sometimes, only the drain is heavily doped to reduce leakage current, but such designs offer very limited performance improvements. These existing memories, using traditional transistor designs, consume a significant amount of energy. Charge transfer in these designs is achieved through thermionic emission in traditional MOSFETs. Therefore, the minimum subthreshold swing (a performance metric measuring the rate of transition between the transistor's on and off states, representing the gate voltage change required for a tenfold change in leakage current) will not fall below the lower limit of 60mV / dec. In this case, the transistor's on / off ratio (I0) at lower operating voltages is limited. on / I off It is difficult to improve the memory charge read speed, so it is difficult to further improve the memory charge read speed; moreover, due to the short-channel effect, as the memory density increases, capacitor leakage becomes more and more obvious, memory time is limited, the refresh frequency is forced to increase, and power consumption is difficult to reduce. Summary of the Invention

[0004] To address the above problems, the present invention aims to provide a memory and its fabrication method. This memory utilizes the existing process flow for pixel regions of CMOS image sensors. It only requires modifying the doping distribution to fabricate a transfer transistor at the source-channel interface that facilitates band-to-band tunneling, serving as the memory's switch. By designing the doping concentration distribution at the source and channel regions, a lower subthreshold swing and a larger on-state current are achieved, thereby improving read / write speeds. Furthermore, by controlling the formation of a lightly doped region between the drain and channel regions, including a region with a doping type opposite to that of the drain, leakage current is reduced, refresh cycles are decreased, and power consumption is lowered. The fabrication method of this memory requires only simple doping concentration control, is compatible with the fabrication of CMOS image sensors, and reduces the complexity of the manufacturing process.

[0005] This invention provides a method for fabricating a memory, the memory comprising a plurality of memory cells, each memory cell comprising a charge storage region and a vertical transfer transistor located on the charge storage region, characterized in that the fabrication method comprises providing a substrate, fabricating a charge storage region on the substrate, and fabricating a vertical transfer transistor on the charge storage region; wherein, by controlling the doping concentration of the source terminal, drain terminal, and channel region of the vertical transfer transistor, band-to-band tunneling is facilitated at the interface between the source terminal and the channel region.

[0006] In some embodiments, the source terminal of the vertical transfer transistor includes a heavily doped first doped type region, the drain terminal includes a heavily doped second doped type region, and the channel region includes an intrinsically doped region or a first lightly doped region, wherein the first doped type is the opposite of the second doped type.

[0007] In some embodiments, after the vertical transfer transistor is etched, the first doped type region is formed by self-aligned implantation to form a first doped type region including a ring region, or a first doped type region including a U-shaped region, or a first doped type region including a first sub-region and a second sub-region with independent spacing.

[0008] In some embodiments, the first doped region is formed by well implantation.

[0009] In some embodiments, the gate of the vertical transfer transistor is in the shape of a flat ring surrounding the channel region in a plane perpendicular to the length direction of the channel.

[0010] In some embodiments, on a plane perpendicular to the length direction of the channel, the gate includes a ring shape or a U-shape around the periphery of the channel region, or the gate includes a first sub-gate and a second sub-gate located on both sides of the channel region.

[0011] In some embodiments, a second lightly doped region is further included between the drain terminal and the channel region, wherein the doping type of the second lightly doped region is opposite to that of the second doped type region.

[0012] In some embodiments, the channel region may further include adjacent heavily doped second doped sub-regions on both sides.

[0013] In some embodiments, the cross-sectional width of the second doped sub-region is smaller than the width of the channel region.

[0014] In some embodiments, one end of the second doped type sub-region is adjacent to the second lightly doped region, and the other end is adjacent to the first doped type region.

[0015] In some embodiments, the doping concentration of the second lightly doped region is greater than the doping concentration of the channel region.

[0016] In some embodiments, the depth dimension of the second lightly doped region is smaller than the depth dimension of the channel region.

[0017] In some embodiments, the width of the first doped region is greater than the width of the second doped region.

[0018] In some embodiments, the charge type of the charge storage region is the same as the doping type of the source end and the opposite to the doping type of the drain end.

[0019] In some embodiments, the substrate includes a first sub-substrate of a first doping type, a second sub-substrate of a second doping type located on the first sub-substrate, and a third sub-substrate of a first doping type located on the second sub-substrate.

[0020] In some embodiments, fabricating a charge storage region on the substrate includes the step of:

[0021] S1: Etching the substrate to form a plurality of first trenches;

[0022] S2: A first dielectric layer is formed in the trench;

[0023] S3: A first polysilicon material is filled on the surface of the first dielectric layer, and the second sub-substrate portion between the adjacent first trenches forms a lateral PN junction with the first polysilicon material as the charge storage region.

[0024] In some embodiments, fabricating the vertical transfer transistor on the charge storage region includes the steps of:

[0025] S4: Perform heavy doping of the first doping type, with the implantation depth below the bottom of the vertical transfer transistor, to form the source end of the vertical transfer transistor;

[0026] S5: Etch the third sub-substrate of the substrate to form a plurality of second trenches;

[0027] S6: A second dielectric layer is formed within the second trench;

[0028] S7: Fill the surface of the second dielectric layer with a second polycrystalline silicon material.

[0029] In some embodiments, fabricating the vertical transfer transistor on the charge storage region further includes the step of: heavily doping the drain terminal of the vertical transfer transistor with a second doping type.

[0030] In some embodiments, fabricating the vertical transfer transistor on the charge storage region includes the steps of: planarizing a second polysilicon material remaining above the silicon surface using chemical mechanical polishing; and then etching the second polysilicon material below the silicon surface using an etching process, such that the gates of the plurality of transfer transistors are separated from each other.

[0031] In some embodiments, the process step of etching the second polysilicon material below the silicon surface is performed simultaneously with the etch-back step of the transistor in the pixel region.

[0032] In some embodiments, fabricating the vertical transfer transistor on the charge storage region includes the step of doping the gate of the vertical transfer transistor.

[0033] In some embodiments, the process steps for doping the gate of the vertical transfer transistor are performed simultaneously with the process steps for doping the gate of the transistor in the pixel region.

[0034] In some embodiments, the vertical transfer transistor is located in the region between two adjacent first trenches.

[0035] In some embodiments, fabricating the vertical transfer transistor on the charge storage region further includes the step of doping the channel region, wherein the doping type includes a first doping type or a second doping type.

[0036] In some embodiments, the first doping type includes P-type or N-type, and the second doping type includes N-type or P-type.

[0037] The present invention also provides a memory prepared according to the method described in any of the foregoing embodiments.

[0038] Compared with the prior art, the present invention has the following advantages:

[0039] (1) By controlling the doping concentration of the source, drain, and channel regions of the vertical transfer transistor, band-to-band tunneling can easily occur at the interface between the source and channel regions to achieve a lower subthreshold swing and a larger on-state current, thereby improving read and write speed. By controlling the source region to include a heavily doped region and the channel region to be an intrinsic or lightly doped region, in the transistor off state, due to the low doping concentration of the channel, depletion occurs under the action of the gate work function. The long and narrow depletion channel exhibits a large resistance, thereby suppressing the leakage of charge from the capacitor to the drain, and ensuring sufficient memory time even without a negative operating voltage. During read and write operations, when the transistor is in the on state, a gate voltage is applied to the gate of the transistor. When the channel and source form a reverse PN junction, the energy band at the interface between the channel and source is significantly bent, and band-to-band tunneling occurs at the interface between the channel and source. Since the tunneling transistor does not rely on carrier thermal diffusion for charge transport, the subthreshold swing of the vertical transfer transistor can break through the thermodynamic limit, achieving a higher on-state current at a lower operating voltage, resulting in faster read and write speeds. When a forward-biased PN junction is formed between the channel and the source, charge transfer is carried out using the entire channel cross-section. The charge transfer cross-section in this state is significantly larger than that of a conventional transfer transistor in its on-state. Traditional MOSFETs rely on a channel inversion layer for read / write operations. This inversion layer forms only on the surface, has a small cross-sectional area, and a high channel resistance. Therefore, the tunneling transistor in this state still exhibits superior write performance. In summary, this invention enables high-speed storage in multi-valued memory, thereby reducing storage power consumption.

[0040] (2) Furthermore, the drain terminal is controlled to form a second doped type region including heavy doping, and a second light doped type region is set between the channel region and the drain terminal. The concentration of the second light doped type region is greater than the doping concentration of the channel region, which can further reduce the leakage current of the depletion region when turned off, reduce the number of refreshes, and reduce storage power consumption.

[0041] (3) Furthermore, a heavily doped region with the opposite doping type to the source end is formed on the side of the channel region and the surface of the first doped type region to connect the source end and the second lightly doped type region, so as to further reduce power consumption.

[0042] (4) The preparation method of this memory only requires simple concentration setting, which is compatible with the fabrication of CMOS image sensors and can reduce the difficulty of the fabrication process. Attached Figure Description

[0043] The present invention will be further described by way of exemplary embodiments, which will be described in detail with reference to the accompanying drawings. These embodiments are not limiting, and in these embodiments, the same reference numerals denote the same structures, wherein:

[0044] Figure 1 This is a partial cross-sectional schematic diagram of a memory in the prior art.

[0045] Figure 2 This is a cross-sectional schematic diagram of a memory according to one embodiment.

[0046] Figure 3 This is a cross-sectional schematic diagram of a memory according to another embodiment.

[0047] Figure 4 This is a cross-sectional schematic diagram of a memory according to yet another embodiment.

[0048] Figure 5 This is a cross-sectional schematic diagram of a memory according to another embodiment.

[0049] Figures 6-1 to 6-5 This is a schematic diagram of an embodiment of the process for fabricating the memory of the present invention.

[0050] Figure 7 This is a schematic diagram of another embodiment of the process for fabricating the memory of the present invention.

[0051] Figure 8 This is a cross-sectional schematic diagram of a memory according to one embodiment, including a specific doping type.

[0052] Figure 9 A schematic diagram of the XZ cross-sectional shape of the gate and channel regions of a vertical transfer transistor. Detailed Implementation

[0053] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are merely some examples or embodiments of the present invention. For those skilled in the art, these drawings can be applied to other similar scenarios without creative effort. Unless obvious from the context or otherwise specified, the same reference numerals in the drawings represent the same structures or operations.

[0054] In response to the problems mentioned in the background section, the following explanation is provided in conjunction with specific embodiments.

[0055] Figure 2 This is a cross-sectional schematic diagram of a memory according to an embodiment. The memory 1 includes a plurality of memory cells Cs fabricated on a substrate 100. Each memory cell Cs includes a charge storage region and a vertical transfer transistor Tx located on the charge storage region Cs. The vertical transfer transistor Tx includes a drain terminal D, a source terminal S, and a channel region CL, wherein the drain terminal D, the channel region CL, and the source terminal S are arranged sequentially in the Y direction. The charge type of the charge storage region Cs is the same as the doping type of the source terminal S and the opposite to the doping type of the drain terminal D.

[0056] Specifically, the doping concentrations of the source terminal S, drain terminal D, and channel region CL of the vertical transfer transistor are controlled. The source terminal S is configured to include a heavily doped first doped type region 106, and the drain terminal D is configured to include a heavily doped second doped type region 109 with a doping type opposite to that of the first doped type region. The channel region CL is configured as an intrinsically doped region or as a first lightly doped type region. The doping type of the first lightly doped type region can be either the first doping type or the second doping type. By setting the source terminal S to include a heavily doped first doped region 106 and the channel region CL to be intrinsically doped or lightly doped (i.e., the doping concentration of the first doped region is much greater than that of the channel region CL), after the gate voltage is applied, the energy band at the interface between the first doped region 106 and the channel region CL becomes more flexed, and band tunneling occurs at the interface between the first doped region 106 and the channel region CL. Since the tunneling transistor does not rely on carrier thermal diffusion for charge transport, the subthreshold swing of the vertical transfer transistor can break through the thermodynamic limit, achieving a higher on-state current under lower operating voltage conditions, improving read / write speed, reducing the operating voltage of the integrated circuit, and reducing power consumption.

[0057] In a preferred embodiment, such as Figure 3 As shown, a second lightly doped region 111 is further provided between the heavily doped second doped region 109 and the channel region CL. The doping concentration of the second lightly doped region 111 is greater than that of the channel region CL, but less than that of the second doped region 109, and the doping type of the second lightly doped region 111 is opposite to that of the second doped region 109. The channel region CL can include intrinsic doping or light doping. If the doping type of the channel region CL is the same as that of the second lightly doped region, then the doping concentration of the channel region CL is required to be less than that of the second lightly doped region 111; otherwise, the channel region is set as an intrinsically doped or lightly doped region with a doping type opposite to that of the second lightly doped region 111. In addition, the depth dimension (i.e., the dimension in the Y direction) of the second lightly doped region 111 is smaller than the depth dimension of the channel region CL. Controlling the formation of a region with decreasing doping concentration at the drain and the channel region can reduce leakage current, reduce refresh frequency, and further reduce power consumption. Furthermore, by controlling the doping concentration of the source terminal S and the channel region CL to increase the band-to-band tunneling probability at the interface, and by controlling the drain terminal D and the channel region CL to form a region with decreasing doping concentration, the transistor's on-state current can be increased while the leakage current is reduced, which can further improve the on-state ratio.

[0058] like Figure 2 or Figure 3 As shown, the first doped region 106 can be formed by well implantation or far-end implantation, including a width dimension larger than that of the second doped region 109. For example... Figure 2As shown, the width of the first doped region 106 in the X direction is approximately equal to the sum of the width of the channel region CL and the widths of the gates G on both sides. That is, the first doped region 106 not only has the width of the second doped region 109, but also extends to both sides. The shape of the first doped region 106 in the XZ cross-section can be a combination of one or more shapes, including blocky, annular, flat annular, and U-shaped. Furthermore, the shape of the first doped region 106 in the XZ cross-section can also form independent first and second sub-regions, which are blocky and symmetrically formed on both sides of the channel region CL, and both the first and second sub-regions form contact interfaces with the channel region CL. The shape of the first doped region 106 can be substantially consistent with the shape of the gate G in the XZ cross-section, such as... Figure 9 As shown, the shape of the gate G in the XZ cross section can be formed into one or more combinations of shapes, including block shape (shown in (a)), ring shape (shown in (c)-(e)), circular ring shape (shown in (e)), flat circular ring shape (shown in (d)), and U-shape (shown in (b)). It can also be formed into a gate G consisting of an independent first block shape and a second block shape, i.e., a dual-gate transistor, such as... Figure 9 As shown in (a). Preferably, the gate G in the XZ cross section is formed into a flat circular ring (as shown in (d)). This ensures that the channel can be fully depleted when the transistor is turned on, enhances the gate's control over the channel, and at the same time, the flat circular ring has a smaller area, ensuring a certain isolation distance from the surrounding area.

[0059] In a preferred embodiment, the first doped region 106 is preferably formed by self-aligned implantation of a vertical transfer transistor Tx to facilitate process compatibility with CMOS image sensors and simplify the fabrication process. Figure 4 The diagram shows a cross-sectional example of an embodiment of the memory disclosed herein. Its first doped region 106 is formed based on self-aligned implantation using a vertical transfer transistor (VLT) Tx. Two discrete regions can be seen in the XY section, but in the XZ section, the first doped region 106, based on self-aligned implantation using the VLT Tx, can form doped regions including annular, flat annular, and U-shaped regions, or it can form a block-shaped, independent first and second sub-region. Specifically, the self-aligned ion implantation using the VLT Tx can be performed after etching the VLT Tx shape and before filling the gate polysilicon material G, forming the heavily doped first doped region 106 based on the VLT Tx shape through self-aligned doping implantation.

[0060] In a preferred embodiment, when forming a heavily doped first doped type region 106 based on self-aligned implantation of the vertical transfer transistor Tx, in order to further reduce the threshold voltage and thus further reduce the operating voltage, which is beneficial for reducing power consumption, a heavily doped second doped type sub-region 112 can also be formed at the side interface of the channel region CL and the upper interface of the first doped type region 106, such as... Figure 5 As shown. The cross-sectional width of the second doped sub-region 112 (specifically, the width in the X direction of one side of the portion located on both sides of the channel region CL, and the width in the Y direction of the portion located at the upper interface of the first doped sub-region 106) is smaller than the width of the channel region CL. One end of the second doped sub-region 112 is adjacent to the second lightly doped sub-region 111 to form an interface, and the other end is adjacent to the first doped sub-region 106 to form an interface. Figure 5 As shown, the second doped sub-region 112 forms positive and negative "L" shapes in the XY section, and the bottom edge of the "L" forms a contact interface with the top surface of the first doped sub-region 106.

[0061] In any embodiment of this disclosure, the first doping type may include P-type or N-type, and the second doping type may include N-type or P-type. Specifically, when the first doping type is P-type, the second doping type includes P-type; when the first doping type is N-type, the second doping type is P-type. The first lightly doped region may be either N-type lightly doped or P-type lightly doped.

[0062] Taking the N-type tunneling transistor as an example, we will introduce it in detail, such as Figure 8As shown, during the process, the drain terminal D and the floating diffusion region FD of the pixel area of ​​the CMOS image sensor are made together to form a heavily doped N+ type region, the control source terminal S is a heavily doped P+ region, the second lightly doped type region 111 is a lightly doped P- region, the channel region CL of the transfer transistor is an N- (N-type lightly doped) region (or intrinsically doped, or P-- region (P-- refers to a P-type lightly doped region with a lower doping concentration than the second lightly doped type region 111 is a P- region), which can be selected according to the required threshold voltage), and the gate G of the vertical transfer transistor Tx is made together with the gate of the pixel area transistor to form an N-type doped gate G, thus forming an N-type tunneling transistor. During read / write operations, when a positive voltage is applied to the gate G, the channel region CL is N-type, and a high voltage is applied to the drain D (writing 1). The N-type of the channel region CL and the P+ type of the source S form a reverse-biased PN junction. This controls the carrier concentration in the P+ region of the source S and the N- region of the channel region CL, increasing the probability of band-to-band tunneling at the interface between the first doped region 106 (or the source S) and the channel region CL. Since the tunneling transistor does not rely on thermal diffusion of carriers for charge transport, the subthreshold swing of the vertical transfer transistor Tx can exceed the thermodynamic limit. Higher on-state current is achieved under lower operating voltage conditions, resulting in faster write (write 1) speeds. On the other hand, when a low voltage is applied to the drain D (writing 0), the N-type of the channel region CL and the P+ type of the source S form a forward-biased PN junction. The forward-biased PN junction can utilize the entire channel cross-section for charge transfer, and the current transfer cross-section in this state is significantly larger than that in the corresponding on-state of a conventional transfer transistor. Compared to traditional field-effect transistors that rely on a channel inversion layer to write "0," where the inversion layer forms only on the channel surface, has a small cross-sectional area, and a high channel resistance, the tunneling transistor of this disclosure exhibits superior write performance under the same conditions. During turn-off, the tunneling transistor of this disclosure, due to the low doping concentration of the channel region CL, undergoes depletion under the gate work function. The long and narrow depletion channel exhibits a large resistance, thereby suppressing the leakage of charge from the capacitor to the drain terminal D, ensuring sufficient memory time without the need for a negative operating voltage. Therefore, the memory of this disclosure can achieve high-speed storage in multi-valued memory while reducing memory power consumption. Furthermore, a second lightly doped region 111 is added near the drain terminal; that is, a second lightly doped region 111 is set between the drain terminal and the channel region. The concentration of the second lightly doped region 111 is greater than the concentration of the channel region CL but less than the doping concentration of the drain terminal. When turned on, band-to-band tunneling is easy to occur at the interface between the source terminal S and the channel region CL. When turned off, due to the presence of the second lightly doped region 111, the channel depletion region resistance is larger, resulting in a lower turn-off current and a higher on / off ratio.

[0063] This disclosure also provides a method for fabricating a memory according to any of the preceding embodiments. The structure of the memory disclosed herein is compatible with existing CMOS image sensor processes. It only requires controlling the doping concentration at the source end and the etching depth of the vertical transfer transistor to form a tunneling transistor. By utilizing the ease with which band-to-band tunneling occurs at the interface between the source end and the channel region, the performance of the memory can be improved.

[0064] The memory includes multiple memory cells, each memory cell including a charge storage region and a vertical transfer transistor located on the charge storage region. The fabrication method includes providing a substrate, fabricating a charge storage region on the substrate, and fabricating a vertical transfer transistor on the charge storage region. The process flow of the fabrication method of the memory disclosed herein is described below with reference to specific embodiments.

[0065] like Figure 6-1 As shown in process (a), a semiconductor substrate 100 is provided. Any silicon-containing material can be used as the material for fabricating the semiconductor substrate, such as silicon, single-crystal or polycrystalline silicon, amorphous silicon, carbon-doped silicon, combinations thereof, or multilayers of two or more of these. The semiconductor substrate 100 can also be germanium, germanium-silicon, or silicon on insulator. The provided substrate 100 includes a first sub-substrate 101 of a first doping type, a second sub-substrate 102 of a second doping type located on the first sub-substrate, and a third sub-substrate 103 of a first doping type located on the second sub-substrate. For example, the bottommost first sub-substrate 101 may include a P-type substrate, the middle second sub-substrate 102 may include an N-type region as a charge storage region (or photodiode region), and the topmost third sub-substrate 103 may include a P-type epitaxial layer for use as a substrate for a functional transistor (e.g., a vertical transfer transistor). The steps of fabricating a charge storage region Cs on the substrate 100 and fabricating a vertical transfer transistor Tx on the charge storage region Cs are described in detail below.

[0066] The process of fabricating the charge storage region Cs on the substrate 100 includes the following steps:

[0067] S1: The substrate 100 is etched to form several first trenches 104; such as Figure 6-1 The process is shown in (b). The vertical transfer transistor Tx fabricated later is located in the region between the two adjacent first trenches 104.

[0068] S2: A buffer layer and a first dielectric layer (not shown) are formed in the trench 104; the material of the dielectric layer can be silicon oxide.

[0069] S3: A first polysilicon material 105 is filled on the surface of the first dielectric layer, and the remaining second sub-substrate (e.g., N-type) region between adjacent first trenches 104 forms a lateral PN junction with the first polysilicon material 105 to serve as a charge storage region Cs; Figure 6-2The process shown is (c). Here, after etching the substrate 100 to form the isolation trench 104, a smaller portion of the substrate remains unetched. When the isolation trench 104 is filled with a buffer layer, a dielectric layer, and polysilicon material, the previously unetched portion of the substrate is compensated for by the P-type buffer layer. Therefore, the unetched portion of the substrate ultimately exhibits a less doped P-type region (i.e., a lightly doped P-type region (P-)). Figure 8 As shown.

[0070] Fabricating a vertical transfer transistor Tx on the charge storage region Cs includes the following steps:

[0071] S4: Perform heavy doping implantation of the first doping type, with the implantation depth below the bottom of the vertical transfer transistor, to form the source terminal S including the first doping type region 106; as Figure 6-2 The process shown is (d). For example, performing heavy doping implantation of the far-end P-type, with the implantation depth below the bottom of the vertical transfer transistor, forms a block-shaped first doped type region 106 with a width dimension larger than the width dimension of the second doped type region 109 (this first doped type doping can also be easily formed by EPI growth). Figure 6-2 The first doped type region 106 of the shape shown in process (d) has certain requirements regarding its doping concentration (e.g., P-type) and etching depth of the vertical transistor Tx. These requirements are designed to ensure that the depletion region bandgap at the interface between the source terminal S and the channel region CL is sufficiently large after reverse bias when the transistor is turned on, thus promoting band-to-band tunneling. For example, a narrower bandgap semiconductor element implantation (e.g., Ge) at the source terminal S can reduce the bandgap on this side, thereby increasing the probability of band-to-band tunneling (BTBT) and further improving the device's on / off ratio.

[0072] S5: Etch the third sub-substrate 103 of the substrate 100 to form a plurality of second trenches 110; such as Figure 6-3 The process shown is (e).

[0073] S6: A second dielectric layer (not shown) is formed in the second trench 110.

[0074] S7: Fill the surface of the second dielectric layer with a second polycrystalline silicon material 108; such as Figure 6-3 The process shown is (f).

[0075] S8: The second polycrystalline silicon material 108 remaining above the surface of the third sub-substrate 103 is planarized using chemical mechanical polishing; such as Figure 6-4 The process shown is (g).

[0076] S9: The drain of the vertical transfer transistor Tx is heavily doped with a second type of doping to form a second-doped region 109. The second-doped region 109 can be completed together with the second-doped doping implantation of the floating diffusion region of the pixel region. For example... Figure 6-4 The process shown is (h).

[0077] S10: The second polycrystalline silicon material 108 is etched below the silicon surface using an etching process, such as... Figure 6-4 The illustrated process (i) ensures that the gates G of multiple transfer transistors are separated from each other. On a plane perpendicular to the length direction of the channel CL, the gate G may be formed in a circular ring, a flat circular ring, or a U-shape around the channel region, or the gate G may be formed by a first sub-gate and a second sub-gate located on both sides of the channel CL to form a dual-gate transistor. Preferably, on a plane perpendicular to the length direction of the channel CL, the gate of the vertical transfer transistor is formed in a flat ring shape surrounding the channel region. This ensures that the channel is fully depleted when the transistor is turned on, enhancing the gate's control over the channel. Simultaneously, the flat ring has a smaller area, ensuring a certain isolation distance from the surrounding area.

[0078] In addition, the fabrication method of the vertical transfer transistor Tx may also include a gate doping step. The gate etch-back and gate doping of the vertical transfer transistor Tx can be performed together with the gate etch-back and doping of the pixel region to reduce the number of process steps. The fabrication method may also include a step of doping the channel region, and the doping type of the channel region may include a first doping type or a light doping of a second doping type.

[0079] In a preferred embodiment, the steps of process (d)-(e) can be replaced by including figures (d')-(e'), as follows: Figure 7 As shown, the third sub-substrate 103 is etched to form the trench 110 of the vertical transfer transistor. As shown in flowchart (d'), the vertical transfer transistor 107 is used for self-alignment to perform first doping type (e.g., P-type) doping implantation to form a heavily doped first doped type region 106. In this way, the implantation depth can be naturally lower than the bottom of the vertical transfer transistor to form the source terminal S of the vertical transfer transistor, which greatly simplifies the process and improves the implantation accuracy. The first doped type region formed in this way can form a first doped type region including a ring region, or a first doped type region including a U-shaped region, or a first doped type region including independently spaced first sub-regions and second sub-regions. More preferably, the first doped type region 106 can form a first doped type region including a flat ring.

[0080] In a preferred embodiment, the fabrication method of the vertical transfer transistor Tx may further include a step of setting a second lightly doped region 111, wherein the doping concentration of the second lightly doped region 111 is controlled to be greater than the doping concentration of the channel region CL and less than the doping concentration of the second doped type region 109. The doping implantation involved in this step can be performed using a well implantation method after the formation of the trench 110 in process (e) diagram (or process (d'), (e') diagram) and before the filling of the second polysilicon material 108.

[0081] In a preferred embodiment, the method for fabricating the vertical transfer transistor Tx may further include an implantation step of a heavily doped second doped sub-region 112, in which a heavily doped second doped sub-region 112 is formed on the side surface of the channel region CL and the upper surface of the first doped region 106. The doping implantation involved in this step may be completed after the formation of the trench 110 in process (e) diagram (or process (d'), (e') diagram) and before the filling of the second polysilicon material 108 by well implantation and self-aligned implantation.

[0082] In a preferred embodiment, the portion of the first polysilicon material 105 filled in the first trench 104 located in the vertical transfer transistor Tx will be etched back to a certain depth (not shown in the figure) in a subsequent process. The etch-back depth can be slightly higher than the bottom of the vertical transfer transistor Tx or slightly lower than the bottom of the vertical transfer transistor Tx. After etch-back, a dielectric layer is filled for isolation.

[0083] The basic concepts have been described above. It is clear that the detailed disclosure above is merely illustrative and does not constitute a limitation of the present invention. Although not explicitly stated herein, various modifications, improvements, and corrections may be made to the present invention by those skilled in the art. Such modifications, improvements, and corrections are suggested in this invention and therefore remain within the spirit and scope of the exemplary embodiments of the present invention.

[0084] It should be understood that the embodiments described in this invention are merely illustrative of the principles of the invention. Other modifications may also fall within the scope of this invention. Therefore, alternative configurations of the embodiments of this invention are considered as examples and not limitations, and are regarded as consistent with the teachings of this invention. Accordingly, the embodiments of this invention are not limited to those explicitly described and illustrated herein.

Claims

1. A method for fabricating a memory, the memory comprising a plurality of memory cells, each memory cell comprising a charge storage region and a vertical transfer transistor located on the charge storage region, characterized in that, The preparation method includes, A substrate is provided, a charge storage region is fabricated on the substrate, and a vertical transfer transistor is fabricated on the charge storage region; Specifically, by controlling the doping concentration of the source, drain, and channel regions of the vertical transfer transistor, band-to-band tunneling is easily achieved at the interface between the source and channel regions. The source of the vertical transfer transistor includes a heavily doped first doping type region, the drain includes a heavily doped second doping type region, and the channel region includes an intrinsic doped region or a first lightly doped region, wherein the first doping type is the opposite of the second doping type.

2. The method according to claim 1, characterized in that, After the vertical transfer transistor is etched, the first doped type region is formed by self-aligned implantation to form a first doped type region including a ring region, or a first doped type region including a U-shaped region, or a first doped type region including a first sub-region and a second sub-region with independent spacing.

3. The method according to claim 1, characterized in that, The first doped region is formed by well implantation.

4. The method according to claim 1, characterized in that, On a plane perpendicular to the length direction of the channel, the gate of the vertical transfer transistor is in the shape of a flat ring surrounding the channel region.

5. The method according to claim 1, characterized in that, On a plane perpendicular to the length direction of the channel, the gate of the vertical transfer transistor includes a ring or U-shape around the periphery of the channel region, or the gate of the vertical transfer transistor includes a first sub-gate and a second sub-gate located on both sides of the channel region.

6. The method according to claim 2, characterized in that, The drain terminal and the channel region further include a second lightly doped region, the doping type of which is opposite to that of the second doped region.

7. The method according to claim 6, characterized in that, The surface of the channel region and the surface of the first doped type region are further formed with a second doped type sub-region including heavy doping.

8. The method according to claim 7, characterized in that, The cross-sectional width of the second doped sub-region is smaller than the width of the channel region.

9. The method according to claim 7, characterized in that, One end of the second doped type sub-region is adjacent to the second lightly doped region, and the other end is adjacent to the first doped type region.

10. The method according to claim 6, characterized in that, The doping concentration of the second lightly doped region is greater than that of the channel region.

11. The method according to claim 6, characterized in that, The depth dimension of the second lightly doped region is smaller than the depth dimension of the channel region.

12. The method according to claim 1, characterized in that, The width of the first doped region is greater than the width of the second doped region.

13. The method according to any one of claims 1 to 12, characterized in that, The charge type of the charge storage region is the same as the doping type of the source end and the opposite to the doping type of the drain end.

14. The method according to any one of claims 1 to 12, characterized in that, The substrate includes a first sub-substrate of a first doping type, a second sub-substrate of a second doping type located on the first sub-substrate, and a third sub-substrate of a first doping type located on the second sub-substrate.

15. The method according to claim 14, characterized in that, The process of fabricating a charge storage region on the substrate includes the following steps: S1: Etching the substrate to form a plurality of first trenches; S2: A first dielectric layer is formed in the trench; S3: A first polysilicon material is filled on the surface of the first dielectric layer, and a second sub-substrate region between adjacent first trenches forms a lateral PN junction with the first polysilicon material as the charge storage region.

16. The method according to claim 15, characterized in that, Fabricating the vertical transfer transistor on the charge storage region includes the following steps: S4: Perform heavy doping of the first doping type, with the implantation depth below the bottom of the vertical transfer transistor, to form the source end of the vertical transfer transistor; S5: Etch the third sub-substrate of the substrate to form a plurality of second trenches; S6: A second dielectric layer is formed within the second trench; S7: Fill the surface of the second dielectric layer with a second polycrystalline silicon material.

17. The method according to claim 16, characterized in that, Fabricating the vertical transfer transistor on the charge storage region further includes the step of: heavily doping the drain terminal of the vertical transfer transistor with a second doping type.

18. The method according to claim 16, characterized in that, Fabricating the vertical transfer transistor on the charge storage region includes the steps of: planarizing a second polysilicon material remaining above the silicon surface using chemical mechanical polishing; and then etching the second polysilicon material below the silicon surface using an etching process, thereby separating the gates of the plurality of transfer transistors from each other.

19. The method according to claim 18, characterized in that, The process of etching the second polysilicon material below the silicon surface is performed simultaneously with the etch-back process of the transistors in the pixel region.

20. The method according to claim 16, characterized in that, The fabrication of the vertical transfer transistor on the charge storage region includes the step of doping the gate of the vertical transfer transistor.

21. The method according to claim 20, characterized in that, The gate doping process of the vertical transfer transistor is performed simultaneously with the gate doping process of the transistor in the pixel region.

22. The method according to claim 16, characterized in that, The vertical transfer transistor is located in the region between two adjacent first trenches.

23. The method according to claim 16, characterized in that, Fabricating the vertical transfer transistor on the charge storage region further includes the step of doping the channel region, wherein the doping type includes a first doping type or a second doping type.

24. The method according to claim 1, characterized in that, The first doping type includes P-type or N-type, and the second doping type includes N-type or P-type.

25. A memory, prepared according to any one of claims 1-24.

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