Semiconductor device and forming method thereof

Abstract

An internal spacer between a source / drain region of a nanostructure transistor and a sacrificial nanostructure layer of the nanostructure transistor is removed prior to forming a gate structure of the nanostructure transistor. The sacrificial nanostructure layer is removed, and then the internal spacers are removed. The sacrificial nanostructure layer is then replaced with a gate structure of the nanostructure transistor such that the gate structure and the source / drain region are spaced apart by an air gap resulting from the removal of the internal spacer. The dielectric constant (or relative dielectric coefficient) of the air gap between the source / drain region and the gate structure is less than the dielectric constant of the material of the internal spacer. The smaller dielectric constant of the air gap reduces the capacitance between the source / drain region and the gate structure. The embodiment of the invention relates to a semiconductor device and a forming method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor devices and methods of forming the same. Background Art

[0002] As semiconductor device manufacturing advances and technology process nodes decrease in size, transistors may become subject to short channel effects (SCE), such as hot carrier degradation, barrier reduction, and quantum confinement, among other examples. In addition, for smaller technology nodes, as the gate length of the transistor decreases, source / drain (S / D) electron tunneling increases, which increases the off current for the transistor (the current flowing through the channel of the transistor when the transistor is in the off configuration). Silicon (Si) / silicon germanium (SiGe) nanostructure transistors, such as nanowires, nanosheets, and all-around gate (GAA) devices, are potential candidate transistors to overcome short channel effects at smaller technology nodes. Nanostructure transistors are efficient structures that can experience reduced SCE and enhanced carrier mobility relative to other types of transistors. Summary of the invention

[0003] Some embodiments of the present application provide a semiconductor device, comprising: a plurality of nanostructure channels, the plurality of nanostructure channels being arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure wrapping each of the plurality of nanostructure channels; and a source / drain region adjacent to ends of the plurality of nanostructure channels and ends of the gate structure, wherein the source / drain region and the ends of the gate structure are separated by a plurality of air gaps.

[0004] Other embodiments of the present application provide a semiconductor device, comprising: a plurality of nanostructure channels, the plurality of nanostructure channels being arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure wrapping each of the plurality of nanostructure channels; a source / drain region adjacent to ends of the plurality of nanostructure channels and an end of the gate structure, wherein the source / drain region and the ends of the gate structure are separated by a plurality of air gaps; and a buffer region located below the source / drain region and adjacent to a mesa region located below the gate structure, wherein the buffer region comprises a semiconductor material, and wherein the buffer region and the source / drain region are separated by air gaps of the plurality of air gaps.

[0005] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a layer stack, the layer stack comprising a plurality of nanostructured channel layers and a plurality of sacrificial layers arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; forming a source / drain groove adjacent to the layer stack; etching the ends of the plurality of sacrificial layers through the source / drain groove to form a cavity between the ends of the plurality of nanostructured channel layers; forming an internal spacer in the cavity; after forming the internal spacer, forming a source / drain region in the source / drain groove; after forming the source / drain region, removing the plurality of sacrificial layers; removing the internal spacer through a first region previously occupied by the sacrificial layer; and after removing the internal spacer, forming a gate structure wrapping each of the plurality of nanostructured channel layers, wherein the gate structure is formed so that an air gap is formed in a second region between the gate structure and the source / drain region previously occupied by the internal spacer. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figures 1A to 1C is a diagram of an exemplary implementation of a fin definition process described herein.

[0008] Figure 2 is a diagram of an exemplary embodiment of a dummy gate formation process described herein.

[0009] Figure 3 is a diagram of an exemplary embodiment of a source / drain recess formation process described herein.

[0010] Figure 4A and Figure 4B is a diagram of an exemplary embodiment of a dummy inner spacer formation process described herein.

[0011] FIG. 5A to FIG. 5D is a diagram of an exemplary embodiment of an internal spacer formation process described herein.

[0012] Figure 6 is a diagram of an exemplary embodiment of a source / drain region formation process and an interlayer dielectric (ILD) formation process described herein.

[0013] 7A to 7D is a diagram of an exemplary embodiment of a replacement gate (RPG) process described herein.

[0014] FIG. 8A to FIG. 8Dare diagrams of exemplary embodiments of forming semiconductor devices described herein.

[0015] Fig. 9 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0016] Fig.10 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0017] Fig.11 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0018] Fig.12 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0019] Fig.13 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0020] Fig.14 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0021] Fig.15 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0022] Fig.16 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0023] Fig.17 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0024] Fig.18 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0025] Fig.19 is a diagram of an exemplary embodiment of a semiconductor device described herein.

[0026] Fig. 20 is a flow chart of an exemplary process associated with forming the semiconductor devices described herein.

[0027] FIG. 21A to FIG. 21E is a diagram of an exemplary embodiment of an internal spacer formation process described herein. DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples for realizing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0029] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0030] As the size of the nanostructure transistor is reduced, the spacing between the structures of the nanostructure transistor is also reduced. The reduced spacing between the structures of the nanostructure transistor can increase the capacitance in the nanostructure transistor. For example, an increased cell capacitance may be generated between the source / drain region of the nanostructure transistor and the gate structure of the nanostructure transistor. As another example, an increased parasitic capacitance may be generated between the gate structure and the buffer region below the source / drain region. The increased capacitance may reduce the performance of the nanostructure transistor because the increased capacitance may generate residual charge stored in the source / drain region of the transistor of the nanostructure transistor and / or in the gate structure, which may make the switching time for the nanostructure transistor longer (for example, between the on state and the off state), which is due to the increased resistance-capacitance (RC) time constant generated by the increased capacitance.

[0031] In some embodiments described herein, before forming the gate structure of the nanostructure transistor, the internal spacer between the source / drain region of the nanostructure transistor and the sacrificial nanostructure layer of the nanostructure transistor is removed. The sacrificial nanostructure layer is removed, and then the internal spacer is removed. The sacrificial nanostructure layer is then replaced with the gate structure of the nanostructure transistor, so that the gate structure and the source / drain region are separated by an air gap generated by the removal of the internal spacer. To form the air gap, a porous interface layer is formed on the internal spacer after removing the sacrificial layer. The internal spacer is then removed through the porous interface layer. The porous interface layer prevents the space previously occupied by the internal spacer from being filled with the material of the gate structure and the associated gate dielectric layer.

[0032] The dielectric constant (or relative permittivity) of the air gap between the source / drain region and the gate structure is smaller than the dielectric constant of the material of the internal spacer. The smaller dielectric constant of the air gap reduces the capacitance between the source / drain region and the gate structure. The cell capacitance C between the gate structure and the source / drain region Cell The quantity can be expressed as:

[0033]

[0034] Where k represents the dielectric constant (e.g., k value) of the medium between the gate structure and the source / drain region; A represents the surface area of ​​the interface between the gate structure and the source / drain region; and d represents the distance between the gate structure and the source / drain region. Therefore, the cell capacitance C between the gate structure and the source / drain region Cell The capacitance between the gate structure and the source / drain region can be reduced by replacing the dielectric between the gate structure and the source / drain region with an air spacer due to the smaller dielectric constant of the air gap. In addition, the porous interfacial layer that prevents the air gap from filling with the material of the gate structure and the associated gate dielectric layer enables the distance between the gate structure and the source / drain region to be reconstrained so as not to contribute to increased cell capacitance. In this way, the air gap between the gate structure and the source / drain region can enable faster switching times (e.g., between an on state and an off state) for the nanostructure transistor due to the reduced RC time constant for the nanostructure transistor.

[0035] Figures 1A to 1Cis a diagram of an exemplary embodiment 100 of a fin definition process described herein. Exemplary embodiment 100 includes an example of forming a fin structure and associated shallow trench isolation (STI) regions for a semiconductor device 105 described herein. The semiconductor device 105 can be manufactured to include one or more transistors. The one or more transistors can include nanostructured transistors, such as nanowire transistors, nanosheet transistors, full-all-around gate (GAA) transistors, multi-bridge channel transistors, nanoribbon transistors, and / or other types of nanostructured transistors. Exemplary embodiment 100 includes an example of forming a fin structure and associated STI regions for a transistor of the semiconductor device 105.

[0036] Figures 1A to 1C Each shows a perspective view of the semiconductor device 105 and a cross-sectional view along line AA in the perspective view. Figure 1A As shown in , processing of the semiconductor device 105 is performed in conjunction with a semiconductor substrate 110. The semiconductor substrate 110 includes a silicon (Si) substrate, a substrate formed of a material including silicon, a III-V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, a germanium (Ge) substrate, a silicon-germanium (SiGe) substrate, a silicon carbide (SiC) substrate, or another type of semiconductor substrate.

[0037] A layer stack 115 is formed on a semiconductor substrate 110. The layer stack 115 may be referred to as a superlattice. The layer stack 115 includes a plurality of alternating layers arranged in a direction (e.g., z-direction) approximately perpendicular to the semiconductor substrate 110. For example, the layer stack 115 includes vertically alternating layers of a sacrificial nanostructure layer 120 and a nanostructure channel layer 125 on the semiconductor substrate 110. Figure 1A The number of sacrificial nanostructure layers 120 and the number of nanostructure channel layers 125 shown in are examples, and other numbers of sacrificial nanostructure layers 120 and nanostructure channel layers 125 are within the scope of the disclosed embodiments.

[0038] The sacrificial nanostructure layer 120 enables a vertical distance to be defined between adjacent nanostructure channels formed by the nanostructure channel layer 125, and serves as a reserved place layer for a subsequently formed gate structure of a transistor of the semiconductor device 105, the gate structure being formed around the nanostructure channel. The sacrificial nanostructure layer 120 includes a first material composition, and the nanostructure channel layer 125 includes a second material composition. In some embodiments, the first material composition and the second material composition are the same material composition. In some embodiments, the first material composition and the second material composition are different material compositions. As an example, the sacrificial nanostructure layer 120 may include silicon germanium (SiGe), and the nanostructure channel layer 125 may include silicon (Si). This enables selective etching of the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 (e.g., enabling etching of the sacrificial nanostructure layer 120 instead of the nanostructure channel layer 125, enabling etching of the nanostructure channel layer 125 instead of the sacrificial nanostructure layer 120), depending on the type of etchant used.

[0039] One or more types of deposition tools may be used to deposit and / or grow alternating layers of the layer stack 115 to include nanostructures (e.g., nanosheets) on the semiconductor substrate 110. For example, the deposition tool may be used to grow the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 by epitaxial growth, which may include epitaxial techniques such as molecular beam epitaxy (MBE), metal organic chemical vapor deposition (MOCVD) processes, and / or another suitable epitaxial technique. Additionally and / or alternatively, the sacrificial nanostructure layer 120 and / or the nanostructure channel layer 125 may be deposited by chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), and / or another suitable deposition technique.

[0040] One or more masking layers may be formed (e.g., using one or more deposition tools) on the layer stack 115. The masking layers may include a hard mask (HM) layer 130, a capping layer 135, an oxide layer 140, and / or a nitride layer 145. The masking layers may be used to perform a fin patterning operation to form a fin structure in the semiconductor substrate 110.

[0041] like Figure 1BAs shown in , the layer stack 115 and the semiconductor substrate 110 are etched to remove portions of the layer stack 115 and portions of the semiconductor substrate 110. This allows the formation of a fin structure 150 extending above the semiconductor substrate 110. The fin structure 150 may extend in the x-direction in the semiconductor device 105 and may be arranged in the y-direction in the semiconductor device 105. The fin structure 150 includes a portion 155 of the layer stack 115 located above and / or on the fin portion 160 above the semiconductor substrate 110. The fin structure 150 may be formed by patterning one or more masking layers and etching the semiconductor substrate 110 based on a pattern formed in one or more of the masking layers. The one or more masking layers may be patterned using photolithography techniques, including double patterning or multiple patterning techniques. The etching tool may be used to etch the semiconductor substrate 110 based on a pattern using a dry etching technique (e.g., reactive ion etching), a wet etching technique, and / or a combination thereof.

[0042] like Figure 1B As further shown in , some fin structures 150 may be formed to have different widths for different types of nanostructure transistors. As an example, a first subset of fin structures 150a may be formed for p-type nanostructure transistors (e.g., p-type metal oxide semiconductor (PMOS) nanostructure transistors), and a second subset of fin structures 150b may be formed for n-type nanostructure transistors (e.g., n-type metal oxide semiconductor (NMOS) nanostructure transistors). As another example, a first subset of fin structures 150a may be formed for nanostructure transistors configured to operate at a lower voltage, and a second subset of fin structures 150b may be formed for nanostructure transistors configured to operate at a higher voltage.

[0043] like Figure 1C As shown in FIG. 1 , a liner 165 and an STI region 170 are formed between adjacent fin portions 160 of the fin structure 150. The liner 165 and the STI region 170 may each include a dielectric material, such as silicon oxide (SiO x ), silicon nitride (Si x N y ), silicon oxynitride (SiON), fluorine-doped silicate glass (FSG), a low-k dielectric material, and / or another suitable insulating material.

[0044] A deposition tool may be used to conformally deposit the liner (e.g., using ALD or another conformal deposition technique), and a dielectric layer may be deposited on the liner 165 (e.g., using CVD, PVD, ALD, and / or another suitable deposition technique) such that the dielectric layer completely fills the spaces between the fin structures 150 and extends over the tops of the fin structures 150. A planarization tool may then be used to perform a planarization or polishing operation (e.g., a chemical mechanical planarization (CMP) operation) to planarize the dielectric layer such that the top surface of the dielectric layer is approximately coplanar with the top of the nitride layer 145. The nitride layer 145 serves as a CMP stop layer in the planarization operation. An etching tool may then be used to etch the dielectric layer to form the STI region 170 such that the top surface of the STI region 170 is approximately coplanar with or below the bottommost sacrificial nanostructure layer 120.

[0045] As noted above, Figures 1A to 1C Provided as an example. Other examples may be related to Figures 1A to 1C The content described is different.

[0046] Figure 2 2 is a diagram of an exemplary embodiment 200 of a dummy gate formation process described herein. Exemplary embodiment 200 includes an example of forming a dummy gate structure 205 for a nanostructure transistor of semiconductor device 105. In some embodiments, the operations described in conjunction with exemplary embodiment 200 are performed in conjunction with Figures 1A to 1C The described process is then carried out.

[0047] Figure 2 A perspective view of a semiconductor device 105 with a dummy gate structure 205 formed thereon is shown. The dummy gate structure 205 (also referred to as a dummy gate stack or temporary gate structure) is formed over a portion of the fin structure 150 and a portion of the STI region 170. The dummy gate structure 205 extends in the y-direction and is arranged in the x-direction such that the dummy gate structure 205 is approximately perpendicular to the fin structure 150. The dummy gate structure 205 is a sacrificial structure that will be replaced by a replacement gate structure or a replacement gate stack in a subsequent processing stage for the semiconductor device 105. The dummy gate structure 205 can also be used to define a source / drain (S / D) recess, where the source / drain region of the nanostructure transistor is formed in the fin structure 150.

[0048] The dummy gate structure 205 may include a gate electrode layer 210, a hard mask layer 215 above and / or on the gate electrode layer 210, a spacer layer 220 on the opposite side of the gate electrode layer 210, and a gate dielectric layer 225 below the gate electrode layer 210. The gate electrode layer 210 includes polycrystalline silicon (poly silicon or PO) or another material. The hard mask layer 215 includes one or more layers, such as an oxide layer (e.g., a pad oxide layer that may include silicon dioxide (SiO2) or another material) and a nitride layer formed above the oxide layer (e.g., a pad nitride layer that may include silicon nitride such as Si3N4 or another material). The spacer layer 220 includes silicon oxycarbide (SiOC), nitrogen-free SiOC, or another suitable material. The gate dielectric layer 225 may include silicon oxide (e.g., SiO2 such as SiO x ), silicon nitride (e.g., Si such as Si3N4 x N y ), a high dielectric constant (high-k) dielectric material (e.g., a dielectric material having a dielectric constant greater than approximately 3.9), and / or another suitable material.

[0049] The layers of the dummy gate structure 205 may be formed using various semiconductor processing techniques, such as depositing the layers of the dummy gate structure 205 , patterning the layers of the dummy gate structure 205 to define the dummy gate structure 205 , and / or other semiconductor processing techniques.

[0050] Figure 2 Reference cross sections used in subsequent figures described herein are also shown. Cross section AA is located in the yz plane (referred to as the y-cut) across the fin structure 150 in the source / drain region of the semiconductor device 105. Cross section BB is located in the xz plane (referred to as the x-cut) perpendicular to cross section AA, and across the dummy gate structure 205 and along the fin structure 150 below. Cross section CC is located in the xz plane parallel to cross section AA and perpendicular to cross section BB, and along the dummy gate structure 205. For clarity, subsequent figures refer to these reference cross sections. In some figures, for ease of depiction of the figures, some reference numerals of components or parts shown therein may be omitted to avoid obscuring other components or parts.

[0051] As noted above, Figure 2 Provided as an example. Other examples may be related to Figure 2 The content described is different.

[0052] Figure 3 is a diagram of an exemplary embodiment 300 of a source / drain recess formation process described herein. Exemplary embodiment 300 includes an example of forming source / drain recesses 305 for source / drain regions of a nanostructure transistor of semiconductor device 105 . Figure 3 is from Figure 2 The multiple viewing angles shown in FIG. 1 include Figure 2 The perspective of the cross-sectional plane AA in Figure 2 The viewing angle of the cross-sectional plane BB in Figure 2 In some embodiments, the operations described in conjunction with exemplary embodiment 300 are combined with Figures 1A to 2 The described process is then carried out.

[0053] like Figure 3 As shown in the cross-sectional plane AA and the cross-sectional plane BB in FIG. 1 , a source / drain recess 305 is formed through the portion 155 of the fin structure 150 during the etching operation. The source / drain recess 305 is formed on the opposite side of the dummy gate structure 205. The etching operation can be performed using an etching tool and can be referred to as a strained source / drain (SSD) etching operation. In some embodiments, the etching operation includes using a plasma etching technique, a wet chemical etching technique, and / or another type of etching technique.

[0054] The source / drain recesses 305 also extend into portions of the fin portion 160 of the fin structure 150. This results in the formation of a mesa region 310 in the fin structure 150. The sidewalls of the portion of each source / drain recess 305 that is located below the layer stack 115 correspond to the sidewalls of the mesa region 310. The mesa region 310 (also referred to as the pedestal) refers to the region of the fin portion 160 of the fin structure 150 on which a nanostructure channel is defined from the nanostructure channel layer 125. The nanostructure channel 315 extends between adjacent source / drain recesses 305 and is located below the dummy gate structure 205 between the adjacent source / drain recesses 305.

[0055] The nanostructure channel 315 includes a silicon-based nanostructure (e.g., a nanosheet or a nanowire, among other examples) used as a semiconductor channel of a nanostructure transistor of the semiconductor device 105. In some embodiments, the nanostructure channel 315 may include silicon germanium (SiGe) or another silicon-based material. The nanostructure channel 315 is arranged in a direction (e.g., a z-direction) approximately perpendicular to the semiconductor substrate 110. In other words, the nanostructure channel 315 is vertically arranged or stacked on the semiconductor substrate 110.

[0056] As noted above, Figure 3 Provided as an example. Other examples may be related to Figure 3 The content described is different.

[0057] Figure 4A and Figure 4Bis a diagram of an exemplary embodiment 400 of a dummy internal spacer formation process described herein. The exemplary embodiment 400 includes an example of forming a dummy internal spacer between ends of a nanostructure channel 315 exposed in a source / drain recess 305. The dummy internal spacer is formed to enable a buffer region to be formed at the bottom of the source / drain recess 305 before forming an internal spacer (replacing the internal spacer) between ends of the nanostructure channel 315 exposed in the source / drain recess 305. Figure 4A and Figure 4B Each is from Figure 2 The multiple viewing angles shown in FIG. 1 include Figure 2 The perspective of the cross-sectional plane AA in Figure 2 The viewing angle of the section plane BB in Figure 2 In some embodiments, the operations described in conjunction with exemplary embodiment 400 are combined with Figures 1A to 3 The described process is then carried out.

[0058] like Figure 4A As shown in cross-sectional plane BB in FIG. 1 , the ends of the sacrificial nanostructure layer 120 exposed in the source / drain recesses 305 are laterally etched (e.g., in the y direction approximately parallel to the length of the sacrificial nanostructure layer 120) during the etching operation, thereby forming a cavity 405 between the ends of the nanostructure channels 120 exposed in the source / drain recesses 305. In particular, the etching tool can be used to laterally etch the ends of the sacrificial nanostructure layer 120 under the dummy gate structure 205 through the source / drain recesses 305 to form the cavity 405 between the ends of the nanostructure channels 315. The cavity 405 can be formed in an approximately curved shape, an approximately concave shape, an approximately triangular shape, an approximately square shape, or in another shape.

[0059] like Figure 4B As shown in cross-sectional plane BB in FIG. 1 , a dummy internal spacer 410 is formed in cavity 405 between ends of vertically adjacent nanostructure channels 315 in source / drain recesses 305 . Dummy internal spacer 410 is included to protect cavity 405 during formation of a buffer region at the bottom of source / drain recesses 305 . FIG. 21A to FIG. 21E An alternative embodiment is shown in which the dummy inner spacer 410 is omitted and the inner spacer is formed directly in the cavity 405. In some embodiments, the dummy inner spacer 410 includes silicon nitride (Si x N y ), silicon carbon nitride (SiCN), silicon oxycarbon nitride (SiOCN), and / or another dielectric material. In some embodiments, the dummy inner spacer 410 includes an oxide material, such as silicon oxide (SiO x), silicon oxynitride (SiON) and / or silicon oxycarbide (SiOC), among other examples. In these embodiments, the dummy inner spacer 410 may be referred to as a disposable oxide interposer (DOI).

[0060] In order to form the pseudo internal spacer 410, a deposition tool can be used to deposit a dielectric material layer in the cavity 405 and along the sidewalls and bottom surface of the source / drain groove. The dielectric material layer can be deposited using a CVD technique, a PVD technique, and an ALD technique and / or another deposition technique. Subsequently, an etching tool is used to remove excess material of the dielectric material layer from the source / drain groove so that the remaining portion corresponds to the pseudo internal spacer 410 in the cavity 405. In some embodiments, the etching operation can cause the surface of the pseudo internal spacer 410 facing the source / drain groove 305 to be curved or concave. In some embodiments, the surface of the pseudo internal spacer 410 facing the source / drain groove 305 is approximately flat, so that the surface of the pseudo internal spacer 410 and the surface of the end of the nanostructure channel 315 are approximately flat and flush.

[0061] As noted above, Figure 4A and Figure 4B Provided as an example. Other examples may be related to Figure 4A and Figure 4B The content described is different.

[0062] FIG. 5A to FIG. 5D is a diagram of an exemplary embodiment 500 of an internal spacer formation process described herein. The exemplary embodiment 500 includes an example of replacing the dummy internal spacers 410 with internal spacers. FIG. 5A to FIG. 5D Each is from Figure 2 The multiple viewing angles shown in FIG. 1 include Figure 2 The perspective of the cross-sectional plane AA in Figure 2 The viewing angle of the section plane BB in Figure 2 In some embodiments, the operations described in conjunction with exemplary embodiment 500 are combined with Figures 1A to 4B The described process is then carried out.

[0063] like Figure 5A As shown in cross-sectional plane AA and cross-sectional plane BB in FIG. 3 , a deposition tool may be used to deposit a buffer region 505 at the bottom of the source / drain recess 305. The dummy inner spacer 410 may protect the cavity 405 during the formation of the buffer region 505. In particular, the dummy inner spacer 410 prevents the material of the buffer region 505 from being deposited in the cavity 405.

[0064] The buffer region 505 may include silicon germanium (SiGe), undoped silicon (Si), silicon doped with boron (Si:B), or another dopant and / or another material. In embodiments where the buffer layer 406 includes silicon germanium, the concentration of germanium (Ge) in the buffer layer 406 may be in the range of about 1% germanium to about 10% germanium. However, other values ​​for the germanium concentration are within the scope of the disclosed embodiments.

[0065] The buffer region 505 may be included between the source / drain region and the mesa region 310 adjacent to the buffer region 505 to reduce, minimize and / or prevent dopant migration and / or current leakage from the source / drain region to the adjacent mesa region 310, which may otherwise cause a short channel effect in the semiconductor device 105. Therefore, the buffer region 505 may improve the performance of the semiconductor device 105 and / or improve the yield of the semiconductor device 105.

[0066] like Figure 5A , the buffer region 505 can be formed such that the top surface of the buffer region 505 is substantially flat and approximately coplanar with the top surface of the adjacent mesa region 310. In some embodiments, the buffer region 505 is formed such that the top surface of the buffer region 505 is curved and recessed below the top surface of the adjacent mesa region 310. In these embodiments, the buffer region 505 has a concave top surface. In some embodiments, the buffer region 505 is formed such that the top surface of the buffer region 505 is convex and extends above the top surface of the adjacent mesa region 310.

[0067] like Figure 5B As shown in cross-sectional plane BB in FIG. 1 , the dummy internal spacer 410 is laterally etched (e.g., in the y direction approximately parallel to the length of the sacrificial nanostructure layer 120) and removed from the cavity 405 in the etching operation, thereby exposing the cavity 405 after forming the buffer region 505. In particular, the etching tool can be used to laterally etch the dummy internal spacer 410 through the source / drain recesses 305 to remove the dummy internal spacer 410.

[0068] like Figure 5C As shown in cross-sectional plane BB in FIG. 4 , a deposition tool may be used to deposit an internal spacer layer 510 in cavity 405 and along the sidewalls and bottom surface of source / drain recesses 305. The dielectric material layer may be deposited using CVD, PVD and ALD techniques, epitaxy and / or another deposition technique.

[0069] like Figure 5DAs shown in cross-sectional plane BB in FIG. 4 , an internal spacer 515 is formed in the cavity 405 between the ends of vertically adjacent nanostructure channels 315 in the source / drain recess 305. The internal spacer 515 is included to protect the source / drain region (which is subsequently formed in the source / drain recess 305) from etching during a nanosheet release operation to remove the sacrificial nanostructure layer 120 between the nanostructure channels 315. An etching tool is used to remove excess material of the internal spacer layer 510 from the source / drain recess 305 (e.g., can be used to trim the internal spacer layer 510 using a dry etching technique, a wet etching technique), so that the remaining portion corresponds to the internal spacer 515 in the cavity 405. In some embodiments, the etching operation can cause the surface of the internal spacer 515 facing the source / drain recess 305 to bend or recess. In some embodiments, the surface of the inner spacer 515 facing the source / drain recess 305 is approximately flat, so that the surface of the inner spacer 515 and the surface of the end of the nanostructure channel 315 are approximately flat and flush.

[0070] like Figure 5D As further shown in FIG. 1 , the internal spacer 515 formed in the source / drain recess 305 may include an internal spacer 515a (e.g., a top internal spacer) formed in the cavity 405 above the bottommost sacrificial nanostructure layer 120 and an internal spacer 515b formed in the cavity 405 in the bottommost sacrificial nanostructure layer 120. The internal spacer 515b (e.g., a bottom internal spacer) may extend along the bottom surface of the source / drain recess 305, and the bottom surface of the source / drain recess 305 corresponds to the top surface of the buffer region 505 in the source / drain recess 305. The portion of the internal spacer 515b located between the cavities 405 in the bottommost sacrificial nanostructure layer 120 may have a curved or arcuate top surface. In particular, the portion of the internal spacer 515b located between the cavities 405 in the bottommost sacrificial nanostructure layer 120 may have a recessed top surface or a concave top surface.

[0071] The internal spacers 515 may include the same material (or the same material composition) as the sacrificial nanostructure layer 120. For example, both the internal spacers 515 and the sacrificial nanostructure layer 120 may include silicon germanium (SiGe). This enables the internal spacers 515 and the sacrificial nanostructure layer 120 to be removed after the source / drain regions are formed, and provides etching selectivity relative to the source / drain regions (which may be formed of a different material and / or a different material composition than the internal spacers 515 and the sacrificial nanostructure layer 120).

[0072] As noted above, FIG. 5A to FIG. 5D Provided as an example. Other examples may be related to FIG. 5A to FIG. 5D The content described is different.

[0073] Figure 6 is a diagram of an exemplary embodiment 600 of a source / drain region formation process and an interlayer dielectric (ILD) formation process described herein. Exemplary embodiment 600 includes an example of forming source / drain regions of a nanostructure transistor of semiconductor device 105 and forming an ILD layer on the source / drain regions. Figure 6 is from Figure 2 The multiple viewing angles shown in FIG. 1 include Figure 2 The perspective of the cross-sectional plane AA in Figure 2 The viewing angle of the section plane BB in Figure 2 In some embodiments, the operations described in conjunction with exemplary embodiment 600 are combined with FIG. 1A to FIG. 5D The described process is then carried out.

[0074] like Figure 6 As shown in , source / drain regions 605 may be formed over buffer regions 505 in source / drain recesses 305. Source / drain regions 605 may refer to source or drain, individually or collectively depending on the context. Source / drain regions 605 may be included on opposite sides of dummy gate structure 205, so that nanostructure channel 315 below dummy gate structure 205 extends between source / drain regions 605 and is electrically coupled to source / drain regions 605. Source / drain regions 605 may have a bottom surface having a curved cross-sectional profile. Source / drain regions 605 each include silicon (Si) and / or silicon germanium (SiGe) with one or more dopants, such as p-type material (e.g., boron (B) or germanium (Ge), and other examples), n-type material (e.g., phosphorus (P) or arsenic (As), and other examples) and / or another type of dopant. Thus, the semiconductor device 105 may include: a p-type metal oxide semiconductor (PMOS) nanostructure transistor including a p-type source / drain region 605, an n-type metal oxide semiconductor (NMOS) nanostructure transistor including an n-type source / drain region 605, and / or other types of nanostructure transistors. In some embodiments, the dopant concentration in the source / drain region may be between about 1×10 17 Ions per cubic centimeter (ions / cm 3 ) to about 5×10 22 Ions / cm 3 However, other values ​​for the range are within the scope of the embodiments of the present disclosure.

[0075] In some embodiments, the sidewalls of the source / drain region 605 can be in physical contact with the internal spacer 515a, and the bottom surface of the source / drain region 605 can be in physical contact with the internal spacer 515b. In some embodiments, multiple internal spacers 515b are formed (e.g., multiple bottom-most internal spacers 515) so that the top surface of the associated buffer region 505 is exposed in the source / drain recess 305 (e.g., so that the top surface of the buffer region 505 is not covered by the internal spacer 515b). In these embodiments, the source / drain region 605 can be formed in the source / drain recess 305 so that the bottom surface of the source / drain region is in physical contact with the top surface of the buffer region 505, and the internal spacer 515b is in physical contact with the sidewalls of the source / drain region 605 in a manner similar to the internal spacer 515a.

[0076] One or more layers of the source / drain region 605 may be epitaxially grown, deposited (e.g., using CVD, PVD, ALD), and / or may be formed using one or more other deposition techniques. For example, a deposition tool may epitaxially grow a first layer (referred to as L1) of the source / drain region 605 over an associated buffer region 505 (which may be referred to as L0), and may epitaxially grow a second layer (referred to as L2, L2-1, and / or L2-2) of the source / drain region 605 over the first layer. The first layer may include lightly doped silicon (e.g., doped with boron (B), phosphorus (P), and / or another dopant), and may be included as a shielding layer to reduce short channel effects in the semiconductor device 105 and reduce dopants that squeeze or migrate into the nanostructure channel 315. The second layer may include highly doped silicon or highly doped silicon germanium. The second layer may be included to provide compressive stress in the source / drain region 605 to reduce the loss of boron or phosphorus.

[0077] like Figure 6 As further shown in FIG. 6 , a contact etch stop layer (CESL) 610 is conformally deposited (e.g., by a deposition tool) over the source / drain regions 605. A dielectric layer 615 is then formed on the CESL 610 over the source / drain regions 605. The CESL 610 may provide a mechanism to stop the etching process when forming contacts or vias for the source / drain regions 605. The CESL may be formed of a dielectric material having a different etch selectivity relative to adjacent layers or components. The CESL 610 may include or may be a nitrogen-containing material, a silicon-containing material, and / or a carbon-containing material. Additionally, the CESL 610 may include or may be silicon nitride (SiN). x N y), silicon carbonitride (SiCN), carbon nitride (CN), silicon oxynitride (SiON), silicon oxycarbide (SiCO), or combinations thereof, among other examples. CESL 610 may be deposited using a deposition process, such as ALD, CVD, or another deposition technique.

[0078] A dielectric layer 615 fills in the region between the dummy gate structures 205. The dielectric layer 615 is formed to reduce the possibility of damage to the source / drain region 605 and / or prevent damage to the source / drain region 605 during a replacement gate process that replaces the dummy gate structure 205. The dielectric layer 615 may be referred to as an ILD zero (ILD 0) layer or another ILD layer.

[0079] As noted above, Figure 6 Provided as an example. Other examples may be related to Figure 6 The content described is different.

[0080] 7A to 7D is a diagram of an exemplary embodiment 700 of a replacement gate (RPG) process described herein. Exemplary embodiment 700 includes an example of a replacement gate process for replacing dummy gate structure 205 with a high-k / metal gate structure (eg, replacement gate structure) for a nanostructure transistor of semiconductor device 105. 7A to 7D Each is from Figure 2 The multiple viewing angles shown in FIG. 1 include Figure 2 The perspective of the cross-sectional plane AA in Figure 2 The viewing angle of the section plane BB in Figure 2 In some embodiments, the operations described in conjunction with exemplary embodiment 700 are combined with Figures 1A to 6 The described operations are then performed.

[0081] like Fig. 7A As shown in cross-sectional plane BB and cross-sectional plane CC in FIG. 1 , the replacement gate process includes a dummy gate removal operation. The dummy gate removal operation includes removing the dummy gate structure 205 from the semiconductor device 105. The removal of the dummy gate structure 205 leaves an opening (or recess) between the dielectric layer 615 and provides access to the sacrificial nanostructure layer 120 below. The dummy gate structure 205 can be removed in one or more etching operations. Such etching operations can include plasma etching techniques, wet chemical etching techniques, and / or another type of etching technique.

[0082] like Fig. 7AAs further shown in , the replacement gate process includes a nanostructure release operation (e.g., a SiGe release operation). The nanostructure release operation is performed to remove the sacrificial nanostructure layer 120 (e.g., a silicon germanium layer). This creates an opening 705 between the nanostructure channels 315 (e.g., the area around the nanostructure channels 315). The internal spacers 515a and 515b are exposed through the opening 705. The sacrificial nanostructure layer 120 can be removed through the space previously occupied by the dummy gate structure 205. The nanostructure release operation can include using an etching tool to perform an etching operation to remove the sacrificial nanostructure layer 120 based on the difference in etching selectivity between the material of the sacrificial nanostructure layer 120 and the material of the nanostructure channels 315. The internal spacers 515a and 515b can be used as an etch stop layer in the etching operation to protect the source / drain region 605 from etching.

[0083] like Figure 7B As shown in the cross-sectional plane BB and the cross-sectional plane CC in FIG. 1 , an interface layer 710 may be formed on the surface of the nanostructure channel 315 exposed in the opening 705. The interface layer 710 may include an oxide layer, such as silicon oxide (SiO x , such as SiO2), and other examples. Figure 7B As further shown in FIG. 7 , a porous interface layer 715 may be formed on the ends of the internal spacers 515a and 515b exposed by the opening 705. The porous interface layer 715 may include the same oxide material as the interface layer 710, except that pores (or openings or holes) are formed through the porous interface layer 715. This enables an etchant to be provided to the internal spacers 515a and 515b through the pores in the porous interface layer 715, so that the internal spacers 515a and 515b can be removed through the pores in the porous interface layer 715.

[0084] Forming the interface layer 710 may include providing an oxidant through the opening 705 to oxidize the exposed surface of the nanostructure channel 315. The oxidant may include an acid, ammonia (NH3), hydrogen peroxide (H2O2), and / or another suitable oxidant. The oxidant reacts with the exposed surface of the nanostructure channel 315 to form an oxide of the material of the nanostructure channel 315.

[0085] Similarly, forming the porous interface layer 715 on the ends of the inner spacers 515a and 515b may include oxidizing the ends of the inner spacers 515a and 515b to form an oxide layer on the ends of the inner spacers 515a and 515b. In addition, in order to form pores in the oxide layer, electrochemical etching of the oxide layer may be performed to remove material from the oxide layer to form the porous interface layer 715.

[0086] In some embodiments, the thickness of the porous interface layer 715 is greater than 0 nanometers and less than or approximately equal to 1 nanometer. If the porous interface layer 715 is not thick enough, the porous interface layer 715 may be damaged and fail, so that a high-K dielectric liner is formed directly on the adjacent source / drain region 605 (causing a gate to source / drain short circuit). If the porous interface layer 715 is too thick, there is not enough spacing in the opening 705 to be used to form a gate structure in the opening 705, resulting in increased gate resistance. If the thickness of the porous interface layer 715 is greater than 0 nanometers and less than or approximately equal to 1 nanometer, a sufficiently low gate resistance can be achieved while reducing the possibility of a gate to source / drain short circuit. However, other values ​​for the range are within the scope of the presently disclosed embodiments.

[0087] like Figure 7C As shown in cross-sectional plane BB in FIG. 7 , the internal spacers 515 a and 515 b are removed from the semiconductor device 105 through the opening 705. In particular, the internal spacers 515 a and 515 b are removed through the opening 705 by removing material of the internal spacers 515 a and 515 b through the pores in the porous interface layer 715. The pores in the porous interface layer 715 enable an etchant to be provided to the internal spacers 515 a and 515 b through the pores in the porous interface layer 715, so that the etchant can be used to remove material from the internal spacers 515 a and 515 b through the pores in the porous interface layer 715.

[0088] Removing the inner spacer 515a forms an air gap 720a in the space previously occupied by the inner spacer 515a. For example, the air gap 720a may be included between the sidewalls of the source / drain region 605 and the porous interface layer 715 formed on the inner spacer 515a.

[0089] Similarly, the removal of the internal spacer 515b forms an air gap 720b in the space previously occupied by the internal spacer 515b. For example, the air gap 720b can be included between the bottom surface of the source / drain region 605 and the buffer region 505 below the bottom surface of the source / drain region 605. In some embodiments, a single air gap 720b spans the entire bottom surface of the source / drain region 605 and is located around the end of the associated nanostructure channel 315. In some embodiments, the bottom surface of the source / drain region 605 is in contact with the underlying buffer region 505, and the air gap 720b is included on the opposite side of the source / drain region 605, similar to the air gap 720a.

[0090] The thickness of the air gap 720b (corresponding to the distance between the bottom surface of the source / drain region 605 and the top surface of the buffer region 505) can be included in the range of about 0.5 nanometers to about 10 nanometers to enable low parasitic capacitance between the buffer region 505 and the gate structure to be formed in the semiconductor device 105. However, other values ​​for the range are within the scope of the embodiments of the present disclosure. In some embodiments, the air gap 720b protrudes into the bottom surface of the source / drain region 605. In some embodiments, the air gap 720b protrudes into the top surface of the buffer region 505. Alternatively, if the bottom surface of the source / drain region 605 and the top surface of the buffer region 505 are substantially flat, the air gap 720b is approximately rectangular in shape.

[0091] In some embodiments, when the internal spacers 515a and 515b are removed, over-etching may occur. In these embodiments, the air gap 720a and / or 720b may protrude into the adjacent source / drain region 605, generating a scalloped sidewall S1 for the source / drain region 605. In some embodiments, the depth D3 of the scallop S1 in the sidewall may be included in the range of about 1 nanometer to about 10 nanometers. However, other values ​​for the range are within the scope of the disclosed embodiments. In some embodiments, if over-etching occurs in the bottom surface of the source / drain region 605 when the associated internal spacer 515b is removed, the air gap 720b protrudes into the bottom surface of the source / drain region 605.

[0092] like Figure 7C As further shown in FIG. 1 , the air gap 720 (eg, air gap 720a, air gap 720b) ​​may have one or more dimensions, such as Figure 7C The horizontal width (e.g., x-direction width) of dimension D1 is represented in Figure 7C Dimension D1 and dimension D2 are each included in a range of about 1 nanometer to about 15 nanometers to enable sufficiently low parasitic capacitance between the associated source / drain regions 605 and the gate structure to be formed in the opening 705. However, other values ​​for the ranges are within the scope of the disclosed embodiments.

[0093] like Fig.7DAs shown in cross-sectional plane BB and cross-sectional plane CC in , the replacement gate operation includes forming a gate structure (e.g., a replacement gate structure) 725 in the opening 705 between the source / drain regions 605. In particular, the gate structure 725 fills the area between and around the nanostructure channels 315 previously occupied by the sacrificial nanostructure layer 120, such that the gate structure 725 completely wraps around the nanostructure channels 315 and surrounds the nanostructure channels 315. This increases control of the nanostructure channels 315, increases the drive current of the nanostructure transistors for the semiconductor device 105, and / or reduces the short channel effect (SCE) of the nanostructure transistors for the semiconductor device 105. The gate structure 725 may also be filled in the gaps previously occupied by the dummy gate structures 205. Portions of the gate structure 725 are formed between pairs of nanostructure channels 315 in an alternating vertical arrangement. In other words, the semiconductor device 105 includes one or more vertical stacks of alternating nanostructure channels 315 and portions of the gate structure 725, such as Fig.7D as shown in .

[0094] like Fig.7D As further shown in , the air gaps 720a and 720b are located between the gate structure 725 and the source / drain regions 605 located on opposite sides of the gate structure 725. The gate structure 725 may include a metal gate electrode 730 and a high-k dielectric liner 735. The metal gate electrode 730 may include one or more metal materials, such as tungsten (W), cobalt (Co), ruthenium (Ru) and / or titanium (Ti), as well as other examples. Additionally and / or optionally, the gate structure 725 may include one or more work function metal layers for adjusting the work function of the metal gate electrode 730.

[0095] The high-k dielectric liner 735 is conformally deposited on the interface layer 710 around the nanostructure channel 315, and the metal gate electrode 730 is formed on the high-k dielectric liner 735. The porous interface layer 715 prevents, minimizes and / or reduces the possibility of the material of the high-k dielectric liner 735 being deposited into the air gaps 720a and 720b. The high-k dielectric liners 735 each include one or more high-k dielectric materials, such as silicon nitride (SiN). x N y ), hafnium oxide (HfO x ), lanthanum oxide (LaO x ) and / or another suitable high-k dielectric material.

[0096] As noted above, 7A to 7D Provided as an example. Other examples may be related to 7A to 7D The content described is different.

[0097] FIG. 8A to FIG. 8Dis a diagram of an exemplary embodiment 800 for forming a semiconductor device 105 described herein. Exemplary embodiment 800 includes an alternative example in which recesses are formed in the ends of nanostructure channels 315 by source / drain recesses 305 prior to forming source / drain regions 605 . FIG. 8A to FIG. 8D Each is from Figure 2 The multiple viewing angles shown in FIG. 1 include Figure 2 The perspective of the cross-sectional plane AA in Figure 2 The viewing angle of the section plane BB in Figure 2 The perspective of the section plane CC in .

[0098] like Fig. 8A As shown in the cross-sectional planes AA, BB, and CC in FIG. 8 , the operations described in conjunction with the exemplary embodiment 800 are combined with FIG. 1A to FIG. 5D The described operations are then performed.

[0099] like Figure 8B As shown in cross-sectional plane BB in FIG. 8 , a cavity 805 is formed in the end of the nanostructure channel 315 exposed by the source / drain recess 305a in the semiconductor device 105. The cavity in the end of the nanostructure channel 315 exposed by the source / drain recess 305b in the semiconductor device 105 may be omitted. The source / drain recess 305a may include a source / drain recess formed for a p-type source / drain region, and the source / drain recess 305b may be formed for an n-type source / drain region.

[0100] The etching tool can be used to laterally etch the ends of the nanostructure channel 315 in the source / drain recess 305a to form the cavity 805. For example, the etching tool can be used to laterally etch the ends of the nanostructure channel 315 in the source / drain recess 305a using a wet etching technique, a dry etching technique, and / or another suitable etching technique. The cavity 805 can be located between vertically adjacent inner spacers 515a and / or between an inner spacer 515a and a vertically adjacent inner spacer 515b.

[0101] like Figure 8B As shown in the cross-sectional plane BB, it can be combined with Figure 6A similar manner is described for forming source / drain regions, CESL 610, and dielectric layer 615 in semiconductor device 105, except that p-type source / drain regions 605a are formed in source / drain recesses 305a, and n-type source / drain regions 605b are formed in source / drain recesses 305b. P-type source / drain regions 605a may be doped with one or more p-type dopants, such as boron (B) and / or gallium (Ga), among other examples. N-type source / drain regions 605b may be doped with one or more n-type dopants, such as phosphorus (P) and / or arsenic (As), among other examples.

[0102] like Figure 8C As further shown in FIG. 1 , a liner 810 may be included on the side of the p-type source / drain region 605a between the p-type source / drain region 605a and the nanostructure channel 315 and between the p-type source / drain region 605a and the inner spacers 515a and 515b. The liner 810 may be included around the p-type source / drain region 605a to prevent (or minimize) etching into the p-type source / drain region 605a when the inner spacers 515a and 515b are removed to form the air gaps 720a and 720b. The liner 810 may be conformally deposited (e.g., by ALD or CVD, among other examples) so that the liner 810 conforms to the contour and profile of the source / drain recess 305a. In particular, liner 810 conforms to the shape of cavity 805 such that liner 810 extends along portions of the top and bottom of inner spacers 515a and 515b that are located in extension 815. P-type source / drain region 605a also extends into extension 815.

[0103] The pad 810 may include a semiconductor pad (e.g., a silicon (Si) pad and / or another type of pad including one or more semiconductor materials). In some embodiments, the pad 810 includes an undoped semiconductor material (e.g., undoped silicon or undoped silicon germanium (SiGe)). In some embodiments, the pad 810 includes a semiconductor material (e.g., silicon or silicon germanium (SiGe)) doped with one or more types of dopants. For example, the pad 810 may be doped with one or more p-type dopants such as boron (B) and / or gallium (Ga) to reduce the resistance of the pad 810, as well as other examples. In some embodiments, the dopant concentration in the pad 810 may include about 1×10 17 Ions per cubic centimeter (ions / cm 3 ) to about 5×10 22 Ions / cm 3 However, other values ​​for the range are within the scope of the embodiments of the present disclosure.

[0104] In some embodiments, the thickness of the liner 810 is included in the range of about 0.5 nanometers to about 10 nanometers. If the thickness of the liner 810 is less than about 0.5 nanometers, the thickness of the liner 810 may not be enough to prevent etching into the p-type source / drain region 605a. If the thickness of the liner 810 is greater than about 10 nanometers, the liner 810 reduces the size of the p-type source / drain region 605a due to the small spacing in the source / drain groove 305a for the p-type source / drain region 605a. This may produce an increased contact resistance for the p-type source / drain region 605a. If the thickness of the liner 810 is included in the range of about 0.5 nanometers to about 10 nanometers, the liner 810 can prevent the p-type source / drain region 605a from being affected by etching when enabling a sufficiently low contact resistance for the p-type source / drain region 605a. However, other values ​​and ranges for the thickness of the liner 810 are within the scope of the disclosed embodiments.

[0105] like Fig.8D As shown in the cross-sectional plane BB, it can be implemented as combined 7A to 7D Similar operations as described are performed to form air gaps 720a and 720b and gate structure 725. The pad 810 and p-type source / drain region 605a in the extension portion 815 are included on the top and bottom sides of the air gap 720a and on the top side of the air gap 720b. In addition, the p-type source / drain region 605a and / or the n-type source / drain region 605b have a rounded bottom surface. In an embodiment where the p-type source / drain region 605a has a rounded bottom surface, the pad 810 can conform to the rounded bottom surface of the p-type source / drain region 605a. The pad 810 is spaced apart from the buffer region 505 below by the air gap 720b.

[0106] As noted above, FIG. 8A to FIG. 8D Provided as an example. Other examples may be related to FIG. 8A to FIG. 8D The content described is different.

[0107] Fig. 9 is a diagram of an exemplary embodiment 900 of a semiconductor device 105 described herein. The exemplary embodiment 900 of the semiconductor device 105 is similar to Fig.8D , except that the top surface of the buffer region 505 below the p-type source / drain region 605a and / or below the n-type source / drain region 605b is curved or arc-shaped, so that the top surface of the buffer region 505 below the p-type source / drain region 605a and / or below the n-type source / drain region 605b is recessed below the top surface of the adjacent mesa region 310.

[0108] As noted above, Fig. 9 Provided as an example. Other examples may be related to Fig. 9 The content described is different.

[0109] Fig.10 is a diagram of an exemplary embodiment 1000 of a semiconductor device 105 described herein. The exemplary embodiment 1000 of the semiconductor device 105 is similar to Fig. 9 , except that the liner 810 is in physical contact with the curved or arcuate top surface of the underlying buffer region 505, and the bottom surface of the n-type source / drain region 605b is in physical contact with the curved or arcuate top surface of the underlying buffer region 505. Therefore, the air gap 720b is located on the opposite side of the p-type source / drain region 605a and is not located between the p-type source / drain region 605a and the underlying buffer region 505. In addition, the air gap 720b is located on the opposite side of the n-type source / drain region 605b and is not located between the n-type source / drain region 605b and the underlying buffer region 505.

[0110] As noted above, Fig.10 Provided as an example. Other examples may be related to Fig.10 The content described is different.

[0111] Fig.11 is a diagram of an exemplary embodiment 1100 of a semiconductor device 105 described herein. The exemplary embodiment 1100 of the semiconductor device 105 is similar to Fig.10 , except that the bottom surface of the p-type source / drain region 605a and the top surface of the underlying buffer region 505 are substantially flat. Additionally and / or alternatively, the bottom surface of the n-type source / drain region 605b and the top surface of the underlying buffer region 505 are substantially flat. The top surface of the buffer region 505 below the p-type source / drain region 605a and / or below the n-type source / drain region 605b can be approximately coplanar with the top surface of the adjacent mesa region 310.

[0112] As noted above, Fig.11 Provided as an example. Other examples may be related to Fig.11 The content described is different.

[0113] Fig.12 is a diagram of an exemplary embodiment 1200 of a semiconductor device 105 described herein. The exemplary embodiment 1200 of the semiconductor device 105 is similar to Fig.8D , except that the extension 815 is omitted from the liner 810 and the p-type source / drain region 605a. Instead, the sidewalls of the p-type source / drain region 605a (and the liner 810 on the sidewalls) extend between the top and bottom of the p-type source / drain region 605a in an approximately straight line.

[0114] As noted above, Fig.12 Provided as an example. Other examples may be related to Fig.12 The content described is different.

[0115] Fig.13 is a diagram of an exemplary embodiment 1300 of a semiconductor device 105 described herein. The exemplary embodiment 1300 of the semiconductor device 105 is similar to Fig.12 , except that the top surface of the buffer region 505 below the p-type source / drain region 605a and / or below the n-type source / drain region 605b is curved or arc-shaped, so that the top surface of the buffer region 505 below the p-type source / drain region 605a and / or below the n-type source / drain region 605b is recessed below the top surface of the adjacent mesa region 310.

[0116] As noted above, Fig.13 Provided as an example. Other examples may be related to Fig.13 The content described is different.

[0117] Fig.14 is a diagram of an exemplary embodiment 1400 of a semiconductor device 105 described herein. The exemplary embodiment 1400 of the semiconductor device 105 is similar to Fig.13 , except that the liner 810 is in physical contact with the curved or arcuate top surface of the underlying buffer region 505, and the bottom surface of the n-type source / drain region 605b is in physical contact with the curved or arcuate top surface of the underlying buffer region 505. Therefore, the air gap 720b is located on the opposite side of the p-type source / drain region 605a and is not located between the p-type source / drain region 605a and the underlying buffer region 505. In addition, the air gap 720b is located on the opposite side of the n-type source / drain region 605b and is not located between the n-type source / drain region 605b and the underlying buffer region 505.

[0118] As noted above, Fig.14 Provided as an example. Other examples may be related to Fig.14 The content described is different.

[0119] Fig.15 is a diagram of an exemplary embodiment 1500 of a semiconductor device 105 described herein. The exemplary embodiment 1500 of the semiconductor device 105 is similar to Fig.14, except that the bottom surface of the p-type source / drain region 605a and the top surface of the underlying buffer region 505 are substantially flat. Additionally and / or alternatively, the bottom surface of the n-type source / drain region 605b and the top surface of the underlying buffer region 505 are substantially flat. The top surface of the buffer region 505 below the p-type source / drain region 605a and / or below the n-type source / drain region 605b can be approximately coplanar with the top surface of the adjacent mesa region 310.

[0120] As noted above, Fig.15 Provided as an example. Other examples may be related to Fig.15 The content described is different.

[0121] Fig.16 is a diagram of an exemplary embodiment 1600 of a semiconductor device 105 described herein. The exemplary embodiment 1600 of the semiconductor device 105 is similar to Fig.12 , except that the side of the p-type source / drain region 605a includes a convex protrusion 1605 that extends laterally outward from the sidewall of the p-type source / drain region 605a and enters into the portion of the air gap 720a and / or 720b. The liner 810 can conform to the shape of the side of the p-type source / drain region 605a and can similarly have a convex protrusion 1605. Additionally and / or alternatively, the side of the n-type source / drain region 605b includes a convex protrusion 1610 that extends laterally outward from the sidewall of the n-type source / drain region 605b and enters into the portion of the air gap 720a and / or 720b.

[0122] The convex protrusions 1605 and 1610 may be referred to as depressions of the air gaps 720a and / or 720b. The convex protrusions 1605 and 1610 may be generated due to the formation of the internal spacers 515a and / or 515b. In particular, when etching or trimming the internal spacer layer 510 to form the internal spacers 515a and / or 515b, the convex protrusions 1605 and 1610 may be generated due to depressions occurring in the surface of the internal spacers 515a and / or 515b. The depressions may occur due to over-etching of the internal spacers 515a and / or 515b, and the air gaps 720a and / or 720b may conform to the shape of the interval previously occupied by the internal spacers 515a and / or 515b.

[0123] As noted above, Fig.16 Provided as an example. Other examples may be related to Fig.16 The content described is different.

[0124] Fig.17 is a diagram of an exemplary embodiment 1700 of a semiconductor device 105 described herein. The exemplary embodiment 1700 of the semiconductor device 105 is similar to Fig.16 , except that the top surface of the buffer region 505 below the p-type source / drain region 605a and / or below the n-type source / drain region 605b is curved or arc-shaped, so that the top surface of the buffer region 505 below the p-type source / drain region 605a and / or below the n-type source / drain region 605b is recessed below the top surface of the adjacent mesa region 310.

[0125] As noted above, Fig.17 Provided as an example. Other examples may be related to Fig.17 The content described is different.

[0126] Fig.18 is a diagram of an exemplary embodiment 1800 of a semiconductor device 105 described herein. The exemplary embodiment 1800 of the semiconductor device 105 is similar to Fig.17 , except that the liner 810 is in physical contact with the curved or arcuate top surface of the underlying buffer region 505, and the bottom surface of the n-type source / drain region 605b is in physical contact with the curved or arcuate top surface of the underlying buffer region 505. Therefore, the air gap 720b is located on the opposite side of the p-type source / drain region 605a and is not located between the p-type source / drain region 605a and the underlying buffer region 505. In addition, the air gap 720b is located on the opposite side of the n-type source / drain region 605b and is not located between the n-type source / drain region 605b and the underlying buffer region 505.

[0127] As noted above, Fig.18 Provided as an example. Other examples may be related to Fig.18 The content described is different.

[0128] Fig.19 is a diagram of an exemplary embodiment 1900 of a semiconductor device 105 described herein. The exemplary embodiment 1900 of the semiconductor device 105 is similar to Fig.18 , except that the bottom surface of the p-type source / drain region 605a and the top surface of the underlying buffer region 505 are substantially flat. Additionally and / or alternatively, the bottom surface of the n-type source / drain region 605b and the top surface of the underlying buffer region 505 are substantially flat. The top surface of the buffer region 505 below the p-type source / drain region 605a and / or below the n-type source / drain region 605b can be approximately coplanar with the top surface of the adjacent mesa region 310.

[0129] As noted above, Fig.19 Provided as an example. Other examples may be related to Fig.19 The content described is different.

[0130] Fig. 20 is a flow chart of an exemplary process 2000 associated with forming a semiconductor device described herein. In some embodiments, Fig. 20 One or more process blocks of the process are performed using one or more semiconductor processing tools, such as a deposition tool, an exposure tool, a development tool, an etching tool, a planarization tool, an ion implantation tool, and / or another type of semiconductor processing tool.

[0131] like Fig. 20 As shown in , process 2000 may include forming a layer stack including a plurality of nanostructure channel layers and a plurality of sacrificial layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device (block 2010). For example, one or more semiconductor processing tools may be used to form layer stack 115 including a plurality of nanostructure channel layers 125 and a plurality of sacrificial nanostructure layers 120 arranged in a direction approximately perpendicular to a semiconductor substrate 110 of a semiconductor device 105 (z direction), as described herein.

[0132] like Fig. 20 As further shown in FIG. 2 , process 2000 may include forming source / drain recesses adjacent to the layer stack (block 2020). For example, one or more semiconductor processing tools may be used to form source / drain recesses (e.g., source / drain recesses 305, 305a, and / or 305b) adjacent to the layer stack 115 as described herein.

[0133] like Fig. 20 As further shown in FIG. 2 , process 2000 may include etching ends of the plurality of sacrificial layers through source / drain recesses to form cavities between ends of the plurality of nanostructure channel layers (block 2030). For example, one or more semiconductor processing tools may be used to etch ends of the plurality of sacrificial nanostructure layers 120 in source / drain recesses to form cavities 405 between ends of the plurality of nanostructure channel layers 125, as described herein.

[0134] like Fig. 20 As further shown in FIG. 2 , process 2000 may include forming an internal spacer in the cavity (block 2040). For example, one or more semiconductor processing tools may be used to form internal spacers (e.g., dummy internal spacer 410, internal spacer 515a, internal spacer 515b) in cavity 405 as described herein.

[0135] like Fig. 20As further shown in FIG. 2 , process 2000 may include forming source / drain regions in the source / drain recesses after forming the internal spacers (block 2050). For example, after forming the internal spacers, one or more semiconductor processing tools may be used to form source / drain regions (e.g., source / drain regions 605, 605a, and / or 605b) in the source / drain recesses, as described herein.

[0136] like Fig. 20 As further shown in , process 2000 may include removing the plurality of sacrificial layers after forming the source / drain regions (block 2060). For example, after forming the source / drain regions, one or more semiconductor processing tools may be used to remove the plurality of sacrificial nanostructure layers 120 as described herein.

[0137] like Fig. 20 As further shown in FIG. 2 , process 2000 may include removing the internal spacer through the first region previously occupied by the sacrificial layer (block 2070). For example, one or more semiconductor processing tools may be used to remove the internal spacer through the first region previously occupied by the sacrificial nanostructure layer 120 (e.g., opening 705), as described herein.

[0138] like Fig. 20 As further shown in , process 2000 may include, after removing the internal spacers, forming a gate structure encapsulating each of the plurality of nanostructure channel layers (block 2080). For example, one or more semiconductor processing tools may be used to form a gate structure 725 encapsulating each of the plurality of nanostructure channels 315 formed by the nanostructure channel layer 125 after removing the internal spacers, as described herein. In some embodiments, gate structure 725 is formed such that an air gap (e.g., air gap 720, 720a, and / or 720b) ​​is formed in a second region between gate structure 725 and the source / drain region previously occupied by the internal spacers.

[0139] Process 2000 may include additional embodiments, such as any single embodiment or any combination of embodiments described below and / or in conjunction with one or more other processes described elsewhere herein.

[0140] In the first embodiment, forming the inner spacer includes: forming the dummy inner spacer 410 in the cavity 405; removing the dummy inner spacer 410 from the cavity 405 after forming the dummy inner spacer 410; and forming the inner spacers 515a and 515b in the cavity 405 after removing the dummy inner spacer 410.

[0141] In a second embodiment, alone or in combination with the first embodiment, process 2000 includes forming a buffer region 505 at the bottom of the source / drain recess after forming the dummy internal spacer 410, wherein removing the dummy internal spacer 410 includes removing the dummy internal spacer 410 after forming the buffer region 505.

[0142] In a third embodiment, alone or in combination with one or more of the first and second embodiments, forming an internal spacer includes forming an internal spacer 515b of the internal spacer on the buffer region 505, wherein removal of the internal spacer 515b results in formation of an air gap 720b between the source / drain region and the buffer region 505.

[0143] In the fourth embodiment, alone or in combination with one or more of the first to third embodiments, the dummy inner spacer 410 includes an oxide material.

[0144] In the fifth embodiment, alone or in combination with one or more of the first to fourth embodiments, the dummy inner spacer 410 includes silicon nitride (Si x N y ), at least one of silicon carbonitride (SiCN) or silicon oxycarbonitride (SiCON).

[0145] In a sixth embodiment, either alone or in combination with one or more of the first to fifth embodiments, process 2000 includes forming a porous interface layer 715 on an end of the internal spacer after removing a sacrificial layer (e.g., a sacrificial nanostructure layer 120) and before removing the internal spacer, wherein removing the internal spacer includes removing the internal spacer through the porous interface layer 715.

[0146] In the seventh embodiment, either alone or in combination with one or more of the first to sixth embodiments, forming the porous interface layer 715 includes: oxidizing the end of the internal spacer to form an oxide layer on the end of the internal spacer; and performing electrochemical etching of the oxide layer to form pores in the oxide layer to form the porous interface layer 715.

[0147] In the eighth embodiment, alone or in combination with one or more of the first to seventh embodiments, forming the gate structure 725 includes forming the gate structure 725 on the porous interface layer 715 , wherein the porous interface layer 715 inhibits formation of the gate structure 725 in the air gap.

[0148] Although Fig. 20 An exemplary block diagram of process 2000 is shown, but in some embodiments, process 2000 includes Fig. 20Additional blocks, fewer blocks, different blocks, or differently arranged blocks than those depicted in process 2000. Additionally or alternatively, two or more of the blocks of process 2000 may be implemented in parallel.

[0149] FIG. 21A to FIG. 21E 21 is a diagram of an exemplary embodiment 2100 of an internal spacer formation process described herein. Exemplary embodiment 2100 includes an example of forming internal spacers 515 without using dummy internal spacers 410. This can reduce the process complexity, process time, and / or process cost of forming internal spacers 515. However, Figure 4A , Figure 4B and FIG. 5A to FIG. 5D The process shown in FIG. 5 may enable minimal to no etching of the buffer region 505 because Figure 4A , Figure 4B and FIG. 5A to FIG. 5D In the process shown in , the cavity 405 is formed before the buffer region 505 is formed.

[0150] FIG. 21A to FIG. 21D Each is from Figure 2 The multiple viewing angles shown in FIG. 1 include Figure 2 The perspective of the cross-sectional plane AA in Figure 2 The viewing angle of the section plane BB in Figure 2 The perspective of the section plane CC in .

[0151] like Fig.21A As shown in the cross-sectional plane AA and the cross-sectional plane BB in FIG. 2 , the operation described in conjunction with the exemplary embodiment 2100 is combined with Figures 1A to 3 The described process is then carried out.

[0152] like Fig.21B As shown in cross-sectional planes AA and BB in FIG. 3 , a deposition tool may be used to deposit a buffer region 505 at the bottom of the source / drain recess 3050. The buffer region 505 may be formed before forming the cavity 405 and without using the dummy inner spacer 410.

[0153] like Fig. 21C As shown in cross-sectional plane BB in FIG. 1 , in the etching operation, the ends of the sacrificial nanostructure layer 120 exposed in the source / drain recesses 305 are laterally etched (e.g., in the y direction approximately parallel to the length of the sacrificial nanostructure layer 120), thereby forming a cavity 405 between the ends of the nanostructure channel 120 exposed in the source / drain recesses 305. The cavity 405 may be formed after forming a buffer region 505 in the source / drain recesses 305.

[0154] like Fig.21DAs shown in cross-sectional plane BB in FIG. 4 , a deposition tool may be used to deposit an internal spacer layer 510 in cavity 405 and along the sidewalls and bottom surface of source / drain recesses 305. The dielectric material layer may be deposited using CVD, PVD and ALD techniques, epitaxy and / or another deposition technique.

[0155] like Fig.21E As shown in cross-sectional plane BB in FIG. 1 , an internal spacer 515 is formed in the cavity 405 between the ends of vertically adjacent nanostructure channels 315 in the source / drain recess 305. The internal spacer 515 is included to protect the source / drain region (which is subsequently formed in the source / drain recess 305) from etching during a nanosheet release operation to remove the sacrificial nanostructure layer 120 between the nanostructure channels 315. An etching tool is used to remove excess material of the internal spacer layer 510 from the source / drain recess 305 (e.g., can be used to trim the internal spacer layer 510 using a dry etching technique, a wet etching technique), so that the remaining portion corresponds to the internal spacer 515 in the cavity 405.

[0156] As noted above, FIG. 21A to FIG. 21E Provided as an example. Other examples may be related to FIG. 21A to FIG. 21E The content described is different.

[0157] In this way, before forming the gate structure of the nanostructure transistor, the internal spacer between the source / drain region of the nanostructure transistor and the sacrificial nanostructure layer of the nanostructure transistor is removed. The sacrificial nanostructure layer is removed, and then the internal spacer is removed. Then, the sacrificial nanostructure layer is replaced with the gate structure of the nanostructure transistor, so that the gate structure and the source / drain region are separated by the air gap generated by removing the internal spacer. The dielectric constant (or relative dielectric constant) of the air gap between the source / drain region and the gate structure is less than the dielectric constant of the material of the internal spacer. The smaller dielectric constant of the air gap reduces the capacitance between the source / drain region and the gate structure.

[0158] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructure channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure that wraps around each of the plurality of nanostructure channels. The semiconductor device includes a source / drain region adjacent to an end of the plurality of nanostructure channels and an end of the gate structure, wherein the source / drain region and the end of the gate structure are separated by a plurality of air gaps.

[0159] As described in more detail above, some embodiments described herein provide a semiconductor device. The semiconductor device includes a plurality of nanostructure channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device. The semiconductor device includes a gate structure that wraps around each of the plurality of nanostructure channels. The semiconductor device includes a source / drain region adjacent to an end of the plurality of nanostructure channels and an end of the gate structure, wherein the source / drain region and the end of the gate structure are separated by a plurality of air gaps. The semiconductor device includes a buffer region located below the source / drain region and adjacent to a mesa region located below the gate structure, wherein the buffer region includes a semiconductor material, and wherein the buffer region and the source / drain region are separated by an air gap of the plurality of air gaps.

[0160] As described in more detail above, some embodiments described herein provide methods. The method includes forming a layer stack, the layer stack including a plurality of nanostructure channel layers and a plurality of sacrificial layers arranged in a direction approximately perpendicular to a semiconductor substrate of a semiconductor device. The method includes forming a source / drain groove adjacent to the layer stack. The method includes etching the ends of the plurality of sacrificial layers through the source / drain groove to form a cavity between the ends of the plurality of nanostructure channel layers. The method includes forming an internal spacer in the cavity. The method includes forming a source / drain region in the source / drain groove after forming the internal spacer. The method includes removing the plurality of sacrificial layers after forming the source / drain region. The method includes removing the internal spacer through a first region previously occupied by the sacrificial layer. The method includes forming a gate structure encapsulating each of the plurality of nanostructure channel layers after removing the internal spacer, wherein the gate structure is formed so that an air gap is formed in a second region previously occupied by the internal spacer between the gate structure and the source / drain region.

[0161] Some embodiments of the present application provide a semiconductor device, comprising: a plurality of nanostructure channels, the plurality of nanostructure channels being arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure wrapping each of the plurality of nanostructure channels; and a source / drain region adjacent to ends of the plurality of nanostructure channels and ends of the gate structure, wherein the source / drain region and the ends of the gate structure are separated by a plurality of air gaps.

[0162] In some embodiments, the source / drain region is in direct contact with the ends of the multiple nanostructure channels. In some embodiments, the semiconductor device further comprises: a liner located between the source / drain region and the ends of the multiple nanostructure channels, wherein the liner comprises a semiconductor material. In some embodiments, the semiconductor material of the liner is doped with one or more p-type dopants. In some embodiments, the thickness of the liner is included in the range of about 0.5 nanometers to about 10 nanometers. In some embodiments, an extended portion of the liner is included on a side of the multiple air gaps. In some embodiments, a side of the source / drain region includes a convex protrusion extending into a portion of the multiple air gaps.

[0163] Other embodiments of the present application provide a semiconductor device, comprising: a plurality of nanostructure channels, the plurality of nanostructure channels being arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure wrapping each of the plurality of nanostructure channels; a source / drain region adjacent to ends of the plurality of nanostructure channels and an end of the gate structure, wherein the source / drain region and the ends of the gate structure are separated by a plurality of air gaps; and a buffer region located below the source / drain region and adjacent to a mesa region located below the gate structure, wherein the buffer region comprises a semiconductor material, and wherein the buffer region and the source / drain region are separated by air gaps of the plurality of air gaps.

[0164] In some embodiments, the top surface of the buffer region and the top surface of the mesa region are approximately coplanar. In some embodiments, the top surface of the buffer region is recessed below the top surface of the mesa region. In some embodiments, the bottom surface of the source / drain region facing the buffer region has a curved cross-sectional profile. In some embodiments, the semiconductor device further includes: a porous interface layer located between the air gap and the gate structure. In some embodiments, the source / drain region includes a p-type source / drain region; and wherein the semiconductor device further includes: a pad located between the source / drain region and the air gap, wherein the pad includes at least one of silicon (Si) or silicon germanium (SiGe). In some embodiments, the pad is doped with at least one of boron (B) or gallium (Ga).

[0165] Still other embodiments of the present application provide a method for forming a semiconductor device, comprising: forming a layer stack, the layer stack comprising a plurality of nanostructured channel layers and a plurality of sacrificial layers arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; forming a source / drain groove adjacent to the layer stack; etching the ends of the plurality of sacrificial layers through the source / drain groove to form a cavity between the ends of the plurality of nanostructured channel layers; forming an internal spacer in the cavity; after forming the internal spacer, forming a source / drain region in the source / drain groove; after forming the source / drain region, removing the plurality of sacrificial layers; removing the internal spacer through a first region previously occupied by the sacrificial layer; and after removing the internal spacer, forming a gate structure wrapping each of the plurality of nanostructured channel layers, wherein the gate structure is formed so that an air gap is formed in a second region between the gate structure and the source / drain region previously occupied by the internal spacer.

[0166] In some embodiments, forming the internal spacer includes: forming a dummy internal spacer in the cavity; after forming the dummy internal spacer, removing the dummy internal spacer from the cavity; and forming the internal spacer in the cavity after removing the dummy internal spacer. In some embodiments, the method further includes: forming a buffer region at the bottom of the source / drain recess after forming the dummy internal spacer, wherein removing the dummy internal spacer includes: removing the dummy internal spacer after forming the buffer region. In some embodiments, the method further includes: forming a porous interface layer on an end of the internal spacer after removing the sacrificial layer and before removing the internal spacer, wherein removing the internal spacer includes: removing the internal spacer through the porous interface layer. In some embodiments, forming the porous interface layer includes: oxidizing the end of the internal spacer to form an oxide layer on the end of the internal spacer; and performing electrochemical etching of the oxide layer to form pores in the oxide layer to form the porous interface layer. In some embodiments, forming the gate structure includes: forming the gate structure on the porous interface layer, wherein the porous interface layer inhibits formation of the gate structure in the air gap.

[0167] The terms "approximately" and "substantially" may refer to a value of a given amount that varies within ±5% of the value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that in view of the embodiments of the present disclosure, the terms "approximately" and "substantially" may refer to a percentage of the value of a given amount.

[0168] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A semiconductor device, comprising: a plurality of nanostructure channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure wrapping each of the plurality of nanostructure channels; as well as a source / drain region adjacent to ends of the plurality of nanostructure channels and an end of the gate structure, The source / drain region and the end of the gate structure are separated by a plurality of air gaps.

2. The semiconductor device according to claim 1, wherein The source / drain regions are in direct contact with the ends of the plurality of nanostructure channels.

3. The semiconductor device according to claim 1, further comprising: a liner located between the source / drain region and the ends of the plurality of nanostructure channels, Wherein, the pad comprises a semiconductor material.

4. The semiconductor device according to claim 3, wherein: The semiconductor material of the liner is doped with one or more p-type dopants.

5. The semiconductor device according to claim 3, wherein: The thickness of the liner is included in the range of about 0.5 nanometers to about 10 nanometers.

6. The semiconductor device according to claim 3, wherein: An extended portion of the liner is included on a side of the plurality of air gaps.

7. The semiconductor device according to claim 1, wherein A side of the source / drain region includes a convex protrusion extending into a portion of the plurality of air gaps.

8. A semiconductor device comprising: a plurality of nanostructure channels arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; a gate structure wrapping each of the plurality of nanostructure channels; a source / drain region adjacent to ends of the plurality of nanostructure channels and an end of the gate structure, wherein the source / drain region and the end of the gate structure are separated by a plurality of air gaps; and a buffer region located below the source / drain region and adjacent to a mesa region located below the gate structure, wherein the buffer region comprises a semiconductor material, and The buffer region and the source / drain region are separated by air gaps of the plurality of air gaps.

9. The semiconductor device according to claim 8, wherein: A top surface of the buffer region and a top surface of the mesa region are approximately coplanar.

10. A method of forming a semiconductor device, comprising: forming a layer stack comprising a plurality of nanostructured channel layers and a plurality of sacrificial layers arranged in a direction approximately perpendicular to a semiconductor substrate of the semiconductor device; forming a source / drain recess adjacent to the layer stack; etching ends of the plurality of sacrificial layers through the source / drain recesses to form cavities between ends of the plurality of nanostructure channel layers; forming an internal partition in the cavity; After forming the inner spacer, forming a source / drain region in the source / drain recess; After forming the source / drain regions, removing the plurality of sacrificial layers; removing the inner spacer through a first region previously occupied by the sacrificial layer; as well as After removing the inner spacer, forming a gate structure encapsulating each of the plurality of nanostructure channel layers, Wherein, the gate structure is formed such that an air gap is formed in a second region between the gate structure and the source / drain region previously occupied by the inner spacer.

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