A SiC MOSFET device with integrated dual self-bias MOS

Abstract

The application relates to a SiC MOSFET device integrated with double self-bias MOS, and belongs to the technical field of semiconductors. The device is symmetrical in structure and comprises a main MOS, a self-bias PMOS and a self-bias NMOS, wherein the self-bias PMOS and the self-bias NMOS are integrated on both sides of the main MOS. The self-bias PMOS is integrated to realize the following functions: when the device is turned on in the positive direction, the self-bias PMOS is turned off, the P-well region is floating, and the on-resistance of the device is reduced; when the device is blocked, the self-bias PMOS is turned on, and the P-well region is clamped, thereby effectively protecting the gate oxide layer of the device compared with a completely floating device. The self-bias NMOS is integrated to realize the freewheeling function in the third quadrant, and under the condition, the P-well is in a floating state, the body diode cannot be turned on, and the bipolar degeneration effect is completely avoided.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductor devices, and relates to a SiC MOSFET device integrated with a double self-bias MOS. BACKGROUND

[0002] Since entering the 21st century, with the vigorous development of emerging fields such as new energy, electric vehicles and smart grids, the demand for high-performance power electronic components has surged, especially for power devices that can withstand extreme conditions, have high-voltage resistance, radiation resistance and support high-frequency and low-power operation. Silicon carbide (SiC) materials have shown excellent capabilities due to their unique physical properties, including a wide bandgap, high critical breakdown field strength and high electron mobility, which can balance the characteristics of "high voltage resistance", "low on-resistance" and "high frequency response".

[0003] In recent years, trench SiC MOSFETs have received widespread attention in the industry because they achieve a compact cell design and effectively weaken the junction field effect transistor (JFET) effect. In particular, trench SiC MOSFETs with excellent gate oxide layer stability have been successfully developed and applied in practice. However, such MOSFETs still face key challenges, namely the high forward voltage drop (typically about 2-3 V) and bidirectional performance degradation caused by parasitic body diodes, which not only increases energy loss but also can affect the overall reliability of the device.

[0004] To overcome the above problems, researchers often use external anti-parallel Schottky barrier diodes (SBDs) to alleviate the problem, but this solution leads to an increase in module volume and the generation of additional capacitance. Therefore, integrating a freewheeling diode into the chip has become the mainstream research direction, such as built-in SBDs, heterojunction diodes or channel diodes. However, these solutions have their own shortcomings, such as the large reverse leakage current of built-in SBDs at high temperatures, and the difficulty of popularizing the application of built-in heterojunction diodes due to complex interface state problems.

[0005] Currently, in traditional design schemes, the P-type shielding layer is mostly directly connected to the source, which increases the on-resistance of the JFET region when turned on. The ideal state is to keep the P-type shielding layer suspended in the on mode and reliably grounded in the off state, so as to fully exert the performance of the device. If this idea is realized, it will greatly improve the technical indicators of SiC MOSFETs, enabling SiC MOSFETs to have higher efficiency and lower energy consumption. SUMMARY

[0006] Therefore, the SiC MOSFET device integrated with double self-bias MOS aims to provide a SiC MOSFET device integrated with double self-bias MOS, which integrates self-bias PMOS and NMOS on the source groove side of the double groove SiC MOSFET device, realizes P-type shielding layer floating in the on state and clamping in the off state through the self-bias PMOS, realizes reverse conduction in the third quadrant through the self-bias NMOS, and the P-type shielding layer is in a floating state, so that the body diode is not conductive, and only the self-bias NMOS realizes the freewheeling function, so as to completely eliminate the bipolar degradation effect.

[0007] To achieve the above-mentioned purpose, the application provides the following technical scheme.

[0008] The SiC MOSFET device integrated with double self-bias MOS comprises an N+ substrate region, an N-drift region located on the surface of the N+ substrate region, a main MOS located on the surface of the N-drift region, a first double self-bias MOS and a second double self-bias MOS located on the surface of the N-drift region and distributed on both sides of the main MOS, a source metal contact region located at the top of the device, and a drain metal contact region located at the bottom of the device.

[0009] The first double self-bias MOS and the second double self-bias MOS are the same in structure and are symmetrically distributed, and the double self-bias MOS comprises a self-bias PMOS and a self-bias NMOS.

[0010] Further, the main MOS comprises a first polysilicon region, a first N+ source region and a first insulating dielectric layer. The first polysilicon region is located above the N-drift region and is completely wrapped by the first insulating dielectric layer; the first N+ source region is distributed on both sides of the first polysilicon region and is separated from the first polysilicon region by the first insulating dielectric layer.

[0011] Further, the first double self-bias MOS and the second double self-bias MOS each comprise a P-well region, a P+ region, a second polysilicon region, a second insulating dielectric layer, a P-base region, a second N+ source region and a P+ drain region. The P-well region is located on the surface of the N-drift region; the P+ region is located above the right side of the P-well region; the second polysilicon region is located above the P-well region and the P+ region and is separated from the second N+ source region, the P-base region, the N-drift region, the P-well region and the P+ region by the second insulating dielectric layer; the P-base region is located on the surface of the N-drift region and is adjacent to the first insulating dielectric layer on the left side and adjacent to the first N+ source region on the top side; the second N+ source region is located above the right side of the P-base region; and the P+ drain region is located on the upper surface of the P-base region and is adjacent to the first N+ source region.

[0012] The P-well region is used as the source of the self-biased PMOS, the second N+ source region is used as the source of the self-biased NMOS, the P+ drain region is used as the drain of the self-biased PMOS, and the second polysilicon region is used as the gate of the self-biased PMOS and the self-biased NMOS.

[0013] The P+ drain region, the second N+ source region and the second polysilicon region are in contact with the source metal contact region, so that the P+ drain region and the second N+ source region are in equipotential connection with the second polysilicon region, thereby short-circuiting the drain and the gate of the self-biased PMOS and short-circuiting the source and the gate of the self-biased NMOS. In addition, the drain of the self-biased NMOS is connected to the drain of the main MOS, and both are connected to the drain metal contact region.

[0014] Further, in the lateral direction of the device, the P-well region protrudes from the second insulating medium layer by a portion, and the protruding portion is used to enhance the conduction capability of the self-biased PMOS.

[0015] The SiC MOSFET device with integrated double self-biased MOSs has the following beneficial effects:

[0016] 1) By short-circuiting the drain and the gate of the self-biased PMOS, when the potential of the drain of the self-biased PMOS rises, the potential of the P-well region also continuously rises until the self-biased PMOS is turned on. Thus, when the device is in the forward conduction state, the drain voltage is not large enough, the potential of the P-well region is not large enough, the self-biased PMOS is turned off, and the P-type shielding layer (i.e. the P-well region) is in a floating state. In the blocking state, the drain voltage continuously rises, the potential of the P-well region continuously rises, the self-biased PMOS is turned on, and the P-well region is in a clamping state, which can better protect the gate oxide layer than the floating P-well.

[0017] 2) By short-circuiting the source and the gate of the self-biased NMOS, in the third quadrant, the potential of the source of the self-biased NMOS rises, and the self-biased NMOS is turned on. In addition, in the third quadrant, the self-biased PMOS is in an off state, and the body diode cannot be turned on, so the reverse current function can only be realized by the self-biased NMOS, thereby completely eliminating the bipolar degradation effect.

[0018] Compared with the conventional double-trench SiC MOSFET device, the SiC MOSFET device with integrated double self-bias MOS has reduced on-resistance, completely shields the bipolar degradation effect, and has no impact on the breakdown voltage; compared with the completely floating device, the SiC MOSFET device with integrated double self-bias MOS can better protect the gate oxide layer of the device, and the dynamic characteristics of the device are improved.

[0019] Other advantages, objects, and features of the application will be set forth in part in the following specification taken in conjunction with the accompanying drawings, and in part will become apparent to those skilled in the art from a consideration of the following specification and drawings. The objects and other advantages of the application will be realized and attained by means of the instrumentalities and combinations pointed out in the following specification. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to make the purposes, technical solutions and advantages of the application more clear, the preferred detailed description of the application will be combined with the drawings to describe the application, in which:

[0021] Figure 1 A structure schematic diagram of a SiC MOSFET device with integrated double self-bias MOS provided by the embodiment of the application is shown in the figure;

[0022] Figure 2 For Figure 1 An equivalent circuit diagram of the device;

[0023] Figure 3 A comparison diagram of on-state characteristics of the conventional double-trench device and the new device, the new device (floating) and the new device (grounded);

[0024] Figure 4 A comparison diagram of total current density of the conventional double-trench device and the new device, the new device (floating) and the new device (grounded) in the on-state;

[0025] Figure 5 A potential change schematic diagram of P-well of the conventional double-trench device and the new device, the new device (floating) and the new device (grounded) in the on-state;

[0026] Figure 6 A schematic diagram of the integrated PMOS of the new device in the on-state with the increase of V ds , thereby opening and closing state;

[0027] Figure 7 A comparison diagram of breakdown characteristics of the conventional double-trench device and the new device, the new device (floating) and the new device (grounded);

[0028] Figure 8 A potential change schematic diagram of P-well of the conventional double-trench device and the new device, the new device (floating) and the new device (grounded) in the on-state;ds Figure 6: Gate oxide electric field vs. V

[0029] Figure 9 Figure 7: P-well voltage vs. V

[0030] Figure 10 Figure 8: PMOS integrated inside the new device vs. V ds Figure 9: NMOS integrated inside the new device vs. V

[0031] Figure 11 Figure 10: Total current density vs. V

[0032] Figure 12 Figure 11: Total current density vs. V Figure 12 a: new device, Figure 12 b: conventional device;

[0033] Figure 13 Figure 12: Hole density vs. V Figure 13 a: new device, Figure 13 b: conventional device;

[0034] Figure 14 Figure 13: NMOS integrated inside the new device vs. V sd Figure 14: NMOS integrated inside the new device vs. V

[0035] Figure 15 Figure 15: Gate charge vs. V

[0036] Figure 16 Figure 16: Capacitance vs. V

[0037] Figure 1: 1 - drain metal contact region, 2 - N+ substrate region, 3 - N- drift region, 4 - right side P-well region, 5 - right side P+ region, 6 - right side source auxiliary gate dielectric region, 7 - right side P-base region, 8 - right side source auxiliary gate polysilicon region, 9 - source metal contact region, 10 - right side self-bias NMOS N+ source region, 11 - right side self-bias PMOS P+ drain region, 12 - right side main MOS N+ source region, 13 - main gate polysilicon region, 14 - main gate dielectric region. DETAILED DESCRIPTION

[0038] The present application is described in greater detail by the following specific examples, and other advantages and effects of the present application will be readily appreciated by skilled in the art from this disclosure. The present application can also be carried out or implemented in other different specific embodiments, and various modifications or changes can be made thereto without departing from the spirit of the present application based on different viewpoints and applications. It should be noted that the drawings provided in the following examples only schematically illustrate the basic concept of the present application, and the following examples and features in the examples can be combined with each other without conflict.

[0039] In the drawings, only for exemplary illustration, only schematic views are shown, and cannot be understood as limitations of the present application; in order to better illustrate the embodiments of the present application, some components in the drawings are omitted, enlarged or reduced, and do not represent the actual product size; for those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings can be omitted.

[0040] In the drawings of the embodiments of the present application, the same or similar reference numerals correspond to the same or similar components; in the description of the present application, it should be understood that if the terms "upper", "lower", "left", "right", "front", "back" and the like indicate the orientation or positional relationship shown in the drawings, only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a particular orientation, be constructed and operated in a particular orientation, therefore the terms describing the positional relationship in the drawings are only for exemplary illustration, and cannot be understood as limitations of the present application, for those skilled in the art, the specific meaning of the above terms can be understood according to the specific circumstances.

[0041] As shown in FIG. 1, a SiC MOSFET device provided by an embodiment of the present application is an integrated double self-bias MOS SiC MOSFET device, which is divided into four parts according to structural characteristics, namely, double self-bias MOS structures on the left and right sides, a main MOS structure and a basic structure. Figure 1 In addition, the structure of the device is in a symmetrical state, has two traditional forward conduction channels, integrates two self-bias NMOSs for reverse conduction and two self-bias PMOSs for controlling floating and clamping.

[0042] The device includes: drain metal contact region 1, N+ substrate region 2, N- drift region 3, right side P-well region 4, right side P+ region 5, right side source auxiliary gate insulating dielectric layer region 6, right side P-base region 7, right side source auxiliary gate polysilicon region 8, source metal contact region 9, right side self-biased NMOS N+ source region 10, right side self-biased PMOS P+ drain region 11, right side main MOS N+ source region 12, main gate polysilicon region 13, main gate insulating dielectric layer region 14. Since the SiC MOSFET device is a symmetrical structure, the left side structure of the device is symmetrical with the right side, which will not be described here.

[0043] Wherein, the basic structure includes drain metal contact region 1, N+ substrate region 2, N- drift region 3, source metal contact region 9. The drain metal contact region 1 is located on the lower surface of the N+ substrate region 2; the N+ substrate layer 2 is located on the lower surface of the N- drift region 3 and the upper surface of the drain metal contact region 1, with a thickness of 3 μm, SiC doped with N-type impurity nitrogen (N), with a doping concentration of 2×10 19 cm -3 ; the N- drift region 3 is located on the upper surface of the N+ substrate region 2, wherein the thickness of the N- drift region 3 between the upper surface of the N+ substrate region 2 and the lower surface of the P-well region 4 is 10 μm, SiC doped with N-type impurity nitrogen (N), with a doping concentration of 7×10 15 cm -3 ; the source metal contact region 9 is located on the upper surface of the right side source auxiliary gate polysilicon region 8, the right side self-biased NMOS N+ source region 10, the right side self-biased PMOS P+ drain region 11, the right side main MOS N+ source region 12 and the main gate insulating dielectric layer region 14.

[0044] The double self-biased MOS structure includes: right side P-well region 4, right side P+ region 5, right side source auxiliary gate insulating dielectric layer region 6, right side P-base region 7, right side source auxiliary gate polysilicon region 8, right side self-biased NMOS N+ source region 10, right side self-biased PMOS P+ drain region 11.

[0045] The right side P-well region 4 is located on the right side of the N- drift region 3 and on the lower surface of the right side source auxiliary gate insulating dielectric layer region 6, wherein the part of the right side P-well region 4 that extends more than the right side source auxiliary gate insulating dielectric layer region 6 is mainly used to enhance the conduction capability of the self-biased PMOS, and the width of this part of the right side P-well region 4 that extends more is the same as the extension width 0.15 μm of the conventional double-trench SiC MOSFET. The thickness of the right side P-well region 4 is 0.7 μm, the total width is 0.85 μm, SiC doped with P-type impurity aluminum (AL), with a doping concentration of 1×10 18 cm -3The right P+ region 5 is located on the upper right of the right P-well region 4 and is adjacent to the lower surface of the insulating medium layer region 6 of the right source auxiliary gate, with a thickness of 0.3 μm, a width of 0.3 μm, SiC doped with P-type impurity aluminum (AL), and a doping concentration of 1 x 1018 cm-3. 19 cm -3 The right P-base region 7 is located on the upper surface of the N-drift region 3 and between the insulating medium layer region 6 of the right source auxiliary gate and the insulating medium layer region 14 of the main gate, with the upper surface of the right P-base region 7 in contact with the lower surface of the N+ source region 10 of the right self-biased NMOS, the P+ drain region 11 of the right self-biased PMOS, and the N+ source region 12 of the right main MOS, a thickness of 0.3 μm, a width of 0.7 μm, SiC doped with P-type impurity aluminum (AL), and a doping concentration of 2 x 1018 cm-3. 17 cm -3 The polysilicon region 8 of the right source auxiliary gate is isolated from the N+ source region 10 of the right self-biased NMOS, the right P-base region 7, the right P-well region 4, and the right P+ region 5 through the insulating medium layer region 6 of the right source auxiliary gate, with the upper surface of the polysilicon region 8 of the right source auxiliary gate in contact with the lower surface of the source metal contact region 9, a thickness of 1.55 μm, a width of 0.68 μm, and pure polysilicon as the material. The left side thickness of the insulating medium layer region 6 of the right source auxiliary gate is 0.02 μm, the lower side thickness is 0.05 μm, and the material is SiO2. The N+ source region 10 of the right self-biased NMOS is located on the upper right of the right P-base region 7 and the lower surface of the source metal contact region 9, with the right side being the insulating medium layer region 6 of the right source auxiliary gate, a thickness of 0.2 μm, a width of 0.15 μm, SiC doped with N-type impurity nitrogen (N), and a doping concentration of 1 x 1018 cm-3. 19 cm -3 The P+ drain region 11 of the right self-biased PMOS is located on the upper surface of the right P-base region 7 and the lower surface of the source metal contact region 9, with the left side being the N+ source region 12 of the right main MOS, a thickness of 0.2 μm, a width of 0.25 μm, SiC doped with P-type impurity aluminum (AL), and a doping concentration of 1 x 1018 cm-3. 19 cm -3 .

[0046] The main MOS structure comprises: N+ source region 12 of the right main MOS, polysilicon region 13 of the main gate and insulating medium layer region 14 of the main gate. The N+ source region 12 of the right main MOS is located on the upper surface of the right P-base region 7 and the lower surface of the source metal contact region 9, the left side is the insulating medium layer region 14 of the main gate, the right side is the P+ drain region 11 of the right self-bias PMOS, the thickness of the N+ source region 12 of the right main MOS is 0.2 μm, the width is 0.3 μm, SiC is doped into N type impurity nitrogen (N), and the doping concentration is 1×10 19 cm -3 . The polysilicon region 13 of the main gate is wrapped by the insulating medium layer region 14 of the main gate, the thickness of the polysilicon region 13 of the main gate is 1.75 μm, the width is 0.6 μm, and the material is pure polysilicon. The thickness of the insulating medium layer region 14 of the main gate is 0.05 μm, and the material is SiO2.

[0047] As Figure 2 shown, it is an equivalent circuit diagram of the device described in the embodiment. As Figure 2 can be seen, the new device proposed in the embodiment actually integrates double self-bias MOS in the metal on both sides of the traditional double-trench device, and each side of the double self-bias MOS includes a self-bias PMOS and a self-bias NMOS. The drain and the gate of the self-bias PMOS are short-circuited, and the source is the potential of the P-well, thereby realizing automatic switching of the device floating and clamping. The source and the gate of the self-bias NMOS are short-circuited, and the drain is the drain of the main MOS, thereby realizing the freewheeling function in the third quadrant and completely eliminating the bipolar degradation effect.

[0048] Figure 3 As shown in the figure, it is a comparison diagram of the conduction characteristics of the traditional double-trench device, the new device, the new device (floating) and the new device (grounded). As Figure 3 can be seen, the conduction characteristics of the new device (floating) are the best, followed by the new device, and the traditional double-trench device and the new device (grounded) both ground the P-well, so the JFET is large and the conduction characteristics are poor. This proves that the new device optimizes the conduction performance of the traditional double-trench device. Among them, the new device (floating) is based on the new device proposed in the embodiment, and the voltage applied on the polysilicon region of the source auxiliary gate on the left and right sides of the device is removed; the new device (grounded) is based on the new device proposed in the embodiment, and the P+ region on the left and right sides of the device is connected to the source metal contact region 9.

[0049] Figure 4 As shown in the figure, it is a comparison diagram of the total current density under the conduction of the traditional double-trench device, the new device, the new device (floating) and the new device (grounded). As Figure 4It can be seen that the new device (floating) has the widest current conduction path, while the traditional double-groove device and the new device (grounded) have the narrowest current conduction paths. The current conduction path of the new device falls in between, which also confirms... Figure 3 The conduction curve results.

[0050] Figure 5 The diagram illustrates the P-well potential changes of a traditional double-trench device, a novel device, a novel device (floating), and a novel device (grounded) under conduction conditions. It can be seen that the P-well potential of the traditional double-trench device and the novel device (grounded) remains around -1.4V, while the potential of the novel device (floating) shows a continuous upward trend, finally slowing down around 11V. This is because the rising P-well potential causes PNP punch-through, allowing holes to flow into the source, thus slowing the potential increase. The novel device achieves floating and clamping through a self-biased PMOS, resulting in a lower clamping voltage and more effective protection of the gate oxide layer. At V... ds <V on At 13.86V, the self-biased PMOS is turned off, and the P-well is in a floating state. At V... ds >V on At 13.86V, the self-biased PMOS is turned on, and the P-well is in a clamped state.

[0051] Figure 6 The image shows the PMOS integrated within the novel device under conduction conditions, which is influenced by V. ds The increase in [a certain value] indicates the on / off state. From [the following]... Figure 6 It can be seen that when V gs =15V, V ds =5V, the self-biased PMOS is turned off, when V gs =15V, V ds At 15V, the self-biased PMOS is turned on.

[0052] Figure 7 The diagram shows a comparison of the breakdown characteristic curves of a traditional double-trench device, a novel device, a novel device (floating), and a novel device (grounded). From... Figure 7 It can be seen that the new device (floating) has the highest breakdown voltage, the new device (grounded) has the lowest, the traditional double trench device is close to the new device, but overall the breakdown voltages of the four devices are not much different.

[0053] Figure 8 The diagram shows the traditional double-groove device compared to the novel device, the novel device (floating), and the novel device (grounded) at V. dsA comparison of the gate oxide electric field strength of the devices under an 800V blocking condition. It can be seen that the gate oxide electric field strength of the novel device (floating) is 3.13MV / cm, exceeding its safe electric field strength, which is detrimental to the long-term use of the device. The remaining three devices all have a field strength less than 3MV / cm, effectively protecting the gate oxide layer. This indicates that the novel device, through self-biased PMOS clamping, reduces the P-well potential, providing better protection for the gate oxide layer compared to a completely floating device.

[0054] Figure 9 The diagram illustrates the potential changes of the P-well under blocking conditions for a traditional double-trench device, a novel device, a novel device (floating), and a novel device (grounded). From... Figure 9 It can be seen that the P-well potential of both the traditional dual-trench device and the new device (grounded) remains around -1.4V. The potential of the new device (floating) shows a continuous upward trend, eventually reaching around 20V, which is not conducive to protecting the gate oxide layer of the device. The final potential of the new device is clamped at around 1.2V, which is more conducive to protecting the gate oxide layer of the device and ensuring the long-term reliability of the device.

[0055] Figure 10 The image shows the PMOS integrated within the novel device under blocking conditions, which varies with V. ds The increase of V indicates the on / off state. It can be seen that when V... gs =0V, V ds =5V, the self-biased PMOS is turned off, when V gs =0V, V ds When the voltage is 15V, the self-biased PMOS turns on to achieve the clamping function.

[0056] Figure 11 The image shows a comparison of the total current density and hole current density curves when the traditional double-trench device and the novel device are in the third quadrant. From... Figure 11 It can be seen that the new device relies entirely on electronic conductivity to achieve freewheeling, even if V sd The voltage reached 4V, exceeding the turn-on voltage of the SiC diode, and the hole current of the device was almost zero, indicating that the novel device provided in this embodiment completely eliminates the bipolar degradation effect. This is because in the third quadrant, the self-biased PMOS is in the off state, the P-well is floating, and freewheeling is impossible. In contrast, traditional double-trench devices rely on the body diode for conduction, and their conduction mode is bipolar, which can lead to the bipolar degradation effect, which is detrimental to the long-term reliability of the device.

[0057] Figure 12 The image shows a comparison of the total current density when the traditional dual-trench device and the novel device are in the third quadrant. It can be seen that the total current path of the novel device is only the self-biased NMOS channel (such as...).Figure 12 As shown in a), traditional dual-groove devices rely on a body diode for conduction, and their total current density permeates the entire device (as shown in a diagram). Figure 12 (as shown in b).

[0058] Figure 13 The image shows a comparison of hole density in the third quadrant when the traditional double-groove device and the novel device are in operation. It can be seen that the hole current density in the novel device is almost zero (e.g., ...). Figure 13 As shown in a), the hole current density of traditional dual-trench devices permeates the entire device (as shown in a). Figure 13 (as shown in b).

[0059] Figure 14 The figure shows the NMOS integrated within the novel device in the third quadrant, which varies with V. sd The increase of V indicates the on / off state. It can be seen that when V... gs =-5V, V ds When V = 0.5V, the self-biased M = NMOS is turned off, and when V gs =-5V, V ds At 2V, the self-biased NMOS turns on, enabling reverse freewheeling. The turn-on voltage of the self-biased NMOS is much lower than the forward voltage of the SiC diode, which can completely eliminate the bipolar degradation effect.

[0060] Figure 15 The diagram shows a comparison of the gate charge characteristic curves of a traditional double-groove device, a novel device, a novel device (floating), and a novel device (grounded). From... Figure 15 It can be seen that the Q of the novel device (floating) gd and Q g The largest value is found in the device with the worst dynamic characteristics. The remaining three devices are similar, with little difference between them.

[0061] Figure 16 The image shows a comparison of the capacitance characteristic curves of a traditional double-groove device, a new device, a new device (floating), and a new device (grounded). From... Figure 16 It can be seen that the C of the novel device (floating) rss Maximum, new device (grounded) and traditional double trench device C rss The minimum value is found in the novel device, while the intermediate value indicates that the switching speed of the novel device also falls between floating and grounded. The C value of the novel device (floating) is... oss The smallest, the remaining three devices are not significantly different. The C of the novel device (floating) iss The smallest, and the remaining three devices are not much different.

[0062] In summary, the application provides a SiC MOSFET device integrated with double self-bias MOS. The device realizes self-bias PMOS off, P-well region floating and reduced on-resistance of the device by integrated self-bias PMOS when forward conducting; realizes self-bias PMOS on and P-well region clamping when blocking, which effectively protects the gate oxide layer of the device compared with the completely floating device; realizes freewheeling function in the third quadrant by integrated self-bias NMOS, and under this condition, P-well is in floating state and body diode cannot be turned on, which completely avoids the bipolar degradation effect. The SiC MOSFET device provided by the application has the following advantages compared with the conventional double-trench SiC MOSFET: the specific on-resistance is reduced by 2% when I ds = 200A; the reverse on-state voltage drop V ds is reduced by 24.15% when I cut-in = -100A; compared with the device with completely floating P-well, the gate oxide layer electric field is reduced by 28.4% and the gate charge Q gd is reduced by 20.81% under the blocking condition, and the gate charge Q g is reduced by 3.1%, and the transfer capacitance C rss is reduced by 74.08% when 200V.

[0063] Finally, it should be pointed out that the above examples are only used to illustrate the technical solutions of the application and not to limit the application. Although the application has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solutions of the application can be modified or replaced equivalently without departing from the purpose and scope of the technical solutions, which should be covered in the scope of the claims of the application.

Claims

1. A SiC MOSFET device integrating dual self-biased MOS, characterized in that, The device includes an N+ substrate region, an N-drift region located on the surface of the N+ substrate region, a main MOS located on the surface of the N-drift region, and a first dual self-biased MOS and a second dual self-biased MOS located on the surface of the N-drift region and distributed on both sides of the main MOS; The first dual self-biased MOS and the second dual self-biased MOS have the same structure and are symmetrically distributed; both the first dual self-biased MOS and the second dual self-biased MOS include a self-biased PMOS and a self-biased NMOS; the self-biased PMOS is used to control floating and clamping; the self-biased NMOS is used for reverse conduction; Both the first and second dual self-biased MOS transistors include a P-well region, a P+ region, a second polysilicon region, a second insulating dielectric layer, a P-base region, a second N+ source region, and a P+ drain region. The P-well region is located on the surface of the N-drift region. The P+ region is located to the upper left or upper right of the P-well region. The second polysilicon region is located above the P-well and P+ regions and is separated from the second N+ source region, P-base region, N-drift region, P-well region, and P+ region by the second insulating dielectric layer. The P-base region is located on the surface of the N-drift region and is adjacent to the main MOS transistor. The second N+ source region is located to the upper left or upper right of the P-base region. The P+ drain region is located on the surface of the P-base region and is adjacent to the main MOS transistor. The P-well region serves as the source of the self-biased PMOS. The second N+ source region serves as the source of the self-biased NMOS. The P+ drain region serves as the drain of the self-biased PMOS; the second polysilicon region serves as the gate of both the self-biased PMOS and the self-biased NMOS; the drain of the self-biased NMOS is connected to the drain of the main MOS. The drain and gate of the self-biased PMOS are shorted; the source and gate of the self-biased NMOS are shorted.

2. The SiC MOSFET device according to claim 1, characterized in that, The main MOS includes a first polysilicon region, a first N+ source region, and a first insulating dielectric layer; the first polysilicon region is located above the N- drift region and is completely enclosed by the first insulating dielectric layer; the first N+ source region is distributed on both sides of the first polysilicon region and is separated from the first polysilicon region by the first insulating dielectric layer.

3. The SiC MOSFET device according to claim 1, characterized in that, In the lateral direction of the device, the P-well region protrudes beyond the second insulating dielectric layer, and this protrusion is used to enhance the conduction capability of the self-biased PMOS.

4. The SiC MOSFET device according to claim 1, characterized in that, The device also includes a source metal contact region located at the top of the device; The source metal contact region is connected to the source of the main MOS, the drain and gate of the self-biased PMOS, and the source and gate of the self-biased NMOS, respectively.

5. The SiC MOSFET device according to claim 1, characterized in that, The device also includes a drain metal contact area located at the bottom of the device; The drain metal contact region is connected to the drain of the main MOS and the drain of the self-biased NMOS, respectively.

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