Method for manufacturing a semiconductor structure and semiconductor structure

Abstract

The present disclosure relates to a semiconductor structure manufacturing method and a semiconductor structure, and relates to the field of integrated circuits. The semiconductor structure manufacturing method comprises: providing a substrate, the substrate comprising a first region and a second region; forming a gate dielectric layer on the substrate; forming a metal oxide layer on the substrate; the metal oxide layer comprising a first part in the first region and a second part in the second region; wherein, in a vertical direction, a top surface of the first part is lower than a top surface of the second part; forming a protective layer on the first region, the protective layer being in direct contact with the metal oxide layer; removing the second part of the metal oxide layer; and removing the protective layer. The selective etching of the second part of the metal oxide layer is achieved, avoiding damage to the first part of the metal oxide layer in the process of etching and removing the second part of the metal oxide layer in the second region, which is conducive to improving the electrical performance and reliability of the semiconductor structure.

Description

Technical Field

[0001] This disclosure relates to the field of integrated circuit technology, and in particular to a method for fabricating a semiconductor structure and the semiconductor structure itself. Background Technology

[0002] With the continuous development of complementary metal-oxide-semiconductor (CMOS) technology, the thickness of the gate dielectric layer is constantly decreasing and the gate length is constantly shrinking. The quantum tunneling effect is becoming more and more significant, and the depletion effect of polysilicon gates is becoming more and more severe. Silicon dioxide gate dielectric and polysilicon gate transistors are gradually approaching their physical limits.

[0003] The semiconductor industry has introduced high-k metal gate (HKMG) technology, which uses high-k dielectric materials to replace silicon dioxide gate dielectrics and metal gates to replace polysilicon gates, in order to improve gate leakage current, enhance gate control capability, and increase carrier mobility.

[0004] During the HKMG technology manufacturing process, especially when simultaneously forming the gate structures of NMOS and PMOS devices, the threshold voltages of NMOS and PMOS devices are different, and the high-k dielectric gate dielectrics of NMOS and PMOS devices are different. The high-k dielectric gate dielectric of NMOS devices may exist in PMOS devices, affecting the performance of PMOS devices. Summary of the Invention

[0005] Therefore, it is necessary to provide a method for fabricating a semiconductor structure and a semiconductor structure to address the problems in the existing technology.

[0006] To achieve the above objectives, in a first aspect, this disclosure provides a method for fabricating a semiconductor structure, comprising:

[0007] A substrate is provided, the substrate comprising a first region and a second region;

[0008] A gate dielectric layer is formed on the substrate;

[0009] Forming a metal oxide layer on the substrate includes:

[0010] The first part is located in the first zone;

[0011] The second part is located in the second zone;

[0012] In the vertical direction, the top surface of the first part is lower than the top surface of the second part;

[0013] A protective layer is formed on the first region, and the protective layer is in direct contact with the metal oxide layer;

[0014] Remove the second portion located in the metal oxide layer;

[0015] Remove the protective layer.

[0016] Optionally, the first region is an NMOS region and the second region is a PMOS region.

[0017] Optionally, a protective layer is formed, comprising:

[0018] A protective material layer is formed on the first and second regions;

[0019] Remove the protective material layer on the second region and form the protective layer on the first region.

[0020] Optionally, the process further includes the following steps before forming the gate dielectric layer:

[0021] A stress adjustment layer is formed on the second region, and the stress adjustment layer is in direct contact with the substrate of the second region.

[0022] Optionally, a gate dielectric layer is formed, comprising:

[0023] A first gate dielectric layer is formed on the substrate and the stress adjustment layer in the first region;

[0024] A second gate dielectric layer is formed on top of the first gate dielectric layer.

[0025] Optionally, the manufacturing method further includes:

[0026] A power function layer is formed on the first portion of the metal oxide layer and on the gate dielectric layer of the second region.

[0027] Secondly, this disclosure provides a semiconductor structure, including:

[0028] Substrate, the substrate comprising a first region and a second region;

[0029] A first gate structure is disposed in the first region, and the first gate structure includes a stacked gate dielectric layer, a metal oxide layer, and a work function layer.

[0030] A second gate structure is disposed in the second region. The second gate structure includes a stress adjustment layer, a gate dielectric layer, and a work function layer stacked on the second region.

[0031] Optionally, the first region is an NMOS region and the second region is a PMOS region.

[0032] Optionally, the gate dielectric layer includes a first gate dielectric layer and a second gate dielectric layer stacked together;

[0033] The material of the first gate dielectric layer includes silicon oxynitride.

[0034] Optionally, the material of the metal oxide layer includes at least one of aluminum oxide or lanthanum oxide.

[0035] The semiconductor structure fabrication method and semiconductor structure disclosed herein form a protective layer after forming a metal oxide layer. The protective layer is used to protect the first part of the metal oxide layer in the first region, thereby enabling selective etching of the second part of the metal oxide layer. This avoids damage to the first part of the metal oxide layer during the etching process of removing the second part of the metal oxide layer in the second region, which is beneficial to improving the electrical performance and reliability of the semiconductor structure. Attached Figure Description

[0036] To more clearly illustrate the technical solutions in the embodiments or conventional technologies of this disclosure, the accompanying drawings used in the description of the embodiments or conventional technologies will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 This is a process flow diagram of a method for fabricating a semiconductor structure provided in one embodiment;

[0038] Figure 2 This is a schematic diagram of the structure after forming a gate dielectric layer and a metal oxide layer on a substrate, as provided in one embodiment;

[0039] Figure 3 This is a schematic diagram of the structure after forming a protective material layer and forming a mask layer on the protective material layer located in the first region, as provided in one embodiment;

[0040] Figure 4 This is a schematic diagram of a structure in which the protective material layer of the first region is etched while the protective material layer of the second region is etched simultaneously in one embodiment.

[0041] Figure 5 This is a schematic diagram of the structure after the protective layer is formed in one embodiment;

[0042] Figure 6 This is a schematic diagram of the structure after etching away the second portion of the metal oxide layer in one embodiment;

[0043] Figure 7 This is a schematic diagram of the structure after the protective layer has been etched away in one embodiment;

[0044] Figure 8This is a schematic diagram of the structure after the function layer is formed in one embodiment;

[0045] Figure 9 This is a schematic diagram of the structure of the first and second devices formed in one embodiment;

[0046] Figure 10 This is a schematic diagram of the structure of the first and second devices formed in another embodiment.

[0047] Explanation of reference numerals in the attached figures:

[0048] 11. Substrate; 12. Stress adjustment layer; 13. Gate dielectric layer; 131. First gate dielectric layer; 132. Second gate dielectric layer; 14. Metal oxide layer; 114. First portion; 214. Second portion; 15. Protective layer; 15a. Protective material layer; 16. Work function layer; 161. First barrier layer; 162. Semiconductor layer; 163. Second barrier layer; 164. Metal gate layer; 17. Mask layer; 18. Isolation layer; A1. First region; A2. Second region. Detailed Implementation

[0049] To facilitate understanding of this disclosure, a more complete description will now be given with reference to the accompanying drawings, in which preferred embodiments of the present disclosure are shown. However, this disclosure may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of this disclosure.

[0051] This disclosure provides a method for fabricating a semiconductor structure in exemplary embodiments. Figure 1 A flowchart illustrating a method for fabricating a semiconductor structure according to an exemplary embodiment of the present disclosure is shown, such as... Figure 1 As shown, the steps include the following:

[0052] Step S101: Provide a substrate, the substrate including a first region and a second region;

[0053] Step S102: Form a gate dielectric layer located on the substrate;

[0054] Step S103: Form a metal oxide layer on the substrate; the metal oxide layer includes a first portion located in a first region and a second portion located in a second region; wherein, in the vertical direction, the top surface of the first portion is lower than the top surface of the second portion;

[0055] Step S104: Form a protective layer on the first region, which is in direct contact with the metal oxide layer;

[0056] Step S105: Remove the second portion located in the metal oxide layer;

[0057] Step S106: Remove the protective layer.

[0058] In the semiconductor structure fabrication method of this embodiment, a protective layer is formed after the metal oxide layer is formed. The protective layer is used to protect the first part of the metal oxide layer in the first region, thereby enabling selective etching of the second part of the metal oxide layer. This avoids damage to the first part of the metal oxide layer during the etching process of removing the second part of the metal oxide layer in the second region, which is beneficial to improving the electrical performance and reliability of the semiconductor structure.

[0059] The following is combined Figures 2-10 The process of fabricating semiconductor structures is explained in detail, including... Figures 2-10 This is a schematic diagram of the semiconductor structure in an exemplary embodiment of the present disclosure during its fabrication process.

[0060] In step S101, refer to Figure 2 As shown, substrate 11 can be a semiconductor substrate, and the material of the semiconductor substrate can include silicon (Si), silicon germanium (SiGe), silicon germanium carbon (SiGeC), silicon carbide (SiC), or other III / V or II / VI semiconductor materials. Alternatively, for example, the semiconductor substrate can be a layered substrate including materials such as Si / SiGe, Si / SiC, silicon-on-insulator (SOI), or silicon germanium-on-insulator.

[0061] The substrate 11 includes a first region A1 and a second region A2. In this embodiment, a first device 100 is formed in the first region A1 and a second device 200 is formed in the second region A2.

[0062] In some embodiments, the first region A1 is an NMOS region with N-type doped ions, the second region A2 is a PMOS region with P-type doped ions, the first device 100 is an NMOS device, and the second device 200 is a PMOS device.

[0063] The first region A1 and the second region A2 have a shallow trench isolation structure (not shown). For example, the N-type dopant ion can be a group V ion such as phosphorus (P) ion, bismuth (Bi) ion, antimony (Sb) ion or arsenic (As) ion, and the P-type dopant ion can be a group III ion such as boron (B) ion, aluminum (Al) ion, gallium (Ga) ion or indium (In) ion.

[0064] In step S102, please continue to refer to... Figure 2A gate dielectric layer 13 is formed, which covers the first region A1 and the second region A2. The gate dielectric layer 13 may include a single-layer structure or a multi-layer structure.

[0065] For example, the material of the gate dielectric layer 13 may include at least one of silicon oxide (SiO2), silicon nitride (Si3N4), or silicon oxynitride (SiON).

[0066] In step S103, please continue to refer to... Figure 2 The metal oxide layer 14 can be formed using metal-organic chemical vapor deposition (MOCVD), atomic layer deposition (ALD), or physical vapor deposition (PVD) processes. The metal oxide layer 14 covers the side of the gate dielectric layer 13 away from the substrate 11. The metal oxide layer 14 includes a first portion 114 located on a first region A1 and a second portion 214 located on a second region A2. The metal oxide layer 14 is a high-dielectric-constant layer of the first device 100. The material of the metal oxide layer 14 may include at least one of lanthanum oxide (La₂O₃), aluminum oxide (AlO), tantalum oxide (TaO), yttrium oxide (Y₂O₃), zirconium dioxide (ZrO₂), strontium titanate (SrTiO₃), or zirconium silicate oxide (ZrSiO₄). In some embodiments, the material of the metal oxide layer 14 includes lanthanum oxide or aluminum oxide.

[0067] In this embodiment, in the vertical direction (perpendicular to the top surface of the substrate 11), the top surface of the first portion 114 is lower than the top surface of the second portion 214. It can be understood that, referring to... Figure 2 As shown, in this embodiment, a first gate structure 110 of a first device 100 is formed on a first region A1, and a second gate structure 110 of a second device 200 is formed on a second region A2. The structure of the second gate structure 110 may be more complex than that of the first gate structure 110. Before forming the gate dielectric layer 13, other film layers may be formed on the second region A2, resulting in a height difference between the film layers on the first region A1 and the second region A2, with the top surface of the first portion 114 being lower than the top surface of the second portion 214. However, this embodiment does not constitute a limitation on the inventive concept of this disclosure. In some other embodiments, in the vertical direction (the direction perpendicular to the top surface of the substrate 11), the top surface of the first portion 114 may be flush with the top surface of the second portion 214, i.e., located on the same horizontal plane. In other embodiments, in the vertical direction (the direction perpendicular to the top surface of the substrate 11), the top surface of the first portion 114 may also be higher than the top surface of the second portion 214.

[0068] In step S104, please refer to Figure 3 , Figure 5 As shown, a protective layer 15 is formed on the first region A1. The protective layer 15 only covers the first portion 114 of the metal oxide layer 14, exposing the second portion 214 of the metal oxide layer 14. In some embodiments, forming the protective layer 15 includes the following steps:

[0069] Step S41: Form a protective material layer 15a on the first region A1 and the second region A2. (Refer to...) Figure 3 As shown, a protective material layer 15a can be deposited using ALD, CVD, or PVD processes. The protective material layer 15a covers the first portion 114 and the second portion 214 of the metal oxide layer 14. In this embodiment, in the vertical direction (perpendicular to the top surface of the substrate 11), the thickness of the protective material layer 15a located in the first region A1 and the protective material layer 15a located in the second region A2 can be the same or different, but the top surface of the protective material layer 15a located in the first region A1 is lower than the top surface of the protective material layer 15a located in the second region A2. For example, the material of the protective material layer 15a may include at least one of monocrystalline silicon, polycrystalline silicon, or amorphous silicon.

[0070] Step S42: Remove the protective material layer 15a on the second region A2 and form a protective layer 15 on the first region A1. In this embodiment, refer to... Figure 3 As shown, a mask layer 17 can be formed on the protective material layer 15a, covering the protective material layer 15a located in the first region A1 and exposing the protective material layer 15a located in the second region A2. The protective material layer 15a located in the second region A2 is etched according to the mask layer 17, removing a portion of the protective material layer 15a located in the second region A2, so that the remaining thickness of the protective material layer 15a located in the second region A2 is less than the thickness of the protective material layer 15a located in the first region A1. In some embodiments, after etching the protective material layer 15a located in the second region A2 according to the mask layer 17, the top surface of the protective material layer 15a located in the second region A2 is lower than the top surface of the protective material layer 15a located in the first region A1. For example, a dry etching process can be used to etch the protective material layer 15a in the second region A2. Then, the mask layer 17 is removed, exposing the protective material layer 15a located in the first region A1.

[0071] Step S43: Refer to Figure 4 , Figure 5As shown, the protective material layer 15a located in the first region A1 and the protective material layer 15a located in the second region A2 are etched simultaneously, completely removing the protective material layer 15a located in the second region A2, exposing the second portion 214 of the metal oxide layer 14 located in the second region A2. Since the thickness of the protective material layer 15a located in the first region A1 is greater than the thickness of the protective material layer 15a located in the second region A2, after all the protective material layer 15a located in the second region A2 is etched away, there is still a protective material layer 15a located in the first region A1 that has not been etched away. The remaining protective material layer 15a located in the first region A1 covers the first portion 114 of the metal oxide layer 14, forming a protective layer 15.

[0072] For example, a wet etching process can be used to etch the protective material layer 15a. For instance, ammonium hydroxide (NH4OH) can be used as the etching solution. In step S105, refer to... Figure 6 As shown, a wet etching process can be used to remove the second portion 214 of the metal oxide layer 14. For example, hydrogen chloride (HCl) can be used to etch and remove the second portion 214 of the metal oxide layer 14. Hydrogen chloride has a high etching selectivity for the metal oxide layer 14 without etching the protective layer 15. Thus, after the second portion 214 of the metal oxide layer 14 is removed by hydrogen chloride etching, exposing the gate dielectric layer 13 located in the second region A2, the structure of the protective layer 15 located in the first region A1 remains relatively intact, avoiding damage from etching by the etching solution. The protective layer 15 covers the first portion 114 of the metal oxide layer 14, preventing the first portion 114 from being contaminated by the etching solution, thus achieving selective etching of the second portion 214 of the metal oxide layer 14.

[0073] In step S106, refer to Figure 7 As shown, the protective layer 15 can be etched away using a wet or dry process to expose the first portion 114 of the metal oxide layer 14. For example, the protective layer 15 can be removed using ammonium hydroxide etching, which avoids damaging the first portion 114 of the metal oxide layer 14 during the etching process, thus allowing the first gate structure 110 formed in the first region A1 (see reference). Figure 9 , Figure 10 The complete structure of semiconductors is beneficial to improving their electrical performance and reliability.

[0074] The semiconductor structure fabrication method of this embodiment involves etching a protective material layer 15a on a mask layer 17 to form a protective material layer 15a with a thickness difference on a metal oxide layer 14. The thickness of the protective material layer 15a located in the first region A1 is greater than the thickness of the protective material layer 15a located in the second region A2. After etching away the protective material layer 15a in the second region A2, the thickness of the protective material layer 15a located in the first region A1 is reduced. The remaining protective material layer 15a after etching the first region A1 can continue to protect the first portion 114 of the metal oxide layer 14, thereby achieving selective etching of the second portion 214 of the metal oxide layer 14. At the same time, it can shorten the time required to remove the protective layer 15, save process time, and improve production efficiency.

[0075] In some other embodiments, reference is made to Figure 3 , Figure 5 Alternatively, after forming the mask layer 17, all of the protective material layer 15a located in the second region A2 can be directly etched away based on the mask layer 17, and the protective material layer 15a located in the first region A1 can form the protective layer 15. Then, the second portion 214 of the metal oxide layer 14 located in the second region A2 is etched away, exposing the top surface of the gate dielectric layer 13 located in the second region A2. Subsequently, the mask layer 17 and the protective layer 15 are removed, exposing the first portion 114 of the metal oxide layer 14 located in the first region A2.

[0076] In some embodiments, the following steps are performed before forming the gate dielectric layer 13 in step S102:

[0077] Step S102-1: A stress adjustment layer 12 is formed on the second region A2, and the stress adjustment layer 12 is in direct contact with the substrate 11 of the second region A2. In this embodiment, a first device 100 is formed in the first region A1, and a second device 200 is formed in the second region A2. To improve the performance of the second device 200, in this embodiment, reference is made to... Figure 2 As shown, before forming the gate dielectric layer 13, a stress adjustment layer 12 is formed on the substrate 11 of the second region A2, and the stress adjustment layer 12 serves as the channel of the second device 200.

[0078] In some embodiments, the substrate 11 is a silicon substrate, and the stress adjustment layer 12 is made of germanium-silicon. Germanium has a higher carrier mobility, and the lattice constant of germanium-silicon is greater than that of silicon. The substrate 11 applies compressive stress to the stress adjustment layer 12, which increases the carrier (electron or hole) mobility of the stress adjustment layer 12, thus improving the driving current and response speed of the second device 200. In other embodiments, the stress adjustment layer 12 may not be formed on the second region A2. Instead, germanium ions can be implanted into the surface of the substrate 11 in the second region A2, using the germanium-doped silicon material as the channel of the second device 200 to improve the carrier mobility of the second device 200.

[0079] In some embodiments, step S102, forming the gate dielectric layer 13, includes the following steps:

[0080] Step S1021: Form a first gate dielectric layer 131, located on the substrate 11 of the first region A1 and on the stress adjustment layer 12. (Refer to...) Figure 2 As shown, the first gate dielectric layer 131 can be formed using processes such as in-situ steam generation (ISSG), ALD, and PVD. The material of the first gate dielectric layer 131 may include at least one of silicon dioxide or silicon oxynitride. The first gate dielectric layer 131 is disposed between the substrate 11 and the metal oxide layer 14 (the high dielectric constant layer of the first device 100), and between the substrate 11 and the high dielectric constant layer of the second device 200. The first gate dielectric layer 131 serves as the interface between the substrate 11 and the metal oxide layer 14 of the first device 100, and between the substrate 11 and the high dielectric constant layer of the second device 200, which is beneficial for improving the carrier mobility of the first device 100 and the second device 200.

[0081] Step S1022: Form a second gate dielectric layer 132, located on the first gate dielectric layer 131, forming a gate dielectric layer 13. (Refer to...) Figure 2 As shown, the second gate dielectric layer 132 is a high dielectric constant layer of the first device 100. The material of the second gate dielectric layer 132 may include hafnium silicate (HfSiO2). x The material of the metal oxide layer 14 is at least one of hafnium oxysilane (HfSiON), hafnium oxide (HfSiO4), or hafnium dioxide (HfO2). In some embodiments, the material of the metal oxide layer 14 includes hafnium silicate, whose high dielectric constant can reduce the effect of the gate voltage on the substrate 11 and reduce the gate-induced leakage current effect of the first device 100.

[0082] In some embodiments, after removing the protective layer 15 in step S106, the following steps are also performed:

[0083] Step S107: Form the power function layer 16, located on the first portion 114 of the metal oxide layer 14 and on the gate dielectric layer 13 of the second region A2. (Refer to...) Figure 8 As shown, the work function layer 16 may include a first barrier layer 161, a semiconductor layer 162, a second barrier layer 163, and a metal gate layer 164 stacked sequentially. The first barrier layer 161 is made of a metallic material, such as titanium nitride or other metal nitrides; the semiconductor layer 162 may be made of polysilicon; and the second barrier layer 163 is also made of a metallic material, such as titanium nitride or other metal nitrides. The metal gate layer 164 is formed on the side of the second barrier layer 163 away from the semiconductor layer 162, and the metal gate layer 164 may be made of tungsten, titanium, tantalum, etc. Thus, using a metallic material as the gate material can improve the pinning phenomenon of the Fermi level and avoid the depletion problem of polysilicon gates. Simultaneously, the second barrier layer 163 can prevent the metallic material of the metal gate layer 164 from diffusing into the semiconductor layer 162, preventing the metallic material of the metal gate layer 164 from contaminating other devices or films.

[0084] For example, a first barrier layer 161 can be formed by ALD, MOCVD, or PVD deposition. A semiconductor layer 162 can be formed by ALD or CVD deposition. A second barrier layer 163 can be formed by ALD, MOCVD, or PVD deposition. A metal gate layer 164 can be formed by ALD, MOCVD, or PVD deposition.

[0085] In this embodiment, please continue to refer to... Figure 8 As shown, after forming the work function layer 16, an isolation layer 18 is formed on the side of the work function layer 16 away from the substrate 11. The material of the isolation layer 18 may include at least one of silicon oxide, silicon nitride, silicon oxynitride, or silicon oxycarbide. For example, the isolation layer 18 may be formed by ALD or CVD deposition.

[0086] Step S108: A first gate structure is formed in the first region, and a second gate structure is formed in the second region.

[0087] In this embodiment, a photoresist layer (not shown) is formed on the side of the isolation layer 18 away from the substrate 11. An exposure-development process is performed on the photoresist layer to pattern the photoresist layer, defining the patterns of the first gate structure 110 and the second gate structure 210. (Refer to...) Figure 9 As shown, the isolation layer 18, work function layer 16, metal oxide layer 14, gate dielectric layer 13 and stress adjustment layer 12 are etched according to the patterned photoresist layer to form a first gate structure 110 in the first region A1 and a second gate structure 110 in the second region A2.

[0088] Step S109: A first source and a first drain are formed in the first region on both sides of the first gate structure to form a first device 100; a second source and a second drain are formed in the second region on both sides of the second gate structure to form a second device 200. Please continue to refer to... Figure 9 As shown, P-type doped ions can be implanted into the substrates 11 on both sides of the first gate structure 110 to form a first source 120 and a first drain 130. The first gate structure 110, the first source 120, and the first drain 130 together form a first device 100. P-type doped ions can be implanted into the substrates 11 on both sides of the second gate structure 210 to form a second source 220 and a second drain 230. The second gate structure 210, the second source 220, and the second drain 230 together form a second device 200.

[0089] It is understood that the above embodiments are preferred implementations of the semiconductor structure fabrication method of this disclosure and do not constitute a limitation on this disclosure.

[0090] For example, in some other embodiments of this application, in step S102, the step of forming the gate dielectric layer 13 may only form the first gate dielectric layer 131, that is, the gate dielectric layer 13 in this embodiment only includes a single-layer structure of the first gate dielectric layer 131. Then, steps S103-S106 are directly executed to form a metal oxide layer 14 only on the first region A1. Subsequently, a second gate dielectric layer 132 is deposited to form, which covers the metal oxide layer 14 in the first region A1 and the first gate dielectric layer 131 in the second region A2.

[0091] In other embodiments of this application (not shown in the accompanying drawings), after forming the gate dielectric layer 13 in step S102, a first protective layer can be formed to cover the gate dielectric layer 13 located in the second region A2, and the second gate dielectric layer 132 located in the first region A1 is etched away. Then, a metal oxide layer 14 is formed to cover the gate dielectric layer 13, a second protective layer is formed to cover the metal oxide layer 14 located in the first region A1, and the metal oxide layer 14 located in the second region A2 is etched away. Thus, the metal oxide layer 14 of the formed first gate structure 110 is in direct contact with the first gate dielectric layer 131, the first gate structure 110 has no second gate dielectric layer 132, and the second gate structure 210 has no metal oxide layer 14, resulting in a semiconductor structure different from other embodiments.

[0092] According to an exemplary embodiment, this embodiment provides a semiconductor structure, referring to... Figure 9 or Figure 10As shown, the semiconductor structure of this embodiment is fabricated using the semiconductor structure fabrication method of the above embodiment. During the fabrication process of the semiconductor structure of this embodiment, a protective layer 15 is formed after the metal oxide layer 14 is formed. The protective layer 15 is used to protect the metal oxide layer 14 located in the first region A1, thereby achieving selective etching of the metal oxide layer 14 located in the second region A2. This avoids damage to the metal oxide layer 14 located in the first region A1 during the etching process of removing the metal oxide layer 14 located in the second region A2, which is beneficial to improving the electrical performance and reliability of the semiconductor structure.

[0093] According to an exemplary embodiment, this embodiment provides a semiconductor structure, such as... Figure 9 As shown, the semiconductor structure includes a substrate 11, a first gate structure 110, and a second gate structure 210. The substrate 11 includes a first region A1 and a second region A2. The first gate structure 110 is disposed in the first region A1. A first source 120 and a first drain 130 are formed on the substrate 11 on both sides of the first gate structure 110. The first gate structure 110, the first source 120, and the first drain 130 together form a first device 100. The first gate structure 110 includes a stacked gate dielectric layer 13, a metal oxide layer 14, and a work function layer 16. The second gate structure 210 is disposed in the second region A2. A second source 220 and a second drain 230 are formed on the substrate 11 on both sides of the second gate structure 210. The second gate structure 210, the second source 220, and the second drain 230 together form a second device 200. The second gate structure 210 includes a stress adjustment layer 12, a gate dielectric layer 13, and a work function layer 16 stacked on the second region A2.

[0094] In this embodiment, the metal oxide layer 14 of the first gate structure 110 has complete structure and function, the metal oxide layer 14 of the first gate structure 110 has less etching damage, and the second gate structure 210 reduces the residual metal oxide layer 14, which is beneficial to improving the electrical performance and reliability of the semiconductor structure.

[0095] In some embodiments, such as Figure 9 As shown, the first region A1 is an NMOS region, and the second region A2 is a PMOS region. The first device 100 is an NMOS device, and the second device 200 is a PMOS device. In some embodiments, as... Figure 9 As shown, the gate dielectric layer 13 includes a first gate dielectric layer 131 and a second gate dielectric layer 132 stacked together; wherein the material of the first gate dielectric layer 131 includes silicon oxynitride. The material of the second gate dielectric layer 132 includes at least one of hafnium silicate, hafnium silicon oxynitride, hafnium oxide, or hafnium dioxide. In some embodiments, such as Figure 9As shown, the material of the metal oxide layer 14 includes at least one of aluminum oxide or lanthanum oxide. The material of the metal oxide layer 14 may also include at least one of tantalum oxide, yttrium oxide, zirconium dioxide, strontium titanate, or zirconium silicate oxide. In some embodiments, such as... Figure 9 As shown, the work function layer 16 includes a first barrier layer 161, a semiconductor layer 162, a second barrier layer 163, and a metal gate layer 164 stacked sequentially. The first barrier layer 161 is made of a metallic material, such as titanium nitride or other metal nitrides; the semiconductor layer 162 may be made of polysilicon; the second barrier layer 163 is made of a metallic material, such as titanium nitride or other metal nitrides; and the metal gate layer 164 may be made of tungsten.

[0096] In other embodiments, the semiconductor structure is as follows: Figure 10 As shown, the first gate structure 110 of the first device 100 includes a first gate dielectric layer 131, a metal oxide layer 14, and a work function layer 16 stacked on the first region A1. The work function layer 16 includes a first barrier layer 161 and a metal gate layer 164 sequentially stacked on the metal oxide layer 14. The second gate structure 110 of the second device 200 includes a first gate dielectric layer 131, a second gate dielectric layer 132, and a work function layer 16 stacked on the second region A2. The work function layer 16 includes a first barrier layer 161 and a metal gate layer 164 sequentially stacked on the second gate dielectric layer 132. The first device 100 is an NMOS device, and the second device 200 is a PMOS device. The material of the first gate dielectric layer 131 includes silicon oxynitride. The material of the second gate dielectric layer 132 includes at least one of hafnium silicate, hafnium silicon oxynitride, hafnium oxide, or hafnium dioxide. The material of the metal oxide layer 14 includes at least one of aluminum oxide or lanthanum oxide. Alternatively, the material of the metal oxide layer 14 may include at least one of tantalum oxide, yttrium oxide, zirconium dioxide, strontium titanate, or zirconium silicate oxide.

[0097] In some other embodiments, the semiconductor structure of this embodiment includes a first gate structure 110 of the first device 100, which includes a first gate dielectric layer 131, a metal oxide layer 14, a second gate dielectric layer 132, and a work function layer 16 stacked on the first region A1; and a second gate structure 110 of the second device 200, which includes a first gate dielectric layer 131, a second gate dielectric layer 132, and a work function layer 16 stacked on the second region A2.

[0098] The semiconductor structure in the above embodiments can be Dynamic Random Access Memory (DRAM), Static Random-Access Memory (SRAM), Flash EPROM, Ferroelectric Random Access Memory (FeRAM), Magnetic Random-Access Memory (MRAM), or other types of memory.

[0099] According to an exemplary embodiment, this embodiment provides an electronic device including the semiconductor structure described in the above embodiments. The electronic device can be a storage device, mobile phone, computer, tablet computer, television, artificial intelligence device, etc.

[0100] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The embodiments described above are merely illustrative of several implementations of this disclosure, and while the descriptions are specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this disclosure, and these all fall within the scope of protection of this disclosure. Therefore, the scope of protection of this patent should be determined by the appended claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A gate dielectric layer is formed on the substrate; Forming a metal oxide layer on the substrate includes: The first part is located in the first zone; The second part is located in the second zone; In the vertical direction, the top surface of the first part is lower than the top surface of the second part; A protective material layer is formed on the first and second regions; A mask layer is formed on the protective material layer, the mask layer covering the protective material layer located in the first region and exposing the protective material layer located in the second region; Remove the protective material layer on the second region and form a protective layer on the first region, the protective layer being in direct contact with the metal oxide layer; Remove the second portion located in the metal oxide layer; Remove the protective layer.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first region is an NMOS region, and the second region is a PMOS region.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Before forming the gate dielectric layer, the following steps are also included: A stress adjustment layer is formed on the second region, and the stress adjustment layer is in direct contact with the substrate of the second region.

4. The method for fabricating a semiconductor structure according to claim 3, characterized in that, Forming a gate dielectric layer includes: A first gate dielectric layer is formed on the substrate and the stress adjustment layer in the first region; A second gate dielectric layer is formed on top of the first gate dielectric layer.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The manufacturing method further includes: A power function layer is formed on the first portion of the metal oxide layer and on the gate dielectric layer of the second region.

6. A semiconductor structure, characterized in that, include: Substrate, the substrate comprising a first region and a second region; A first gate structure is disposed in the first region, and the first gate structure includes a stacked gate dielectric layer, a metal oxide layer, and a work function layer. A second gate structure is disposed in the second region. The second gate structure includes a stress adjustment layer, a gate dielectric layer, and a work function layer stacked on the second region. In the vertical direction, the top surface of the metal oxide layer in the first region is lower than the top surface of the gate dielectric layer in the second region.

7. The semiconductor structure according to claim 6, characterized in that, The first region is an NMOS region, and the second region is a PMOS region.

8. The semiconductor structure according to claim 6, characterized in that, The gate dielectric layer includes a stacked first gate dielectric layer and a second gate dielectric layer; The material of the first gate dielectric layer includes silicon oxynitride.

9. The semiconductor structure according to claim 6, characterized in that, The material of the metal oxide layer includes at least one of aluminum oxide or lanthanum oxide.

10. A method for fabricating a semiconductor structure, characterized in that, include: A substrate is provided, the substrate comprising a first region and a second region; A stress adjustment layer is formed on the second region, and the stress adjustment layer is in direct contact with the substrate of the second region; A gate dielectric layer is formed on the substrate in the first region and the stress adjustment layer in the second region; Forming a metal oxide layer on the substrate includes: The first part is located in the first zone; The second part is located in the second zone; In the vertical direction, the top surface of the first part is lower than the top surface of the second part; A protective layer is formed on the first region, and the protective layer is in direct contact with the metal oxide layer; Remove the second portion located in the metal oxide layer; Remove the protective layer.

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