Display device, wearable electronic device, and method of manufacturing display device

Abstract

A display device, a wearable electronic device, and a method of manufacturing the display device are provided. The display device comprises a first sub-pixel, a second sub-pixel and a third sub-pixel, wherein each of the first sub-pixel, the second sub-pixel, and the third sub-pixel includes a reflective electrode on the base layer, a planarization layer on the reflective electrode and configured to provide a flat upper surface, a positive electrode on the planarization layer, an emission structure on the positive electrode, and a negative electrode on the emission structure, wherein the first sub-pixel further includes a first buffer pattern between the base layer and the reflective electrode, and wherein, in the third sub-pixel, the reflective electrode is directly on the base layer.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0151686 filed in the Korean Intellectual Property Office on November 6, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] Aspects of some embodiments of the present disclosure relate to a display device, a wearable electronic device, and a method of manufacturing a display device. Background Art

[0004] Organic light emitting diodes (OLEDs) are active emission display elements that not only have the characteristics of a large viewing angle and excellent contrast, but can also be operated at a relatively low voltage. OLEDs have the advantages of being relatively lightweight and thin and having relatively fast response time characteristics.

[0005] The above information disclosed in this Background section is only for enhancement of background understanding and therefore the information discussed in this Background section does not necessarily constitute prior art. Summary of the invention

[0006] Aspects of some embodiments of the present disclosure relate to a display device having relatively improved optical characteristics, a wearable electronic device, and a method of manufacturing the display device.

[0007] The embodiments according to the present disclosure are not limited to the above-mentioned features, and other unmentioned features will be clearly understood by those skilled in the art from the accompanying claims and their equivalents.

[0008] Aspects of some embodiments of the present disclosure may include a display device including a first sub-pixel, a second sub-pixel, and a third sub-pixel. According to some embodiments, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may include: a reflective electrode on a base layer, a planarization layer on the reflective electrode and configured to provide a flat upper surface, an anode electrode on the planarization layer, an emission structure on the anode electrode, and a cathode electrode on the emission structure. According to some embodiments, the first sub-pixel may also include a first buffer pattern between the base layer and the reflective electrode. According to some embodiments, in the third sub-pixel, the reflective electrode may be directly on the base layer.

[0009] According to some embodiments, an average distance between the anode electrode and the reflective electrode in the first sub-pixel may be smaller than an average distance between the anode electrode and the reflective electrode in the third sub-pixel.

[0010] According to some embodiments, the first sub-pixel may further include a second buffer pattern between the first buffer pattern and the reflective electrode. According to some embodiments, the second sub-pixel may further include a first buffer pattern between the base layer and the reflective electrode. According to some embodiments, the average distance between the anode electrode and the reflective electrode in the second sub-pixel may be smaller than the average distance between the anode electrode and the reflective electrode in the third sub-pixel and greater than the average distance between the anode electrode and the reflective electrode in the first sub-pixel.

[0011] According to some embodiments, a thickness of the anode electrode in the first sub-pixel, a thickness of the anode electrode in the second sub-pixel, and a thickness of the anode electrode in the third sub-pixel may be equal to each other.

[0012] According to some embodiments, the first buffer pattern may include a conductive material. According to some embodiments, the second buffer pattern may include an insulating material.

[0013] According to some embodiments, a thickness of the first buffer pattern may be substantially equal to a thickness of the second buffer pattern.

[0014] According to some embodiments, the average thickness of the planarization layer in the second sub-pixel may be about 1.4 times to about 1.7 times the average thickness of the planarization layer in the first sub-pixel. According to some embodiments, the average thickness of the planarization layer in the third sub-pixel may be about 1.9 times to about 2.4 times the average thickness of the planarization layer in the first sub-pixel.

[0015] According to some embodiments, the emission structure may include: a first emission layer commonly arranged in the first subpixel, the second subpixel, and the third subpixel and configured to emit light of a first color, and a second emission layer on the first emission layer and configured to emit light of a second color.

[0016] According to some embodiments, the emission structure may further include a third emission layer on the second emission layer and configured to emit light of a third color.

[0017] According to some embodiments, in the second sub-pixel, the reflective electrode may be directly on the base layer.

[0018] According to some embodiments, the anode electrode may cover the reflective electrode and contact a side surface of the reflective electrode.

[0019] According to some embodiments, the display device may further include: a pixel defining layer on the base layer between the first to third subpixels, and a protrusion pattern on the pixel defining layer and having a width increasing in an upward direction.

[0020] According to some embodiments, the display device may further include: a plurality of grooves formed to partially penetrate the planarization layer in a boundary region between the first to third sub-pixels. The plurality of grooves may be separated from each other.

[0021] According to some embodiments, each of the first to third sub-pixels may further include a color filter on the cathode electrode.

[0022] Aspects of some embodiments of the present disclosure may include a wearable electronic device, the wearable electronic device including: a display panel configured to emit light, and at least one lens on the display panel. According to some embodiments, the display panel may include a first sub-pixel, a second sub-pixel, and a third sub-pixel. According to some embodiments, each of the first sub-pixel, the second sub-pixel, and the third sub-pixel may include: a reflective electrode on a base layer, a planarization layer on the reflective electrode and configured to provide a flat upper surface, an anode electrode on the planarization layer, an emission structure on the anode electrode, and a cathode electrode on the emission structure. According to some embodiments, the first sub-pixel may also include a first buffer pattern between the base layer and the reflective electrode. In the third sub-pixel, the reflective electrode may be directly on the base layer.

[0023] According to some embodiments, an average distance between the anode electrode and the reflective electrode in the first sub-pixel may be smaller than an average distance between the anode electrode and the reflective electrode in the third sub-pixel.

[0024] According to some embodiments, the first sub-pixel may further include a second buffer pattern between the first buffer pattern and the reflective electrode. According to some embodiments, the second sub-pixel may further include a first buffer pattern between the base layer and the reflective electrode. According to some embodiments, the average distance between the anode electrode and the reflective electrode in the second sub-pixel may be smaller than the average distance between the anode electrode and the reflective electrode in the third sub-pixel and greater than the average distance between the anode electrode and the reflective electrode in the first sub-pixel.

[0025] Aspects of some embodiments of the present disclosure may include a method for manufacturing a display device, the method including: forming a buffer pattern on a base layer in a first sub-pixel region; forming a reflective electrode throughout the buffer pattern in the first sub-pixel region and in a second sub-pixel region and a third sub-pixel region of the base layer; forming a planarization layer to cover the reflective electrode and provide a flat upper surface; and forming a light emitting element on the planarization layer. According to some embodiments, in the third sub-pixel region, the reflective electrode may be directly on the base layer.

[0026] According to some embodiments, forming the buffer pattern may include: forming a first buffer pattern in each of the first to third sub-pixel regions, and forming a second buffer pattern on the first buffer pattern; forming a photoresist layer in the first sub-pixel region, and removing the second buffer pattern from the second and third sub-pixel regions; and forming a photoresist layer in the first and second sub-pixel regions, and removing the first buffer pattern from the third sub-pixel region. The buffer pattern of the first sub-pixel region may include a first buffer pattern and a second buffer pattern.

[0027] According to some embodiments, the first buffer pattern may include a conductive material, and the second buffer pattern may include an insulating material.

[0028] Further details of various embodiments are included in the detailed description and accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a block diagram illustrating aspects of a display device according to some embodiments.

[0030] Figure 2 is a diagram showing some embodiments of the present invention. Figure 1 A block diagram of various aspects of any one of the sub-pixels.

[0031] Figure 3 is a diagram showing some embodiments of the present invention. Figure 2 Circuit diagram of various aspects of a sub-pixel.

[0032] Figure 4 is a diagram showing some embodiments of the present invention. Figure 1 A plan view showing further details of the panel.

[0033] Figure 5 is a diagram showing some embodiments of the present invention. Figure 4 An exploded perspective view of various aspects of a portion of a display panel.

[0034] Figure 6 is a diagram showing some embodiments of the present invention. Figure 5 A plan view of further details of any one of the pixels.

[0035] Figure 7 is a diagram showing the Figure 6 A cross-sectional view of various aspects of a pixel taken along line II'.

[0036] Figure 8 is a diagram showing the Figure 6 A cross-sectional view of further details of the pixel taken along line II'.

[0037] Fig. 9 is a diagram showing the Figure 6 A cross-sectional view of further details of the pixel taken along line II'.

[0038] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.10E and Fig.10F is a cross-sectional view for describing a method of manufacturing a display device according to some embodiments.

[0039] Fig.11 is a diagram showing the inclusion of Figure 7 A cross-sectional view of various aspects of the emission structure in any one of the first to third light-emitting elements.

[0040] Fig.12 is a diagram showing the inclusion of Figure 7 A cross-sectional view of various aspects of the emission structure in any one of the first to third light-emitting elements.

[0041] Fig.13 is a diagram showing the Figure 6 A cross-sectional view of further details of the pixel taken along line II'.

[0042] Fig.14 is a diagram showing some embodiments of the present invention. Figure 5 A floor plan of the pixels for further details.

[0043] Fig.15 is a diagram showing some embodiments of the present invention. Figure 5 A floor plan of the pixels for further details.

[0044] Fig.16 is a block diagram illustrating aspects of a display system according to some embodiments.

[0045] Fig.17 is a diagram showing some embodiments of the present invention. Fig.16 A perspective view showing an application example of the display system.

[0046] Fig.18 FIG. 1 is a diagram showing a device worn on a user according to some embodiments. Fig.17 FIG. 1 is a diagram of a head mounted display device. DETAILED DESCRIPTION

[0047] Hereinafter, various aspects of some disclosed embodiments will be described in more detail with reference to the accompanying drawings. In the following description, only the parts required for understanding the operation according to the present disclosure will be described, and the explanation of other parts may be omitted so as not to make the subject of the present disclosure unclear. Accordingly, the present disclosure is not limited to the embodiments set forth herein, but may be implemented in other types. On the contrary, these embodiments are provided so that the present disclosure will be thorough and complete, and the technical spirit of the present disclosure will be fully conveyed to those skilled in the art.

[0048] It should be understood that when an element is referred to as "connected" or "connected" to another element, it can be directly connected or connected to another element, or there may be an intermediate element between them. The terms used herein are for the purpose of describing specific embodiments only, and are not intended to be limiting. In the specification, when an element is referred to as "including" or "comprising" a component, it does not exclude another component, and may also include other components, unless otherwise clearly indicated in the context. In the present disclosure, the phrases "at least one of X, Y, and Z" and "at least one selected from the cluster consisting of X, Y, and Z" may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z (e.g., XYZ, XY, YZ, and XZ). As used herein, the term "and / or" may include any and all combinations of one or more of the items listed in the relevant.

[0049] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below may be referred to as the second element.

[0050] Spatially relative terms such as "beneath," "below," "under," "lower," "above," "upper," "over," "higher," "side" (e.g., as in "sidewall"), and similar may be used herein for descriptive purposes, and thus, to describe the relationship of one element or feature to another element or feature as shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is turned upside down, elements described as being "below" or "beneath" other elements or features would subsequently be oriented to be "above" the other elements or features. Thus, the term "below" is capable of including both above and below orientations. Furthermore, the device may be oriented in other ways (e.g., rotated 90 degrees or in other orientations), and thus, the spatially relative descriptors used herein are interpreted accordingly.

[0051] Herein, aspects of some embodiments will be described in more detail with reference to the accompanying drawings which are schematic illustrations of idealized embodiments. Thus, variations in the shapes of the illustrations resulting from, for example, manufacturing techniques and / or tolerances are to be expected. Therefore, the embodiments disclosed herein should not be construed as limited to the shapes of the specific illustrated regions, but rather include deviations in shape resulting from, for example, manufacturing. Thus, the shapes illustrated in the accompanying drawings may not illustrate the actual shapes of the regions of the device, and are thus not intended to be limiting.

[0052] Figure 1 is a block diagram illustrating aspects of a display device 100 according to some embodiments.

[0053] Reference Figure 1 , the display device 100 may include a display panel DP (or a display member), a gate driver 120 , a data driver 130 , a voltage generator 140 , and a controller 150 .

[0054] The display panel DP may include a plurality of sub-pixels SP. The plurality of sub-pixels SP may be connected to the gate driver 120 through first to m-th gate lines GL1 to GLm. The plurality of sub-pixels SP may be connected to the data driver 130 through first to n-th data lines DL1 to DLn. Each of n and m may be an integer greater than 1.

[0055] Each of the plurality of sub-pixels SP may include at least one light emitting element configured to generate light. Accordingly, each of the plurality of sub-pixels SP may generate light of a specific color such as red, green, blue, cyan, magenta, or yellow. Two or more sub-pixels among the plurality of sub-pixels SP may form one pixel PXL. For example, Figure 1 As shown in FIG. , three sub-pixels may form one pixel PXL.

[0056] The gate driver 120 may be connected to the sub-pixels SP arranged in the row direction through the first to m-th gate lines GL1 to GLm. The gate driver 120 may output gate signals to the first to m-th gate lines GL1 to GLm in response to the gate control signal GCS. According to some embodiments, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting a gate signal in synchronization with a timing of applying a data signal, and the like.

[0057] According to some embodiments, first to m-th emission control lines EL1 to ELm connected to the sub-pixels SP in the row direction may also be provided. In this case, the gate driver 120 may include an emission control driver configured to control the first to m-th emission control lines EL1 to ELm. The emission control driver may operate under the control of the controller 150.

[0058] The gate driver 120 may be positioned on one side of the display panel DP. However, the embodiment is not limited to the above example. For example, the gate driver 120 may be divided into two or more drivers that are physically and / or logically distinguished from each other. The driver may be positioned on a first side of the display panel DP and on a second side of the display panel DP opposite to the first side. Thus, the gate driver 120 may be arranged around the display panel DP in various forms according to the embodiment.

[0059] The data driver 130 may be connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the nth data line DLn. The data driver 130 may receive the image data DATA and the data control signal DCS from the controller 150. The data driver 130 may operate in response to the data control signal DCS. According to some embodiments, the data control signal DCS may include a source start pulse, a source shift clock, a source output enable signal, and the like.

[0060] The data driver 130 may apply a data signal having a grayscale voltage corresponding to the image data DATA to the first to n-th data lines DL1 to DLn using a voltage from the voltage generator 140. When a gate signal is applied to each of the first to m-th gate lines GL1 to GLm, a data signal corresponding to the image data DATA may be applied to the first to n-th data lines DL1 to DLn. Therefore, the corresponding sub-pixel SP may generate light corresponding to the data signal. As a result, an image may be displayed on the display panel DP.

[0061] According to some embodiments, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0062] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and provide the generated voltages to components of the display device 100. For example, the voltage generator 140 may receive an input voltage from an external device provided outside the display device 100, adjust the received voltage, and regulate the adjusted voltage, thereby generating the plurality of voltages.

[0063] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS. The generated first power supply voltage VDD and the second power supply voltage VSS may be provided to the sub-pixel SP. The first power supply voltage VDD may have a relatively high voltage level. The second power supply voltage VSS may have a voltage level lower than the voltage level of the first power supply voltage VDD. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be provided by an external device of the display device 100.

[0064] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage to be applied to the sub-pixel SP. For example, during a sensing operation for sensing electrical characteristics of a transistor and / or a light-emitting element of the sub-pixel SP, a certain reference voltage may be applied to each of the first to n-th data lines DL1 to DLn. The voltage generator 140 may generate a reference voltage.

[0065] The controller 150 may control the overall operation of the display device 100. The controller 150 may receive input image data IMG and a control signal CTRL for controlling an operation of displaying the input image data IMG from an external device. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0066] The controller 150 may convert the input image data IMG to be suitable for the display device 100 or the display panel DP and then output the image data DATA. According to some embodiments, the controller 150 may align the input image data IMG by rows to be suitable for the sub-pixels SP and then output the image data DATA.

[0067] Two or more components of the data driver 130, the voltage generator 140, and the controller 150 may be mounted into a single integrated circuit. Figure 1 As shown in , the data driver 130, the voltage generator 140 and the controller 150 may be included in the driving integrated circuit DIC. In this case, the data driver 130, the voltage generator 140 and the controller 150 may be functionally separated components in a single driving integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140 and the controller 150 may be provided as a component separated from the driving integrated circuit DIC.

[0068] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense an ambient temperature and generate temperature data TEP indicating the sensed temperature. According to some embodiments, the temperature sensor 160 may be positioned adjacent to the display panel DP and / or the driving integrated circuit DIC.

[0069] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. According to some embodiments, the controller 150 may adjust the brightness of an image output from the display panel DP in response to the temperature data TEP. For example, the controller 150 may control components such as the data driver 130 and / or the voltage generator 140 to adjust the data signal and the first power supply voltage VDD and the second power supply voltage VSS.

[0070] Figure 2 is a diagram showing some embodiments of the present invention. Figure 1 A block diagram of various aspects of any one of the sub-pixels SP. Figure 2 , a sub-pixel SPij located in the i-th row (where i is an integer greater than or equal to 1 and less than or equal to m) and the j-th column (where j is an integer greater than or equal to 1 and less than or equal to n) is shown.

[0071] Reference Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0072] The light emitting element LD is connected between the first power supply voltage node VDDN and the second power supply voltage node VSSN. Here, the first power supply voltage node VDDN may be provided as a transmission Figure 1The second power supply voltage node VSSN may be a node provided to transmit the second power supply voltage VSS.

[0073] The anode electrode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC. The cathode electrode CE of the light emitting element LD may be connected to the second power supply voltage node VSSN. For example, the anode electrode AE ​​of the light emitting element LD may be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0074] The sub-pixel circuit SPC can be connected to Figure 1 The i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm, Figure 1 The i-th emission control line ELi among the first emission control line EL1 to the m-th emission control line ELm and Figure 1 The sub-pixel circuit SPC is configured to control the light emitting element LD in response to a signal received through the above-mentioned signal line.

[0075] The sub-pixel circuit SPC may operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. Figure 2 As shown in , the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC may operate in response to a gate signal received through the first sub-gate line SGL1 and the second sub-gate line SGL2. Thus, in the case where the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC may operate in response to a gate signal received through the corresponding sub-gate line.

[0076] The sub-pixel circuit SPC may operate in response to an emission control signal received through the i-th emission control line ELi. According to some embodiments, the i-th emission control line ELi may include one or more sub-emission control lines. In the case where the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC may operate in response to an emission control signal received through the corresponding sub-emission control line.

[0077] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC may adjust a current flowing from the first power supply voltage node VDDN to the second power supply voltage node VSSN through the light emitting element LD according to the stored voltage in response to the emission control signal received through the i-th emission control line ELi. Therefore, the light emitting element LD may emit light at a brightness corresponding to the data signal.

[0078] Figure 3 is a diagram showing some embodiments of the present invention. Figure 2 A circuit diagram of various aspects of the sub-pixel. Figure 3 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light emitting element LD.

[0079] The sub-pixel circuit SPC may be connected to the i-th gate line GLi', the i-th emission control line ELi', and the j-th data line DLj. Figure 2 Compared with the i-th gate line GLi, the i-th gate line GLi′ may further include a third sub-gate line SGL3. Figure 2 Compared with the i-th emission control line ELi, the i-th emission control line ELi′ may include a first sub-emission control line SEL1 and a second sub-emission control line SEL2.

[0080] The sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2.

[0081] The first transistor T1 is connected between the first power supply voltage node VDDN and the first node N1. The gate of the first transistor T1 may be connected to the second node N2. Therefore, the first transistor T1 may be turned on according to the voltage level of the second node N2. The first transistor T1 may be referred to as a driving transistor.

[0082] The second transistor T2 may be connected between the jth data line DLj and the second node N2. The gate of the second transistor T2 may be connected to the first sub-gate line SGL1. Therefore, the second transistor T2 may be turned on in response to the gate signal of the first sub-gate line SGL1. The second transistor T2 may be referred to as a switching transistor.

[0083] The third transistor T3 may be connected between the first node N1 and the second node N2. A gate of the third transistor T3 may be connected to the second sub-gate line SGL2. Therefore, the third transistor T3 may be turned on in response to a gate signal of the second sub-gate line SGL2.

[0084] The fourth transistor T4 may be connected between the first node N1 and the anode electrode AE ​​of the light emitting element LD. A gate of the fourth transistor T4 may be connected to the second sub-emission control line SEL2. Therefore, the fourth transistor T4 may be turned on in response to the emission control signal of the second sub-emission control line SEL2.

[0085] The fifth transistor T5 may be connected between the anode electrode AE ​​of the light emitting element LD and the initialization voltage node VINTN. The initialization voltage node VINTN is configured to transmit the initialization voltage. According to some embodiments, the initialization voltage may be Figure 1 The initialization voltage may be provided by the voltage generator 140 of the display device 100. In other embodiments, the initialization voltage may be provided by an external device of the display device 100. The gate of the fifth transistor T5 may be connected to the third sub-gate line SGL3. Therefore, the fifth transistor T5 may be turned on in response to the gate signal of the third sub-gate line SGL3.

[0086] The sixth transistor T6 is connected between the first power supply voltage node VDDN and the first transistor T1. A gate of the sixth transistor T6 may be connected to the first sub emission control line SEL1. Therefore, the sixth transistor T6 may be turned on in response to the emission control signal of the first sub emission control line SEL1.

[0087] The first capacitor C1 is connected between the second transistor T2 and the second node N2. The second capacitor C2 is connected between the first power supply voltage node VDDN and the second node N2.

[0088] Thus, the sub-pixel circuit SPC may include first to sixth transistors T1 to T6 and first and second capacitors C1 and C2. However, the embodiment is not limited to the above. The sub-pixel circuit SPC may be implemented as any of various forms of circuits each including a plurality of transistors and one or more capacitors. For example, the sub-pixel circuit SPC may include two transistors and one capacitor. Depending on the embodiment of the sub-pixel circuit SPC, the number of sub-gate lines included in the i-th gate line GLi' and the number of sub-emission control lines included in the i-th emission control line ELi' may vary.

[0089] The first transistor T1 to the sixth transistor T6 may be formed by a P-type transistor. Each of the first transistor T1 to the sixth transistor T6 may be formed by a metal oxide semiconductor field effect transistor (MOSFET). However, the embodiment is not limited to the above. For example, at least one of the first transistor T1 to the sixth transistor T6 may be replaced by an N-type transistor.

[0090] According to some embodiments, the first to sixth transistors T1 to T6 may include an amorphous silicon semiconductor, a single crystal silicon semiconductor, a polycrystalline silicon semiconductor, an oxide semiconductor, or the like.

[0091] The light emitting element LD may include an anode electrode AE, a cathode electrode CE, and an emission layer. The emission layer may be positioned between the anode electrode AE ​​and the cathode electrode CE. After the data signal transmitted through the j-th data line DLj is reflected in the voltage of the second node N2, when the emission control signals of the first sub-emission control line SEL1 and the second sub-emission control line SEL2 are enabled to be low, the fourth transistor T4 and the sixth transistor T6 may be turned on. In addition, the first transistor T1 may be turned on in response to the voltage of the second node N2 so that current may flow from the first power supply voltage node VDDN to the second power supply voltage node VSSN. The light emitting element LD may emit light corresponding to the amount of current.

[0092] Figure 4 is a diagram showing some embodiments of the present invention. Figure 1 A plan view of further details of the display panel DP. Figure 4 , the display panel DP may include a display area DA and a non-display area NDA. The display panel DP may display an image through the display area DA. The non-display area NDA may be arranged around the display area DA.

[0093] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD.

[0094] In the case where the display panel DP is used as a display screen for a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, and the like, the display panel DP may be positioned very close to the user's eyes. In this case, a relatively high density of sub-pixels SP may be required or desired. In order to increase the pixel density of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on a substrate SUB which is a silicon substrate. A display device 100 (refer to FIG. 1 ) including a display panel DP formed on a substrate SUB which is a silicon substrate Figure 1 ) can be called a silicon-based OLED (OLEDoS) display device.

[0095] The plurality of sub-pixels SP may be positioned in the display area DA on the substrate SUB. The plurality of sub-pixels SP may be arranged in a matrix along a first direction DR1 and a second direction DR2 intersecting the first direction DR1. However, the embodiment is not limited to the above example. For example, the plurality of sub-pixels SP may be arranged in a zigzag pattern in the first direction DR1 and the second direction DR2. For example, the plurality of sub-pixels SP may be arranged in a zigzag pattern in the first direction DR1 and the second direction DR2. The first direction DR1 may refer to a row direction, and the second direction DR2 may refer to a column direction.

[0096] Two or more sub-pixels among the plurality of sub-pixels SP may form one pixel PXL.

[0097] A component for controlling the sub-pixel SP may be located in the non-display area NDA on the substrate SUB. For example, a line (such as a Figure 1 The first to m-th gate lines GL1 to GLm and the first to n-th data lines DL1 to DLn) may be positioned in the non-display area NDA.

[0098] Figure 1 At least one of the gate driver 120, the data driver 130, the voltage generator 140, the controller 150, and the temperature sensor 160 of the display panel DP may be integrated in the non-display area NDA of the display panel DP. According to some embodiments, Figure 1 The gate driver 120 may be mounted on the display panel DP and positioned in the non-display area NDA. In other embodiments, the gate driver 120 may be implemented as an integrated circuit separated from the display panel DP. According to some embodiments, the temperature sensor 160 may be positioned in the non-display area NDA to sense the temperature of the display panel DP.

[0099] The pad PD may be positioned in the non-display area NDA on the substrate SUB. The pad PD may be electrically connected to the sub-pixel SP through a line. For example, the pad PD may be connected to the sub-pixel SP through the first to nth data lines DL1 to DLn.

[0100] The pad PD can connect the display panel DP to the display device 100 (see Figure 1 According to some embodiments, voltages and signals required for the operation of components included in the display panel DP may be obtained from Figure 1 The gate control signal GCS may be provided to the driver integrated circuit DIC through the pad PD. For example, the first data line DL1 to the nth data line DLn may be connected to the driver integrated circuit DIC through the pad PD. For example, the first power supply voltage VDD and the second power supply voltage VSS may be received from the driver integrated circuit DIC through the pad PD. For example, in the case where the gate driver 120 is mounted on the display panel DP, the gate control signal GCS may be transmitted from the driver integrated circuit DIC to the gate driver 120 through the pad PD.

[0101] According to some embodiments, the circuit board may be electrically connected to the pad PD by a conductive adhesive member such as an anisotropic conductive film. Here, the circuit board may be a flexible circuit board or a flexible film made of a flexible material. The driving integrated circuit DIC may be mounted on the circuit board and electrically connected to the pad PD.

[0102] According to some embodiments, the display area DA may have various shapes. The display area DA may have a closed loop shape including straight and / or curved edges. For example, the display area DA may have a shape such as a polygon, a circle, a semicircle, an ellipse, and the like.

[0103] According to some embodiments, the display panel DP may have a flat display surface. According to some embodiments, the display panel DP may have a display surface that is at least partially rounded. According to some embodiments, the display panel DP is bendable, foldable, or rollable. In the above case, the display panel DP and / or the substrate SUB may include a material having a flexible property.

[0104] Figure 5 is a diagram showing some embodiments of the present invention. Figure 4 Exploded perspective views of various aspects of a portion of a display panel DP. Figure 5 In the figure, for the sake of clarity and concise explanation, the display panel DP is schematically shown. Figure 4 The remaining portions of the display panel DP corresponding to other pixels may also be configured in the same manner.

[0105] Reference Figure 4 and Figure 5 , each of the first pixel PXL1 and the second pixel PXL2 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiment is not limited to the above example. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels, or may include two sub-pixels.

[0106] exist Figure 5 2 shows a case where the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 have a rectangular shape and have the same size when viewed in a third direction DR3 intersecting the first direction DR1 and the second direction DR2. However, the embodiment is not limited to the above example. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be modified to have various shapes.

[0107] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light emitting element layer LDL, an encapsulation layer TFE, an optical function layer OFL, an overcoat layer OC, and a cover window CW.

[0108] According to some embodiments, the substrate SUB may include a silicon wafer substrate formed by a semiconductor process. The substrate SUB may include a semiconductor material suitable for forming a circuit element. For example, the semiconductor material may include silicon, germanium and / or silicon-germanium. The substrate SUB may be provided from a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, or the like. According to some embodiments, the substrate SUB may include a glass substrate. According to some embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0109] The pixel circuit layer PCL may be positioned on the substrate SUB. The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and a conductive pattern positioned between the insulating layers. The conductive pattern of the pixel circuit layer PCL may be used as at least some of circuit elements, lines, and the like. The conductive pattern may include copper, but the embodiment is not limited thereto.

[0110] The circuit element may include corresponding sub-pixel circuits SPC of the first sub-pixel SP1, the second sub-pixel SP2 and the third sub-pixel SP3 (refer to Figure 2 ). The sub-pixel circuit SPC may include a plurality of transistors and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. According to some embodiments, in the case where the substrate SUB is formed of a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. According to some embodiments, in the case where the substrate SUB is formed of a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3 with an insulating layer interposed therebetween.

[0111] The lines of the pixel circuit layer PCL may include signal lines connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, for example, a gate line, an emission control line, and a data line. The lines may also include signal lines connected to Figure 2 In addition, the line may also include a line connected to the first power supply voltage node VDDN. Figure 2 A line to the second power supply voltage node VSSN.

[0112] The light emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, an emission structure EMS, and a cathode electrode CE.

[0113] The anode electrode AE ​​may be positioned on the pixel circuit layer PCL. The anode electrode AE ​​may contact a circuit element of the pixel circuit layer PCL. The anode electrode AE ​​may include an opaque conductive material capable of reflecting light, but the embodiment is not limited thereto.

[0114] The pixel defining layer PDL may be positioned on the anode electrode AE. The pixel defining layer PDL may include an opening OP exposing a portion of each anode electrode AE. The opening OP in the pixel defining layer PDL may be understood as a respective emission region corresponding to the first to third subpixels SP1 to SP3.

[0115] According to some embodiments, the pixel defining layer PDL may include an inorganic material. In this case, the pixel defining layer PDL may include a plurality of inorganic layers stacked one above the other. For example, the pixel defining layer PDL may include silicon oxide (SiO x ) and silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL may include an organic material. However, the material of the pixel defining layer PDL is not limited to the above examples.

[0116] The emission structure EMS may be positioned on the anode electrode AE ​​exposed through the opening OP in the pixel defining layer PDL. The emission structure EMS may include an emission layer configured to generate light, an electron transport layer configured to transport electrons, and a hole transport layer configured to transport holes.

[0117] According to some embodiments, the emission structure EMS may be loaded into an opening OP in the pixel defining layer PDL and positioned on the entire surface of the upper portion of the pixel defining layer PDL. In other words, the emission structure EMS may extend over the first sub-pixel SP1 to the third sub-pixel SP3. In this case, at least some of the multiple layers in the emission structure EMS may be interrupted or bent on the boundaries between the first sub-pixel SP1 to the third sub-pixel SP3. However, the embodiments are not limited to the above examples. For example, portions of the emission structure EMS corresponding to the first sub-pixel SP1 to the third sub-pixel SP3 may be separated from each other, and each may be positioned in a corresponding opening OP in the pixel defining layer PDL.

[0118] The cathode electrode CE may be positioned on the emission structure EMS. The cathode electrode CE may extend throughout the first to third subpixels SP1 to SP3. Thus, the cathode electrode CE may be provided as a common electrode of the first to third subpixels SP1, SP2, and SP3.

[0119] The cathode electrode CE may be a thin film metal layer having a thickness that allows light emitted from the emission structure EMS to pass through. The cathode electrode CE may be made of a metal material or a transparent conductive material having a relatively small thickness. According to some embodiments, the cathode electrode CE may include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. According to some embodiments, the cathode electrode CE may include at least one of silver (Ag), magnesium (Mg), and a compound thereof. However, the material of the cathode electrode CE is not limited to the above examples.

[0120] Any one of the anode electrodes AE, the portion of the emission structure EMS overlapping with the any one of the anode electrodes AE, and the portion of the cathode electrode CE overlapping with the portion of the emission structure EMS can be understood as constituting one light emitting element LD (refer to Figure 2). In other words, each of the light-emitting elements of the first subpixel SP1 to the third subpixel SP3 may include an anode electrode, a portion of the emission structure EMS overlapping the anode electrode, and a portion of the cathode electrode CE overlapping the portion of the emission structure. In each of the first subpixel SP1 to the third subpixel SP3, holes injected from the anode electrode AE ​​and electrons injected from the cathode electrode CE are transferred to the emission layer of the emission structure EMS, thereby forming excitons. When the excitons transition from an excited state to a ground state, light can be generated. The brightness of the light can be determined based on the amount of current flowing through the emission layer. The wavelength range of the light to be generated can be determined based on the configuration of the emission layer.

[0121] The encapsulation layer TFE may be positioned on the cathode electrode CE. The encapsulation layer TFE may cover the light emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE may be configured to prevent or reduce the situation where pollutants such as oxygen and / or water or the like penetrate into the light emitting element layer LDL. According to some embodiments, the encapsulation layer TFE may include a structure formed by alternately stacking one or more inorganic layers and one or more organic layers. For example, the inorganic layer may include, for example, silicon nitride, silicon oxide, or silicon oxynitride (SiO x N y ). For example, the organic layer may include an organic insulating material such as polyacrylate resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene resin, polyphenylene sulfide resin or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited to the above examples.

[0122] The encapsulation layer TFE may also include aluminum oxide (AlO x ) film to improve the encapsulation efficiency of the encapsulation layer TFE. The film containing aluminum oxide may be positioned on the upper surface of the encapsulation layer TFE facing the optical function layer OFL and / or under the lower surface of the encapsulation layer TFE facing the light emitting element layer LDL.

[0123] The thin film including aluminum oxide may be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited to the above example. The encapsulation layer TFE may also include a thin film formed of at least one of various materials suitable for improving encapsulation efficiency.

[0124] The optical function layer OFL may be positioned on the encapsulation layer TFE. The optical function layer OFL may include a color filter layer CFL and a lens array LA.

[0125] The color filter layer CFL may be positioned between the encapsulation layer TFE and the lens array LA. The color filter layer CFL may be configured to filter the light emitted from the emission structure EMS to selectively output light of a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include a plurality of color filters CF corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. Each of the plurality of color filters CF allows light within a wavelength range corresponding to the associated sub-pixel to pass through. For example, the color filter corresponding to the first sub-pixel SP1 allows red light to pass through, the color filter corresponding to the second sub-pixel SP2 allows green light to pass through, and the color filter corresponding to the third sub-pixel SP3 allows blue light to pass through. Depending on the light emitted from the emission structure EMS of each sub-pixel, at least some of the plurality of color filters CF may be omitted.

[0126] The lens array LA may be positioned on the color filter layer CFL. The lens array LA may include a plurality of lenses LS corresponding to the first to third sub-pixels SP1 to SP3, respectively. Each of the plurality of lenses LS may output and guide the light emitted from the emission structure EMS along a desired path, thereby improving light output efficiency. The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index higher than that of the overcoat layer OC. According to some embodiments, the lens LS may include an organic material. According to some embodiments, the lens LS may include an acrylate material. However, the material of the lens LS is not limited to the above examples.

[0127] According to some embodiments, compared to the opening OP of the pixel defining layer PDL, at least some of the plurality of color filters CF of the color filter layer CFL and at least some of the plurality of lenses LS of the lens array LA may be displaced in a direction parallel to the plane defined by the first direction DR1 and the second direction DR2. Specifically, in the central area of ​​the display area DA, the center of each color filter and the center of each lens may be aligned or overlapped with the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the central area of ​​the display area DA, each opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. In the area of ​​the display area DA adjacent to the non-display area NDA, when viewed in the third direction DR3, the center of the color filter and the center of the lens LS may be displaced in a plane direction from the center of the corresponding opening OP of the pixel defining layer PDL. For example, in the area adjacent to the non-display area NDA in the display area DA, each opening OP of the pixel defining layer PDL may partially overlap with the corresponding color filter of the color filter layer CFL and the corresponding lens of the lens array LA. Accordingly, light emitted from the emission structure EMS in the central portion of the display area DA can be effectively output in the normal direction of the display surface. Light emitted from the emission structure EMS around the periphery of the display area DA can be effectively output in a direction inclined at a certain angle relative to the normal direction of the display surface.

[0128] The outer coating OC may be positioned on the lens array LA. The outer coating OC may cover the optical function layer OFL, the encapsulation layer TFE, the emission structure EMS and / or the pixel circuit layer PCL. The outer coating OC may include various materials suitable for protecting the underlying layers from foreign matter such as dust, water or the like. For example, the outer coating OC may include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC may include an epoxy resin, but the embodiment is not limited thereto. The outer coating OC may have a refractive index lower than that of the lens array LA.

[0129] The cover window CW may be positioned on the outer coating layer OC. The cover window CW may be configured to protect the lower layer. The cover window CW may have a refractive index higher than that of the outer coating layer OC. The cover window CW may include glass, but the embodiment is not limited thereto. For example, the cover window CW may be an encapsulation glass layer configured to protect components located thereunder. In other embodiments, the cover window CW may be omitted.

[0130] Figure 6 is a diagram showing some embodiments of the present invention. Figure 5 A plan view of further details of any of the pixels. Figure 6 In the example, for the sake of clarity and simplicity of explanation, the Figure 5The first pixel PXL1 of the first pixel PXL1 and the second pixel PXL2 may be configured in the same manner as the first pixel PXL1.

[0131] Reference Figure 5 and Figure 6 , the first pixel PXL1 may include first to third sub-pixels SP1 to SP3 arranged in the first direction DR1.

[0132] The first subpixel SP1 may include a first emission area EMA1 and a non-emission area NEA formed around the first emission area EMA1. The second subpixel SP2 may include a second emission area EMA2 and a non-emission area NEA formed around the second emission area EMA2. The third subpixel SP3 may include a third emission area EMA3 and a non-emission area NEA formed around the third emission area EMA3.

[0133] The first emission area EMA1 may be a region where the emission structure EMS (see Figure 5 ) may be an area where light is emitted from a portion of the emission structure EMS corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area where light is emitted from a portion of the emission structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the emission structure EMS corresponding to the third sub-pixel SP3. Figure 5 As described above, each emission region may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first to third sub-pixels SP1 to SP3 .

[0134] Figure 7 is a diagram showing the Figure 6 A cross-sectional view of various aspects of a pixel taken along line II'. Figure 8 is a diagram showing the Figure 6 A cross-sectional view of a pixel taken along line II' of FIG. Figure 8 In addition to the separator SPR, Figure 8 The embodiments described in Figure 7 The embodiments depicted in are substantially the same.

[0135] Reference Figure 7 , a substrate SUB and a pixel circuit layer PCL positioned on the substrate SUB are provided.

[0136] The substrate SUB may include a silicon wafer substrate formed by a semiconductor process. For example, the substrate SUB may include silicon, germanium and / or silicon-germanium.

[0137] The pixel circuit layer PCL may be positioned on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include corresponding circuit elements of the first sub-pixel SP1 to the third sub-pixel SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be a sub-pixel circuit SPC (refer to Figure 2 ). The transistor T_SP2 of the second sub-pixel SP2 may be any one of the multiple transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2. The transistor T_SP3 of the third sub-pixel SP3 may be any one of the multiple transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. Figure 7 , for the sake of clarity and concise explanation, one of the multiple transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0138] The transistor T_SP1 of the first subpixel SP1 may include a source area SRA, a drain area DRA, and a gate electrode GE.

[0139] The source region SRA and the drain region DRA may be positioned in the substrate SUB. The well WL formed by the ion implantation process may be positioned in the substrate SUB. The source region SRA and the drain region DRA may be spaced apart from each other in the well WL. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0140] The gate electrode GE may overlap the channel region between the source region SRA and the drain region DRA and may be positioned in the pixel circuit layer PCL. The gate electrode GE may be spaced apart from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0141] The plurality of layers included in the pixel circuit layer PCL may include an insulating layer and a conductive pattern positioned between the insulating layers. The conductive pattern may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA via a drain connector DRC passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA via a source connector SRC passing through one or more insulating layers.

[0142] As the gate electrode GE and the first and second conductive patterns CP1 and CP2 are connected to other circuit elements and / or lines, the transistor T_SP1 of the first subpixel SP1 may be provided as one of the plurality of transistors of the first subpixel SP1.

[0143] Each of the transistor T_SP2 of the second subpixel SP2 and the transistor T_SP3 of the third subpixel SP3 may be configured in the same manner as the transistor T_SP1 of the first subpixel SP1.

[0144] Thus, the substrate SUB and the pixel circuit layer PCL may include corresponding circuit elements of the first to third sub-pixels SP1 to SP3 .

[0145] The via layer VIAL (or base layer) may be positioned on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL and have an overall flat surface. The via layer VIAL is configured to flatten the step portion on the pixel circuit layer PCL. The via layer VIAL may include silicon oxide (SiO x ), Silicon Nitride (SiN x ) and at least one of silicon carbonitride (SiCN), but the embodiment is not limited thereto.

[0146] The light emitting element layer LDL may be positioned on the via layer VIAL and may include first to third reflective electrodes RE1 to RE3 , a planarization layer PLNL, first to third anode electrodes AE1 to AE3 , a pixel defining layer PDL, an emission structure EMS, and a cathode electrode CE.

[0147] The first to third reflective electrodes RE1 to RE3 may be respectively positioned in the first to third subpixels SP1 to SP3 on the via layer VIAL. Each of the first to third reflective electrodes RE1 to RE3 may contact a circuit element positioned in the pixel circuit layer PCL through a corresponding via hole passing through the via layer VIAL.

[0148] The first to third reflective electrodes RE1 to RE3 may be used as total reflectors provided to reflect light emitted from the emission structure EMS toward the display surface (or cover window CW). The first to third reflective electrodes RE1 to RE3 may include a metal material suitable for reflecting light. The first to third reflective electrodes RE1 to RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), and titanium (Ti), or an alloy of two or more materials selected from the above materials.

[0149] The first to third reflective electrodes RE1 to RE3 may have the same thickness. For example, the thickness of each of the first to third reflective electrodes RE1 to RE3 may be from about 100 Å to about 500 Å. To about range, or may be approximately

[0150] According to some embodiments, the first buffer pattern BFP1 (or the connection electrode) may be positioned under at least one of the first to third reflective electrodes RE1 to RE3. The first buffer pattern BFP1 may include a conductive material and improve electrical connection characteristics between the corresponding reflective electrode and the corresponding circuit element of the pixel circuit layer PCL. The first buffer pattern BFP1 may include a material such as titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), but the embodiment is not limited thereto. The first buffer pattern BFP1 may have a multilayer structure.

[0151] Reference Figure 7 , for example, in the first sub-pixel SP1, the first buffer pattern BFP1 may be positioned between the first reflective electrode RE1 and the via layer VIAL. In addition, in the second sub-pixel SP2, the first buffer pattern BFP1 may be positioned between the second reflective electrode RE2 and the via layer VIAL. In the third sub-pixel SP3, the first buffer pattern BFP1 is not positioned between the third reflective electrode RE3 and the via layer VIAL. The third reflective electrode RE3 may be positioned directly on the via layer VIAL.

[0152] According to some embodiments, the second buffer pattern BFP2 (or buffer pattern) may be positioned under at least one of the first to third reflective electrodes RE1 to RE3. The second buffer pattern BFP2 may include an insulating material. For example, the second buffer pattern BFP2 includes a silicon nitride (SiN x ), silicon carbonitride, silicon oxide (SiO x ), but the embodiment is not limited thereto. As the second buffer pattern BFP2 (and the first buffer pattern BFP1) are positioned, the height of the corresponding reflective electrode in the third direction DR3 may be adjusted.

[0153] Reference Figure 7 For example, in the first sub-pixel SP1, the second buffer pattern BFP2 may be positioned between the first reflective electrode RE1 and the first buffer pattern BFP1 to adjust the height of the first reflective electrode RE1. In the second sub-pixel SP2, the second buffer pattern BFP2 is not positioned between the second reflective electrode RE2 and the first buffer pattern BFP1. The second reflective electrode RE2 may be positioned directly on the first buffer pattern BFP1.

[0154] The first to third reflective electrodes RE1 to RE3 can be used as full reflective mirrors, and the cathode electrode CE can be used as a half reflective mirror. By reciprocating between the corresponding reflective electrodes and the cathode electrode CE, the light emitted from the emission layer of the emission structure EMS can be at least partially amplified. The amplified light can be output through the cathode electrode CE. In this way, the distance between each reflective electrode and the cathode electrode CE can be understood as the resonance distance of the light emitted from the emission layer of the corresponding emission structure EMS.

[0155] For example, the first to third subpixels SP1 to SP3 may correspond to red, green, and blue, respectively. The distance between the first reflective electrode RE1 and the cathode electrode CE may be smaller than the distance between the second reflective electrode RE2 and the cathode electrode CE. The distance between the second reflective electrode RE2 and the cathode electrode CE may be smaller than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0156] Due to the first buffer pattern BFP1 and the second buffer pattern BFP2, the first sub-pixel SP1 may have a resonance distance shorter than the resonance distances of the second sub-pixel SP2 and the third sub-pixel SP3. Similarly, due to the first buffer pattern BFP1, the second sub-pixel SP2 may have a resonance distance shorter than the resonance distance of the third sub-pixel SP3. Thus, the adjusted resonance distance may enable light in a specific wavelength range (e.g., red or green) to be effectively amplified. Therefore, each of the first sub-pixel SP1 and the second sub-pixel SP2 may effectively and efficiently output light in the corresponding wavelength range.

[0157] exist Figure 7 , a case where the first buffer pattern BFP1 is provided in the first subpixel SP1 and the second subpixel SP2 but not in the third subpixel SP3 is shown, but the embodiments of the present disclosure are not limited thereto. For example, the first buffer pattern BFP1 (or the connection electrode) may be provided in the third subpixel SP3.

[0158] exist Figure 7 2 shows a case where the second buffer pattern BFP2 is provided in the first sub-pixel SP1 but not in the second sub-pixel SP2 and the third sub-pixel SP3, but the embodiment is not limited thereto. For example, the second buffer pattern BFP2 may be provided in at least one of the second sub-pixel SP2 and the third sub-pixel SP3 to enable adjustment of the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3.

[0159] According to some embodiments, the thickness of the second buffer pattern BFP2 (or the thickness with respect to the third direction DR3) may be substantially the same as the thickness of the first buffer pattern BFP1. For example, the thickness of each of the first buffer pattern BFP1 and the second buffer pattern BFP2 may be from about To about range, or may be approximately

[0160] In order to flatten the step portions between the first to third reflective electrodes RE1 to RE3, the flattening layer PLNL may be positioned on the via layer VIAL and the first to third reflective electrodes RE1 to RE3. The flattening layer PLNL may cover the entire surfaces of the first to third reflective electrodes RE1 to RE3 and the via layer VIAL and have a flat surface. The flattening layer PLNL may include an insulating material. For example, the flattening layer PLNL may include a silicon oxide (SiO x ) and silicon nitride (SiN x ) of an inorganic material, but the embodiment is not limited thereto.

[0161] On the planarization layer PLNL, the first to third anode electrodes AE1 to AE3 may be positioned to overlap the first to third reflective electrodes RE1 to RE3, respectively. When viewed in the third direction DR3, the first to third anode electrodes AE1 to AE3 may have the same Figure 6 The first to third emitting areas EMA1 to EMA3 are similar in shape. The first to third anodic electrodes AE1 to AE3 are respectively connected to the first to third reflective electrodes RE1 to RE3. The first anodic electrode AE1 may be connected to the first reflective electrode RE1 through a first via hole VIA1 passing through the planarization layer PLNL. The second anodic electrode AE2 may be connected to the second reflective electrode RE2 through a second via hole VIA2 passing through the planarization layer PLNL. The third anodic electrode AE3 may be connected to the third reflective electrode RE3 through a third via hole VIA3 passing through the planarization layer PLNL.

[0162] According to some embodiments, the first to third anode electrodes AE1 to AE3 may include, for example, indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO) and indium tin zinc oxide (ITZO). However, the materials of the first to third anode electrodes AE1 to AE3 are not limited to the above examples. For example, the first to third anode electrodes AE1 to AE3 may include titanium nitride.

[0163] The first to third anode electrodes AE1 to AE3 may have the same thickness. For example, the thickness of each of the first to third anode electrodes AE1 to AE3 may be from about 100 to 200 Å. To about range, or may be approximately

[0164] According to some embodiments, the distance TH1 (or average distance, shortest distance) between the first anode electrode AE1 and the first reflective electrode RE1 in the first subpixel SP1 may be smaller than the distance TH2 between the second anode electrode AE2 and the second reflective electrode RE2 in the second subpixel SP2. The distance TH2 (or average distance, shortest distance) between the second anode electrode AE2 and the second reflective electrode RE2 in the second subpixel SP2 may be smaller than the distance TH3 between the third anode electrode AE3 and the third reflective electrode RE3 in the third subpixel SP3.

[0165] For example, the average thickness of the planarization layer PLNL in the second sub-pixel SP2 (i.e., the distance TH2) may be about 1.4 times to about 1.7 times the average thickness of the planarization layer PLNL in the first sub-pixel SP1 (i.e., the distance TH1). The average thickness of the planarization layer PLNL in the third sub-pixel SP3 (i.e., the distance TH3) may be about 1.9 times to about 2.4 times the average thickness of the planarization layer PLNL in the first sub-pixel SP1 (i.e., the distance TH1). For example, the average thickness of the planarization layer PLNL in the first sub-pixel SP1 (i.e., the distance TH1) may be about 1.9 times to about 2.4 times the average thickness of the planarization layer PLNL in the first sub-pixel SP1 (i.e., the distance TH1). To about range, or may be approximately The average thickness of the planarization layer PLNL in the second sub-pixel SP2 (ie, the distance TH2) may be from about To about range, or may be approximately The average thickness of the planarization layer PLNL in the third sub-pixel SP3 (ie, the distance TH3) may be from about To about range, or may be approximately

[0166] The pixel defining layer PDL may be positioned on the planarization layer PLNL and portions of the first to third anode electrodes AE1 to AE3. The pixel defining layer PDL may include an opening OP exposing respective portions of the first to third anode electrodes AE1 to AE3. The opening OP in the pixel defining layer PDL may define respective emission regions of the first to third sub-pixels SP1 to SP3. Thus, the pixel defining layer PDL may be positioned Figure 6 The non-emitting area NEA is defined as Figure 6 The first emission area EMA1 to the third emission area EMA3.

[0167] According to some embodiments, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x ) at least one of. Figure 8 , for example, the pixel defining layer PDL may include first to third inorganic insulating layers stacked sequentially. The first to third inorganic insulating layers may include silicon nitride, silicon oxide, and silicon nitride, respectively. However, the embodiment is not limited to the above example. The first to third inorganic insulating layers may have a step shape in a region adjacent to each of the openings OP.

[0168] A separator SPR may be provided in the boundary area BDA between adjacent sub-pixels SP. In other words, a separator SPR may be provided in each of the boundary areas BDA between the sub-pixels SP.

[0169] The separator SPR may cause generation of a discontinuous portion in the emission structure EMS in the boundary area BDA. For example, the emission structure EMS may be interrupted or bent in the boundary area BDA by the separator SPR.

[0170] The separation member SPR may be provided in or on the pixel defining layer PDL.

[0171] According to some embodiments, the pixel defining layer PDL may include a protrusion pattern PRT as a separator SPR in the boundary area BDA.

[0172] like Figure 7 As shown in , a protruding pattern PRT additionally stacked on the pixel defining layer PDL may be provided in the boundary area BDA. The width of the protruding pattern PRT may increase upward (or in the third direction DR3). For example, the protruding pattern PRT may include a plurality of inorganic insulating patterns. The uppermost inorganic insulating pattern among the plurality of inorganic insulating patterns may have a width greater than the width of the inorganic insulating pattern immediately below. For example, in the boundary area BDA, the first to third inorganic insulating patterns may be stacked continuously from the pixel defining layer PDL. The uppermost third inorganic insulating pattern may have a width greater than the width of the second inorganic insulating pattern. For example, the protruding pattern PRT may have a "T"-shaped or "I"-shaped cross-section in the boundary area BDA. Depending on the shape of the protruding pattern PRT, the plurality of layers included in the emission structure EMS may be at least partially interrupted or bent in the boundary area BDA.

[0173] The separator SPR may be modified in various ways to allow the emission structure EMS to have a discontinuous portion in the boundary area BDA. According to some embodiments, the pixel defining layer PDL may include one or more trenches (eg, first and second trenches TRCH1 and TRCH2 ) as the separator SPR in the boundary area BDA.

[0174] like Figure 8As shown in , one or more grooves (e.g., the first groove TRCH1 and the second groove TRCH2) may pass through the pixel defining layer PDL and partially pass through the planarization layer PLNL. In other embodiments, one or more grooves (e.g., the first groove TRCH1 and the second groove TRCH2) may pass through the pixel defining layer PDL and the planarization layer PLNL and partially pass through the via layer VIAL. In other embodiments, one or more grooves (e.g., the first groove TRCH1 and the second groove TRCH2) may at least partially pass through the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL may be positioned in the one or more grooves (e.g., the first groove TRCH1 and the second groove TRCH2).

[0175] For example, two grooves (e.g., a first groove TRCH1 and a second groove TRCH2) separated from each other may be provided in the boundary area BDA. For example, a first groove TRCH1 and a second groove TRCH2 may be positioned in the boundary area BDA between the second sub-pixel SP2 and the third sub-pixel SP3, the first groove TRCH1 may be arranged along the periphery of the second sub-pixel SP2, and the second groove TRCH2 may be arranged along the periphery of the third sub-pixel SP3. In the case where the first groove TRCH1 and the second groove TRCH2 are separated from each other, the width of each of the first groove TRCH1 and the second groove TRCH2 remains constant, and the discontinuous portion of the emission structure EMS in the boundary area BDA may be made uniform. In the case where the first groove TRCH1 and the second groove TRCH2 are connected to each other, the width of the connection portion between the first groove TRCH1 and the second groove TRCH2 may be greater than the width of the other portions, the discontinuous portion of the emission structure EMS may become uneven, and the characteristics of the emission structure EMS may become uneven.

[0176] exist Figure 8 , a case where two grooves (e.g., a first groove TRCH1 and a second groove TRCH2) are provided in the boundary area BDA is shown. However, embodiments are not limited to the above. For example, the pixel defining layer PDL may include one groove in the boundary area BDA. Alternatively, the pixel defining layer PDL may include three or more grooves in the boundary area BDA.

[0177] Due to the first trench TRCH1 and the second trench TRCH2, discontinuous portions in the boundary area BDA, such as the first void VD1 and the second void VD2, may be formed in the emission structure EMS. Some of the plurality of layers stacked in the emission structure EMS may be interrupted or bent by the first void VD1 and the second void VD2. For example, at least one charge generation layer included in the emission structure EMS may be interrupted by the first void VD1 and the second void VD2. Thus, due to the first trench TRCH1 and the second trench TRCH2, portions of the emission structure EMS included in the first to third sub-pixels SP1 to SP3 are at least partially separated from each other.

[0178] exist Figure 8 2 shows a case where the first gap VD1 and the second gap VD2 are formed in the emission structure EMS in the boundary area BDA, but this is for illustration only and the embodiment is not limited thereto. For example, a valley having a concave shape may be formed in the emission structure EMS in the boundary area BDA. Depending on the shapes of the first trench TRCH1 and the second trench TRCH2, the discontinuous portion formed in the emission structure EMS may be changed in various ways.

[0179] According to some embodiments, the emission structure EMS may be formed by a process such as vacuum deposition or inkjet printing. In this case, the same material as that of the emission structure EMS may be positioned on the bottom surface adjacent to the via layer VIAL in the first and second trenches TRCH1 and TRCH2.

[0180] The emission structure EMS may be positioned on the anode electrode AE ​​exposed through the opening OP in the pixel defining layer PDL. The emission structure EMS may be loaded into the opening OP of the pixel defining layer PDL and arranged over the entire area of ​​the first to third sub-pixels SP1 to SP3. As described above, the emission structure EMS may be at least partially interrupted or bent in the boundary area BDA by the separator SPR. Therefore, during operation of the display panel DP, current leaking from each of the first to third sub-pixels SP1 to SP3 through the layers included in the emission structure EMS to the adjacent sub-pixels may be reduced. As a result, the first to third light emitting elements LD1 to LD3 may operate with relatively high reliability.

[0181] The cathode electrode CE may be positioned on the emission structure EMS. The cathode electrode CE may be commonly provided in the first to third sub-pixels SP1 to SP3. The cathode electrode CE may function as a half mirror that partially transmits and partially reflects light emitted from the emission structure EMS.

[0182] The first anode electrode AE1, the portion of the emission structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 may form a first light emitting element LD1. The second anode electrode AE2, the portion of the emission structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 may form a second light emitting element LD2. The third anode electrode AE3, the portion of the emission structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 may form a third light emitting element LD3.

[0183] The encapsulation layer TFE may be positioned on the cathode electrode CE. The encapsulation layer TFE may prevent or reduce the penetration of pollutants such as oxygen and / or water or the like into the light emitting element layer LDL.

[0184] The optical functional layer OFL may be positioned on the encapsulation layer TFE. According to some embodiments, the optical functional layer OFL may be attached to the encapsulation layer TFE through an adhesive layer APL. For example, the optical functional layer OFL may be manufactured through a separate process and attached to the encapsulation layer TFE through an adhesive layer APL. The adhesive layer APL may also perform the function of protecting the lower layer including the encapsulation layer TFE.

[0185] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include first to third color filters CF1 to CF3 corresponding to the first to third subpixels SP1 to SP3, respectively. The first to third color filters CF1 to CF3 may transmit light in different wavelength ranges. For example, the first to third color filters CF1 to CF3 may transmit red light, green light, and blue light, respectively.

[0186] According to some embodiments, the first to third color filters CF1 to CF3 may partially overlap each other in the boundary area BDA. In other embodiments, the first to third color filters CF1 to CF3 may be spaced apart from each other, and a black matrix may be provided between the first to third color filters CF1 to CF3.

[0187] The lens array LA may be positioned on the color filter layer CFL. The lens array LA may include first to third lenses LS1 to LS3 corresponding to the first to third sub-pixels SP1 to SP3, respectively. The first to third lenses LS1 to LS3 may guide the light emitted from the first to third light emitting elements LD1 to LD3 on predetermined paths, respectively, thereby improving light output efficiency.

[0188] Fig. 9 is a diagram showing the Figure 6 A cross-sectional view of further details of the pixel taken along line II'.

[0189] Reference Figure 8 and Fig. 9 , in addition to the buffer pattern BFP, Fig. 9 The embodiments described in Figure 8 The embodiments described in the foregoing are substantially the same or similar. Therefore, some repeated explanations thereof may be omitted.

[0190] According to some embodiments, the buffer pattern BFP may be positioned under at least one of the first to third reflective electrodes RE1 to RE3 .

[0191] The buffer pattern BFP may include a reference Figure 7 At least one of the first buffer pattern BFP1 and the second buffer pattern BFP2 is described. For example, the buffer pattern BFP may include the first buffer pattern BFP1 and the second buffer pattern BFP2, but the embodiment is not limited thereto.

[0192] As the buffer pattern BFP is positioned, the height of the corresponding reflective electrode in the third direction DR3 can be adjusted. For example, the buffer pattern BFP can be positioned between the first reflective electrode RE1 and the via layer VIAL in the first sub-pixel SP1. The buffer pattern BFP is not positioned between the second reflective electrode RE2 and the via layer VIAL in the second sub-pixel SP2. The second reflective electrode RE2 can be directly positioned on the via layer VIAL. Similarly, in the third sub-pixel SP3, the buffer pattern BFP is not positioned between the third reflective electrode RE3 and the via layer VIAL. The third reflective electrode RE3 can be directly positioned on the via layer VIAL.

[0193] Due to the buffer pattern BFP, the first subpixel SP1 may have a resonance distance shorter than the resonance distances of other subpixels. Thus, the adjusted resonance distance may enable light in a specific wavelength range (e.g., red) to be effectively amplified. Therefore, the first subpixel SP1 may effectively and efficiently output light in the corresponding wavelength range.

[0194] exist Fig. 9 , a case where the buffer pattern BFP is provided in the first sub-pixel SP1 but not in the second sub-pixel SP2 and the third sub-pixel SP3 is shown, but the embodiment is not limited thereto. The buffer pattern may also be provided in at least one of the second sub-pixel SP2 and the third sub-pixel SP3 so that the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3 can be adjusted. For example, the buffer pattern BFP may also be provided in the second sub-pixel SP2 so that the resonance distance of the second sub-pixel SP2 can be adjusted. For example, the distance between the second reflective electrode RE2 and the cathode electrode CE may be the same as the distance between the first reflective electrode RE1 and the cathode electrode CE. The distance between the third reflective electrode RE3 and the cathode electrode CE may be greater than the distance between the first reflective electrode RE1 and the cathode electrode CE.

[0195] Fig. 9 The buffer pattern BFP can also be applied to Figure 7 The embodiment shown.

[0196] Fig. 10A , Fig. 10B , Fig. 10C , Fig. 10D , Fig.10E and Fig.10F is a cross-sectional view for describing a method for manufacturing a display device according to an embodiment. Figure 7 The display device of the embodiment can be FIG. 10A to FIG. 10F For the sake of convenience, the method for manufacturing a display device can be omitted. Figure 7 Some redundant explanations are repeated for the embodiments.

[0197] Reference Figure 7 and Fig. 10A A buffer pattern is formed in the first sub-pixel region (ie, the region for the first sub-pixel SP1) of the via layer VIAL (or the base layer). Here, the buffer pattern may include a first buffer pattern BFP1 and a second buffer pattern BFP2.

[0198] According to some embodiments, the first buffer pattern BFP1 and the second buffer pattern BFP2 may be formed in each of the first to third sub-pixel regions (i.e., regions for the first to third sub-pixels SP1 to SP3). The first buffer pattern BFP1 may be formed on the via layer VIAL. The second buffer pattern BFP2 may be formed on the first buffer pattern BFP1.

[0199] Thereafter, a photoresist layer PR may be formed in the first sub-pixel region. The photoresist layer PR may cover the first buffer pattern BFP1 and the second buffer pattern BFP2 in the first sub-pixel region.

[0200] Subsequently, the second buffer pattern BFP2 may be removed from the second and third sub-pixel regions. For example, the second buffer pattern BFP2 may be removed by an etching process. The first buffer pattern BFP1 includes a material different from that of the second buffer pattern BFP2. Therefore, only the second buffer pattern BFP2 may be removed.

[0201] Thereafter, the photoresist layer PR may be removed. Therefore, the second buffer pattern BFP2 may exist only in the first sub-pixel region.

[0202] Reference Fig. 10B , remove the first buffer pattern BFP1 in the third sub-pixel area.

[0203] According to some embodiments, a photoresist layer PR may be formed in the first sub-pixel region and the second sub-pixel region. The photoresist layer PR may cover the second buffer pattern BFP2 in the first sub-pixel region and the first buffer pattern BFP1 in the second sub-pixel region.

[0204] Subsequently, the first buffer pattern BFP1 in the third sub-pixel region may be removed. For example, the first buffer pattern BFP1 may be removed by an etching process.

[0205] Thereafter, the photoresist layer PR may be removed.

[0206] pass Fig. 10A and Fig. 10B A first buffer pattern BFP1 and a second buffer pattern BFP2 are formed in the first sub-pixel region, only the first buffer pattern BFP1 is formed in the second sub-pixel region, and no buffer pattern is provided in the third sub-pixel region.

[0207] Reference Fig. 10C , first to third reflective electrodes RE1 to RE3 may be formed in the first to third sub-pixel regions, respectively.

[0208] According to some embodiments, the reflective electrode layer REL may be formed on the entire surface of the via layer VIAL. The reflective electrode layer REL may cover the via layer VIAL, the second buffer pattern BFP2 in the first sub-pixel region, and the first buffer pattern BFP1 in the second sub-pixel region.

[0209] Thereafter, a photoresist layer PR may be formed on the reflective electrode layer REL. The photoresist layer PR may be formed in each of the first to third sub-pixel regions, and in the region between the first to third sub-pixels SP1 to SP3 (or in the boundary region BDA (refer to Figure 7 ) may not be formed or may be removed.

[0210] Thereafter, the first to third reflective electrodes RE1 to RE3 may be formed from the reflective electrode layer REL using the photoresist layer PR. For example, the reflective electrode layer REL is removed from the region between the first to third sub-pixels SP1 to SP3 by an etching process using the photoresist layer PR as a mask so that the first to third reflective electrodes RE1 to RE3 may be separated from each other.

[0211] Thereafter, the photoresist layer PR may be removed.

[0212] Reference Fig. 10D , a planarization layer PLNL is formed to cover the first to third reflective electrodes RE1 to RE3 and provide a flat upper surface.

[0213] According to some embodiments, a planarization layer PLNL may be formed on the entire surface of the via layer VIAL. The planarization layer PLNL may include an inorganic material. Due to the difference in height between the first to third reflective electrodes RE1 to RE3, an upper surface of the planarization layer PLNL may have a stepped portion.

[0214] Thereafter, the upper surface of the planarization layer PLNL may be planarized by a planarization process. For example, the upper surface of the planarization layer PLNL may be planarized by a chemical mechanical polishing (CMP) process.

[0215] Reference Figure 7 , Fig.10E and Fig.10F , first to third light emitting elements LD1 to LD3 may be formed on the planarization layer PLNL.

[0216] like Fig.10E As shown in FIG. 1 , first to third anode electrodes AE1 to AE3 are formed on the planarization layer PLNL.

[0217] According to some embodiments, a photoresist layer PR may be formed on the planarization layer PLNL. A contact hole through which the first to third reflective electrodes RE1 to RE3 are partially exposed may be formed in the planarization layer PLNL using the photoresist layer PR as a mask. After forming the contact hole, the photoresist layer PR may be removed.

[0218] Thereafter, first to third connection electrodes CNT1 to CNT3 may be formed in corresponding contact holes of the sub-pixel region. First to third anode electrodes AE1 to AE3 may be formed on the planarization layer PLNL.

[0219] For example, the contact hole of the planarization layer PLNL in the first sub-pixel region may be filled with the first connection electrode CNT1. The contact hole of the planarization layer PLNL in the second sub-pixel region may be filled with the second connection electrode CNT2. The contact hole of the planarization layer PLNL in the third sub-pixel region may be filled with the third connection electrode CNT3. The first connection electrode CNT1 to the third connection electrode CNT3 may include a metal. For example, each connection electrode may include tungsten (W).

[0220] The first anode electrode AE1 may be positioned in the first sub-pixel region and may be electrically connected to the first reflective electrode RE1 through the first connection electrode CNT1. The second anode electrode AE2 may be positioned in the second sub-pixel region and may be electrically connected to the second reflective electrode RE2 through the second connection electrode CNT2. The third anode electrode AE3 may be positioned in the third sub-pixel region and may be electrically connected to the third reflective electrode RE3 through the third connection electrode CNT3.

[0221] Although in Fig.10E 1 to 3 are shown as being positioned in the contact holes, but the embodiment is not limited thereto. For example, the first to third anode electrodes AE1 to AE3 may be connected to the first to third reflective electrodes RE1 to RE3, respectively, without connecting electrodes. In other words, the first to third connection electrodes CNT1 to CNT3 may be omitted.

[0222] like Fig.10F As shown in FIG. 1 , a pixel defining layer PDL may be formed on the planarization layer PLNL and the first to third anode electrodes AE1 to AE3 .

[0223] According to some embodiments, a pixel defining layer PDL may be formed on the entire surface of the planarization layer PLNL The pixel defining layer PDL may cover the first to third anode electrodes AE1 to AE3 .

[0224] Thereafter, a protruding pattern PRT may be formed on the pixel defining layer PDL. The protruding pattern PRT may be used as a separating member SPR (refer to Figure 7 ).

[0225] Subsequently, openings may be formed in the pixel defining layer PDL, and respective portions of the first to third anode electrodes AE1 to AE3 are exposed through the openings.

[0226] Although referenced Fig.10F The formation of the protruding pattern PRT is described, but the embodiment is not limited thereto. For example, instead of forming the protruding pattern PRT, the first trench TRCH1 and the second trench TRCH2 may be formed in the pixel defining layer PDL (refer to Figure 8 ).

[0227] Thereafter, the Figure 7 As a result, the other components shown in FIG. 1 , such as the emission structure EMS, the cathode electrode CE and the encapsulation layer TFE, can be manufactured according to Figure 7 A display device of an embodiment.

[0228] Fig.11 is a diagram showing the inclusion of Figure 7 sectional views of various aspects of the emission structure in any one of the first to third light emitting elements LD1 to LD3.

[0229] Reference Fig.11 The emission structure EMS may have a tandem structure in which the first emission element EU1 and the second emission element EU2 are stacked. Figure 7 Each of the first to third light emitting elements LD1 to LD3 has substantially the same configuration.

[0230] Each of the first emission component EU1 and the second emission component EU2 may include at least one emission layer configured to generate light in response to a current applied thereto. The first emission component EU1 may include a first emission layer EML1, a first electron transport component ETU1, and a first hole transport component HTU1. The first emission layer EML1 may be positioned between the first electron transport component ETU1 and the first hole transport component HTU1. The second emission component EU2 may include a second emission layer EML2, a second electron transport component ETU2, and a second hole transport component HTU2. The second emission layer EML2 may be positioned between the second electron transport component ETU2 and the second hole transport component HTU2.

[0231] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, and the like as needed. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same configuration or different configurations.

[0232] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, and the like as needed. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have the same configuration or different configurations.

[0233] A connection layer that can be provided in the form of a charge generation layer CGL may be positioned between the first emission component EU1 and the second emission component EU2 to connect the first emission component EU1 and the second emission component EU2 to each other. According to some embodiments, the charge generation layer CGL may have a stacked structure including a p-dopant layer and an n-dopant layer. For example, the p-dopant layer may include a p-type dopant such as HAT-CN, TCNQ, or NDP-9, and the n-dopant layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the embodiments are not limited to the above examples.

[0234] According to some embodiments, the first emission layer EML1 and the second emission layer EML2 may generate light of different colors. The light emitted from the first emission layer EML1 and the second emission layer EML2 may be mixed into visible white light. For example, the first emission layer EML1 may generate blue light, and the second emission layer EML2 may generate yellow light. According to some embodiments, the second emission layer EML2 may include a stacked structure including a first sub-emission layer configured to generate red light and a second sub-emission layer configured to generate green light. The red light and the green light may be mixed to provide yellow light. In this case, an intermediate layer configured to perform the function of transporting holes and / or blocking electron transport may also be positioned between the first sub-emission layer and the second sub-emission layer.

[0235] In other embodiments, the first emission layer EML1 and the second emission layer EML2 may generate light of the same color.

[0236] The emission structure EMS may be formed through a scheme such as vacuum deposition, inkjet printing, or the like, but the embodiment is not limited thereto.

[0237] Fig.12 is a diagram showing the inclusion of Figure 7 sectional views of various aspects of the emission structure in any one of the first to third light emitting elements LD1 to LD3.

[0238] Reference Fig.12 , the emission structure EMS' may have a series structure in which the first emission element EU1' to the third emission element EU3' are stacked. Figure 7 Each of the first to third light emitting elements LD1 to LD3 has substantially the same configuration.

[0239] Each of the first emission component EU1' to the third emission component EU3' may include an emission layer configured to generate light in response to a current applied thereto. The first emission component EU1' may include a first emission layer EML1', a first electron transport component ETU1', and a first hole transport component HTU1'. The first emission layer EML1' may be positioned between the first electron transport component ETU1' and the first hole transport component HTU1'. The second emission component EU2' may include a second emission layer EML2', a second electron transport component ETU2', and a second hole transport component HTU2'. The second emission layer EML2' may be positioned between the second electron transport component ETU2' and the second hole transport component HTU2'. The third emission component EU3' may include a third emission layer EML3', a third electron transport component ETU3', and a third hole transport component HTU3'. The third emission layer EML3' may be positioned between the third electron transport component ETU3' and the third hole transport component HTU3'.

[0240] Each of the first to third hole transport units HTU1' to HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, and the like as needed. The first to third hole transport units HTU1' to HTU3' may have the same configuration or different configurations.

[0241] Each of the first to third electron transport units ETU1' to ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, and the like as needed. The first to third electron transport units ETU1' to ETU3' may have the same configuration or different configurations.

[0242] The first charge generation layer CGL1' may be positioned between the first emission element EU1' and the second emission element EU2'. The second charge generation layer CGL2' may be positioned between the second emission element EU2' and the third emission element EU3'.

[0243] According to some embodiments, the first emission layer EML1' to the third emission layer EML3' may generate light of different colors. The light emitted from the first emission layer EML1' to the third emission layer EML3' may be mixed into visible white light. For example, the first emission layer EML1' may generate blue light, the second emission layer EML2' may generate green light, and the third emission layer EML3' may generate red light.

[0244] According to some embodiments, two or more emission layers among the first to third emission layers EML1 ′ to EML3 ′ may generate light of the same color.

[0245] With reference Fig.11 and Fig.12 The situations described are different. Figure 7 The emission structure EMS of the embodiment may include one emission component in each of the first to third light emitting elements LD1 to LD3. Here, the respective emission components included in the first to third light emitting elements LD1 to LD3 may be configured to emit light of different colors. For example, the emission component of the first light emitting element LD1 may emit red light, the emission component of the second light emitting element LD2 may emit green light, and the emission component of the third light emitting element LD3 may emit blue light. In this case, as with reference Figure 7 Unlike the described case, emission parts of the first to third subpixels SP1 to SP3 may be separated from each other and each may be positioned in a corresponding opening OP of the pixel defining layer PDL. In this case, at least some of the first to third color filters CF1 to CF3 may be omitted.

[0246] Fig.13 is a diagram showing the Figure 6 A cross-sectional view of further details of the pixel taken along line II'.

[0247] Reference Figure 7 and Fig.13 , except for the first to third anode electrodes AE1 to AE3, Fig.13 The embodiments described in Figure 7 The embodiments described in the foregoing are substantially the same or similar. Therefore, some repeated explanations thereof may be omitted.

[0248] According to some embodiments, the first to third anode electrodes AE1 to AE3 may cover the first to third reflective electrodes RE1 to RE3 and contact side surfaces of the first to third reflective electrodes RE1 to RE3.

[0249] In the first subpixel SP1, the first anode electrode AE1 may cover the first buffer pattern BFP1, the second buffer pattern BFP2, the first reflective electrode RE1, and the planarization layer PLNL (or the insulating pattern), and may contact the corresponding side surfaces of the first buffer pattern BFP1, the second buffer pattern BFP2, the first reflective electrode RE1, and the planarization layer PLNL.

[0250] Likewise, in the second subpixel SP2 , the second anode electrode AE2 may cover the first buffer pattern BFP1 , the second reflective electrode RE2 , and the planarization layer PLNL, and may contact respective side surfaces of the first buffer pattern BFP1 , the second reflective electrode RE2 , and the planarization layer PLNL.

[0251] In the third sub-pixel SP3 , the third anode electrode AE3 may cover the third reflective electrode RE3 and the planarization layer PLNL, and may contact respective side surfaces of the third reflective electrode RE3 and the planarization layer PLNL.

[0252] In this case, the contact holes (or corresponding connection electrodes) of the planarization layer PLNL for connection between the first to third anode electrodes AE1 to AE3 and the first to third reflective electrodes RE1 to RE3 may be omitted. The size of the emission region (or the region outputting the amplified light) of each of the first to third subpixels SP1 to SP3 may be increased.

[0253] The pixel defining layer PDL may be positioned on the via layer VIAL and some portions of the first to third anode electrodes AE1 to AE3 . The pixel defining layer PDL may be positioned directly on the via layer VIAL.

[0254] Fig.14 is a diagram showing some embodiments of the present invention. Figure 5A floor plan of the pixels for further details.

[0255] Reference Fig.14 , the first pixel PXL1 ′ may include first to third sub-pixels SP1 ′ to SP3 ′.

[0256] The first subpixel SP1' may include a first emission area EMA1' and a non-emission area NEA' formed around the first emission area EMA1'. The second subpixel SP2' may include a second emission area EMA2' and a non-emission area NEA' formed around the second emission area EMA2'. The third subpixel SP3' may include a third emission area EMA3' and a non-emission area NEA' formed around the third emission area EMA3'.

[0257] The first subpixel SP1' and the second subpixel SP2' may be arranged in the second direction DR2. The third subpixel SP3' may be positioned in the first direction with respect to each of the first subpixel SP1' and the second subpixel SP2'.

[0258] The second sub-pixel SP2' may have a surface area larger than that of the first sub-pixel SP1'. The third sub-pixel SP3' may have a surface area larger than that of the second sub-pixel SP2'. Therefore, the second emission area EMA2' may have a surface area larger than that of the first emission area EMA1'. The third emission area EMA3' may have a surface area larger than that of the second emission area EMA2'. However, the embodiments are not limited to the above examples. For example, the first sub-pixel SP1' and the second sub-pixel SP2' may have substantially the same surface area. The third sub-pixel SP3' may have a surface area larger than the surface area of ​​each of the first sub-pixel SP1' and the second sub-pixel SP2'. Thus, the surface areas of the first to third sub-pixels SP1' to SP3' may be changed in various ways depending on the embodiments.

[0259] Fig.15 is a diagram showing some embodiments of the present invention. Figure 5 A floor plan of the pixels for further details.

[0260] Reference Fig.15 The first pixel PXL1" may include the first sub-pixel SP1" to the third sub-pixel SP3". The first sub-pixel SP1" may include the first emission area EMA1" and the non-emission area NEA" formed around the first emission area EMA1". The second sub-pixel SP2" may include the second emission area EMA2" and the non-emission area NEA" formed around the second emission area EMA2". The third sub-pixel SP3" may include the third emission area EMA3" and the non-emission area NEA" formed around the third emission area EMA3".

[0261] Each of the first to third sub-pixels SP1″ to SP3″ may have a polygonal shape in the third direction DR3. Fig.15 As shown in FIG. 1 , the shapes of the first to third sub-pixels SP1 ″ to SP3 ″ may be hexagonal.

[0262] Each of the first to third emission areas EMA1 ″ to EMA3 ″ may have a circular shape in the third direction DR3 . However, embodiments are not limited to the above examples. For example, each of the first to third emission areas EMA1 ″ to EMA3 ″ may have a polygonal shape.

[0263] The first subpixel SP1" and the third subpixel SP3" may be arranged in the first direction DR1. The second subpixel SP2" may be arranged in a direction (or an oblique direction) inclined at an acute angle based on the second direction DR2 with respect to the first subpixel SP1".

[0264] Figure 6 , Fig.14 and Fig.15 The arrangement of the sub-pixels shown in is illustrative, and the embodiments are not limited thereto. Each pixel may include two or more sub-pixels, and the sub-pixels may be arranged in various ways. Each of the sub-pixels may have various shapes. Each of the emission regions of the sub-pixels may also have various shapes.

[0265] Fig.16 is a block diagram illustrating aspects of a display system according to some embodiments.

[0266] Reference Fig.16 , the display system 1000 may include a processor 1100, and one or more display devices (eg, a first display device 1210 and a second display device 1220).

[0267] The processor 1100 may perform various tasks and operations. According to some embodiments, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system to control the components.

[0268] exist Fig.16 2 shows a case where the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1, and may be connected to the second display device 1220 through a second channel CH2.

[0269] The processor 1100 may transmit the first image data IMG1 and the first control signal CTRL1 to the first display device 1210 through the first channel CH1. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. Figure 1 In this case, the first image data IMG1 and the first control signal CTRL1 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0270] The processor 1100 may transmit the second image data IMG2 and the second control signal CTRL2 to the second display device 1220 through the second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. Figure 1 In this case, the second image data IMG2 and the second control signal CTRL2 may be provided as Figure 1 Input image data IMG and control signal CTRL.

[0271] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (tablet PC), a smart watch, a watch phone, a portable multimedia player, a navigation system, and an ultra mobile personal computer (UMPC). In addition, the display system 1000 may include at least one of a head mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0272] Fig.17 is a diagram showing some embodiments of the present invention. Fig.16 A perspective view showing an application example of the display system.

[0273] Reference Fig.17 , Fig.16 The display system 1000 may be applied to a head mounted display device 2000. The head mounted display device 2000 may be a wearable electronic device that can be worn on the head of a user.

[0274] The head mounted display device 2000 may include a head mounting band 2100 and a display device housing 2200. The head mounting band 2100 may be connected to the display device housing 2200. The head mounting band 2100 may include a transverse band and / or a longitudinal band to fasten the head mounted display device 2000 to the user's head. The transverse band may surround the sides of the user's head, and the longitudinal band may surround the top of the user's head. However, embodiments are not limited to the above examples. For example, the head mounting band 2100 may be implemented in the form of a glasses frame, a helmet, etc.

[0275] The display device receiving case 2200 can receive Fig.16 The first display device 1210 and the second display device 1220. The display device receiving case 2200 may also receive Fig.16 Processor 1100.

[0276] Fig.18 FIG. 1 is a diagram showing a device worn on a user according to some embodiments. Fig.17 FIG. 1 is a diagram of a head mounted display device.

[0277] Reference Fig.18 The head mounted display device 2000 (or wearable electronic device) may include a display panel configured to emit light, and a lens component positioned on the display panel (or on a light emission path). The display panel may include a first display panel DP1 of a first display device 1210 and a second display panel DP2 of a second display device 1220. The lens component may include one or more lenses (e.g., a left eye lens LLNS and a right eye lens RLNS).

[0278] In the display device receiving container 2200, the right eye lens RLNS may be positioned between the first display panel DP1 and the right eye of the user. In the display device receiving container 2200, the left eye lens LLNS may be positioned between the second display panel DP2 and the left eye of the user.

[0279] The image output from the first display panel DP1 can be viewed by the right eye of the user through the right eye lens RLNS. The right eye lens RLNS may refract light emitted from the first display panel DP1 toward the right eye of the user. The right eye lens RLNS may perform an optical function to adjust the viewing distance between the first display panel DP1 and the right eye of the user.

[0280] The image output from the second display panel DP2 can be viewed by the user's left eye through the left eye lens LLNS. The left eye lens LLNS may refract light emitted from the second display panel DP2 toward the user's left eye. The left eye lens LLNS may perform an optical function to adjust the viewing distance between the second display panel DP2 and the user's left eye.

[0281] According to some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pancake-shaped cross-section. According to some embodiments, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including a plurality of sub-regions having different optical characteristics. In this case, each display panel may output a plurality of images respectively corresponding to the plurality of sub-regions of the multi-channel lens. The outputted plurality of images may be viewed by a user through the corresponding sub-regions.

[0282] In a display device and a wearable electronic device according to an embodiment of the present disclosure, a buffer pattern may be positioned below a reflective electrode of some sub-pixels. In this case, the corresponding sub-pixel may have a resonance distance shorter than the resonance distance of other sub-pixels. The adjusted resonance distance may enable light in a specific wavelength range (e.g., red) to be effectively and efficiently amplified. Therefore, the sub-pixel may effectively and relatively efficiently output light in the corresponding wavelength range.

[0283] In the method of manufacturing a display device according to an embodiment of the present disclosure, the buffer pattern may be formed under the reflective electrode of only some of the plurality of sub-pixels.

[0284] The characteristics of the embodiments according to the present disclosure are not limited to the above contents, and include various other characteristics herein.

[0285] Although some embodiments and aspects of implementations have been described herein, other embodiments and modifications will be apparent from the above description. Accordingly, the concepts according to the embodiments of the present disclosure are not limited to the above embodiments, but are defined by the broader scope of the claims presented and various obvious modifications and equivalent arrangements.

Claims

1. A display device, comprising: a first sub-pixel, a second sub-pixel and a third sub-pixel, Wherein, each of the first sub-pixel, the second sub-pixel and the third sub-pixel comprises: a reflective electrode, the reflective electrode being on the base layer; a planarization layer on the reflective electrode and configured to provide a flat upper surface; an anode electrode, the anode electrode being on the planarization layer; an emitting structure, the emitting structure being on the anode electrode; and a cathode electrode, the cathode electrode being on the emitting structure, The first sub-pixel further includes a first buffer pattern between the base layer and the reflective electrode, and Wherein, in the third sub-pixel, the reflective electrode is directly on the base layer.

2. The display device according to claim 1, wherein: An average distance between the anode electrode and the reflective electrode in the first sub-pixel is smaller than an average distance between the anode electrode and the reflective electrode in the third sub-pixel.

3. The display device according to claim 1, wherein: The first sub-pixel further includes a second buffer pattern between the first buffer pattern and the reflective electrode, The second sub-pixel further includes the first buffer pattern between the base layer and the reflective electrode, and The average distance between the anode electrode and the reflective electrode in the second sub-pixel is smaller than the average distance between the anode electrode and the reflective electrode in the third sub-pixel and is larger than the average distance between the anode electrode and the reflective electrode in the first sub-pixel.

4. The display device according to claim 3, wherein: A thickness of the anode electrode in the first sub-pixel, a thickness of the anode electrode in the second sub-pixel, and a thickness of the anode electrode in the third sub-pixel are equal to each other.

5. The display device according to claim 3, wherein: The first buffer pattern includes a conductive material, and Wherein, the second buffer pattern comprises insulating material.

6. The display device according to claim 3, wherein: A thickness of the first buffer pattern is equal to a thickness of the second buffer pattern.

7. The display device according to claim 3, wherein: an average thickness of the planarization layer in the second sub-pixel is in a range of 1.4 to 1.7 times the average thickness of the planarization layer in the first sub-pixel, and The average thickness of the planarization layer in the third sub-pixel is in a range from 1.9 times to 2.4 times the average thickness of the planarization layer in the first sub-pixel.

8. The display device according to claim 1, wherein: The transmitting structure comprises: a first emission layer commonly disposed in the first sub-pixel, the second sub-pixel, and the third sub-pixel and configured to emit light of a first color; and A second emitting layer is on the first emitting layer and is configured to emit light of a second color.

9. The display device according to claim 8, wherein: The transmitting structure further comprises: A third emitting layer is on the second emitting layer and is configured to emit light of a third color.

10. The display device according to claim 1, wherein: In the second sub-pixel, the reflective electrode is directly on the base layer.

11. The display device according to claim 1, wherein: The anode electrode covers the reflective electrode and contacts a side surface of the reflective electrode.

12. The display device according to claim 1, further comprising: a pixel defining layer, the pixel defining layer being on the base layer between the first sub-pixel to the third sub-pixel; as well as A protruding pattern is on the pixel defining layer and has a width increasing in an upward direction.

13. The display device according to claim 1, further comprising: a plurality of grooves formed to partially penetrate the planarization layer in a boundary region between the first to third sub-pixels, and Wherein, the plurality of grooves are separated from each other.

14. The display device according to claim 1, wherein: Each of the first to third sub-pixels further includes a color filter on the cathode electrode.

15. A wearable electronic device comprising: a display panel configured to emit light; as well as at least one lens, the at least one lens being on the display panel, The display panel includes a first sub-pixel, a second sub-pixel and a third sub-pixel. Wherein, each of the first sub-pixel, the second sub-pixel and the third sub-pixel comprises: a reflective electrode, the reflective electrode being on the base layer; a planarization layer on the reflective electrode and configured to provide a flat upper surface; an anode electrode, the anode electrode being on the planarization layer; an emitting structure, the emitting structure being on the anode electrode; and a cathode electrode, the cathode electrode being on the emitting structure, The first sub-pixel further includes a first buffer pattern between the base layer and the reflective electrode, and Wherein, in the third sub-pixel, the reflective electrode is directly on the base layer.

16. The wearable electronic device according to claim 15, wherein: An average distance between the anode electrode and the reflective electrode in the first sub-pixel is smaller than an average distance between the anode electrode and the reflective electrode in the third sub-pixel.

17. The wearable electronic device according to claim 15, wherein: The first sub-pixel further includes a second buffer pattern between the first buffer pattern and the reflective electrode, The second sub-pixel further includes the first buffer pattern between the base layer and the reflective electrode, and The average distance between the anode electrode and the reflective electrode in the second sub-pixel is smaller than the average distance between the anode electrode and the reflective electrode in the third sub-pixel and is larger than the average distance between the anode electrode and the reflective electrode in the first sub-pixel.

18. A method for manufacturing a display device, comprising: forming a buffer pattern on the base layer in the first sub-pixel region; forming a reflective electrode throughout the buffer pattern in the first sub-pixel region and in the second sub-pixel region and the third sub-pixel region of the base layer; forming a planarization layer to cover the reflective electrode and provide a flat upper surface; as well as forming a light emitting element on the planarization layer, Wherein, in the third sub-pixel region, the reflective electrode is directly on the base layer.

19. The method for manufacturing a display device according to claim 18, wherein: Forming the buffer pattern includes: forming a first buffer pattern in each of the first to third sub-pixel regions, and forming a second buffer pattern on the first buffer pattern; forming a photoresist layer in the first sub-pixel region, and removing the second buffer pattern from the second sub-pixel region and the third sub-pixel region; and forming a photoresist layer in the first sub-pixel region and the second sub-pixel region, and removing the first buffer pattern from the third sub-pixel region, The buffer pattern of the first sub-pixel area includes the first buffer pattern and the second buffer pattern.

20. The method for manufacturing a display device according to claim 19, wherein: The first buffer pattern includes a conductive material, and the second buffer pattern includes an insulating material.

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