Display device

Abstract

A display device is provided. The display device includes a base layer including a display area including a light emitting element and a non-display area adjacent to the display area and including a pad, and a signal line connecting the light emitting element to the pad. In the non-display area, the pad includes a lower conductive pattern on the base layer, a first pattern on the lower conductive pattern and including a first photosensitive material, an upper conductive pattern on the lower conductive pattern and overlapping the first pattern, and a second pattern on the first pattern and including a second photosensitive material different from the first photosensitive material.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0151549, filed on November 6, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] The present disclosure relates to a display device and more particularly to a display device having improved structural stability in a pad region. Background Art

[0003] The display device includes a display area activated in response to an electrical signal, senses an external input applied thereto through the display area, and displays an image to provide information to the outside of the display device (eg, to a user of the display device).

[0004] The display device includes a display panel and a circuit board. The display panel is connected to a main board via the circuit board. A driving chip is mounted on the display panel. Summary of the invention

[0005] The present disclosure provides a display device including a pad having improved structural stability.

[0006] An embodiment of the present invention provides a display device, which includes a base layer including a display area and a non-display area adjacent to the display area, a lower insulating layer arranged on the base layer, a light-emitting element arranged in the display area, a pad arranged in the non-display area, and a signal line connected to the light-emitting element and the pad.

[0007] The pad may include a lower conductive pattern arranged on the lower insulating layer, a first pattern arranged on the lower conductive pattern and including a first photosensitive material, an upper conductive pattern arranged on the lower conductive pattern and overlapping at least a portion of the first pattern, and a second pattern arranged on the first pattern and including a second photosensitive material different from the first photosensitive material.

[0008] The first photosensitive material may be a polymer having negative photosensitivity.

[0009] The second photosensitive material may be a polymer having positive photosensitivity or a metal material having positive photosensitivity.

[0010] The second pattern may include an upper surface having a curvature.

[0011] A width of the second pattern in a direction in which the plurality of pads are arranged decreases as a distance from the base layer increases.

[0012] The second pattern may be disposed on the upper conductive pattern.

[0013] The upper conductive pattern may be disposed between the first pattern and the second pattern.

[0014] The upper conductive pattern may cover an upper surface of the first pattern, a plurality of side surfaces of the first pattern, and at least a portion of an upper surface of the lower conductive pattern.

[0015] The display device may further include a metal layer covering an upper surface of the second pattern and at least a portion of the plurality of side surfaces of the upper conductive pattern, and an upper insulating layer covering the metal layer and at least a portion of the upper conductive pattern.

[0016] The metal layer may include a metal layer upper portion covering the second pattern and a metal layer side portion disposed on each of the plurality of side surfaces of the upper conductive pattern, and the metal layer side portion may contact the upper insulating layer.

[0017] The metal layer may further include a metal layer tip portion disposed on the upper insulating layer and protruding in a direction in which the plurality of pads are arranged.

[0018] The display device may further include a driving chip that provides a data signal to the light emitting element, and a bump that is disposed under the driving chip and contacts the metal layer.

[0019] The bump, the metal layer, the upper conductive pattern, and the lower conductive pattern may be electrically connected to each other.

[0020] The shape of the upper portion of the metal layer may be deformed by pressure applied thereto by the bump in a direction toward the base layer.

[0021] An anchor portion defined when at least a portion of the metal layer side portion is bent and recessed in a direction toward the first pattern may be formed on the metal layer side portion.

[0022] A separation space may be defined between the driving chip and the base layer.

[0023] The separation space may be filled with a non-conductive adhesive.

[0024] The metal layer may include a first metal layer including titanium (Ti), a second metal layer disposed on the first metal layer and including aluminum (Al), and a third metal layer disposed on the second metal layer and including titanium (Ti).

[0025] The upper conductive pattern may include a first upper pattern layer including titanium (Ti), a second upper pattern layer disposed on the first upper pattern layer and including aluminum (Al), and a third upper pattern layer disposed on the second upper pattern layer and including titanium (Ti).

[0026] The lower conductive pattern may include a first lower pattern layer including titanium (Ti), a second lower pattern layer disposed on the first lower pattern layer and including aluminum (Al), and a third lower pattern layer disposed on the second lower pattern layer and including titanium (Ti).

[0027] The metal layer may cover at least a portion of an upper surface of the upper conductive pattern.

[0028] The display device may further include sub-patterns.

[0029] The metal layer may cover at least a portion of the second pattern and the sub-pattern.

[0030] One side surface of the first pattern when viewed in a plane substantially parallel to the base layer may be spaced apart from the sub-pattern with an upper conductive pattern interposed therebetween.

[0031] A portion of the upper conductive pattern covering the other side surface opposite to the one side surface of the first pattern may be at least partially covered by the metal layer.

[0032] At least a portion of a side surface of the upper conductive pattern may be exposed without being covered by the sub-pattern.

[0033] The at least a portion of the upper conductive pattern that is exposed without being covered by the sub-pattern may contact at least a portion of the metal layer.

[0034] The display device may further include a first sub-pattern and a second sub-pattern.

[0035] When viewed in cross section, one side surface of the first pattern may be spaced apart from the first sub-pattern with an upper conductive pattern interposed therebetween, and when viewed in cross section, another side surface of the first pattern opposite to the one side surface of the first pattern may be spaced apart from the second sub-pattern with an upper conductive pattern interposed therebetween.

[0036] One side surface of the upper conductive pattern and a portion of another side surface of the upper conductive pattern opposite to the one side surface of the upper conductive pattern may be exposed without being covered by the first sub-pattern and the second sub-pattern, respectively.

[0037] Portions of the upper conductive pattern that are exposed without being covered by the first sub-pattern and the second sub-pattern, respectively, may contact at least a portion of the metal layer.

[0038] The upper conductive pattern may cover an upper surface of the second pattern, a plurality of side surfaces of the first pattern, and at least a portion of an upper surface of the lower conductive pattern.

[0039] The second pattern may be disposed between the first pattern and the upper conductive pattern.

[0040] The display device may further include a bump directly contacting the upper conductive pattern.

[0041] The display device may further include a metal layer covering at least a portion of the upper conductive pattern.

[0042] The display device may further include a first sub-pattern and a second sub-pattern.

[0043] When viewed in cross section, one side surface of the first pattern may be spaced apart from the first sub-pattern with an upper conductive pattern interposed therebetween, and when viewed in cross section, another side surface of the first pattern opposite to the one side surface of the first pattern may be spaced apart from the second sub-pattern with an upper conductive pattern interposed therebetween.

[0044] Each of the first sub-pattern and the second sub-pattern has a width that increases downward when viewed in a cross-section (eg, in a downward direction).

[0045] According to the above, the display panel is bonded to the electronic component without using an anisotropic conductive film. Accordingly, even if the signal pads are densely arranged in the pad area, defects such as short circuits caused by the conductive balls are prevented, thereby improving the reliability of the display device with high resolution. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] The above and other advantages of the present disclosure will become readily apparent by referring to the following detailed description when considered in conjunction with the accompanying drawings, in which:

[0047] Figure 1A is a perspective view of an electronic device according to an embodiment of the present disclosure;

[0048] Figure 1B is an exploded perspective view of an electronic device according to an embodiment of the present disclosure;

[0049] Figure 2 is a cross-sectional view of a display device according to an embodiment of the present disclosure;

[0050] Figure 3A is a plan view of a display panel according to an embodiment of the present disclosure;

[0051] Figure 3B is an enlarged cross-sectional view of a display panel according to an embodiment of the present disclosure;

[0052] Figure 4A is a cross-sectional view of an input sensing unit according to an embodiment of the present disclosure;

[0053] Figure 4B is a plan view of an input sensing unit according to an embodiment of the present disclosure;

[0054] Figure 4C is along Figure 4B An enlarged cross-sectional view of the display device taken along line II';

[0055] Figure 5 is an enlarged exploded perspective view of a pad region of a display device according to an embodiment of the present disclosure;

[0056] Fig. 6A and Figure 6Bis along Figure 5 A cross-sectional view of a portion of the display device taken along line II-II'; and

[0057] 7A to 7E is along Figure 5 A cross-sectional view of a portion of the display device taken along line II-II'. DETAILED DESCRIPTION

[0058] The present disclosure can be variously modified and implemented in many different forms, and therefore specific embodiments will be exemplified in the drawings and described in detail below. However, the present disclosure should not be limited to the specific disclosed form, and should be interpreted as including all modifications, equivalents or replacements included in the spirit and scope of the present disclosure.

[0059] In the present disclosure, it will be understood that when an element (or region, layer or portion) is referred to as being associated with another element, such as being "on", "connected to" or "coupled to" another element or layer, the element can be directly on, directly connected to or coupled to another element or layer, or there may be intervening elements or layers. Conversely, when an element (or region, layer or portion) is referred to as being associated with another element, such as being "directly" "on", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0060] The terms used herein are only for the purpose of describing specific embodiments, and are not intended to be limiting. Unless the context clearly indicates otherwise, "a", "an", "the" and "at least one" as used herein do not represent a limit to quantity, and are intended to include both the singular and the plural. Therefore, the element mentioned in a claim that subsequently mentions the "said" element includes one element and multiple elements. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one" should not be interpreted as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" may include any and all combinations of one or more of the relevant listed items.

[0061] Throughout the specification, similar reference numerals refer to similar elements. For example, in the figures and text of the present disclosure, reference numerals indicating elements in the singular form may also be used to refer to singular elements in the plural form. In the drawings, the thickness, proportion and size of the components are exaggerated for the effective description of the technical content.

[0062] It will be understood that, although the terms first, second, etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another element. Therefore, without departing from the teachings of the present disclosure, the first element discussed below can be referred to as the second element. Unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" as used herein are also intended to include plural forms.

[0063] Spatially relative terms, such as “beneath,” “below,” “lower,” “above,” “upper,” and the like, may be used herein for convenience of description to describe the relationship of one element or feature to another element or feature as shown in the figures.

[0064] It will also be understood that when the terms “include” and / or “including” are used in this specification, it specifies the presence of stated features, integers, steps, operations, elements and / or components, but does not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or clusters thereof.

[0065] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will also be understood that, unless expressly defined as such herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology, and will not be interpreted in an idealized or overly formal sense.

[0066] Embodiments are described herein with reference to schematically illustrated cross-sectional views of idealized embodiments. Thus, variations in the shapes of the diagrams resulting from, for example, manufacturing techniques and / or tolerances will be expected. Therefore, the embodiments described herein should not be construed as being limited to the shapes of the specific zones as shown herein, but will include deviations in shapes resulting from, for example, manufacturing. For example, a zone shown or described as flat may typically have rough and / or nonlinear features. In addition, the sharp corners shown may be rounded. Therefore, the zones shown in the figures are schematic in nature, and their shapes are not intended to illustrate the precise shapes of the zones, and are not intended to limit the scope of the claims.

[0067] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0068] Figure 1A is a perspective view of an electronic device ED according to an embodiment of the present disclosure. Figure 1Bis an exploded perspective view of an electronic device ED according to an embodiment of the present disclosure.

[0069] Figure 1A and Figure 1B A mobile phone is shown as a representative example of the electronic device ED, however, the present disclosure should not be limited thereto or thereby. The electronic device ED can be applied to large display devices such as televisions, monitors, etc. and small and medium-sized display devices such as tablet computers, smart watches, navigation units, etc. In addition, the electronic device ED can be provided in the form of a foldable electronic device.

[0070] Reference Figure 1A , the electronic device ED can display the image IM through the display surface ED-IS (or at the display surface ED-IS). Figure 1A An icon image is shown as a representative example of the image IM.

[0071] The display surface ED-IS may be substantially parallel to a plane defined by the first direction DR1 and the second direction DR2 crossing each other. The third direction DR3 may indicate a direction intersecting the display surface ED-IS, such as a normal direction of the display surface ED-IS, for example, a thickness direction of the electronic device ED.

[0072] In the following description, the expression "when viewed in a plane" or "in a plane" may mean a state viewed in the third direction DR3 (or along the third direction DR3). The front surface (or upper surface) and the rear surface (or lower surface) of the components included in the electronic device ED may be defined relative to the third direction DR3.

[0073] The display surface ED-IS may include a display area ED-DA and a non-display area ED-NDA. The display area ED-DA may be an area (e.g., a plane area) that displays an image IM and / or an area that senses an external input to the electronic device ED. The non-display area ED-NDA may be an area that does not display the image IM. The non-display area ED-NDA may be defined to be adjacent to the display area ED-DA. Figure 1A A structure in which the non-display area ED-NDA surrounds the display area ED-DA is shown. However, the present disclosure should not be limited thereto or thereby, and the non-display area ED-NDA may be defined to be adjacent to one side of the display area ED-DA or may be omitted.

[0074] When the electronic device ED is provided in the form of a foldable electronic device, the electronic device ED may include a folding region and non-folding regions spaced apart from each other with the folding region interposed therebetween. The folding region may be a region where the electronic device ED may be folded (such as folded relative to an imaginary folding axis defined in the electronic device ED).

[0075] When the electronic device ED is folded, the electronic device ED can be folded inward (inward fold) to allow the non-folding areas to face each other in the thickness direction when fully folded (for example, fully folded inward), or can be folded outward (outward fold) to allow the non-folding areas to face opposite directions when fully folded (for example, fully folded outward).

[0076] Reference Figure 1B , the electronic device ED may include a window WM, a display device DD and a housing BC. Figure 1B Although not shown in the figure, when the electronic device ED is a foldable electronic device, the electronic device ED may further include a mechanical structure (eg, a hinge) to control its folding operation. In addition, the housing BC may be provided in plural according to the number of non-folding regions.

[0077] The window WM may be arranged above the display device DD, such as in the image display direction or light emission direction of the display device DD. The window WM may protect the display device DD and may display the image IM (refer to FIG. 1 ) provided from the display device DD. Figure 1A ) is transmitted to the outside of the electronic device ED. The window WM may include glass or plastic material. The window WM may have a single-layer or multi-layer structure. As an example, the window WM may include a plurality of plastic films attached to each other by an adhesive or a glass substrate combined with a plastic film.

[0078] The window WM may include a transmissive area TA (eg, a light-transmitting area) and a non-transmissive area NTA (eg, a light-blocking area).

[0079] The transmissive area TA may be aligned with the display area ED-DA (refer to Figure 1A ) overlaps (or corresponds to) and may have a shape (eg, a planar shape) corresponding to the shape of the display area ED-DA. The transmission area TA may have a high light transmittance and thus may transmit an image IM (refer to Figure 1A ) is transmitted to the outside of the electronic device ED.

[0080] The non-transmitting area NTA may be aligned with the non-display area ED-NDA (refer to Figure 1A ) and may have a shape corresponding to the non-display area ED-NDA. The non-transmission area NTA may have a relatively low light transmittance compared to the transmission area TA. That is, the light transmittance at the non-transmission area NTA may be lower than the light transmittance at the transmission area TA. However, the present disclosure should not be limited thereto or thereby, and the non-transmission area NTA may be omitted.

[0081] The display device DD may be arranged below the window WM. The display device DD may generate an image IM (see Figure 1A ) and / or can sense external input to the electronic device ED.

[0082] The display device DD may include a display panel DP and an input sensing unit ISU disposed on the display panel DP. Although not shown in the figure, the display device DD may further include an anti-reflection member disposed on the input sensing unit ISU. The anti-reflection member may include a polarizer and a retarder, or may include a color filter and a black matrix.

[0083] The input sensing unit ISU may include one of a capacitive sensor, an optical sensor, an ultrasonic sensor, and an electromagnetic induction sensor. The input sensing unit ISU may be formed (or provided) on the display panel DP through a continuous process, or may be attached to the upper portion of the display panel DP through a separate member such as an adhesive layer after being manufactured (or provided) separately from the display panel DP.

[0084] The display panel DP may have a substantially generated image IM (refer to Figure 1A ) configuration. The display panel DP may be a self-luminous light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel, an inorganic light-emitting display panel, an organic-inorganic light-emitting display panel, a quantum dot display panel, a micro light-emitting diode (micro-LED) display panel, or a nano-LED display panel. Hereinafter, an organic light-emitting display panel will be described as a representative example of the display panel DP, however, the present disclosure should not be limited thereto or thereby.

[0085] The display device DD may further include a driving chip DC and a circuit board PB. Figure 1B A structure in which the driving chip DC is mounted on the display panel DP is shown, however, it should not be limited thereto or thereby.

[0086] The driving chip DC may generate a driving signal required for the operation of the display panel DP in response to a control signal applied thereto from the circuit board PB.

[0087] Figure 1B 1 shows a structure in which the circuit board PB is bent at its bending area and includes a portion of the circuit board PB arranged on the rear surface of the display panel DP. However, the present disclosure should not be limited thereto or thereby. According to an embodiment, the portion of the display panel DP to which the circuit board PB is attached may be bent at the bending area of ​​the display panel DP (for example, in a direction away from the window WM) to allow the driving chip DC to face downward. In this case, the non-display area DP-NDA (refer to Figure 2 ) can be bent at its bending area. The circuit board PB can be arranged on the base layer BL (refer to Figure 2 ) and can be connected to the circuit element layer DP-CL of the display panel DP (refer to Figure 2 ).

[0088] In the above description, the mobile phone terminal is shown as the electronic device ED, but the electronic device ED according to the present disclosure may be described as a device including two or more electronic components bonded to each other. As an example, the electronic device ED may include only a display panel DP and a driver chip DC mounted on the display panel DP. Hereinafter, the electronic device ED will be described with emphasis on the bonding structure between the display panel DP and the driver chip DC mounted on the display panel DP.

[0089] Figure 2 is a cross-sectional view of a display device DD according to an embodiment of the present disclosure.

[0090] Reference Figure 2 , the display device DD may include a display panel DP and an input sensing unit ISU disposed on the display panel DP.

[0091] The display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and an encapsulation layer TFL disposed on the display element layer DP-OLED.

[0092] The display panel DP may include a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP may be connected to the electronic device ED (eg, Figure 1A and Figure 1B ) display area ED-DA (refer to Figure 1A ) and the transmissive area TA (refer to Figure 1B ), and the non-display area DP-NDA of the display panel DP may correspond to the non-display area ED-NDA of the electronic device ED (refer to Figure 1A ) and non-transmissive area NTA (refer to Figure 1B )correspond.

[0093] The base layer BL may be arranged at the lowermost position of the display panel DP, and may provide a base surface on which components of the display panel DP are arranged. The base layer BL may include a synthetic resin layer. The synthetic resin layer may include a thermosetting resin. Specifically, the synthetic resin layer may include a polyimide resin, however, it should not be limited to or thereby. The synthetic resin layer may include at least one of an acrylic resin, a methacrylic resin, a polyisoprene resin, a vinyl resin, an epoxy resin, a urethane resin, a cellulose resin, a siloxane resin, a polyamide resin, and a perylene resin. The base layer BL may include a glass substrate, a metal substrate, or an organic / inorganic composite material substrate.

[0094] The base layer BL may have a structure in which an organic layer and an inorganic layer are alternately stacked. As an example, the base layer BL may have a structure in which a first organic layer including polyimide, a first inorganic layer disposed on the first organic layer, a second organic layer including polyimide and disposed on the first inorganic layer, and a second inorganic layer disposed on the second organic layer are sequentially stacked, however, it should not be particularly limited.

[0095] The circuit element layer DP-CL may include a plurality of insulating layers and circuit elements. The plurality of insulating layers may include at least one inorganic layer and at least one organic layer. The circuit element may include a signal line and a driving circuit. The insulating layer, the semiconductor layer and the conductive layer may be formed by coating and deposition processes. Then, the insulating layer, the semiconductor layer and the conductive layer may be selectively patterned by a photolithography process and an etching process. The semiconductor pattern, the conductive pattern and the signal line of the circuit element layer DP-CL may be formed by the above-mentioned processes.

[0096] In this article, patterns arranged on (or in) the same layer may be formed by the same process. As used herein, the expression "patterns are formed by the same process" means that the patterns include the same material and have the same stacking structure. For example, when in the same layer, multiple elements may be formed in the same process and / or include the same material as each other, multiple elements may be corresponding parts of the same material layer, multiple elements may be on the same layer by forming an interface with the same lower layer or upper layer, etc., without limitation thereto.

[0097] The display element layer DP-OLED may include a pixel definition layer PDL (refer to Figure 3B ) and the light emitting element LD (refer to Figure 3B ).

[0098] The encapsulation layer TFL may be disposed on the display element layer DP-OLED and may cover the display element layer DP-OLED. The encapsulation layer TFL may prevent moisture and oxygen from entering the display element layer DP-OLED. The encapsulation layer TFL may have a stack structure of inorganic layer / organic layer / inorganic layer.

[0099] The input sensing unit ISU may be disposed directly on the display panel DP. In the present disclosure, the expression "component A is disposed directly on component B" means that there is no intervening element between component A and component B. Layers or components that are "directly" disposed relative to each other may contact each other, may form an interface therebetween, etc.

[0100] Figure 3A is a plan view of a display panel DP according to an embodiment of the present disclosure.

[0101] Reference Figure 3A , the display panel DP may include a plurality of pixels PX, a gate driving circuit GDC, a plurality of signal lines SGL, and a plurality of signal pads DP-PD.

[0102] A plurality of pixels PX may be arranged in the display area DP-DA. Each of the plurality of pixels PX may include a light emitting element LD (eg, referring to Figure 3B ) and a pixel driving circuit connected to the light emitting element LD. In this embodiment, the light emitting element LD may be an organic light emitting element.

[0103] The gate driving circuit GDC may be arranged in the non-display area DP-NDA of the display panel DP. The gate driving circuit GDC may sequentially output gate signals as electrical signals to the gate lines GL. The gate driving circuit GDC (e.g., the non-display area DP-NDA) may include transistors having layers or patterns formed by the same process (e.g., a low temperature polycrystalline silicon (LTPS) process, a low temperature polycrystalline oxide (LTPO) process, or a mixed oxide and polycrystalline silicon (HOP) process) as the layers or patterns of transistors of the pixels PX (e.g., the display area DP-DA).

[0104] However, the driving circuit of the display panel DP should not be limited to the gate driving circuit GDC, and the display panel DP may further include another driving circuit to apply a light emission control signal to the pixel PX. As an example, the display panel DP may include a light emission driving circuit.

[0105] The signal line SGL may be arranged in the display area DP-DA and the non-display area DP-NDA, such as extending from the display area DP-DA to the non-display area DP-NDA. The signal line SGL may include a gate line GL, a data line DL, a power line PL, and a control signal line CSL. Each of the gate lines GL may be connected to a corresponding pixel PX among a plurality of pixels PX, and each of the data lines DL may be connected to a corresponding pixel PX among a plurality of pixels PX. The power line PL may be connected to the pixel PX. The control signal line CSL may provide a control signal as an electrical signal to the gate drive circuit GDC.

[0106] Each of the signal lines SGL may include a line portion LP. Figure 3A Although not shown in the figure, the signal line SGL may further include a pad portion. The line portion LP may overlap the display area DP-DA and the non-display area DP-NDA, such as extending from the display area DP-DA to be arranged in the non-display area DP-NDA. The pad portion may be connected to or defined by one end (e.g., a distal end or a terminal end) of the line portion LP. The distal end may be arranged at an end portion (e.g., Figure 3A At the lowermost part of the display panel DP in the display panel.

[0107] The signal pads DP-PD may include a first pad PD1 , a second pad PD2 , and a third pad PD3 .

[0108] The first pad area PA1 and the second pad area PA2 may be arranged in the non-display area DP-NDA. The first pad area PA1 where the first pad PD1 and the second pad PD2 are arranged may be connected to the driving chip DC (refer to Figure 1B The second pad area PA2 where the third pads PD3 are arranged may overlap with the circuit board PB.

[0109] The first pad area PA1 and the second pad area PA2 may be spaced apart from each other in (or along) the first direction DR1.

[0110] The first pad area PA1 may include a first region B1 (eg, a first sub-region) where the first pads PD1 are arranged and a second region B2 (eg, a second sub-region) where the second pads PD2 are arranged.

[0111] A region (eg, a plane region) where the first and second pads PD1 and PD2 are arranged may be referred to as a first pad region PA1, and a region (eg, a plane region) where the third pads PD3 are arranged may be referred to as a second pad region PA2.

[0112] In the present embodiment, the first pads PD1 may be arranged in a row in the first region B1, wherein the row extends along the second direction DR2. However, the arrangement of the first pads PD1 in the first region B1 should not be limited thereto or thereby. As an example, the first pads PD1 may be arranged in two or more rows in the first region B1, each row extending along the second direction DR2.

[0113] Reference Figure 3A The second area B2 may be defined below the first area B1, such as closer to the far end of the display panel DP. The second pads PD2 arranged in the second area B2 may be connected to the third pads PD3 arranged in the second pad area PA2 as display panel pads via the connection signal lines S-CL.

[0114] The circuit board PB may include substrate bumps PB-BP as circuit board bumps. The substrate bumps PB-BP may be arranged in the second direction DR2. The substrate bumps PB-BP of the circuit board PB may be connected to the third pads PD3 of the second pad area PA2. The circuit board bumps may correspond to the display panel pads, respectively.

[0115] Figure 3B is a cross-sectional view of a display panel DP according to an embodiment of the present disclosure. Figure 3B The cross section of the display panel DP corresponding to one light emitting area LA and a portion of the non-light emitting area NLA is shown. The light emitting area LA and the non-light emitting area NLA will be described later.

[0116] The display panel DP may include a base layer BL, a circuit element layer DP-CL disposed on the base layer BL, a display element layer DP-OLED disposed on the circuit element layer DP-CL, and an encapsulation layer TFL disposed on the display element layer DP-OLED.

[0117] For the convenience of explanation, Figure 3B Only one transistor TFT is shown as a representative example of a transistor of a pixel driving circuit, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, a pixel PX (eg, referring to Figure 3A ) may include multiple transistors within a pixel driving circuit.

[0118] In the present embodiment, the circuit element layer DP-CL may include a barrier layer BRL, a buffer layer BFL, a first lower insulating layer 10, a second lower insulating layer 20, a third lower insulating layer 30, a fourth lower insulating layer 40, and a fifth lower insulating layer 50, a transistor TFT, a first connection electrode CNE1, and a second connection electrode CNE2, however, the present disclosure should not be limited thereto or thereby. The barrier layer BRL or the buffer layer BFL may be omitted, one or more of the first lower insulating layer 10, the second lower insulating layer 20, the third lower insulating layer 30, the fourth lower insulating layer 40, and the fifth lower insulating layer 50 may be omitted, or the circuit element layer DP-CL may further include other insulating layers. As used herein, the aforementioned barrier layer BRL, the buffer layer BFL, and a plurality of layers among the insulating layers 10 to 50 may be collectively referred to as "insulating layers".

[0119] The barrier layer BRL may be disposed on the base layer BL. The barrier layer BRL may prevent foreign matter from entering from the outside. The barrier layer BRL may include a silicon oxide layer and / or a silicon nitride layer. Each of the silicon oxide layer and the silicon nitride layer may be provided in plurality, and the plurality of silicon oxide layers may be alternately stacked with the plurality of silicon nitride layers.

[0120] The blocking layer BRL may include a light blocking layer BML as a light blocking pattern therein. The light blocking layer BML may block or absorb external light to prevent an active portion AC1 of a transistor TFT described later from being photo-degraded by external light traveling thereto. Accordingly, the reliability of the display panel DP may be improved.

[0121] The buffer layer BFL may be disposed on the barrier layer BRL. The buffer layer BFL may improve adhesion between the semiconductor pattern of the transistor TFT and the base layer BL and / or between the conductive pattern and the base layer BL. The buffer layer BFL may include a silicon oxide layer and / or a silicon nitride layer.

[0122] The semiconductor pattern of the transistor TFT may be disposed on the buffer layer BFL. The semiconductor pattern may include polysilicon, however, it should not be limited thereto or thereby. According to an embodiment, the semiconductor pattern may include amorphous silicon or metal oxide.

[0123] Figure 3B A portion of a semiconductor pattern within a semiconductor layer is shown, and when viewed in cross section, the semiconductor pattern may also be arranged in other areas of the display panel DP. The semiconductor pattern may include a first region and a second region. The first region may be doped with an N-type dopant or a P-type dopant, and may have a relatively high conductivity compared to the conductivity of the second region. The first region may substantially correspond to (or serve as) an electrode or signal line for transmitting an electrical signal. The second region may be a non-doped region or a region doped with a concentration lower than that of the first region. The second region may substantially correspond to an active portion (or channel) of a transistor.

[0124] In the semiconductor layer, the drain electrode DA1, the active portion AC1, and the source electrode SA1 may be arranged on the buffer layer BFL. The drain electrode DA1, the active portion AC1, and the source electrode SA1 may form a transistor TFT having a gate electrode GT1 described later. When the display panel DP includes another transistor in addition to the transistor TFT, the other transistor may include a material different from that of the transistor TFT and / or a layer or pattern of the other transistor may be arranged on a layer different from that of the transistor TFT. The source electrode SA1, the active portion AC1, and the drain electrode DA1 of the transistor TFT may be corresponding regions or patterns formed from a semiconductor pattern (or semiconductor layer).

[0125] The first lower insulating layer 10 may be disposed on the buffer layer BFL. The first lower insulating layer 10 may cover the semiconductor pattern. The first lower insulating layer 10 may overlap with a plurality of pixels in common.

[0126] The gate GT1 may be disposed on the first lower insulating layer 10. The gate GT1 may be part of a metal pattern of the first conductive layer (or first metal material layer). The gate GT1 may overlap the active portion AC1. The gate GT1 may be used as a mask in a process of doping a semiconductor pattern in a method of providing a display panel DP.

[0127] The gate GT1 may include titanium (Ti), silver (Ag), a silver (Ag) alloy, molybdenum (Mo), a molybdenum (Mo) alloy, aluminum (Al), an aluminum (Al) alloy, aluminum nitride (AlN), tungsten (W), tungsten nitride (WN), copper (Cu), indium tin oxide (ITO), indium zinc oxide (IZO), or the like, but should not be particularly limited.

[0128] The second lower insulating layer 20 may be disposed on the first lower insulating layer 10 and may cover the gate GT1. The second lower insulating layer 20 may overlap the plurality of pixels PX in common. Although not shown in the drawing, an upper electrode may be disposed on the second lower insulating layer 20 to overlap the gate GT1.

[0129] The third lower insulating layer 30 may be disposed on the second lower insulating layer 20 to cover the upper electrode. The first connection electrode CNE1 disposed on the third lower insulating layer 30 may be connected to the drain electrode DA1 of the transistor TFT via a contact hole CNT-1 defined by the first lower insulating layer 10, the second lower insulating layer 20, and the third lower insulating layer 30.

[0130] The fourth lower insulating layer 40 may be disposed on the third lower insulating layer 30. The second connection electrode CNE2 may be disposed on the fourth lower insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 via a contact hole CNT-2 defined by the fourth lower insulating layer 40.

[0131] The fifth lower insulating layer 50 may be disposed on the fourth lower insulating layer 40 and may cover the second connection electrode CNE2 .

[0132] The display element layer DP-OLED may include a pixel defining layer PDL and a light emitting element LD.

[0133] A pixel defining layer PDL may be disposed on the fifth lower insulating layer 50. The pixel defining layer PDL may cover a portion of the first electrode AE ​​(eg, anode) of the light emitting element LD.

[0134] The pixel opening PDL-OP may be defined by the solid material portion of the pixel defining layer PDL through the pixel defining layer PDL to expose a portion of the first electrode AE ​​to the outside of the pixel defining layer PDL. The light emitting area LA may be defined as a portion of the first electrode AE ​​exposed by the pixel opening PDL-OP. That is, the plane area of ​​the exposed portion of the first electrode AE ​​may define the light emitting area LA. The area overlapping the solid material portion of the pixel defining layer PDL may be defined as the non-light emitting area NLA.

[0135] The light emitting element LD may include a first electrode (or anode) AE, a light emitting layer EML, and a second electrode (or cathode) CE. Figure 3B Although not shown in the figure, the light emitting element LD may further include a hole control layer arranged between the first electrode AE ​​and the light emitting layer EML and an electron control layer arranged between the second electrode CE and the light emitting layer EML. The hole control layer may include a hole transport layer and a hole injection layer, and the electron control layer may include an electron transport layer and an electron injection layer.

[0136] The first electrode AE ​​may be arranged on the fifth lower insulating layer 50. The first electrode AE ​​may be a semi-transmissive electrode, a transmissive electrode, or a reflective electrode. According to an embodiment, the first electrode AE ​​may include a reflective layer formed of (or containing) Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include an electrode selected from indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ) and aluminum-doped zinc oxide (AZO). For example, the first electrode AE ​​of the light emitting element LD may have a stacked structure of ITO / Ag / ITO.

[0137] The first electrode AE ​​may be disposed on the fifth lower insulating layer 50. The first electrode AE ​​may be connected to the second connection electrode CNE2 via a contact hole CNT-3 defined by the fifth lower insulating layer 50.

[0138] The light emitting layer EML may be arranged on the first electrode AE. The light emitting layer EML may be arranged in a region corresponding to the pixel opening PDL-OP. That is, the material layer forming the light emitting layer EML as a pattern may be divided into a plurality of parts (e.g., a pattern of a light emitting material), and the divided parts of the light emitting layer EML may be respectively arranged in the pixels PX, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the light emitting layer EML may be formed in common throughout a plurality of pixels PX, such as by using an opening mask.

[0139] The second electrode CE may be disposed on the light emitting layer EML. The second electrode CE may have an integral shape and may be commonly disposed throughout the plurality of pixels PX.

[0140] The encapsulation layer TFL may be disposed on the display element layer DP-OLED. The encapsulation layer TFL may include a first inorganic layer 141, an organic layer 142 disposed on the first inorganic layer 141, and a second inorganic layer 143 disposed on the organic layer 142, however, it should not be limited thereto or thereby. According to an embodiment, the encapsulation layer TFL may further include an organic layer and an inorganic layer.

[0141] The first inorganic layer 141 and the second inorganic layer 143 may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer. The organic layer 142 may include an acrylic organic layer.

[0142] Figure 4A is a cross-sectional view of an input sensing unit ISU according to an embodiment of the present disclosure.

[0143] The input sensing unit ISU may include a first upper insulating layer IS-IL1, a first sensing conductive layer IS-CL1 disposed on the first upper insulating layer IS-IL1, a second upper insulating layer IS-IL2 disposed on the first sensing conductive layer IS-CL1, a second sensing conductive layer IS-CL2 disposed on the second upper insulating layer IS-IL2, and a third upper insulating layer IS-IL3 disposed on the second sensing conductive layer IS-CL2. The first upper insulating layer IS-IL1 may be disposed directly on the encapsulation layer TFL.

[0144] However, the first upper insulating layer IS-IL1 and / or the third upper insulating layer IS-IL3 may be omitted. When the first upper insulating layer IS-IL1 is omitted, the first sensing conductive layer IS-CL1 may be directly disposed on the encapsulation layer TFL. The third upper insulating layer IS-IL3 may be replaced with an adhesive layer or an insulating layer of an anti-reflection member of the input sensing unit ISU.

[0145] Each of the first upper insulating layer IS-IL1, the second upper insulating layer IS-IL2, and the third upper insulating layer IS-IL3 may include an inorganic layer or an organic layer. The inorganic layer may include silicon oxide, silicon nitride, or silicon oxynitride. The organic layer may include at least one of acrylic resin, methacrylic resin, polyisoprene resin, vinyl resin, epoxy resin, urethane resin, cellulose resin, siloxane resin, polyimide resin, polyamide resin, and perylene resin.

[0146] In the present embodiment, at least one of the first upper insulating layer IS-IL1, the second upper insulating layer IS-IL2, and the third upper insulating layer IS-IL3 may be an organic layer. For example, the third upper insulating layer IS-IL3 may include an organic layer.

[0147] Figure 4A Each of the first sensing conductive layer IS-CL1 and the second sensing conductive layer IS-CL2 is shown as being integrally overlapped with the display panel DP (e.g., integrally overlapped with the display panel DP) to schematically represent a single layer of the stacked structure, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, each of the first sensing conductive layer IS-CL1 and the second sensing conductive layer IS-CL2 may be patterned such as to define discrete patterns separated from each other along the encapsulation layer TFL.

[0148] Figure 4B is a plan view of an input sensing unit ISU according to an embodiment of the present disclosure. Figure 4C is along Figure 4B The display device DD (for example, referring to Figure 2 ) portion of a cross-sectional view.

[0149] Reference Figure 4B, the input sensing unit ISU may include a sensing area IS-DA and a non-sensing area IS-NDA adjacent to the sensing area IS-DA. The sensing area IS-DA and the non-sensing area IS-NDA may correspond to Figure 2 The display area DP-DA and the non-display area DP-NDA are shown in FIG.

[0150] Reference Figure 4B The input sensing unit ISU may include first electrodes E1-1 to E1-5 as first sensing electrodes, second electrodes E2-1 to E2-4 as second sensing electrodes, a first signal line SL1 as a first sensing signal line, and a second signal line SL2 as a second sensing signal line.

[0151] The first electrodes E1 - 1 to E1 - 5 and the second electrodes E2 - 1 to E2 - 4 may be arranged in the sensing area IS-DA, and may be insulated from each other while crossing each other in a plan view.

[0152] The first signal line SL1 and the second signal line SL2 may be arranged in the non-sensing area IS-NDA. The first signal line SL1 may be electrically connected to the first electrodes E1-1 to E1-5, respectively, and the second signal line SL2 may be electrically connected to the second electrodes E2-1 to E2-4, respectively.

[0153] The first electrodes E1-1 to E1-5, the second electrodes E2-1 to E2-4, the first signal line SL1 and the second signal line SL2 may be a first sensing conductive layer IS-CL1 (eg, referring to Figure 4A ) or the second sensing conductive layer IS-CL2 (eg, referring to Figure 4A ) part.

[0154] Each of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may include a plurality of conductive wires crossing each other. The plurality of conductive wires may define a plurality of openings therebetween, and each of the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 may have a mesh shape defined by the openings and the solid material portions of the conductive wires crossing each other. Each of the openings may be defined as corresponding to Figure 3B The pixel opening PDL-OP of the pixel defining layer PDL shown in FIG.

[0155] The first electrodes E1-1 to E1-5 may include a sensing portion KP1 as a first sensing pattern and a middle portion CP1 extending from and provided integrally with the sensing portion KP1. That is, the sensing portion KP1 and the middle portion CP1 may be patterned by the same process and may be integrally formed with each other as a pattern such as the same material layer, but for convenience of explanation, they will be explained separately.

[0156] The second electrodes E2 - 1 to E2 - 4 may include a sensing pattern KP2 as a second sensing pattern and a bridge pattern (or connection pattern) CP2 .

[0157] Reference Figure 4B and Figure 4C The two sensing patterns KP2 adjacent to each other may be connected to the bridge pattern CP2 via the contact hole CH-1 defined by the second upper insulating layer IS-IL2. The bridge pattern CP2 may be exposed to the outside of the second upper insulating layer IS-IL2 through the contact hole CH-1.

[0158] One of the first signal line SL1 and the second signal line SL2 can transmit a transmission signal from an external circuit to sense an external input, and the other of the first signal line SL1 and the second signal line SL2 can transmit a change in capacitance between the first electrodes E1-1 to E1-5 and the second electrodes E2-1 to E2-4 as a receiving signal to the external circuit.

[0159] The first signal line SL1 and the second signal line SL2 may have a multi-layer structure, and the first layer line and the second layer line may be connected to each other via a contact hole CH-I defined by the second upper insulating layer IS-IL2 (refer to Figure 4C ) are connected to each other.

[0160] Figure 5 is a display device DD according to an embodiment of the present disclosure (for example, referring to Figure 2 ) is an enlarged exploded perspective view of the pad area. As an example, Figure 5 The driving chip DC and the circuit board PB are shown as being separated from the display panel DP. Figure 3A The arrangement and connection relationship between the first pad area PA1 and the second pad area PA2 are described, and thus a redundant description will be omitted.

[0161] Reference Figure 5 The driving chip DC may be bonded to the display panel DP at the first pad area PA1 through the first adhesive layer CF1, and the circuit board PB may be bonded to the display panel DP at the second pad area PA2 through the second adhesive layer CF2.

[0162] In the present embodiment, the first adhesive layer CF1 and the second adhesive layer CF2 may include a non-conductive film (NCF) instead of an anisotropic conductive film (ACF). Accordingly, the first adhesive layer CF1 and the second adhesive layer CF2 as non-conductive adhesives may include a synthetic resin having an adhesive property and may not include a conductive member such as a conductive ball. Therefore, as will be described later, defects such as electrical short circuits that occur when the first adhesive layer CF1 and the second adhesive layer CF2 include conductive balls in the first pad area PA1 and the second pad area PA2, respectively, may be prevented.

[0163] The driving chip DC may include a driving integrated circuit D-IC and a driving bump DC-BP provided in the driving chip DC.

[0164] The driving integrated circuit D-IC may include an upper surface DC-US and a lower surface DC-DS opposite to the upper surface DC-US. The lower surface DC-DS of the driving integrated circuit D-IC may face the first and second pads PD1 and PD2.

[0165] The driving bumps DC-BP may be arranged on the lower surface DC-DS of the driving integrated circuit D-IC. The driving bumps DC-BP may include first bumps BP1 at which the driving chip DC is electrically connected to the first pads PD1, respectively, and second bumps BP2 at which the driving chip DC is electrically connected to the second pads PD2, respectively.

[0166] The first bumps BP1 may be arranged in the second direction DR2 , and the second bumps BP2 may be spaced apart from the first bumps BP1 in the first direction DR1 and may be arranged in the second direction DR2 . Figure 5 A structure in which each of the first bumps BP1 and the second bumps BP2 is arranged in a single row along the second direction DR2 is shown as a representative example, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, each of the first bumps BP1 and the second bumps BP2 may be arranged in two or more rows.

[0167] The driving chip DC may receive the first signal via the second pad PD2 as the output pad of the display panel DP and the second bump BP2 as the input pad of the driving chip DC. The driving chip DC may apply the second signal generated based on the first signal to the first pad PD1 as the input pad of the display panel DP via the first bump BP1 as the output pad of the driving chip DC. As an example, the driving chip DC may include a data driving circuit, and may generate the second signal based on the first signal using the data driving circuit.

[0168] The first signal may be an image signal which is a digital signal provided from the outside, and the second signal may be a data signal which is an analog signal. The driving chip DC may generate an analog voltage corresponding to the grayscale value of the image signal. The data signal may be transmitted via the data line DL (refer to Figure 3A ) is applied to the pixel PX (refer to Figure 3A ) of the light emitting element LD (refer to Figure 3B ).

[0169] Although in Figure 5Although not shown in the figure, the first bump BP1 and the second bump BP2 may protrude from the lower surface DC-DS of the driving integrated circuit D-IC and may be exposed to the outside of the driving chip DC. When the first adhesive layer CF1 is cured, the first pad PD1 may be attached and fixed to the first bump BP1, and the second pad PD2 may be attached and fixed to the second bump BP2, so that the driving chip DC and the display panel DP are electrically connected to each other. That is, the display pads may be physically and electrically connected to the driving chip bumps, so that the driving chip DC and the display panel DP are electrically connected to each other.

[0170] The circuit board PB may include a base layer P-BS and a substrate bump PB-BP provided on the base layer P-BS. The circuit board PB may include an upper surface PB-US and a lower surface PB-DS opposite to the upper surface PB-US, and the lower surface PB-DS of the circuit board PB may face the third pad PD3.

[0171] The substrate bumps PB-BP may be disposed on the lower surface PB-DS of the base layer P-BS. The substrate bumps PB-BP may be electrically connected to the display panel DP at the third pads PD3, respectively.

[0172] The substrate bumps PB-BP may be arranged in the second direction DR2. Figure 5 A structure in which the substrate bumps PB-BP are arranged in a single row along the second direction DR2 is shown as a representative example, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the substrate bumps PB-BP may be arranged in two or more rows.

[0173] The circuit board PB may provide an image signal, a driving voltage, and a control signal to the driving chip DC.

[0174] Although not shown in the figure, the substrate bump PB-BP may protrude from the lower surface PB-DS of the base layer P-BS and may be exposed to the outside of the circuit board PB. When the second adhesive layer CF2 is cured, the third pad PD3 may be (physically and electrically) attached and fixed to the substrate bump PB-BP so that the circuit board PB and the display panel DP are electrically connected to each other.

[0175] Fig. 6A and Figure 6B is along Figure 5 The display device DD (for example, referring to Figure 2 ) portion of a cross-sectional view.

[0176] In the following, reference will be made to Fig. 6A and Figure 6B The first areas B1 (refer to Figure 5 ) in the display panel DP (refer to Figure 5)'s bonding structure between the first pad PD1 and the first bump BP1 of the driving chip DC.

[0177] Fig. 6A The structure in which the first pad PD1 (e.g., electrically and physically) is joined to the first bump BP1 in the first region B1 to form a contact point CTP is shown. The contact point CTP may be defined by the physical interface of the corresponding display pad and the corresponding driver chip bump (or circuit board bump). The contact point CTP may be a point contact with the minimum contact area between the elements. Figure 6B Shows Fig. 6A The first pad PD1 and the first bump BP1 are moved or pressed toward each other to form a structure of a contact surface CTL. The contact surface may be defined by a physical interface between a corresponding display pad and a corresponding driver chip bump (or circuit board bump). The contact surface CTL may be a multi-point contact such as having a planar area greater than the planar area of ​​the contact point CTP.

[0178] Fig. 6A and Figure 6B The first pad PD1 is shown as a representative pad and the first bump BP1 is shown as a representative bump. Fig. 6A and Figure 6B The description of the contact between the first pad PD1 and the first bump BP1 can also be applied to the second region B2 (refer to Figure 5 ) between the second pad PD2 and the second bump BP2 and the third pad PD3 in the second pad area PA2 and the substrate bump PB-BP. As used herein, the driving chip DC and the circuit board PB (eg, referring to Figure 5 ) may be considered to be electrically connected to the non-display area DP-NDA (eg, a pad among the signal pads DP-PD) at a display pad (eg, a pad among the signal pads DP-PD). Figure 3A ) electrical components.

[0179] Fig. 6A and Figure 6B The signal line SGL (see Figure 3A ) is a representative example of a signal line (such as a data line DL (refer to Figure 3A )) of the end portion DL-E. In addition to the data line DL, refer to Fig. 6A and Figure 6B For the signal line SGL (refer to Figure 3A ) may also be applied to other signal lines SGL. The end portion DL-E may correspond to the corresponding first pad PD1.

[0180] Reference Fig. 6A The display panel DP may be in the first area B1 (refer to Figure 5 ) includes an insulating layer PD-CL, a data line DL (refer to Figure 3A ), an end portion DL-E of the first bonding pad PD1, a metal layer MTL, a first bump BP1, a first adhesive layer CF1 and a driving chip DC.

[0181] The insulating layer PD-CL may include a plurality of layers, such as a base layer BL, a barrier layer BRL, a first lower insulating layer 10, a second lower insulating layer 20, a third lower insulating layer 30, and an upper insulating layer ISL, which are sequentially stacked in the third direction DR3. In the present embodiment, the insulating layer PD-CL may include a base layer BL, a barrier layer BRL, a buffer layer BFL, a first lower insulating layer 10, a second lower insulating layer 20, a third lower insulating layer 30, and an upper insulating layer ISL, which are sequentially stacked in the third direction DR3.

[0182] Fig. 6A and Figure 6B The barrier layer BRL, the buffer layer BFL, and the first to third lower insulating layers 10 to 30 shown in FIG. 3 may be formed by Figure 3B The barrier layer BRL, the buffer layer BFL and the first to third lower insulating layers 10 to 30 of the display area DP-DA shown in FIG. are formed by the same process. That is, Fig. 6A and Figure 6B The stacked structure of the base layer BL, the barrier layer BRL, the buffer layer BFL, and the first to third lower insulating layers 10 to 30 shown in FIG. 1 may be configured according to the circuit element layer DP-CL (refer to FIG. 1 ). Figure 3B )'s stacking structure.

[0183] (Refer to Figure 3A ) The end portion DL-E of the data line DL may correspond to (refer to Figure 3A ) An extension portion of the data line DL disposed in the first pad area PA1 and the second pad area PA2. The end portion DL-E may be disposed on the first lower insulating layer 10 and may be covered by the second lower insulating layer 20.

[0184] In this embodiment, the terminal portion DL-E can be connected to the gate GT1 (refer to Figure 3B ) is formed by the same process. Accordingly, the end portion DL-E can be arranged at the same position as the gate electrode GT1 (refer to Figure 3B ) on the same layer (or in) and may include a gate electrode GT1 (refer to Figure 3B ) of the same material, however, the present disclosure should not be limited thereto or thereby. As an example, the end portion DL-E may be connected to the first connection electrode CNE1 (refer to Figure 3B ) or the second connection electrode CNE2 (refer to Figure 3B ) or can be formed by the same process as reference Figure 3BThat is, the end portion DL-E in the non-display area DP-NDA is connected to the display area DP-DA.

[0185] The first pad PD1 may be disposed on the third lower insulating layer 30. The first pad PD1 may include an insulating pattern SP and a conductive pattern CL. The insulating pattern SP may include a first pattern SP1 as a first insulating pattern and a second pattern SP2 as a second insulating pattern, and the conductive pattern CL may include a lower conductive pattern CL1 and an upper conductive pattern CL2.

[0186] The lower conductive pattern CL1 may be disposed on the insulating layer PD-CL. As an example, the lower conductive pattern CL1 may be disposed on the third lower insulating layer 30. Although not shown in the drawings, the lower conductive pattern CL1 may make contact (e.g., physically and / or electrically) with the end portion DL-E via a contact hole (not shown) defined by the second lower insulating layer 20 and the third lower insulating layer 30. Accordingly, the lower conductive pattern CL1 may be electrically connected to the end portion DL-E.

[0187] The first pattern SP1 may be disposed on the lower conductive pattern CL1 (hereinafter may also be referred to as the first conductive pattern CL1). The first pattern SP1 may have a quadrangular shape when viewed in cross section, however, the cross-sectional shape of the first pattern SP1 should not be limited to the quadrangular shape.

[0188] Reference Fig. 6A , the first pattern SP1 may be in contact with the first conductive pattern CL1, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, an insulating layer may be further disposed between the first pattern SP1 and the first conductive pattern CL1. In this case, the first pattern SP1 may not be in contact with the first conductive pattern CL1. Since the first conductive pattern CL1 extends farther than the outer surface (or sidewall) of the first pattern SP1, the outer surface of the first conductive pattern CL1 may be exposed to the outside of the first pattern SP1.

[0189] The upper conductive pattern CL2 may be arranged on the lower conductive pattern CL1 and may overlap at least a portion of the first pattern SP1. In the present embodiment, the upper conductive pattern CL2 may be arranged on the first pattern SP1. The upper conductive pattern CL2 may be at least partially arranged between the first pattern SP1 and the second pattern SP2. The upper conductive pattern CL2 may cover the upper surface S1U of the first pattern SP1 and the side surface S1S of the first pattern SP1 and may cover at least a portion of the upper surface C1U of the lower conductive pattern CL1.

[0190] The second pattern SP2 may be disposed on the first pattern SP1. In the present embodiment, the second pattern SP2 may be disposed on the upper conductive pattern CL2.

[0191] The upper surface S2U of the second pattern SP2 may have a predetermined curvature. The second pattern SP2 may have a width in a plane direction along the insulating layer PD-CL, which decreases as the distance from the base layer BL increases. That is, in the present embodiment, the width of the second pattern SP2 in the second direction DR2 (and / or the first direction DR1) may decrease as the distance from the base layer BL in the thickness direction increases. In an embodiment, the second pattern SP2 may include an upper surface convexly curved in a direction away from the base layer BL and a width in a direction along the base layer BL that decreases as the distance from the base layer BL increases.

[0192] The second pattern SP2 may have a dome shape whose curved surface faces the third direction DR3. Fig. 6A A structure in which the second pattern SP2 has a semicircular cross-sectional shape having a curved surface facing the third direction DR3 is shown as a representative example, however, the cross-sectional shape of the second pattern SP2 should not be limited thereto or thereby.

[0193] The lower surface S2B of the second pattern SP2 may cover at least a portion of the upper surface C2U of the upper conductive pattern CL2 . Fig. 6A A structure is shown in which the width of the lower surface S2B of the second pattern SP2 in the second direction DR2 when viewed in section is smaller than the width of the upper surface C2U of the upper conductive pattern CL2 in the second direction DR2 when viewed in section, and the lower surface S2B of the second pattern SP2 covers a portion of the upper surface C2U of the upper conductive pattern CL2.

[0194] The metal layer MTL may include a metal layer upper portion MU extending along the upper surface S2U and covering the second pattern SP2, and a metal layer side portion MS arranged adjacent to the upper conductive pattern CL2 in the second direction DR2 and extending along the outer surface of the upper conductive pattern CL2. In addition, the metal layer MTL may further include a metal layer tip portion MT arranged on the upper insulating layer ISL and protruding in the plane direction in which the first pads PD1 are arranged. That is, in the present embodiment, the metal layer tip portion MT as the protruding portion of the metal layer MTL may protrude in the second direction DR2. According to an embodiment, the metal layer side portion MS and the metal layer tip portion MT may be provided in plurality.

[0195] For convenience of explanation, the metal layer upper portion MU, the metal layer side portion MS, and the metal layer tip portion MT are defined as the metal layer MTL passing through the metal layer MTL. Fig. 6A However, the metal layer MTL may have a continuous shape defined by the various aforementioned portions.

[0196] The metal layer MTL may be disposed on the first pad PD1 to at least partially cover the upper surface S2U of the second pattern SP2 and the side surface C2S of the upper conductive pattern CL2. Fig. 6A The metal layer upper portion MU may cover the upper surface S2U of the second pattern SP2, and the metal layer side portion MS may be arranged on the side surface C2S of the upper conductive pattern CL2 to cover at least a portion of the side surface C2S of the upper conductive pattern CL2.

[0197] The metal layer MTL may cover at least a portion of the upper surface C2U of the upper conductive pattern CL2 . Fig. 6A A structure in which the metal layer upper portion MU covers both ends of the upper surface C2U of the upper conductive pattern CL2 in the second direction DR2 is shown as a representative example.

[0198] The metal layer side portion MS may contact at least a portion of the upper insulating layer ISL. Fig. 6A A structure in which the lower end of the metal layer side portion MS is in contact with the upper insulating layer ISL is shown as a representative example.

[0199] The upper insulating layer ISL may be disposed to at least partially cover the third lower insulating layer 30 and the upper conductive patterns CL2 .

[0200] The upper insulating layer ISL may contact at least a portion of the metal layer MTL. Fig. 6A The structure in which the upper insulating layer ISL contacts the side surface of the metal layer side portion MS and the lower surface of the metal layer tip portion MT is shown as a representative example. However, the position in which the upper insulating layer ISL contacts the metal layer side portion MS should not be limited thereto or thereby.

[0201] The upper insulating layer ISL may include a first upper insulating layer IS-IL1 (refer to Figure 4C ) and the second upper insulating layer IS-IL2 (refer to Figure 4C That is, the upper insulating layer ISL in the non-display area DP-NDA may be an extended portion of the upper insulating layer in the input sensing unit ISU corresponding to the display area DP-DA.

[0202] The driving chip DC and the first bumps BP1 arranged to be spaced apart from each other under the driving chip DC may be disposed on the first pad PD1. As the first pad PD1 and the first bump BP1 move toward each other (by Figure 6B As indicated by the downward arrow in FIG), an interface between each of the first bumps BP1 and the corresponding pad (ie, the corresponding first pad PD1) may be increased at the metal layer upper portion MU of the corresponding pad (ie, the corresponding first pad PD1).

[0203] The second pattern SP2 and the metal layer upper portion MU covering the second pattern SP2 may have a dome shape on the upper conductive pattern CL2. That is, the cross-sectional shape of the metal layer upper portion MU may correspond to the cross-sectional shape of the second pattern SP2. Accordingly, the cross-section of each of the second pattern SP2 and the metal layer upper portion MU may have a size that decreases in a direction away from the insulating layer PD-CL (i.e., the third direction DR3).

[0204] Accordingly, in the embodiment, when the first bump BP1 descends and contacts the metal layer upper portion MU overlapping therewith, a point contact as an initial point contact may occur. In the present embodiment, the point contact may be defined as a contact in which each of the first bumps BP1 and the metal layer upper portion MU meet in the form of a point or an area with a very small surface. Fig. 6A A contact point CTP formed at a contact portion between the metal layer upper portion MU and the first bump BP1 is shown.

[0205] As the metal layer upper portion MU makes point contact with the first bump BP1, the force applied to the metal layer upper portion MU by the first bump BP1 may be concentrated on the contact point CTP. That is, the force applied to the metal layer upper portion MU by the first bump BP1 may be concentrated in a small plane area at the contact point CTP. The pressure applied to the metal layer MTL by the first bump BP1 may increase, and the metal layer upper portion MU may be deformed in the direction of the pressure. As an example, the metal layer upper portion MU may be tensioned. That is, the metal layer upper portion MU may be tensioned due to the pressure applied to the metal layer MTL by the first bump BP1 in a direction toward the base layer BL (e.g., along the thickness direction).

[0206] In the present disclosure, pressure applied to the metal layer MTL by the first bump BP1 in the bonding process may be referred to as bonding pressure.

[0207] The first pattern SP1 may include a first photosensitive material, and the second pattern SP2 may include a second photosensitive material different from the first photosensitive material.

[0208] The first photosensitive material may be a polymer having negative photosensitivity, and the second photosensitive material may be a polymer having positive photosensitivity. Accordingly, in the photoresist process, the first pattern SP1 and the second pattern SP2 may be easily manufactured (or provided) into different discrete pattern shapes. As an example, the second pattern SP2 may be easily etched into a dome shape.

[0209] In addition, since the polymer has a modulus (e.g., elastic modulus) smaller than that of the metal material, the first pattern SP1 and the second pattern SP2 can absorb the bonding pressure applied to the metal layer MTL in the bonding process. As such, the first pattern SP1 and / or the second pattern SP2 can be referred to as an elastic pattern, an impact absorbing pattern, a bonding pressure absorbing pattern, a compressible pattern, or the like. Accordingly, the occurrence of cracks in the layer of the first pad PD1 due to the bonding pressure can be prevented.

[0210] However, the present disclosure should not be limited thereto or thereby. As an example, the first photosensitive material may be a polymer having negative photosensitivity, and the second photosensitive material may be a metal material having positive photosensitivity. Accordingly, the second pattern SP2 may absorb the bonding pressure and may also have a relatively high modulus, and therefore, the structural stability of the first pad PD1 may be improved.

[0211] The lower conductive pattern CL1 and the upper conductive pattern CL2 can be connected by referring to Figure 3B and Figure 4A As an example, the lower conductive pattern CL1 and the upper conductive pattern CL2 in the non-display area DP-NDA may be formed by the same process as the first connection electrode CNE1 and the second connection electrode CNE2 of the display area DP-DA, respectively. Accordingly, the lower conductive pattern CL1 and the upper conductive pattern CL2 may be arranged on (or in) the same layer as the first connection electrode CNE1 and the second connection electrode CNE2, respectively, and may include the same material as the first connection electrode CNE1 and the second connection electrode CNE2, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the lower conductive pattern CL1 and the upper conductive pattern CL2 may be formed by the same process as the conductive patterns included in other conductive layers or by a different process from the conductive patterns included in other conductive layers.

[0212] The lower conductive pattern CL1 may include a metal material and may have a single-layer or multi-layer structure. As an example, the lower conductive pattern CL1 may include a first lower pattern layer including titanium (Ti), a second lower pattern layer disposed on the first lower pattern layer and including aluminum (Al), and a third lower pattern layer disposed on the second lower pattern layer and including titanium (Ti).

[0213] The upper conductive pattern CL2 may include a metal material and may have a single-layer or multi-layer structure. As an example, the upper conductive pattern CL2 may include a first upper pattern layer including titanium (Ti), a second upper pattern layer disposed on the first upper pattern layer and including aluminum (Al), and a third upper pattern layer disposed on the second upper pattern layer and including titanium (Ti).

[0214] The metal layer MTL can be Figure 3B and Figure 4AThe other conductive patterns described above are formed by the same process. As an example, the metal layer MTL in the non-display area DP-NDA may be formed by contacting the first sensing conductive layer IS-CL1 (refer to Figure 4A ) or the second sensing conductive layer IS-CL2 (refer to Figure 4A ), however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the metal layer MTL may be formed by the same process as the conductive patterns included in other conductive layers or by a different process from the conductive patterns included in other conductive layers.

[0215] The metal layer MTL may include a metal material and may have a single-layer or multi-layer structure. As an example, the metal layer MTL may include a first metal layer including titanium (Ti), a second metal layer disposed on the first metal layer and including aluminum (Al), and a third metal layer disposed on the second metal layer and including titanium (Ti). That is, within the corresponding display pad, each of the upper conductive pattern CL2 and the lower conductive pattern CL1 may include a first metal layer including titanium, a second metal layer on the first metal layer and including aluminum, and a third metal layer on the second metal layer and including titanium. The above metal layers may be arranged in a direction normal to the lower surface along which the metal layers are arranged, respectively.

[0216] Figure 6B The driving chip DC and the first bump BP1 are lowered together and structural deformation occurs in the first pad PD1 and the metal layer MTL. However, the deformed shape of the first pad PD1 and the metal layer MTL may vary according to the lowering degree of the driving chip DC and the first bump BP1.

[0217] Reference Figure 6B As the metal layer upper portion MU is deformed, the size of the contact portion (or contact area) between the first bump BP1 and the metal layer upper portion MU may become larger than the contact point CTP (refer to Fig. 6A ). Figure 6B The contact portion between the first bump BP1 and the metal layer upper portion MU becomes a contact surface CTL (refer to Figure 6B ) is taken as a representative example. Accordingly, after the metal layer upper portion MU is sufficiently tensioned, the force applied to the metal layer upper portion MU by the first bump BP1 can be distributed over a wide planar area, and thus the bonding pressure can be reduced.

[0218] The bonding pressure may be transmitted to the metal layer side portion MS through the metal layer upper portion MU. Accordingly, the metal layer side portion MS may be partially bent or deformed from the vertical direction to be recessed in a direction toward the first pattern SP1 (i.e., protruding in a direction away from the first pattern SP1). Therefore, the first anchor portion A1 may be formed in the metal layer side portion MS by recessing part of the metal layer side portion MS.

[0219] Reference Figure 6B , the first anchoring portion A1 may be formed between the metal layer side portion MS and the metal layer tip portion MT, however, the position of the first anchoring portion A1 should not be limited thereto or thereby. Figure 6B ) can be arranged below the outer side wall of the metal layer side portion MS or arranged further inside relative to the outer side wall of the metal layer side portion MS, and the metal layer side portion MS is adjacent to the metal layer tip portion MT ( Fig. 6A ) corresponding to the first anchor portion A1 coincides with the outer side wall of the metal layer side portion MS.

[0220] As the first anchor portion A1 is formed, the contact state between the metal layer side portion MS and the upper insulating layer ISL may be maintained, and the bonding pressure may be dispersed. Accordingly, the risk of cracks occurring in the first pad PD1 during the bonding process may be reduced.

[0221] The bonding pressure may be transmitted to the first pattern SP1 through the metal layer MTL and the second pattern SP2. As the first pattern SP1 is compressed downward while contacting the lower conductive pattern CL1, the side surface S1S of the first pattern SP1 may be provided as an outward curved surface. Accordingly, the second anchor portion A2 may be formed at least a portion of the side surface S1S of the first pattern SP1. Figure 6B , the second anchor portion A2 may be formed below the side surface S1S of the first pattern SP1, however, the position of the second anchor portion A2 should not be limited thereto or thereby. Figure 6B ) can be arranged below the outer sidewall of the first pattern SP1 or arranged further inside relative to the outer sidewall of the first pattern SP1, and the first pattern SP1 and the lower conductive pattern CL1 ( Fig. 6A ) corresponding to the second anchor portion A2 coincides with the outer side wall of the first pattern SP1.

[0222] A separation space may be defined between the driving chip DC and the base layer BL, and the separation space may be filled with a non-conductive adhesive material. In an embodiment, a gap (e.g., a separation space) is defined between the driving chip DC and the display pad, wherein the non-conductive adhesive material fills the gap. Since there is no need to align the conductive balls, the non-conductive adhesive material may have a relatively low viscosity compared to an anisotropic conductive film. Fig. 6A, the non-conductive adhesive material may be represented by a first adhesive layer CF1 between the driving chip DC and the stack structure in contact with the driving chip DC.

[0223] As the first bump BP1 descends, the first bump BP1 may contact the contact portion of the upper conductive pattern CL2 (or the metal layer upper portion MU) after penetrating the first adhesive layer CF1. That is, the movement of the first bump BP1 and the stacked structure (e.g., the metal layer MTL to the base layer BL) in a direction toward each other may include the first bump BP1 penetrating the first adhesive layer CF1.

[0224] According to an embodiment, the first bump BP1, the metal layer MTL, the upper conductive pattern CL2, the lower conductive pattern CL1, and the end portion DL-E may sequentially contact each other (e.g., physically and / or electrically) along a signal transmission path. Accordingly, the first bump BP1, the metal layer MTL, the upper conductive pattern CL2, the lower conductive pattern CL1, and the end portion DL-E may be electrically connected to each other. Therefore, a driving signal provided from the driving chip DC (e.g., at the first bump BP1) may be transmitted along the signal transmission path (e.g., through the metal layer MTL, the upper conductive pattern CL2, the lower conductive pattern CL1, and the end portion DL-E) to the end portion DL-E (refer to Figure 6B ) is electrically connected to a light emitting element LD at a signal transmission path.

[0225] The first pad PD1 and the first bump BP1 can be directly bonded to each other without being connected to each other through an anisotropic conductive film requiring a conductive ball. Therefore, even if the display panel DP has a high resolution and includes a plurality of pixels PX, a short circuit phenomenon caused by a conductive ball can be prevented. Accordingly, the electronic device ED (for example, referring to Figure 1B ) reliability.

[0226] 7A to 7E is along Figure 5 A cross-sectional view of a portion of the display device taken along line II-II'.

[0227] 7A to 7E Each of the first pads (eg, a corresponding one of the first pads PD1-1, PD1-2, PD1-3, PD1-4, and PD1-5) is shown as a representative example of the pad and the first bump BP1 is shown as a representative example of the bump. 7A to 7E The description of the contact between the first pads (eg, the first pads PD1-1, PD1-2, PD1-3, PD1-4, and PD1-5) and the first bump BP1 may be applied to (refer to Figure 5 ) the contact between the second pad PD2 and the second bump BP2 in the second region B2 and (refer to Figure 5) Contact between the third pad PD3 in the second pad area PA2 and the substrate bump PB-BP. Therefore, redundant description will be omitted.

[0228] 7A to 7E The signal line SGL (see Figure 3A ) of the data line DL (refer to Figure 3A ) end portion DL-E. In addition to the data line DL, refer to 7A to 7E For the signal line SGL (refer to Figure 3A ) can also be applied to other signal lines SGL.

[0229] exist 7A to 7E In the same / similar reference numerals, Fig. 6A and Figure 6B , and thus, a detailed description of the same elements will be omitted, and the description will focus on different features.

[0230] Reference Fig. 7A , the display panel DP (for example, refer to Figure 5 ) can be in the first area (refer to Figure 5 The first area B1) includes an insulating layer PD-CL1, a data line (refer to Figure 3A The first pad PD1-1, the metal layer MTL-1, the first bump BP1, the first adhesive layer CF1 and the driving chip DC.

[0231] The first pad PD1 - 1 may be disposed on the third lower insulating layer 30 included in the insulating layer PD-CL.

[0232] The first pad PD1-1 may include a lower conductive pattern CL1, a first pattern SP1, an upper conductive pattern CL2, a second pattern SP2-1, and a first sub-pattern SUB1. Fig. 6A Compared with the first pad PD1 described above, the first pad PD1-1 may further include a first sub-pattern SUB1. Accordingly, the following description will focus on different features.

[0233] The second pattern SP2-1 may be arranged on the first pattern SP1 and the upper conductive pattern CL2. An upper surface S2U of the second pattern SP2-1 may have a predetermined curvature. In addition, the second pattern SP2-1 may have a thickness in the second direction DR2 that decreases as it increases in the third direction DR3 (e.g., as the distance from the insulating layer PD-CL1 increases, i.e., in the upward direction) when viewed in a cross section. The second pattern SP2-1 may have a dome shape having a curved surface toward the third direction DR3. Fig. 7AA structure in which the second pattern SP2 - 1 has a semicircular shape having a curved surface facing the third direction DR3 is shown as a representative example, however, the shape of the second pattern SP2 - 1 should not be limited thereto or thereby.

[0234] The lower surface S2B-1 of the second pattern SP2-1 may cover at least a portion of the upper surface C2U of the upper conductive pattern CL2. Fig. 7A When observed in a cross-section, the lower surface S2B-1 of the second pattern SP2-1 may have the same width as the upper surface C2U of the upper conductive pattern CL2, and therefore, the lower surface S2B-1 of the second pattern SP2-1 may completely cover the upper surface C2U of the upper conductive pattern CL2 (for example, may cover the entire upper surface C2U).

[0235] The first sub-pattern SUB1 may be disposed on the upper conductive pattern CL2. Fig. 7A , when viewed in a plane substantially parallel to the base layer BL, the first sub-pattern SUB1 may be arranged to be spaced apart from the side surface S1S on the right side of the first pattern SP1 with the upper conductive pattern CL2 interposed therebetween, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the first sub-pattern SUB1 may be arranged at the left side of the first pattern SP1.

[0236] When viewed in cross-section, the width of the first sub-pattern SUB1 in the second direction DR2 may increase downward (eg, as the distance from the insulating layer PD-CL1 decreases, ie, in the downward direction). Fig. 7A As shown in FIG. 1 , the first sub-pattern SUB1 may have a triangular shape when viewed in cross section, however, the present disclosure should not be limited thereto or thereby.

[0237] The metal layer MTL-1 may include a metal layer upper portion MU-1 covering the second pattern SP2-1, a first metal layer side portion MS1-1 arranged at the left side of the upper conductive pattern CL2 when viewed in cross-section, a second metal layer side portion MS2-1 arranged at the right side of the upper conductive pattern CL2, and a metal layer tip portion MT-1 arranged on the upper insulating layer ISL-1 and protruding in the second direction DR2.

[0238] Fig. 7A A structure in which the metal layer tip portion MT-1 is not formed in the second metal layer side portion MS2-1 is shown, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the metal layer tip portion MT-1 may be formed in the second metal layer side portion MS2-1 to cover the upper insulating layer ISL-1.

[0239] However, although for the convenience of explanation, the metal layer upper portion MU-1, the first metal layer side portion MS1-1, the second metal layer side portion MS2-1 and the metal layer tip portion MT-1 may be defined as referring to portions of the metal layer MTL-1 respectively, the metal layer MTL-1 may have a continuous shape.

[0240] The metal layer MTL-1 may at least partially cover the second pattern SP2-1 and the first sub-pattern SUB1. Fig. 7A , the second metal layer side portion MS2-1 may cover a portion of the first sub-pattern SUB1. However, the position where the second metal layer side portion MS2-1 covers the first sub-pattern SUB1 should not be limited thereto or thereby.

[0241] The portion of the upper conductive pattern CL2 covering the side surface S1S of the first pattern SP1 in the second direction DR2 may be at least partially covered by the first metal layer side portion MS1-1. That is, the exposed portion of the side surface C2S of the upper conductive pattern CL2 may be exposed without being covered by the first sub-pattern SUB1, and the exposed portion of the side surface C2S of the upper conductive pattern CL2 not covered by the first sub-pattern SUB1 may contact at least a portion of the metal layer MTL-1. Fig. 7A A first side surface exposed portion CLP1 where the side surface C2S of the upper conductive pattern CL2 contacts the metal layer MTL- 1 is shown.

[0242] The second metal layer side portion MS2-1 may contact at least a portion of the upper insulating layer ISL-1. Fig. 7A , a lower end of the second metal layer side portion MS2-1 may contact the upper insulating layer ISL-1.

[0243] The upper insulating layer ISL-1 may contact at least a portion of the metal layer MTL-1. Fig. 7A , the upper insulating layer ISL-1 may contact the side surface of the first metal layer side portion MS1-1 and may contact the lower surface of the second metal layer side portion MS2-1, however, the position where the upper insulating layer ISL-1 contacts the metal layer MTL-1 should not be limited to this or thereby.

[0244] The first sub-pattern SUB1 may be formed by the same process as the second pattern SP2-1. Accordingly, the first sub-pattern SUB1 may include the same material as the second pattern SP2-1. As an example, the first sub-pattern SUB1 may include a second photosensitive material, and the second photosensitive material may be a polymer having negative photosensitivity.

[0245] In this document, various components or patterns including a polymer having a modulus that allows absorption of bonding pressure may be referred to as the aforementioned elements. Within the same display pad, various components or patterns including a polymer having a modulus that allows absorption of bonding pressure may together define an elastic pattern, an impact absorption pattern, a bonding pressure absorption pattern, a compressible pattern, or the like. In an embodiment, the first pattern SP1, the second pattern SP2-1, and / or the corresponding sub-patterns within the same display pad may together be considered as the pressure absorption pattern of the same pad.

[0246] like Fig. 7A As shown in FIG. 1 , as the first pad PD1 - 1 includes the first sub-pattern SUB1 , the first pad PD1 - 1 may have an asymmetrical shape when viewed in cross section.

[0247] The first sub-pattern SUB1 may support a layer or pattern included in the first pad PD1-1 other than the first sub-pattern SUB1 at one side of the first pad PD1-1. As an example, in the case where the first pattern SP1 has a relatively low modulus (e.g., elastic modulus), when the first sub-pattern SUB1 has a material having a modulus higher than that of the first pattern SP1, the first pattern SP1 may be prevented from being excessively compressed or cracks may be prevented from occurring in the first pattern SP1 under bonding pressure. Accordingly, the structural stability of the first pad PD1-1 may be improved.

[0248] When the bonding pressure from the first bump BP1 compresses the metal layer MTL-1, the bonding pressure may be transmitted to the first metal layer side portion MS1-1 and the second metal layer side portion MS2-1 through the metal layer upper portion MU-1.

[0249] In this case, since the second metal layer side portion MS2-1 is spaced apart from the upper conductive pattern CL2 via the first sub-pattern SUB1 interposed therebetween, a portion of the second metal layer side portion MS2-1 may compress the first sub-pattern SUB1 and may be recessed deeper than the first metal layer side portion MS1-1. Accordingly, the anchor portion formed in the second metal layer side portion MS2-1 (e.g., the first anchor portion A1 at the right side) may be recessed deeper (e.g., further inward toward the first pattern SP1) than the anchor portion formed in the first metal layer side portion MS1-1 (e.g., the first anchor portion A1 at the left side). Therefore, the effect of the anchor portion dispersing the bonding pressure within the first pad PD1-1 may be increased.

[0250] Reference Figure 7B , the display panel DP (for example, refer to Figure 5 ) can be in the first area B1 (refer to Figure 5 ) includes the insulating layer PD-CL2, the data line (refer to Figure 3AThe first pad PD1-2, the metal layer MTL-2, the first bump BP1, the first adhesive layer CF1 and the driving chip DC.

[0251] The first pad PD1-2 may include a lower conductive pattern CL1, a first pattern SP1, an upper conductive pattern CL2, a second pattern SP2-2, a first sub-pattern SUB1-2, and a second sub-pattern SUB2-2. Fig. 7A Compared with the first pad PD1-1 described above, the first pad PD1-2 may further include a second sub-pattern SUB2-2. Accordingly, the following description will focus on Fig. 7A and Figure 7B The different characteristics between the display panels.

[0252] When viewed in cross section, one side surface of the first pattern SP1 may be spaced apart from the first sub-pattern SUB1-2 with the upper conductive pattern CL2 interposed therebetween, and the other side surface of the first pattern SP1 opposite to the one side surface of the first pattern SP1 may be spaced apart from the second sub-pattern SUB2-2 with the upper conductive pattern CL2 interposed therebetween. Figure 7B , a left side surface of the first pattern SP1 may be spaced apart from the second sub-pattern SUB2-2 with the upper conductive pattern CL2 interposed therebetween, and a right side surface of the first pattern SP1 may be spaced apart from the first sub-pattern SUB1-2 with the upper conductive pattern CL2 interposed therebetween.

[0253] At least portions of side surfaces of the upper conductive pattern CL2 may be exposed without being covered by the first and second sub-patterns SUB1-2 and SUB2-2, respectively, and portions of the upper conductive pattern CL2 exposed without being covered by the first and second sub-patterns SUB1-2 and SUB2-2, respectively, may contact at least a portion of the metal layer MTL-2.

[0254] Reference Figure 7B , a second side surface exposed portion CLP2 exposed without being covered by the second sub-pattern SUB2-2 may be defined in the side surface on the left side of the upper conductive pattern CL2, and a first side surface exposed portion CLP1 exposed without being covered by the first sub-pattern SUB1-2 may be defined in the side surface on the right side of the upper conductive pattern CL2. Since the metal layer MTL-2 and the upper conductive pattern CL2 may contact each other at the first side surface exposed portion CLP1 and the second side surface exposed portion CLP2, the metal layer MTL-2 and the upper conductive pattern CL2 may at least partially contact each other and may be electrically connected to each other. The upper insulating layer ISL-2 may contact at least a portion of the metal layer MTL-2.

[0255] As the first pad PD1-2 includes the first sub-pattern SUB1-2 and the second sub-pattern SUB2-2, the first pad PD1-2 may have a symmetrical structure when viewed in cross section, however, the present disclosure should not be limited thereto or thereby. When the first sub-pattern SUB1-2 and the second sub-pattern SUB2-2 have shapes different from each other, the first pad PD1-2 may have an asymmetrical structure when viewed in cross section.

[0256] The second sub-pattern SUB2-2 may be formed by the same process as the first sub-pattern SUB1-2. Accordingly, the second sub-pattern SUB2-2 may include the same material as the first sub-pattern SUB1-2. As an example, the second sub-pattern SUB2-2 may include a second photosensitive material, and the second photosensitive material may be a polymer having negative photosensitivity. In an embodiment, the second sub-pattern SUB2-2 and the first sub-pattern SUB1-2 may be formed by the same process as the second pattern SP2-2. The lower surface S2B-2 and the upper surface S2U-2 of the second pattern SP2-2 may be the same / similar to the lower surface S2B-1 and the upper surface S2U of the second pattern SP2-1.

[0257] The first sub-pattern SUB1-2 and the second sub-pattern SUB2-2 may support layers or patterns included in the first pad PD1-2 other than the first sub-pattern SUB1-2 and the second sub-pattern SUB2-2 at both sides of the first pad PD1-2. As an example, in the case where the first pattern SP1 has a relatively low modulus (e.g., elastic modulus), when the first sub-pattern SUB1-2 and the second sub-pattern SUB2-2 include a material having a modulus higher than that of the first pattern SP1, the first pattern SP1 may be prevented from being excessively compressed or cracks may be prevented from occurring in the first pattern SP1 under bonding pressure. Accordingly, the structural stability of the first pad PD1-2 may be improved.

[0258] When the bonding pressure from the first bump BP1 compresses the metal layer MTL-2, the bonding pressure may be transmitted to the metal layer side portion MS-2 through the metal layer upper portion MU-2.

[0259] In this case, since the metal layer side portion MS-2 is spaced apart from the upper conductive pattern CL2 via the first sub-pattern SUB1-2 and the second sub-pattern SUB2-2 interposed therebetween, portions of the metal layer side portion MS-2 may respectively compress the first sub-pattern SUB1-2 and the second sub-pattern SUB2-2 to form an anchor portion deeply recessed inwardly toward the first pattern SP1 in the metal layer MTL-2. Accordingly, the effect of dispersing the bonding pressure of the anchor portion within the first pad PD1-2 may be enhanced.

[0260] Reference Figure 7C , the display panel DP (for example, refer to Figure 5) can be in the first area (refer to Figure 5 The first area B1) includes an insulating layer PD-CL3, a data line (refer to Figure 3A The first pad PD1-3, the first bump BP1, the first adhesive layer CF1, and the driving chip DC.

[0261] The insulating layer PD-CL3 may include a base layer BL, a barrier layer BRL, a first lower insulating layer 10, a second lower insulating layer 20, and a third lower insulating layer 30 that are sequentially stacked. In the present embodiment, the insulating layer PD-CL3 may include a base layer BL, a barrier layer BRL, a buffer layer BFL, a first lower insulating layer 10, a second lower insulating layer 20, and a third lower insulating layer 30 that are sequentially stacked. Figure 7C Although not shown, the insulating layer PD-CL3 may further include an upper insulating layer (eg, the upper insulating layers ISL, ISL-1, and ISL-2 referred to in the previous embodiments).

[0262] The first pad PD1-3 may include a lower conductive pattern CL1, a first pattern SP1, an upper conductive pattern CL2-3, and a second pattern SP2-3.

[0263] The upper conductive pattern CL2 - 3 may be arranged to cover portions of the upper surface S2U- 3 of the second pattern SP2 - 3 , portions of the side surface S1S of the first pattern SP1 , and at least a portion of the upper surface C1U of the lower conductive pattern CL1 .

[0264] The second pattern SP2-3 may be arranged between the first pattern SP1 and the upper conductive pattern CL2-3. The lower surface S2B-3 of the second pattern SP2-3 may contact the upper surface S1U-3 of the first pattern SP1. The upper surface S2U-3 of the second pattern SP2-3 may be covered by the upper conductive pattern CL2-3, such as having the same plane area as the upper conductive pattern CL2-3.

[0265] Reference Figure 7C , the width of the lower surface S2B-3 of the second pattern SP2-3 in the cross section may be substantially the same as the width of the upper surface S1U-3 of the first pattern SP1 in the cross section, however, the present disclosure should not be limited thereto or thereby. According to an embodiment, the width of the lower surface S2B-3 of the second pattern SP2-3 in the cross section may be smaller than the width of the upper surface S1U-3 of the first pattern SP1. In this case, the upper conductive pattern CL2-3 may cover at least a portion of the upper surface S1U-3 of the first pattern SP1, and a portion of the upper surface S1U-3 may be exposed to the outside of the upper conductive pattern CL2-3.

[0266] The display panel DP may not include the metal layer MTL (refer to Fig. 6A). Accordingly, it is possible to prevent the first pattern SP1 and / or the second pattern SP2-3 from being in contact with the metal layer MTL (refer to Fig. 6A )Deformation in the structure of the first pad PD1-3 caused by connection.

[0267] The upper conductive pattern CL2 - 3 may directly contact the first bump BP1 , and thus, a contact point CTP- 3 may be formed between the upper conductive pattern CL2 - 3 and the first bump BP1 .

[0268] The first bump BP1, the upper conductive pattern CL2-3, the lower conductive pattern CL1, and the end portion DL-E may sequentially contact each other (e.g., physically and / or electrically) along the signal transmission path. Accordingly, the first bump BP1, the upper conductive pattern CL2-3, the lower conductive pattern CL1, and the end portion DL-E may be electrically connected to each other. Accordingly, the driving signal provided from the driving chip DC may be transmitted to the light emitting element (refer to Figure 3B light emitting element LD).

[0269] Reference Fig.7D , the display panel DP (for example, refer to Figure 5 ) can be in the first area (refer to Figure 5 The first area B1) includes an insulating layer PD-CL4, a data line (refer to Figure 3A The first pad PD1-4, the first bump BP1, the metal layer MTL-4, the first adhesive layer CF1 and the driving chip DC.

[0270] and Figure 7C Compared to the display panel shown in Fig.7D The display panel DP shown in FIG. 4 may further include a metal layer MTL- 4 and an upper insulating layer ISL- 4 .

[0271] The metal layer MTL-4 may include a metal layer upper portion MU-4 covering the upper conductive pattern CL2-3 and a metal layer side portion MS-4 disposed at the left and right sides of the upper conductive pattern CL2-3, respectively. In addition, the metal layer MTL-4 may further include a metal layer tip portion MT-4 disposed on the upper insulating layer ISL-4 and protruding in the second direction DR2.

[0272] However, for convenience of explanation, the metal layer upper portion MU-4, the metal layer side portion MS-4, and the metal layer tip portion MT-4 may be defined as portions respectively referring to the metal layer MTL-4, and the metal layer MTL-4 may have a continuous shape.

[0273] The metal layer MTL-4 may cover at least a portion of the upper conductive pattern CL2 - 3 and at least a portion of the upper insulating layer ISL-4 . Fig.7DA structure is shown in which an upper surface C2U of the upper conductive pattern CL2 - 3 contacts the metal layer MTL- 4 , and a metal layer side portion MS- 4 and a metal layer tip portion MT- 4 contact the upper insulating layer ISL- 4 .

[0274] The first bump BP1, the metal layer MTL-4, the upper conductive pattern CL2-3, the lower conductive pattern CL1, and the end portion DL-E may sequentially contact each other (e.g., physically and / or electrically) along the signal transmission path. Accordingly, the first bump BP1, the metal layer MTL-4, the upper conductive pattern CL2-3, the lower conductive pattern CL1, and the end portion DL-E may be electrically connected to each other. Therefore, the driving signal provided from the driving chip DC may be transmitted to the light emitting element (refer to Figure 3B light emitting element LD).

[0275] Reference Fig. 7E , the display panel DP (for example, refer to Figure 5 ) can be in the first area (refer to Figure 5 The first area B1) includes an insulating layer PD-CL5, a data line (refer to Figure 3A The end portion DL-E of the data line DL), the first pad PD1-5, the first bump BP1, the metal layer MTL-5, the first adhesive layer CF1 and the driving chip DC.

[0276] The first pad PD1-5 may include a lower conductive pattern CL1, a first pattern SP1, an upper conductive pattern CL2-3, a second pattern SP2-3, a first sub-pattern SUB1-5, and a second sub-pattern SUB2-5.

[0277] and Figure 7C Compared with the first pad PD1-3 shown in Fig. 7E The first pad PD1-5 shown in FIG. 1 may also include a first sub-pattern SUB1-5 and a second sub-pattern SUB2-5. Accordingly, the following description will focus on Figure 7C and Fig. 7E The different characteristics between the display panels.

[0278] The description about the first sub-pattern SUB1-5 and the second sub-pattern SUB2-5 may correspond to the description about the first sub-pattern SUB1-5 and the second sub-pattern SUB2-5. Figure 7B The description of the first sub-pattern SUB1-2 and the second sub-pattern SUB2-2 will be described below, and therefore, details about the same elements will be omitted. In addition, the description about the upper insulating layer ISL-5 may correspond to the description of the upper insulating layer ISL-5. Fig.7D Description of the upper insulating layer ISL-4.

[0279] When viewed in cross section, one side surface of the first pattern SP1 may be spaced apart from the first sub-pattern SUB1-5 with the upper conductive pattern CL2-3 interposed therebetween, and the other side surface of the first pattern SP1 opposite to the one side surface may be spaced apart from the second sub-pattern SUB2-5 with the upper conductive pattern CL2-3 interposed therebetween. Fig. 7E , the right side surface of the first pattern SP1 may be spaced apart from the second sub-pattern SUB2-5 with the upper conductive pattern CL2-3 interposed therebetween, and the left side surface of the first pattern SP1 may be spaced apart from the first sub-pattern SUB1-5 with the upper conductive pattern CL2-3 interposed therebetween.

[0280] When viewed in cross section, the width of each of the first sub-pattern SUB1-5 and the second sub-pattern SUB2-5 in the second direction DR2 may increase in a downward direction. Fig. 7E , each of the first sub-pattern SUB1 - 5 and the second sub-pattern SUB2 - 5 may have a triangular shape when viewed in cross section, however, the present disclosure should not be limited thereto or thereby.

[0281] The first sub-pattern SUB1-5 and the second sub-pattern SUB2-5 may support components included in the first pad PD1-5 other than the first sub-pattern SUB1-5 and the second sub-pattern SUB2-5 at both sides of the first pad PD1-5. As an example, in the case where the first pattern SP1 has a relatively low modulus (e.g., elastic modulus), when the first sub-pattern SUB1-5 and the second sub-pattern SUB2-5 include a material having a modulus higher than that of the first pattern SP1, the first pattern SP1 may be prevented from being excessively compressed or cracks may be prevented from occurring in the first pattern SP1 under bonding pressure. Accordingly, the structural stability of the first pad PD1-5 may be improved.

[0282] When the bonding pressure from the first bump BP1 compresses the metal layer MTL-5, the bonding pressure may be transmitted to the metal layer side portion MS-5 through the metal layer upper portion MU-5.

[0283] In this case, since the metal layer side portion MS-5 is spaced apart from the upper conductive pattern CL2-3 via the first sub-pattern SUB1-5 or the second sub-pattern SUB2-5 interposed therebetween, a portion of the metal layer side portion MS-5 may compress the first sub-pattern SUB1-5 or the second sub-pattern SUB2-5 to form a deeply recessed anchor portion. Accordingly, the effect of the anchor portion dispersing the bonding pressure may be enhanced.

[0284] In one or more embodiments, Figure 2 , Figure 3A , Figure 3B , 6A to 7EAs shown in , the display device DD (or display panel DP) includes a base layer BL and a signal line SGL, the base layer BL includes (for example, in a plan view) a display area DP-DA including a light emitting element LD and a non-display area DP-NDA adjacent to the display area DP-DA and (for example, in a plan view) including a pad, and the signal line SGL connects the light emitting element LD to the pad. In the non-display area DP-NDA, the pad among the signal pads DP-PD includes (with or without any one or more of the barrier layer BRL to the third lower insulating layer 30) a lower conductive pattern CL1 on the base layer BL, a first pattern (for example, a first pattern SP1) on the lower conductive pattern CL1 and including a first photosensitive material, an upper conductive pattern (for example, an upper conductive pattern CL2) on the lower conductive pattern CL1 and overlapping the first pattern, and a second pattern (for example, a second pattern SP2) on the first pattern and including a second photosensitive material different from the first photosensitive material.

[0285] In an embodiment, the pad may further include a sub-pattern (eg, a sub-pattern such as Fig. 7A In the pad, the first side surface of the first pattern is opposite to the second side surface of the first pattern. In the pad, the upper conductive pattern (e.g., the upper conductive pattern CL2) extends from the second side surface to the first side surface and between the first side surface and the sub-pattern, and the metal layer (e.g., the metal layer MTL-1) extends along the outer surface of each of the second pattern and the sub-pattern. Here, a portion of the side surface of the upper conductive pattern (e.g., the upper conductive pattern CL2) extending along the first side surface of the first pattern is exposed to the outside of the sub-pattern, and the metal layer (e.g., the metal layer MTL-1) extending along the outer surface of each of the second pattern and the sub-pattern contacts a portion of the side surface of the upper conductive pattern (e.g., the upper conductive pattern CL2).

[0286] In an embodiment, the pad may further include a first sub-pattern (eg, like Figure 7B The first sub-pattern SUB1-2 in the figure and the second sub-pattern facing the second side surface opposite to the first side surface of the first pattern (for example, like Figure 7B In the pad, an upper conductive pattern (eg, upper conductive pattern CL2) extends between the first side surface and the first sub-pattern and between the second side surface and the second sub-pattern.

[0287] In an embodiment, the metal layer (e.g., metal layer MTL) of the pad has a shape of a cross-section that is deformable due to pressure (e.g., bonding pressure) applied thereto by the bump in a direction toward the base layer BL, and the shape of the metal layer (e.g., metal layer MTL) deformed due to the pressure applied by the bump defines a recess (e.g., an anchoring portion) in a metal layer side portion (e.g., metal layer side portion MS) that is recessed in a direction toward the first pattern, and the recess is below the metal layer side portion (e.g., metal layer side portion MS) along the thickness direction of the pad.

[0288] Although the embodiments of the present disclosure have been described, it is to be understood that the present disclosure should not be limited to these embodiments, but a person of ordinary skill in the art can make various changes and modifications within the spirit and scope of the present disclosure as claimed in the accompanying claims. Therefore, the disclosed subject matter should not be limited to any single embodiment described herein, and the scope of the present invention should be determined according to the appended claims.

Claims

1. A display device, comprising: a base layer, the base layer comprising a display area and a non-display area adjacent to the display area; a lower insulating layer, the lower insulating layer being arranged on the base layer; a light emitting element, wherein the light emitting element is arranged in the display area; A pad, wherein the pad is arranged in the non-display area; as well as A signal line connected to the light emitting element and the pad, wherein the pad comprises: a lower conductive pattern, the lower conductive pattern being arranged on the lower insulating layer; a first pattern disposed on the lower conductive pattern and including a first photosensitive material; an upper conductive pattern disposed on the lower conductive pattern and overlapping at least a portion of the first pattern; and A second pattern is arranged on the first pattern and includes a second photosensitive material different from the first photosensitive material.

2. The display device according to claim 1, wherein: The first photosensitive material is a polymer having negative photosensitivity, and The second photosensitive material is a polymer having positive photosensitivity or a metal material having the positive photosensitivity.

3. The display device according to claim 1, wherein: The second pattern includes an upper surface that is convexly curved in a direction away from the base layer and a width in a direction along the base layer that decreases as a distance from the base layer increases.

4. The display device according to claim 1, wherein: The second pattern is disposed on the upper conductive pattern, the upper conductive pattern is disposed between the first pattern and the second pattern, and the upper conductive pattern covers an upper surface of the first pattern, a plurality of side surfaces of the first pattern, and at least a portion of an upper surface of the lower conductive pattern.

5. The display device according to claim 4, further comprising: a metal layer covering an upper surface of the second pattern and at least a portion of a plurality of side surfaces of the upper conductive pattern; as well as An upper insulating layer, the upper insulating layer covering the metal layer and at least a portion of the upper conductive pattern, wherein the metal layer includes an upper portion of the metal layer covering the second pattern and a side portion of the metal layer arranged on each of the multiple side surfaces of the upper conductive pattern, and the side portion of the metal layer is in contact with the upper insulating layer.

6. The display device according to claim 5, wherein: The metal layer further comprises: A metal layer tip portion is disposed on the upper insulating layer and protrudes in a direction in which the plurality of pads are arranged.

7. The display device according to claim 5, further comprising: a driving chip, the driving chip providing a data signal to the light emitting element, the driving chip comprising a bump in contact with the metal layer, The driving chip is electrically connected to the pad through the bump, the metal layer, the upper conductive pattern and the lower conductive pattern.

8. The display device according to claim 7, wherein: The metal layer of the pad has a cross-sectional shape that is deformable due to pressure applied to the metal layer by the bump in a direction toward the base layer, and The shape of the metal layer deformed by the pressure applied by the bump defines a recess in a side portion of the metal layer recessed in a direction toward the first pattern, the recess being below the side portion of the metal layer in a thickness direction of the pad.

9. The display device according to claim 7, wherein: A gap is defined between the driving chip and the pad, and The gap is filled with a non-conductive adhesive.

10. The display device according to claim 5, wherein: In the pad, each of the upper conductive pattern and the lower conductive pattern includes: a first metal layer comprising titanium; a second metal layer on the first metal layer and comprising aluminum; and A third metal layer is on the second metal layer and includes titanium.

11. The display device according to claim 5, wherein: In the pad, A portion of the upper surface of the upper conductive pattern is exposed to the outside of the second pattern, and The metal layer also extends along the portion of the upper surface of the upper conductive pattern.

12. The display device according to claim 5, further comprising a sub-pattern, in, The metal layer covers the second pattern and at least a portion of the sub-pattern, and when viewed in a plane parallel to the base layer, one side surface of the first pattern is separated from the sub-pattern via the upper conductive pattern interposed therebetween, and a portion of the upper conductive pattern covering the other side surface opposite to the one side surface of the first pattern is at least partially covered by the metal layer.

13. The display device according to claim 12, wherein: At least a portion of a side surface of the upper conductive pattern is exposed without being covered by the sub-pattern, and the at least a portion of the upper conductive pattern exposed without being covered by the sub-pattern contacts at least a portion of the metal layer.

14. The display device according to claim 5, further comprising: A first sub-pattern and a second sub-pattern, wherein, when observed in a cross-section, one side surface of the first pattern is separated from the first sub-pattern via the upper conductive pattern interposed therebetween, and when observed in the cross-section, another side surface of the first pattern opposite to the one side surface of the first pattern is separated from the second sub-pattern via the upper conductive pattern interposed therebetween.

15. The display device according to claim 14, wherein: One side surface of the upper conductive pattern and another side surface of the upper conductive pattern opposite to the one side surface of the upper conductive pattern are respectively at least partially exposed and not covered by the first sub-pattern and the second sub-pattern, and the portions of the upper conductive pattern respectively exposed and not covered by the first sub-pattern and the second sub-pattern are in contact with at least a portion of the metal layer.

Images