Array substrate, display panel and display device

Abstract

An array substrate, a display panel and a display device are provided. The array substrate comprises: a substrate (1); a plurality of gate line groups (2); a plurality of data lines (3); a plurality of transistors (T); a first pixel electrode (41) and a second pixel electrode (42) located in an area formed by the intersection of the gate line groups (2) and the data lines (3); at least one common line (5) in a plurality of common lines (5) in the orthographic projection of the substrate (1) is located between the orthographic projections of adjacent gate line groups (2) on the substrate (1); at least one connection line (6) in a plurality of connection lines (6) in the orthographic projection of the substrate (1) is located in the gap between adjacent pixel electrode rows (400) in the orthographic projection of the substrate (1); an insulating layer is located between the connection line (6) and the common line (5) and has a plurality of first through holes (K1), the first through holes (K1) in the orthographic projection of the substrate (1) are located in the area between the two pixel edge extension lines (w1, w2) along the second direction (Y) in which the pixel electrodes (4) extend in the orthographic projection of the substrate (1).

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor, and in particular to an array substrate, a display panel and a display device. BACKGROUND

[0002] There are various commonly used display modes for thin film transistor-liquid crystal displays (TFT-LCDs), such as a twisted nematic (TN) display mode, a vertically alignment (VA) display mode, a fringe field switching (FFS) display mode, and an in-plane switching (IPS) display mode. The VA mode has better dark state performance and higher contrast ratio than other display modes. SUMMARY

[0003] Embodiments of the present disclosure provide an array substrate, a display panel and a display device. The array substrate comprises:

[0004] a substrate;

[0005] a plurality of gate line groups located on one side of the substrate and extending along a first direction, at least one of the plurality of gate line groups comprising two gate lines extending along the first direction;

[0006] a plurality of data lines extending along a second direction;

[0007] a plurality of transistors;

[0008] a plurality of pixel electrodes, the plurality of pixel electrodes comprising a plurality of pixel electrode rows extending along the first direction and arranged along the second direction, at least one of the plurality of pixel electrode rows comprising a first pixel electrode and a second pixel electrode located in an area formed by the intersection of the gate line group and the data line and connected to the data line through the plurality of transistors, the second pixel electrode being located on a side of the first pixel electrode away from the connected data line;

[0009] a plurality of common lines located on the same side of the substrate as the gate line groups, at least one of the plurality of common lines being located between the projections on the substrate of adjacent gate line groups;

[0010] a plurality of connection lines located on the same side of the substrate as the gate line groups, at least one of the plurality of connection lines being located in a gap between adjacent pixel electrode rows in the projection on the substrate.

[0011] an insulating layer between the connection lines and the common lines, having a plurality of first vias, the common lines being conductive with the connection lines at the first vias to electrically connect at least part of the common lines through the connection lines, and the first vias being in the orthographic projection of the substrate between two pixel edge extension lines of the pixel electrodes extending along the second direction in the orthographic projection of the substrate.

[0012] In a possible implementation, the pixel electrodes have a first symmetry axis extending along the second direction and passing through the central region of the pixel electrodes, the first symmetry axis passing through a central region of the first vias.

[0013] In a possible implementation, the first vias are in the orthographic projection of the substrate within a gap between adjacent rows of the pixel electrodes in the orthographic projection of the substrate.

[0014] In a possible implementation, the first vias include first sub-vias and second sub-vias, and the connection lines include first sub-connection lines and second sub-connection lines extending along the first direction.

[0015] The first sub-connection lines are electrically connected with the common lines on one side of the gate line group through the first sub-vias.

[0016] The second sub-connection lines are electrically connected with the common lines on the other side of the gate line group through the second sub-vias.

[0017] In a possible implementation, the first sub-connection lines have first outer protrusions protruding towards one side of the pixel electrodes, the common lines have second outer protrusions protruding towards one side of the gate line group, the first outer protrusions have a first overlapping region with the second outer protrusions in the orthographic projection of the substrate, and the first sub-vias are conductive in the first overlapping region.

[0018] The second sub-connection lines have third outer protrusions protruding towards one side of the pixel electrodes, the common lines have fourth outer protrusions protruding towards one side of the gate line group, the third outer protrusions have a second overlapping region with the fourth outer protrusions in the orthographic projection of the substrate, and the second sub-vias are conductive in the second overlapping region.

[0019] In a possible implementation, the pixel electrode has a first recess at a position opposite to the first outer protrusion, the first recess has a gap between a projection of the first recess on the substrate and a projection of the first outer protrusion on the substrate; the gate line has a second recess at a position opposite to the second outer protrusion, the second recess has a gap between a projection of the second recess on the substrate and a projection of the second outer protrusion on the substrate.

[0020] The pixel electrode has a third recess at a position opposite to the third outer protrusion, the third recess has a gap between a projection of the third recess on the substrate and a projection of the third outer protrusion on the substrate; the gate line has a fourth recess at a position opposite to the fourth outer protrusion, the fourth recess has a gap between a projection of the fourth recess on the substrate and a projection of the fourth outer protrusion on the substrate.

[0021] In a possible implementation, the connection line includes a plurality of connection rings arranged in the first direction in sequence, and a series connection part connecting adjacent connection rings; the connection ring includes the first sub-connection line and the second sub-connection line.

[0022] In a possible implementation, the first sub-via hole and the second sub-via hole are located in different connection rings.

[0023] In a possible implementation, the first sub-via hole and the second sub-via hole are located in the same connection ring.

[0024] In a possible implementation, the first pixel electrode has a first outer edge extending in the second direction away from the second pixel electrode, and the second pixel electrode has a second outer edge extending in the second direction away from the first pixel electrode.

[0025] The connection ring is located in a region between an extension line of the first outer edge and an extension line of the second outer edge in the projection of the substrate.

[0026] In a possible implementation, a length of the connection ring in the first direction is 1-2 times a length of the pixel electrode in the first direction.

[0027] A minimum line width of the first sub-connection line is smaller than a maximum width of the gate line in the second direction; a minimum line width of the second sub-connection line is smaller than the maximum width of the gate line in the second direction; and a line width of the series connection part is smaller than the maximum width of the gate line in the second direction.

[0028] In a possible implementation, the connection ring has an outer edge along the first direction, and a projection of the outer edge on the substrate coincides with a portion of a projection of an outer edge of the gate line toward the pixel electrode on the substrate.

[0029] In a possible implementation, the connection line is in the same layer and of the same material as the pixel electrode.

[0030] In a possible implementation, at least one of the plurality of transistors comprises a gate electrically connected to the gate line, a first electrode electrically connected to the data line, and a second electrode electrically connected to the pixel electrode.

[0031] The second electrode of the transistor connected to the first pixel electrode is symmetrical to the second electrode of the transistor connected to the second pixel electrode with respect to the data line.

[0032] In a possible implementation, the second electrode comprises a first portion and a second portion extending along the second direction and not overlapping with each other, and a third portion extending along the first direction and connecting the first portion and the second portion.

[0033] A length of the third portion in the transistor connected to the first pixel electrode is substantially equal to a length of the third portion in the transistor connected to the second pixel electrode.

[0034] In a possible implementation, a projection of the first portion on the substrate in the transistor connected to the first pixel electrode is within a gap between adjacent pixel electrodes in a projection of the substrate.

[0035] In a possible implementation, a projection of the second portion on the substrate overlaps with a projection of the pixel electrode on the substrate.

[0036] In a possible implementation, the second electrode comprises a fourth portion extending along the second direction, and a fifth portion extending along the first direction and connecting one end of the fourth portion.

[0037] A projection of the fourth portion on the substrate overlaps with a gap between adjacent pixel electrodes in a projection of the substrate.

[0038] In a possible implementation, the array substrate comprises a first common signal line between adjacent groups of the gate lines and extending along the first direction, and a first common signal extension line connected to one side of the first common signal line and extending along the second direction.

[0039] At least part of the first common signal extension line serves as the common trace.

[0040] In one possible implementation, the array substrate includes: a second common signal line group located between adjacent gate line groups and extending along the second direction, the second common signal line group including two second common signal lines located on different sides of the data lines; the second common signal line includes: a main portion of the second common signal line extending along the second direction, and a branch portion of the second common signal line extending from one end of the main portion of the second common signal line along the first direction;

[0041] At least a portion of the second common signal line serves as the common trace, and the second common signal line is electrically connected to the connecting line through a branch of the second common signal line.

[0042] In one possible implementation, the array substrate includes a third common signal line located between adjacent gate line groups and extending along the second direction, the third common signal line being projected onto the substrate and positioned between the projected projections of the first pixel electrode onto the substrate and the projected projections of the second pixel electrode onto the substrate.

[0043] In one possible implementation, the common trace is in the same layer and made of the same material as the gate line.

[0044] Based on the same inventive concept, this disclosure also provides a display panel, which includes the array substrate as provided in the embodiments of this disclosure, and a counter substrate disposed opposite to the array substrate, wherein the counter substrate has a common electrode layer disposed on the side facing the array substrate.

[0045] Based on the same inventive concept, embodiments of this disclosure also provide a display device, which includes the display panel as described in embodiments of this disclosure. Attached Figure Description

[0046] Figure 1 One of the schematic diagrams illustrating the principle behind the formation of head-shaking wrinkles;

[0047] Figure 2 The second schematic diagram illustrating the principle behind the formation of head wrinkles;

[0048] Figure 3 This is a diagram illustrating head shake lines.

[0049] Figure 4A This is one of the schematic diagrams of the array substrate provided in the embodiments of this disclosure;

[0050] Figure 4B for Figure 4A Schematic diagram of a single film layer containing the middle gate line;

[0051] Figure 4C for Figure 4A A schematic diagram of a single-film layer containing the active layer;

[0052] Figure 4D For Figure 4A The single film layer schematic diagram of the layer where the data line is located in the middle;

[0053] Figure 4E For Figure 4A The first via hole schematic diagram in the middle;

[0054] Figure 4F For Figure 4A The single film layer schematic diagram of the layer where the pixel electrode is located in the middle;

[0055] Figure 5A The second array substrate schematic diagram provided by the embodiment of the present disclosure;

[0056] Figure 5B For Figure 5A The single film layer schematic diagram of the layer where the gate line is located in the middle;

[0057] Figure 5C For Figure 5A The single film layer schematic diagram of the layer where the active layer is located in the middle;

[0058] Figure 5D For Figure 5A The single film layer schematic diagram of the layer where the data line is located in the middle;

[0059] Figure 5E For Figure 5A The first via hole schematic diagram in the middle;

[0060] Figure 5F For Figure 5A The single film layer schematic diagram of the layer where the pixel electrode is located in the middle;

[0061] Figure 6A The third array substrate schematic diagram provided by the embodiment of the present disclosure;

[0062] Figure 6B For Figure 6A The single film layer schematic diagram of the layer where the gate line is located in the middle;

[0063] Figure 6C For Figure 6A The single film layer schematic diagram of the layer where the active layer is located in the middle;

[0064] Figure 6D For Figure 6A The single film layer schematic diagram of the layer where the data line is located in the middle;

[0065] Figure 6E For Figure 6A The first via hole schematic diagram in the middle;

[0066] Figure 6F For Figure 6A The single film layer schematic diagram of the layer where the pixel electrode is located in the middle;

[0067] Figure 7A FIG. 4 is a schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0068] Figure 7B FIG. 5 is a schematic diagram of a single film layer of a layer where a gate line is located in the array substrate of FIG. 4; Figure 7A

[0069] Figure 7C FIG. 6 is a schematic diagram of a single film layer of a layer where an active layer is located in the array substrate of FIG. 4; Figure 7A

[0070] Figure 7D FIG. 7 is a schematic diagram of a single film layer of a layer where a data line is located in the array substrate of FIG. 4; Figure 7A

[0071] Figure 7E FIG. 8 is a schematic diagram of a first via in the array substrate of FIG. 4; Figure 7A

[0072] Figure 7F FIG. 9 is a schematic diagram of a single film layer of a layer where a pixel electrode is located in the array substrate of FIG. 4; Figure 7A

[0073] Figure 8A FIG. 10 is a schematic diagram of a cross section corresponding to a dashed line AA' in the array substrate of FIG. 4; Figure 7A

[0074] Figure 8B FIG. 11 is a schematic diagram of a cross section corresponding to a dashed line BB' in the array substrate of FIG. 4; Figure 7A

[0075] Figure 8C FIG. 12 is a schematic diagram of a cross section corresponding to a dashed line CC' in the array substrate of FIG. 4; Figure 7A

[0076] Figure 8D FIG. 13 is a schematic diagram of a cross section corresponding to a dashed line DD' in the array substrate of FIG. 4; Figure 7A

[0077] Figure 9A FIG. 14 is a schematic diagram of an array substrate provided by an embodiment of the present disclosure;

[0078] Figure 9B FIG. 15 is a schematic diagram of a single film layer of a layer where a gate line is located in the array substrate of FIG. 14; Figure 7A

[0079] FIG. 16 is an equivalent schematic diagram of a pixel circuit provided by an embodiment of the present disclosure; Figure 10

[0080] FIG. 17 is a schematic diagram of liquid crystal alignment in different regions provided by an embodiment of the present disclosure. Figure 11 DETAILED DESCRIPTION

[0081] ​​​​​​​​​​In order to make the objectives, technical solutions and advantages of the embodiments of the present disclosure clearer, the following will clearly and completely describe the technical solutions of the embodiments of the present disclosure with reference to the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are some but not all of the embodiments of the present disclosure. Based on the described embodiments of the present disclosure, all other embodiments obtained by a person of ordinary skill in the art without creative effort belong to the scope of the present disclosure.

[0082] Unless otherwise defined, technical terms or scientific terms used in the present disclosure shall have the ordinary meanings as understood by a person of ordinary skill in the art to which the present disclosure pertains. The terms "first", "second" and similar terms used in the present disclosure do not denote any order, quantity or importance, but are used to distinguish different components. The terms "include", "comprise" and similar terms mean that the elements or objects before the terms encompass the elements or objects listed after the terms and their equivalents, and do not exclude other elements or objects. The terms "connect" or "connected" and similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms "upper", "lower", "left", "right" and the like are used only to represent relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0083] As used herein, "about" or "approximately" includes the recited value and means within an acceptable range of deviation for a particular value as determined by one of ordinary skill in the art to which the discussion pertains, and which relates to the error in measurement of the particular quantity (i.e., limitations of the measurement system). For example, "approximately" can mean that the difference with respect to a stated value is within one or more standard deviations, or within ± 30%, 20%, 10%, 5%.

[0084] In the drawings, the thicknesses of layers, films, panels, regions, etc., can be exaggerated for clarity. Descriptive terminology such as "above", "below", "left", "right", "upper", "lower", "up", "down", "top" and "bottom" as used herein refers to the orientation of the figure as it is shown in the drawings. Where appropriate, the descriptive terminology is used solely to more particularly indicate the relative location of an object as it is shown in the drawing. Thus, the exemplary embodiments described herein are not to be interpreted as precluding the use of other embodiments that are analogous to those described but which are not explicitly described herein. For example, a feature shown as an integral part of one embodiment can be separate and a feature shown as a separate component can be an integral part of another embodiment. Similarly, for another example, components shown as integrally formed can be constructed of multiple parts or components which can or can not be physically or electrically connected together, and the components shown as separate units can or can not be physically or electrically connected together. As will be apparent to those of ordinary skill in the art, many of the useful embodiments of the present disclosure are capable of being practiced without such specific details.

[0085] In order to keep the following description of the embodiments of the present disclosure clear and brief, the present disclosure omits the detailed description of known functions and known components.

[0086] Dual gate design is a great challenge to the design and process of the panel, mainly: 1, the number of date is reduced, the number of gate line (Gate) is increased, which makes the charging of the panel more difficult; 2, the area of the pixel (Pixel) is small, the storage capacitance Ccs of the pixel is small, and the parasitic capacitance of the pixel is almost unchanged, which is easy to be affected by the parasitic capacitance (for example, the coupling capacitance Cgs (the capacitance between the Gate and the Pixel, which can be understood as the pixel electrode and the whole structure formed by other structures electrically connected with the pixel electrode)), resulting in the generation of shaking stripe defect; and for VA product, the storage capacitance is further reduced compared with the Advanced Super Dimension Switch (ADS) product, which makes the VA Dual gate product more susceptible to the influence of the parasitic capacitance, thereby generating shaking stripe and various defects.

[0087] Specifically, in the Dual gate design, as shown in Figure 1 , the signal loaded by the long pixel is opposite to the signal loaded by the data line (for example, the first long pixel from left to right in Figure 1 is opposite to the signal loaded by the data line on the left side) near the long pixel, which will cause the long pixel to be bright when the data line (Data) signal coupling the signal (COM) of the common electrode fluctuates; the signal loaded by the short pixel is the same as the signal loaded by the data line (for example, the first short pixel from left to right in Figure 1 is the same as the second data line from left to right) near the short pixel, which will cause the short pixel to be dark when the data line (Data) signal coupling the signal (COM) of the common electrode fluctuates. Half of the colors in space are of the same polarity and cannot be averaged, and need to rely on time averaging, and in time, when the head moves, several frames of pictures may be lost, further causing the average effect in space to be poor, as shown in Figure 2 . When the head shakes left and right, the picture can be seen to have a rolling vertical stripe, which is called shaking stripe, as shown in Figure 3 .

[0088] Therefore, the present disclosure provides an array substrate, as shown in Figures 4A-4F , Figures 5A-5F , Figures 6A-6F , Figures 7A-7F , Figures 8A-8C , wherein Figure 4A is one of the schematic diagrams of the array substrate provided by the present disclosure, Figure 4B is a single film layer schematic diagram of the layer where the gate line is located in Figure 4A , Figure 4C is a single film layer schematic diagram of the layer where the active layer is located in Figure 4A , Figure 4Dfor Figure 4A A schematic diagram of the single-film layer containing the data cable. Figure 4E for Figure 4A Schematic diagram of the first through hole in the middle. Figure 4F for Figure 4A A schematic diagram of a single film layer containing the middle pixel electrode. Figure 5A This is a second schematic diagram of the array substrate provided in an embodiment of this disclosure. Figure 5B for Figure 5A A schematic diagram of a single film layer containing the middle gate line. Figure 5C for Figure 5A A schematic diagram of a single-film layer containing the active layer. Figure 5D for Figure 5A A schematic diagram of the single-film layer containing the data cable. Figure 5E for Figure 5A Schematic diagram of the first through hole in the middle. Figure 5F for Figure 5A A schematic diagram of a single film layer containing the middle pixel electrode. Figure 6A This is one of the schematic diagrams of the array substrate provided in the embodiments of this disclosure. Figure 6B for Figure 6A A schematic diagram of a single film layer containing the middle gate line. Figure 6C for Figure 6A A schematic diagram of a single-film layer containing the active layer. Figure 6D for Figure 6A A schematic diagram of the single-film layer containing the data cable. Figure 6E for Figure 6A Schematic diagram of the first through hole in the middle. Figure 6F for Figure 6A A schematic diagram of a single film layer containing the middle pixel electrode. Figure 7A This is one of the schematic diagrams of the array substrate provided in the embodiments of this disclosure. Figure 7B for Figure 7A A schematic diagram of a single film layer containing the middle gate line. Figure 7C for Figure 7A A schematic diagram of a single-film layer containing the active layer. Figure 7D for Figure 7A A schematic diagram of the single-film layer containing the data cable. Figure 7E for Figure 7A Schematic diagram of the first through hole in the middle. Figure 7F for Figure 7A A schematic diagram of a single film layer containing the middle pixel electrode. Figure 8A To and Figure 7A A schematic diagram of the cross section corresponding to the dashed line AA' in the middle. Figure 8B To and Figure 7A A schematic diagram of the cross section corresponding to the dashed line BB' in the middle. Figure 8C To and Figure 7A A cross-sectional view along the dashed line CC' is shown. The array substrate includes:

[0089] Substrate 1;

[0090] a plurality of gate line groups 2 located on one side of the substrate 1 and extending along a first direction X, at least one gate line group 2 of the plurality of gate line groups 2 comprising two gate lines 20 extending along the first direction X; specifically, the two gate lines 20 of the gate line group 2 can be a first gate line 21 and a second gate line 22 respectively;

[0091] a plurality of data lines 3 extending along a second direction Y;

[0092] a plurality of transistors T; the plurality of transistors T can comprise a plurality of first transistors T1 and a plurality of second transistors T2;

[0093] a plurality of pixel electrodes 4, the plurality of pixel electrodes 4 comprising a plurality of pixel electrode rows 400 extending along the first direction X and arranged along the second direction Y; at least one pixel electrode row 400 of the plurality of pixel electrode rows 400 comprising a first pixel electrode 41 and a second pixel electrode 42 located in an area formed by the intersection of the gate line group 2 and the data line 3 and connected to the data line 3 through the plurality of transistors T, the second pixel electrode 42 being located on a side of the first pixel electrode 41 away from the connected data line 3; specifically, the first pixel electrode 41 and the second pixel electrode 42 can be connected to the same data line 3 through different transistors T, that is, the first pixel electrode 41 is electrically connected to the data line 3 through the first transistor T1, and the second pixel electrode 42 is electrically connected to the data line 3 through the second transistor T2; the first pixel electrode 41 and the second pixel electrode 42 located in the same intersection area can serve as a pixel electrode group 40;

[0094] a plurality of common wires 5, at least one common wire 5 of the plurality of common wires 5 being located between the projections on the substrate 1 of adjacent gate line groups 2; that is, the plurality of common wires 5 can be located on different sides of the gate line group 2, and the common wires 5 on different sides of the gate line group 2 are disconnected at the location of the gate line group 2; for example, as shown in Figure 4B specifically, the plurality of common wires 5 comprises a first common signal extension line 511 located on the upper side of the gate line group 2 and another first common signal extension line 511 located on the lower side of the gate line group 2, the two first common signal extension lines 511 being disconnected at the gate line group 2;

[0095] a plurality of connection lines 6 located on the same side of the substrate 1 as the gate line group 2, at least one connection line 6 of the plurality of connection lines 6 being located in the gap between adjacent pixel electrode rows 400 in the projection on the substrate 1;

[0096] An insulating layer, located between the connecting line 6 and the common trace 5, has multiple first vias K. The common trace 5 is connected to the connecting line 6 at the first vias K, so that at least a portion of the common trace 5 is electrically connected through the connecting line 6. The orthographic projection of the first vias K onto the substrate 1 is the orthographic projection of the region between the two pixel edge extension lines of the pixel electrode 4 extending along the second direction Y onto the substrate 1. Figure 4A In the image, the pixel electrode 4 has a first edge extension line w1 extending along the second direction Y, and a second edge extension line w2. The first via K is projected onto the substrate 1, and the region located between the first edge extension line w1 and the second edge extension line w2 is projected onto the substrate 1.

[0097] In this common embodiment, the first via K1 connecting the common trace 5 and the connecting line is located in the orthographic projection of the area between the two pixel edge extension lines extending along the second direction Y of the pixel electrode 4 onto the substrate 1. That is, it is not located in the area corresponding to the vertical gap between adjacent pixel electrodes 4. This provides more space for the first transistor T1 connected to the first pixel electrode 41 and the second transistor T2 connected to the second pixel electrode 42, making the coupling capacitance formed by the gate line 20 and the first pixel electrode 41 and the connected structure approximately equal to the coupling capacitance formed by the gate line 20 and the second pixel electrode 42 and the connected structure. This improves the problem of head-shaking pattern defects in the dual-gate structure display panel. Moreover, the connecting line 6 is located in the gap between adjacent pixel electrode rows 400, which can shield the capacitance between the gate line 20 and the second electrode Tb, improving the effect of process fluctuations on the coupling capacitance of different pixels, thus preventing the head-shaking pattern problem.

[0098] Specifically, such as Figure 5D As shown, at least one of the plurality of transistors T includes: a gate (not shown in the figure, the gate line 20 can be used as the gate) electrically connected to the gate line 20, a first electrode Ta electrically connected to the data line 3, a second electrode Tb electrically connected to the pixel electrode 4, and a connection portion Tc connected to one end of the second electrode Tb; the connection portion Tc is electrically connected to the pixel electrode 4 through a second via Q; the coupling capacitance formed by the gate line 20 and the first pixel electrode 41 and the connected structure may include: the capacitance between the gate line 20 and the first pixel electrode 41, and the capacitance between the gate line 20 and the second electrode 32 of the first transistor T1; the coupling capacitance formed by the gate line 20 and the second pixel electrode 42 and the connected structure may include: the capacitance between the gate line 20 and the second pixel electrode 42, and the capacitance between the gate line 20 and the second electrode 32 of the second transistor T2.

[0099] For details, see Figure 4A and Figure 4CAs shown, the transistor T can further include the coupling capacitor formed by the gate line 20 and the first pixel electrode 41 and the connected structures, and can further include: the capacitor between the gate line 20 and the active layer 7 of the first transistor T1; the coupling capacitor formed by the gate line 20 and the second pixel electrode 42 and the connected structures, and can further include: the capacitor between the active layer 7 of the second transistor T2 connected with the second pixel electrode 42. Specifically, the capacitor generated by the gate line 20 and the active layer 7 can be only in the period when the transistor T is turned on, and in the period when the transistor T is turned off, it can be considered that the gate line 20 and the active layer 7 do not generate the capacitor, which does not affect the coupling capacitor. For example, when the first transistor T1 is turned on, the active layer 7 of the first transistor T1 is electrically connected with the second electrode Tb, the second electrode Tb is electrically connected with the first pixel electrode 41, at this time, the coupling capacitor formed by the gate line 20 and the first pixel electrode 41 and the connected structures includes: the capacitor between the gate line 20 and the first pixel electrode 41, the capacitor between the gate line 20 and the second electrode Tb of the first transistor T1, and the capacitor formed between the gate line 20 and the active layer 7 of the first transistor T1; when the second transistor T2 is turned on, the active layer 7 is electrically connected with the second electrode Tb of the second transistor T2, the second electrode Tb is electrically connected with the second pixel electrode 42, at this time, the coupling capacitor formed by the gate line 20 and the second pixel electrode 42 and the connected structures includes: the capacitor between the gate line 20 and the second pixel electrode 42, the capacitor between the gate line 20 and the second electrode Tb of the second transistor T2, and the capacitor between the gate line 20 and the active layer 7 of the second transistor T2.

[0100] It should be noted that, in the actual manufacturing process, it can be difficult to make the coupling capacitor formed by the gate line 20 and the first pixel electrode 41 and the connected structures and the coupling capacitor formed by the gate line 20 and the second pixel electrode 42 and the connected structures completely equal, therefore, in the embodiment of the present disclosure, the difference between the two can be within the range of 0F-0.0001F, that is, it is considered that the two are approximately equal. Specifically, for example, the difference between the two is within the range of 0F-0.00007F; specifically, for example, the difference between the two is 0; specifically, for example, the difference between the two is 0.00007F; specifically, for example, the difference between the two is 0.000061F; specifically, the difference between the two is within the range of 0.000036F. Specifically, for the coupling capacitor in the embodiment of the present disclosure, it can be obtained by software simulation before manufacturing the array substrate.

[0101] Specifically, the material of the active layer 5 can be Indium Gallium Zinc Oxide (IGZO), and the active layer 5 can also be amorphous silicon, low-temperature polysilicon material, etc., which is not limited here.

[0102] In one possible implementation, referring to Figures 4A-4F , Figures 5A-5FAs shown, the array substrate includes: a first common signal line 51 located between adjacent gate line groups 2 and extending along a first direction X, and a first common signal extension line 511 connected to one side of the first common signal line 51 and extending along a second direction Y; the orthographic projection of the first common signal line 51 onto the substrate 1 passes through the center of the orthographic projection of the pixel electrode 4 onto the substrate 1; at least a portion of the first common signal extension line 511 serves as a common trace 5.

[0103] In one possible implementation, such as Figure 9A and Figure 9B As shown, the array substrate may include only a first common signal extension line 511 for connection with the connection line 6; in another possible implementation, such as Figure 5A and Figure 5B As shown, the array substrate may include, in addition to the first common signal extension line 511 for connection with the connection line 6, also a first common signal extension line 511 not for connection with the connection line 6, such as... Figure 5B In the second pixel electrode row, the two first common signal extension lines 511 on the left and right are used to connect with the connecting line 6, while the first common signal extension line 511 in the middle is not connected with the connecting line 6.

[0104] For details, see Figures 4A-4F , Figures 5A-5F , Figures 6A-6F , Figures 7A-7F As shown, the extensions of the two first common signal extension lines 511 located on different sides of the gate line group 2 and connected by the connecting line 6 may not overlap, that is, they may be staggered, for example, as Figure 4A In the middle, the first common signal extension line 511 on the upper side of the gate line group 2 is not located in the same vertical direction as the first common signal extension line 511 on the lower side of the gate line group 2, so as to avoid the second electrode Tb of the transistor T.

[0105] In one possible implementation, see Figures 5A-5F , Figures 6A-6F , Figures 7A-7F As shown, the array substrate further includes a common electrode portion 512 connected to the first common signal line 51; the orthographic projection of the common electrode portion 512 onto the substrate 1 covers the orthographic projection of the connection portion Tc onto the substrate 1. Thus, a first storage capacitor is formed through the common electrode portion 60 and the connection portion Tc.

[0106] In one possible implementation, see Figures 5A-5F , Figures 6A-6F , Figures 7A-7F As shown, the orthographic projection shape of the common electrode portion 512 on the substrate 1 is similar to the orthographic projection shape of the connecting portion Tc on the substrate 1; and the center of the orthographic projection of the common electrode portion 512 on the substrate 1 coincides with the center of the orthographic projection of the connecting portion Tc on the substrate 1.

[0107] In a possible implementation, referring to Figures 6A-6F , Figures 7A-7F , Figures 8A-8C , the array substrate comprises: a second common signal line group located between the adjacent gate line groups 2 and extending along the second direction Y, the second common signal line group comprising two second common signal lines 52 respectively located at different sides of the data line 3; at least one second common signal line 52 comprises: a second common signal line main part 521 extending along the second direction Y, and a second common signal line branch 522 extending from one end of the second common signal line main part 521 along the first direction X; at least part of the second common signal line 52 acts as a common wire, and the second common signal line 52 is electrically connected to the connection line 6 through the second common signal line branch 522.

[0108] Specifically, referring to Figures 6A-6F , Figures 7A-7F , Figures 8A-8C , the extension directions of the second common signal line branches 522 located at different sides of the gate line group 2 are the same, for example, as shown in Figure 6A , the second common signal line branch 522 on the upper side of the gate line group 2 extends to the right, and the second common signal line branch 522 on the lower side of the gate line group 2 also extends to the right, so that the two second common signal line branches 522 at different sides of the gate line group 2 are conveniently connected.

[0109] Specifically, the extension lengths of the second common signal line branches 522 located at different sides of the gate line group 2 in the first direction X are the same. Specifically, the extension lengths of the second common signal line branches 522 located at different sides of the gate line group 2 in the first direction X are one fourth to three fourths of the extension length of the pixel electrode 4 in the first direction X, and specifically, the extension lengths of the second common signal line branches 522 located at different sides of the gate line group 2 in the first direction X are one half of the extension length of the pixel electrode 4 in the first direction X.

[0110] Specifically, the two ends of the same second common signal line main part 521 in the extension direction can be provided with the second common signal line branch 522, and the two second common signal line branches 522 connected to the same second common signal line main part 521 both extend to the same side direction, for example, as shown in Figure 6A , the two second common signal line branches 522 connected to the same second common signal line main part 521 both extend to the right side.

[0111] Specifically, the second common signal line branch 522 on different sides of the gate line group 2 are connected to the second common signal line main part 521 on the same side of the data line 3, for example, as shown in 6A, the second common signal line branch 522 on the upper side of the gate line group 2 is connected to the second common signal line main part 521 on the right side of the data line 3; the second common signal line branch 522 on the lower side of the gate line group 2 is also connected to the second common signal line main part 521 on the right side of the data line 3.

[0112] In a possible implementation, referring to Figures 6A-6F , Figures 7A-7F , Figures 8A-8C , the second common signal line 52 is in the orthographic projection of the substrate 1, and at least partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. In this way, the second storage capacitor is formed by the second common signal line 52 and the pixel electrode 4.

[0113] In a possible implementation, referring to Figures 4A-4F , Figures 5A-5F , Figures 6A-6F , Figures 7A-7F , the array substrate comprises: a third common signal line 53 located between adjacent gate line groups 2 and extending along the second direction Y, the orthographic projection of the third common signal line 53 on the substrate 1 is located between the orthographic projection of the first pixel electrode 41 on the substrate 1 and the orthographic projection of the second pixel electrode 42 on the substrate 1.

[0114] In a possible implementation, referring to Figure 4A and Figure 4B , the orthographic projection of the third common signal line 53 on the substrate 1 partially overlaps with the orthographic projection of the pixel electrode 4 on the substrate 1. In this way, the third storage capacitor is formed by the third common signal line 53 and the pixel electrode 4.

[0115] In a possible implementation, referring to Figures 4A-4F , Figures 5A-5F , Figures 6A-6F , Figures 7A-7F , the second common signal line 52 and the third common signal line 53 between adjacent gate line groups 2 are electrically connected to the first common signal line 51.

[0116] Specifically, as shown in Figure 10 , the first storage capacitor, the second storage capacitor and the third storage capacitor can form a storage capacitor Ccs, the drain of the transistor T (i.e. the second pole Tb) and the structure electrically connected to the drain (such as the pixel electrode 4, the active layer 7), and the gate line 20 can form a coupling capacitor Cgs, and Clc can be the capacitor generated by the liquid crystal between the array substrate and the opposite substrate.

[0117] In a possible implementation, in combination with Figure 4A andFigure 4D As shown, the first common signal extension line 511 is as the common line 5; the second poles Tb of the transistors T connected with the first pixel electrode 41 and the second poles Tb of the transistors T (i.e. the first transistor T1) connected with the second pixel electrode 42 are symmetrical about the data line 3 (optionally, here the first pixel electrode 41 and the second pixel electrode 42 can be not connected to the same data line 3, in the row direction, the first pixel electrode 41 and the second pixel electrode 42 are arranged alternately, for example, the arrangement is first pixel electrode 41, second pixel electrode 42, first pixel electrode 41, second pixel electrode 42, and so on). Specifically, in combination with Figure 4A and Figure 4D As shown, the second poles Tb of the transistors T connected with the first pixel electrode 41 (i.e. the second transistor T2) and the second poles Tb of the transistors T connected with the second pixel electrode 42 are the same in pattern shape and size. Specifically, for example, the second poles Tb of the first transistor T1 and the second transistor T2 each include: a first part Tb1 and a second part Tb2 extending along the second direction Y and the extension lines do not coincide, and a third part Tb3 extending along the first direction X and connecting the first part Tb1 and the second part Tb2; the first part Tb1 of the first transistor T1 and the first part Tb1 of the second transistor T2 are the same in width along the first direction X and the same in length along the second direction Y; the second part Tb2 of the first transistor T1 and the second part Tb2 of the second transistor T2 are the same in width along the first direction X and the same in length along the second direction Y; the third part Tb3 of the first transistor T1 and the third part Tb3 of the second transistor T2 are the same in length along the first direction X and the same in width along the second direction Y; specifically, the minimum distance between the third part Tb3 of the first transistor T1 and the gate line 20 along the second direction Y is the same as the minimum distance between the third part Tb3 of the second transistor T2 and the gate line 20 along the second direction Y.

[0118] In a possible implementation, in combination with Figure 4A and Figure 4D As shown, the length c1 of the third part Tb3 of the transistor T connected with the first pixel electrode 41 is substantially equal to the length c2 of the third part Tb3 of the transistor T connected with the second pixel electrode 42.

[0119] In a possible implementation, in combination with Figure 4A and Figure 4D As shown, Figure 5A and Figure 5DAs shown, the orthographic projection of the first portion Ta of the transistor T (i.e., the first transistor T1) connected to the first pixel electrode 41 onto the substrate 1, lies within the orthographic projection of the gap between adjacent pixel electrodes 4. That is, the first transistor T1 can be positioned at a location corresponding to the vertical gap between adjacent pixel electrodes 4, approximately the same as the position of the second transistor T2. Consequently, the lengths of the third portion Tb3 of the first transistor T1 and the third portion Tb3 of the second transistor T2 in the first direction X are approximately equal. Specifically, the orthographic projection of the first portion Ta of the transistor T (i.e., the second transistor T2) connected to the second pixel electrode 42 onto the substrate 1, lies within the orthographic projection of the gap between adjacent pixel electrodes 4.

[0120] In one possible implementation, see Figures 4A-4F , Figures 5A-5F , Figures 6A-6F , Figures 7A-7F As shown, the orthographic projection of the second part Tb2 onto the substrate 1 overlaps with the orthographic projection of the pixel electrode 4 onto the substrate 1. Specifically, the second part Tb2 extends along the second direction Y, and its orthographic projection onto the substrate 1 passes through the center of the pixel electrode 4, so as to roughly coincide with the vertical dark lines in the middle of the pixel electrode 4 on the display panel. This avoids the vertical dark lines in the middle being too thick when they do not coincide, which would affect the aperture ratio of the display panel.

[0121] In one possible implementation, see Figures 6A-6F , Figures 7A-7F As shown, the second common signal line 52 serves as a common trace; the second electrode Tb includes: a fourth part Tb4 extending along the second direction Y, and a fifth part Tb5 extending along the first direction X and connected to one end of the fourth part Tb4; the orthographic projection of the fourth part Tb4 on the substrate 1 overlaps with the orthographic projection of the gap between adjacent pixel electrodes 4 on the substrate 1. That is, the fourth part Tb4 of the first transistor T1 and the fourth part Tb4 of the second transistor T2 are both disposed at the vertical gap position between adjacent pixel electrodes 4 (i.e., no similar...). Figure 4A The third part Tb3, which is closer to the gate line 20 and extends along the first direction X, can reduce or eliminate the capacitance between the gate line 20 and the third part Tb3, thereby improving the problem of head-shaking pattern defects in the dual-gate structure display panel.

[0122] For details, see Figures 6A-6F , Figures 7A-7FAs shown in FIG. 1, the fourth part Tb4 of the first transistor T1 and the fourth part Tb4 of the second transistor T2 can be located at the vertical gap between the first pixel electrode 41 and the second pixel electrode 42. The fifth part Tb5 of the first transistor T1 can extend from the end of the fourth part Tb4 to the side close to the data line 3 connected to the first transistor T1; the fifth part Tb5 of the second transistor T2 can extend from the end of the fourth part Tb4 to the side away from the data line 3 connected to the second transistor T2.

[0123] Specifically, referring to FIG. 1, Figures 6A-6F , Figures 7A-7F As shown in FIG. 1, the fifth part Tb5 of the first transistor T1 extends along the first direction X and passes through the central region of the pixel electrode 4 in the orthographic projection of the substrate 1; the fifth part Tb5 of the second transistor T1 extends along the first direction X and passes through the central region of the pixel electrode 4 in the orthographic projection of the substrate 1.

[0124] Specifically, referring to FIG. 1, Figures 6A-6F , Figures 7A-7F As shown in FIG. 1, the extension length of the fourth part Tb4 in the second direction Y can be one fourth to three fourths of the length of the pixel electrode 4 in the second direction Y, and specifically, can be one half. Specifically, the extension length of the fifth part Tb5 in the first direction X can be one fourth to three fourths of the length of the pixel electrode 4 in the first direction X, and specifically, can be one half.

[0125] Specifically, the extension length of the fourth part Tb4 of the first transistor T1 in the second direction Y is substantially equal to the extension length of the fourth part Tb4 of the second transistor T2 in the second direction Y. Specifically, the extension length of the fifth part Tb5 of the first transistor T1 in the first direction X is substantially equal to the extension length of the fifth part Tb5 of the second transistor T2 in the first direction X.

[0126] In a possible implementation, referring to FIG. 1, Figure 4A As shown in FIG. 1, the pixel electrode 4 has a first axis of symmetry L extending along the second direction Y and passing through the central region of the pixel electrode 4, and the first axis of symmetry L passes through the central region of the first via K. That is, the first via K is located in the central region of the pixel electrode 4, and provides more setting space for the first transistor T1 connected to the first pixel electrode 41 and the second transistor T2 connected to the second pixel electrode 42.

[0127] In a possible implementation, referring to FIG. 1, Figures 4A-4F , Figures 5A-5F , Figures 6A-6F , Figures 7A-7FAs shown, the orthographic projection of the first via K onto the substrate 1 is located within the gap between adjacent pixel electrode rows 400, which lies within the orthographic projection of the substrate 1. This is to avoid affecting the normal display of the display panel if the first via K1 is located in the area where the pixel electrode 4 is located.

[0128] In one possible implementation, see Figures 4A-4F , Figures 5A-5F , Figures 6A-6F , Figures 7A-7F As shown, the first via K includes a first sub-via K1 and a second sub-via K2; the connecting line 6 includes a first sub-connecting line 61 and a second sub-connecting line 62 extending along the first direction X, specifically, as shown... Figure 4A and Figure 4E As shown, the extension lines of the first sub-connection line 61 and the second sub-connection line 62 may not coincide, and they may not be located in the same extension direction. They are staggered in the first direction X. Specifically, the orthographic projection of the first sub-connection line 61 on the substrate 1 may partially coincide with the orthographic projection of the first gate line 21 on the substrate 1, and the orthographic projection of the first sub-connection line 61 on the substrate 1 may not coincide with the orthographic projection of the second gate line 22 on the substrate 1. The orthographic projection of the second sub-connection line 62 on the substrate 1 may partially coincide with the orthographic projection of the second gate line 22 on the substrate 1, and the orthographic projection of the second sub-connection line 62 on the substrate 1 may not coincide with the orthographic projection of the first gate line 21 on the substrate 1. The first sub-connection line 61 is electrically connected to the common trace 5 on one side of the gate line group 2 through the first sub-via K1. The second sub-connection line 62 is electrically connected to the common trace 5 on the other side of the gate line group 2 through the second sub-via K2.

[0129] For details, see Figure 8D As shown, where, Figure 8D It can be Figure 7A The cross-sectional diagram at the dashed line DD' shows that the first via K can be a semi-suspended via. Specifically, the first via K partially exposes the common trace 5 and partially exposes the substrate 1. The connecting line 6 partially contacts the common trace 5 and partially contacts the substrate 1 at the first via K. In this embodiment, the common trace 5 and the connecting line 6 are connected through the semi-suspended via, so that the first via K forms a stepped structure inside. This helps to guide the alignment liquid, prevents the alignment liquid from not adhering, improves the uniformity of the alignment liquid on the array substrate, avoids moiré patterns on the screen, and improves display quality.

[0130] Specifically, in combination Figures 8A-8D As shown, the insulating layer may include one or a combination of the following film layers:

[0131] Gate insulating layer 11;

[0132] Passivation layer 12;

[0133] Planarization layer 13.

[0134] Specifically, the flat layer 13 can be an organic film layer, and the passivation layer 12 can be a PVX layer, for example, including a silicon nitride material layer.

[0135] In a possible implementation, referring to Figures 4A-4F illustrated, the first sub-connection line 61 has a first outer protrusion 64 protruding toward the side of the pixel electrode 4, the common wire 5 has a second outer protrusion 54 protruding toward the side of the gate line group 2, the first outer protrusion 64 has a first overlapping area with the second outer protrusion 54 in the orthographic projection of the substrate 1, and is conductive through the first sub-via K1 in the first overlapping area; the second sub-connection line 62 has a third outer protrusion 65 protruding toward the side of the pixel electrode 4, the common wire 5 has a fourth outer protrusion 55 protruding toward the side of the gate line group 2, the third outer protrusion 65 has a second overlapping area with the fourth outer protrusion 55 in the orthographic projection of the substrate 1, and is conductive through the second sub-via K2 in the second overlapping area.

[0136] Specifically, for the first common signal extension line 511 as the common wire 5, the second outer protrusion 54 and the fourth outer protrusion 55 can be connected to the end of the first common signal extension line 511; for the second common signal line 52 as the common wire, the second outer protrusion 54 and the fourth outer protrusion 55 can be connected to the end of the second common signal line branch 52.

[0137] In a possible implementation, referring to Figures 4A-4F illustrated, the pixel electrode 4 has a first recess 43 at a position opposite to the first outer protrusion 64, the first recess 43 has a gap between the orthographic projection of the substrate 1 and the first outer protrusion 64 in the orthographic projection of the substrate 1; the gate line 20 has a second recess 23 at a position opposite to the second outer protrusion 54, the second recess 23 has a gap between the orthographic projection of the substrate 1 and the second outer protrusion 54 in the orthographic projection of the substrate 1; the pixel electrode 4 has a third recess 44 at a position opposite to the third outer protrusion 65, the third recess 44 has a gap between the orthographic projection of the substrate 1 and the third outer protrusion 65 in the orthographic projection of the substrate 1; the gate line 20 has a fourth recess 24 at a position opposite to the fourth outer protrusion 55, the fourth recess 24 has a gap between the orthographic projection of the substrate 1 and the fourth outer protrusion 54 in the orthographic projection of the substrate 1.

[0138] In a possible implementation, referring to Figures 4A-4F , Figures 5A-5F , Figures 6A-6F , Figures 7A-7FAs shown, the connection line 6 includes: a plurality of connection rings distributed in the first direction in sequence, and a series part 63 connecting adjacent connection rings; the connection ring includes a first sub-connection line 61, and a second sub-connection line 62. In this way, the capacitance between the gate line 20 and the second electrode Tb can be shielded by the connection ring, and the influence of process fluctuation on the coupling capacitance of different pixels is improved, thereby avoiding the problem of wobbling lines.

[0139] In a possible implementation, referring to Figure 5A and Figure 5F As shown, the array substrate further includes: an in-ring bump 60 located in the connection ring, which can be used to identify the position of a specific pixel, for example, the in-ring bump 60 is used to identify the position of a red pixel, or is used to identify the position of a green pixel, or is used to identify the position of a blue pixel.

[0140] In a possible implementation, referring to Figures 4A-4F , Figures 5A-5F The first sub-via K1 and the second sub-via K2 are located in different connection rings.

[0141] In a possible implementation, referring to Figures 6A-6F , Figures 7A-7F The first sub-via K1 and the second sub-via K2 are located in the same connection ring.

[0142] In a possible implementation, referring to Figure 4F and Figure 5F The first pixel electrode 41 has a first outer edge a1 extending along the second direction Y away from the second pixel electrode 42, and the second pixel electrode 42 has a second outer edge a2 extending along the second direction Y away from the first pixel electrode 41; in the orthographic projection of the substrate 1, the connection ring is located in the region between the extension line of the first outer edge a1 and the extension line of the second outer edge a2.

[0143] In a possible implementation, referring to Figures 4A-4F As shown, the length b1 of the connection ring in the first direction X is 1-2 times the length b2 of the pixel electrode 4 in the first direction X; the minimum line width b3 of the first sub-connection line 61 is smaller than the maximum width b4 of the gate line 20 in the second direction Y; the minimum line width b5 of the second sub-connection line 62 is smaller than the maximum width b4 of the gate line 20 in the second direction Y; and the line width b6 of the series part 63 is smaller than the maximum width b4 of the gate line 20 in the second direction Y.

[0144] In a possible implementation, referring to Figures 4A-4F , Figures 5A-5F , Figures 6A-6F , Figures 7A-7FAs shown, the outer edge a3 of the connecting ring along the first direction X is in the orthographic projection of the substrate 1, which coincides with the part of the outer edge a4 of the gate line 20 toward the pixel electrode 4 in the orthographic projection of the substrate 1. In this way, the capacitance between the gate line 20 and the second electrode Tb can be shielded by the connecting line 6, and the influence of process fluctuation on the coupling capacitance of different pixels is improved, thereby avoiding the problem of wobbling lines.

[0145] In a possible implementation, the connecting line 6 is in the same layer and of the same material as the pixel electrode 4. In this way, the connecting line 6 is formed at the same time as the pixel electrode 4, so as to simplify the manufacturing process of the display panel and reduce the manufacturing cost of the display panel.

[0146] In a possible implementation, the common wire 5 is in the same layer and of the same material as the gate line 20. In this way, the common wire 5 is formed at the same time as the gate line 20, so as to simplify the manufacturing process of the display panel and reduce the manufacturing cost of the display panel.

[0147] Based on the same inventive concept, the display panel provided by the embodiments of the present disclosure also includes the array substrate provided by the embodiments of the present disclosure, and further includes an opposite substrate arranged opposite to the array substrate, and the opposite substrate is provided with a common electrode layer on a side facing the array substrate.

[0148] In a possible implementation, a liquid crystal layer can be arranged between the array substrate and the opposite substrate, and the liquid crystal layer has a plurality of liquid crystal regions in the region where the pixel electrode 4 is located, and the liquid crystal layers in different liquid crystal regions have different orientations in the initial state. Specifically, refer to Figure 11 As shown, for example, the liquid crystal layer has four liquid crystal regions in the region where the pixel electrode 4 is located, and the four liquid crystal regions can be located in the first region, the second region on one side of the orthographic projection of the first common signal line 51 on the substrate 1, and the third region, the fourth region on the other side of the orthographic projection of the first common signal line 51 on the substrate 1. Specifically, the array substrate can have a first alignment film layer 81, and the opposite substrate can be provided with a second alignment film layer 82, and the orientations of the first alignment film layer 81 and the second alignment film layer 82 in different regions can be as shown in Figure 11 As shown, the orientation of the first alignment film layer 81 can be perpendicular to the orientation of the second alignment film layer 82.

[0149] Specifically, the liquid crystal layer in different liquid crystal regions in the initial state can be understood as the deflection state of the liquid crystal layer in different liquid crystal regions when no electric field is applied, that is, the state when no voltage is formed between the pixel electrode 4 and the common electrode.

[0150] Specifically, in combination with Figure 8A , Figure 8B and Figure 8CThe opposite substrate can further include an opposite substrate 90, a black matrix layer 91 and a color filter layer (not shown in the figure) on one side of the opposite substrate 90. Optionally, in a direction perpendicular to the substrate, the black matrix layer covers the data line and the second common signal line extending along the second direction on both sides of the data line, and can cover the pixel electrode or at least partially cover the pixel electrode. The color filter layer is away from the substrate side of the common electrode layer. Optionally, the common electrode layer of the opposite substrate and the common wiring of the array substrate transmit the same common signal. Optionally, the common wiring can also be a different signal from the common electrode layer of the opposite substrate.

[0151] In a possible implementation, in order to reduce the number of masks, the data line 3 and the active layer 5 can be formed by one mask process, that is, the side of the data line 3 facing the substrate 1 can further include an active layer (the material of the active layer can be amorphous silicon, low-temperature polycrystalline silicon, or metal oxide, etc.).

[0152] Based on the same inventive concept, the display device provided by the embodiments of the present disclosure includes the display panel provided by the embodiments of the present disclosure.

[0153] Although the preferred embodiments of the present application have been described, those skilled in the art can make further changes and modifications to the embodiments once they know the basic inventive concept. Therefore, the appended claims are intended to be interpreted as including all the preferred embodiments and all the changes and modifications falling within the scope of the present application.

[0154] Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application is also intended to include these modifications and variations.

Claims

1. An array substrate, wherein, include: Substrate; Multiple gate line groups are located on one side of the substrate and extend along a first direction, and at least one of the multiple gate line groups includes two gate lines extending along the first direction. Multiple data lines extend along the second direction; Multiple transistors; A plurality of pixel electrodes, the plurality of pixel electrodes comprising: a plurality of pixel electrode rows extending along a first direction and arranged along a second direction; at least one of the plurality of pixel electrode rows comprises: a first pixel electrode and a second pixel electrode located in the region formed by the intersection of the gate line group and the data line and connected to the data line through the plurality of transistors, wherein the second pixel electrode is located on the side of the first pixel electrode away from the connected data line; Multiple common traces are located on the same side of the substrate as the gate line group, and at least one of the multiple common traces is located between the orthographic projections of adjacent gate line groups on the substrate. Multiple connection lines are located on the same side of the substrate as the gate line group, and at least one of the multiple connection lines is projected onto the substrate, with the gap between adjacent pixel electrode rows located within the projected area of ​​the substrate; at least one of the connection lines includes: a first sub-connection line and a second sub-connection line extending along the first direction. An insulating layer, located between the connecting line and the common trace, has a plurality of first vias. The common trace is connected to the connecting line at the first vias to electrically connect at least a portion of the common trace through the connecting line. The orthographic projection of the first vias onto the substrate is the orthographic projection of the region between two pixel edge extension lines extending along the second direction of the pixel electrode onto the substrate. The first vias include: a first sub-via and a second sub-via. The first sub-connecting line is electrically connected to the common trace on one side of the gate line group through the first sub-via. The second sub-connecting line is electrically connected to the common trace on the other side of the gate line group through the second sub-via.

2. The array substrate as claimed in claim 1, wherein, The pixel electrode has a first axis of symmetry extending along the second direction and passing through the central region of the pixel electrode, the first axis of symmetry passing through the central region of the first via.

3. The array substrate as described in claim 1 or 2, wherein, The first via is projected onto the substrate in the orthographic projection, and the gap between adjacent rows of pixel electrodes is located within the orthographic projection of the substrate.

4. The array substrate as claimed in claim 1, wherein, The first sub-connection line has a first outward protrusion protruding towards the pixel electrode side, and the common trace has a second outward protrusion protruding towards the gate line group side. The first outward protrusion and the second outward protrusion have a first overlapping area in the orthographic projection on the substrate, and are connected through the first sub-via in the first overlapping area. The second sub-connection line has a third protrusion that protrudes toward the pixel electrode side, and the common trace has a fourth protrusion that protrudes toward the gate group side. The orthographic projection of the third protrusion onto the substrate and the orthographic projection of the fourth protrusion onto the substrate have a second overlapping area, and are connected through the second sub-via in the second overlapping area.

5. The array substrate as claimed in claim 4, wherein, The pixel electrode has a first recess at a position opposite to the first protrusion, and there is a gap between the first recess and the first protrusion in the orthographic projection of the substrate; the gate line has a second recess at a position opposite to the second protrusion, and there is a gap between the second recess and the second protrusion in the orthographic projection of the substrate. The pixel electrode has a third recess at a position opposite to the third protrusion, and there is a gap between the third recess and the third protrusion in the orthographic projection of the substrate; the gate line has a fourth recess at a position opposite to the fourth protrusion, and there is a gap between the fourth recess and the fourth protrusion in the orthographic projection of the substrate.

6. The array substrate as claimed in claim 1, wherein, The connecting line includes: a plurality of connecting loops distributed sequentially along the first direction, and a series portion connecting adjacent connecting loops; the connecting loop includes a first sub-connecting line and a second sub-connecting line.

7. The array substrate as claimed in claim 6, wherein, The first sub-via and the second sub-via are located in different connecting rings.

8. The array substrate as claimed in claim 6, wherein, The first sub-via and the second sub-via are located on the same connecting ring.

9. The array substrate as claimed in claim 6, wherein, The first pixel electrode has a first outer edge extending along the second direction on the side away from the second pixel electrode, and the second pixel electrode has a second outer edge extending along the second direction on the side away from the first pixel electrode. The region between the extension lines of the first outer edge and the second outer edge of the connecting ring in the orthographic projection of the substrate is within the orthographic projection of the substrate.

10. The array substrate as claimed in claim 6, wherein, The length of the connecting ring in the first direction is 1 to 2 times the length of the pixel electrode in the first direction; The minimum linewidth of the first sub-connecting line is less than the maximum width of the gate line in the second direction; the minimum linewidth of the second sub-connecting line is less than the maximum width of the gate line in the second direction; the linewidth of the serial connection portion is less than the maximum width of the gate line in the second direction.

11. The array substrate as claimed in claim 6, wherein, The orthographic projection of the outer edge of the connecting ring along the first direction onto the substrate coincides with the portion of the orthographic projection of the outer edge of the gate line toward the pixel electrode onto the substrate.

12. The array substrate as claimed in claim 1, wherein, The connecting line is in the same layer and made of the same material as the pixel electrode.

13. The array substrate as claimed in claim 1, wherein, At least one of the plurality of transistors includes: a gate electrically connected to the gate line, a first electrode electrically connected to the data line, and a second electrode electrically connected to the pixel electrode; The second electrode of the transistor to which the first pixel electrode is connected is symmetrical about the data line to the second electrode of the transistor to which the second pixel electrode is connected.

14. The array substrate as claimed in claim 13, wherein, The second pole includes: a first part and a second part extending along the second direction and whose extension lines do not coincide, and a third part extending along the first direction and connecting the first part and the second part; The length of the third part in the transistor to which the first pixel electrode is connected is equal to the length of the third part in the transistor to which the second pixel electrode is connected.

15. The array substrate as claimed in claim 14, wherein, The first extension line of the transistor to which the first pixel electrode is connected is projected onto the substrate, and the gap between adjacent pixel electrodes is located within the projection of the substrate.

16. The array substrate as claimed in claim 14 or 15, wherein, The second part, in its orthographic projection onto the substrate, overlaps with the pixel electrode, in its orthographic projection onto the substrate.

17. The array substrate as claimed in claim 13, wherein, The second pole includes: a fourth portion extending along the second direction, and a fifth portion extending along the first direction and connected to one end of the fourth portion; The fourth part, in its orthographic projection onto the substrate, overlaps with the gap between the adjacent pixel electrodes in its orthographic projection onto the substrate.

18. The array substrate as claimed in claim 1, wherein, The array substrate includes: a first common signal line located between adjacent gate line groups and extending along the first direction, and a first common signal extension line connected to one side of the first common signal line and extending along the second direction; At least a portion of the first common signal extension line serves as the common trace.

19. The array substrate as claimed in claim 1, wherein, The array substrate includes: a second common signal line group located between adjacent gate line groups and extending along the second direction; the second common signal line group includes two second common signal lines located on different sides of the data line; the second common signal line includes: a main portion of the second common signal line extending along the second direction, and a branch portion of the second common signal line extending from one end of the main portion of the second common signal line along the first direction. At least a portion of the second common signal line serves as the common trace, and the second common signal line is electrically connected to the connecting line through a branch of the second common signal line.

20. The array substrate as claimed in claim 1, wherein, The array substrate includes a third common signal line located between adjacent gate line groups and extending along the second direction. The orthographic projection of the third common signal line onto the substrate is located between the orthographic projections of the first pixel electrode onto the substrate and the orthographic projections of the second pixel electrode onto the substrate.

21. The array substrate as claimed in claim 1, wherein, The common trace is in the same layer and made of the same material as the gate line.

22. A display panel, wherein, The array substrate includes the array substrate as described in any one of claims 1-21, and further includes a counter substrate disposed opposite to the array substrate, wherein the counter substrate has a common electrode layer disposed on the side facing the array substrate.

23. A display device, wherein, Includes the display panel as described in claim 22.

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