Electronic paper, display device and display control method

Abstract

The invention discloses electronic paper, a display device and a display control method, and belongs to the technical field of display, and the electronic paper comprises a substrate (1) and a plurality of pixel units (2) which are arranged on the substrate (1) and are arranged in an array; each pixel unit (2) comprises a pixel driving circuit (21) and a display unit (22); the display unit (22) comprises a first electrode (221), an electronic ink layer (222) and a second electrode (223) which are stacked; the electronic ink layer (222) comprises a plurality of microcapsules or a plurality of microcups; wherein the pixel driving circuits (21) in the pixel units (2) in the same column are connected with the same data line, and the pixel driving circuits (21) in the pixel units (2) in different columns are connected with different data lines; the plurality of pixel units (2) are divided into a plurality of pixel unit groups (3) arranged in an array; the pixel driving circuits (21) in the same pixel unit group (3) are connected with different grid lines; the electronic paper comprises a plurality of first connection bonding pads located on the substrate; at least two columns of data lines connected with the pixel driving circuits (21) connected with different grid lines are connected with the same first connection bonding pad.

Description

Electronic paper, display device and display control method Technical Field

[0001] The present disclosure belongs to the field of display technology, and particularly relates to an electronic paper, a display device, and a display control method. Background Art

[0002] ESL (Electronic Shelf Label) is an electronic price tag. ESL technology is primarily implemented through cholesteric liquid crystal display (LCD), electrophoretic display (EPD), and electrowetting display (EWD) technologies. Currently, the driver circuit for EPD panels typically uses a one-to-one drive scheme, where one gate line and one data line drive one pixel. For example, as shown in Figure 1, if the resolution of an EPD panel is M (Data) x N (Gate), the driver integrated circuit (IC) requires at least M data pins and N gate pins.

[0003] However, in the e-paper manufacturing process, the cost of the gate driver chip (Gate IC) is approximately 1 / 4 of the source driver chip (Source IC). In other words, the traditional technology uses a one-to-one driving method, and the number of source IC pins is large, resulting in a higher cost of the source driver chip, which in turn increases the cost of e-paper and affects the market application of e-paper.

[0004] Summary of the Invention

[0005] The present disclosure aims to solve at least one of the technical problems existing in the prior art and provides an electronic paper, a display device and a display control method.

[0006] In a first aspect, the technical solution adopted to solve the technical problem of the present disclosure is an electronic paper, comprising a base substrate, a plurality of pixel units arranged in an array on the base substrate; each of the pixel units comprises a pixel driving circuit and a display unit; the display unit comprises a first electrode, an electronic ink layer, and a second electrode arranged in a stacked manner; the electronic ink layer comprises a plurality of microcapsules or a plurality of microcups, wherein a plurality of charged particles are provided in the microcapsules or microcups, and the charged particles comprise multiple colors; the pixel driving circuit in each pixel unit is electrically connected to the first electrode of the display unit therein; wherein,

[0007] The pixel driving circuits in the pixel units in the same column are connected to the same data line, and the pixel driving circuits in the pixel units in different columns are connected to different data lines;

[0008] The plurality of pixel units are divided into a plurality of pixel unit groups arranged in an array; the pixel driving circuits in the same pixel unit group are connected to different gate lines;

[0009] The electronic paper includes a plurality of first connection pads on the base substrate; at least two columns of data lines connected to the pixel driving circuits connected to different gate lines are connected to the same first connection pad.

[0010] In some embodiments, the pixel unit group includes n pixel units arranged side by side along a row direction, where n≥2, and n is a positive integer;

[0011] For the pixel units located in the same row, the pixel driving circuit in the i-th pixel unit in each pixel unit group is electrically connected to the same gate line; i ranges from 1 to n, and i is a positive integer.

[0012] In some embodiments, the pixel driving circuits in the pixel unit group are staggered along a column direction.

[0013] In some embodiments, the pixel driving circuit is located in a non-display area of ​​the pixel unit;

[0014] For the pixel units located in the same row, centers of the non-display areas where the pixel driving circuits connected to the same gate line are located are located on the same straight line, and the extension direction of the straight line is the row direction.

[0015] In some embodiments, the data lines connected to the pixel driving circuits in the pixel unit group located in the same column are connected to the same first connection pad.

[0016] In some embodiments, a portion of the data lines connected to the pixel driving circuits in the pixel unit group located in the same column are connected to the same first connection pad.

[0017] In some embodiments, every two data lines adjacent to each other in the row direction are connected to the same first connecting pad.

[0018] In some embodiments, the pixel driving circuit includes at least one transistor and a storage capacitor; the storage capacitor includes a first plate and a second plate disposed opposite to each other;

[0019] For any of the pixel units, the first electrode of the display unit is electrically connected to the first plate of the storage capacitor.

[0020] In some embodiments, the electronic paper includes a first conductive layer, a semiconductor layer, and a second conductive layer sequentially disposed on the base substrate;

[0021] For any of the pixel units, the control electrode of the transistor is located in the first conductive layer; the active layer of the transistor is located in the semiconductor layer; and the first electrode and the second electrode of the transistor are located in the second conductive layer.

[0022] In some embodiments, for any of the pixel units, the first plate of the storage capacitor is located in the second conductive layer; and the second plate of the storage capacitor is located in the first conductive layer.

[0023] In some embodiments, for any of the pixel units, the second plate of the storage capacitor is divided into a first sub-portion and a second sub-portion;

[0024] For the pixel units located in the same row, the first sub-portion of the second electrode plate of each storage capacitor is an integrally formed structure; the second sub-portion of the second electrode plate of each storage capacitor is an integrally formed structure;

[0025] For each of the pixel units, the integrally formed first sub-portion and the integrally formed second sub-portion are both connected to the same first common signal line.

[0026] In some embodiments, for the pixel units located in the same row, the second plates of the storage capacitors are integrally formed.

[0027] For each of the pixel units, the second electrode plate formed integrally is connected to the same second common signal line.

[0028] In some embodiments, for any of the pixel units, the first plate of the storage capacitor is located in the first conductive layer; and the second plate of the storage capacitor is located in the second conductive layer.

[0029] In some embodiments, the second plates of the storage capacitors in the pixel units in the same column are integrally formed.

[0030] For each of the pixel units, the second electrode plate formed integrally is connected to the same third common signal line.

[0031] In some embodiments, for any of the pixel units, the second electrode of the display unit is disposed on a side of the first electrode away from the base substrate, and the second electrode of the display unit is electrically connected to the second plate of the storage capacitor through a second connecting via.

[0032] In some embodiments, the electronic paper further comprises a third conductive layer disposed on a side of the second conductive layer facing away from the base substrate;

[0033] For any of the pixel units, the first electrode of the display unit is located in the third conductive layer.

[0034] In some embodiments, for the pixel units located in the same row, the second electrodes of the display units are in the same layer and are an integrated structure.

[0035] In a second aspect, an embodiment of the present disclosure further provides a display device, which includes the electronic paper as described in any one of the first aspects.

[0036] In a third aspect, an embodiment of the present disclosure further provides a display control method, which is applied to the electronic paper as described in any one of the first aspects; the display control method includes:

[0037] For the pixel units located in the same row, each gate line is scanned in sequence, a first voltage is applied to each gate line, and when one gate line is scanned, a third voltage is applied to other gate lines; the other gate lines are gate lines that have been scanned before the gate line currently being scanned;

[0038] When scanning different gate lines, different second voltages are applied to the data lines connected to the pixel driving circuits connected to the different gate lines, so that the first electrode of the display unit receives the second voltage and drives the charged particles with the same charging properties as the second voltage to move toward the second electrode.

[0039] In some embodiments, the different second voltages include voltages within at least three different voltage ranges: 10V to 15V, 5V to 8V, and -10V to -15V. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] FIG1 is a schematic diagram of a conventional pixel driving circuit;

[0041] FIG2a is a schematic structural diagram of an electronic paper provided by an embodiment of the present disclosure;

[0042] FIG2 b is a schematic structural diagram of a pixel unit provided in an embodiment of the present disclosure;

[0043] FIG3 is a plan view of a plurality of pixel units arranged in an array according to an embodiment of the present disclosure;

[0044] FIG4 is a plan view of another embodiment of the present disclosure showing a plurality of pixel units arranged in an array;

[0045] FIG5 is a plan view of another embodiment of the present disclosure showing a plurality of pixel units arranged in an array;

[0046] FIG6 is a plan view schematically showing a pixel driving circuit according to an embodiment of the present disclosure;

[0047] FIG7 is a plan view schematically illustrating another pixel driving circuit provided by an embodiment of the present disclosure;

[0048] FIG8 is a plan view of another pixel driving circuit provided by an embodiment of the present disclosure;

[0049] FIG9 is a plan view schematically illustrating another pixel driving circuit provided by an embodiment of the present disclosure;

[0050] FIG10 is a cross-sectional view of the pixel driving circuit shown in FIG6 and FIG8;

[0051] FIG11 is a cross-sectional view of the pixel driving circuit shown in FIG7 and FIG9;

[0052] FIG12 is an equivalent circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0053] FIG13 is a timing control diagram of a pixel driving circuit provided in an embodiment of the present disclosure.

[0054] The reference numerals are as follows: 1, substrate; 2, pixel unit; 21, pixel driving circuit; 22, display unit; 41, pixel driving circuit layer; 42, display layer; 221, first electrode; 222, electronic ink layer; 223, second electrode; ITO, pixel electrode; Vcom1, first common electrode; 222a, charged particles; TFT1, first thin film transistor; TFT2, second thin film transistor; TFT_a, first electrode; TFT_b, second electrode; TFT_c, control electrode; TFT_d, active layer; C st, storage capacitor; Cst_1, first electrode; Cst_2, second electrode; Vcom2, second common electrode; Cst_2a, first sub-unit; Cst_2b, second sub-unit; Data, data line; Gate, gate line; 3, pixel unit group; X, row direction; Y, column direction; BB, non-display area; S, first side; M1, first conductive layer; M2, second conductive layer; M3, third conductive layer; Active, semiconductor layer; R1, first insulating layer; R2, second insulating layer; R3, third insulating layer. DETAILED DESCRIPTION

[0055] In order to make the purpose, technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. The components of the embodiments of the present disclosure generally described and shown in the drawings herein can be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of the present disclosure provided in the drawings is not intended to limit the scope of the disclosure for which protection is sought, but merely represents selected embodiments of the present disclosure. Based on the embodiments of the present disclosure, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present disclosure.

[0056] Unless otherwise defined, the technical or scientific terms used in this disclosure should have the usual meanings understood by people with ordinary skills in the field to which this disclosure belongs. The words "first", "second" and similar words used in this disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, words such as "one", "an" or "the" do not indicate a quantity limitation, but rather indicate the existence of at least one. Words such as "include" or "comprise" mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the object being described changes, the relative positional relationship may also change accordingly.

[0057] In this disclosure, "multiple or several" refers to two or more. "And / or" describes the relationship between associated objects, indicating that three possible relationships exist. For example, "A and / or B" can mean: A exists alone, A and B exist simultaneously, or B exists alone. The character " / " generally indicates that the associated objects are in an "or" relationship.

[0058] Among related technologies, electrophoretic display (EPD) technology is the most widely used. Electrophoretic technology is typically implemented using microstructures such as microcapsules and microcup arrays. Both microcapsules and microcup arrays utilize the movement of charged particles to form an image. As shown in Figure 1, it is a schematic diagram of an existing pixel driver circuit. Through fanout wiring, gate signals (Gate signals) and data signals (Data signals) are input from the driver integrated circuit 01 to the module display area. The input Gate and Data signals then control the thin-film transistors (TFTs) within the pixel unit 02 to turn on. The turned-on TFTs transmit signals to the pixel electrodes, which form a vertical electric field with the common electrode on the paper mold. This vertical electric field drives the charged particles within the paper film to move, forming the target image.

[0059] However, the driving circuit of an EPD panel typically uses a 1G1D driving method. As shown in Figure 1, during the e-paper manufacturing process, the cost of the gate driver chip (Gate IC) is approximately 1 / 4 of the cost of the source driver chip (Source IC). This means that the traditional 1G1D driving method uses a larger number of source IC pins, resulting in a higher source driver chip cost. This, in turn, increases the cost of e-paper, hindering its market adoption.

[0060] In view of this, the embodiments of the present disclosure provide an electronic paper in which multiple data lines are connected to the same first connection pad. This method of driving multiple columns of pixel units using the same Data signal reduces the number of Source IC pins. At the same time, by utilizing the bi-stable characteristics of the EPD display and the characteristics of the gate driver chip (Gate IC) controlling the thin film transistor (TFT) switches in the pixel driver circuit through the Gate signal, multiple columns of pixel units controlled by the same Data signal can display different images, making the image display more delicate and optimizing the display effect.

[0061] The specific structure of an electronic paper provided by an embodiment of the present disclosure is described in detail below. Figure 2a is a schematic diagram of the structure of the electronic paper provided by an embodiment of the present disclosure, Figure 2b is a schematic diagram of the structure of a pixel unit provided by an embodiment of the present disclosure, Figure 3 is a plan view of a plurality of pixel units arranged in an array provided by an embodiment of the present disclosure, Figure 4 is a plan view of another plurality of pixel units arranged in an array provided by an embodiment of the present disclosure, and Figure 5 is a plan view of another plurality of pixel units arranged in an array provided by an embodiment of the present disclosure.

[0062] As shown in Figure 2a, the electronic paper includes a base substrate 1, and a plurality of pixel units 2 arranged in an array on the base substrate 1. Each pixel unit 2 includes a pixel driving circuit 21 and a display unit 22. The display unit 22 is disposed on the side of the pixel driving circuit 21 facing away from the base substrate 1. The electronic paper also includes a pixel layer disposed on the base substrate 1, the pixel layer including a pixel driving circuit layer 41 and a display layer 42. The plurality of pixel units 2 arranged in an array are located in the pixel layer, the plurality of pixel driving circuits 21 are located in the pixel driving circuit layer 42, and the plurality of display units 22 are located in the display layer 42.

[0063] As shown in Figure 2b, the display unit 22 includes a stacked first electrode 221, an electronic ink layer 222, and a second electrode 223. One of the first electrode 221 and the second electrode 223 is an ITO pixel electrode, and the other is a first common electrode Vcom1. For ease of understanding, the present embodiment uses an example in which the first electrode 221 is an ITO pixel electrode and the second electrode 223 is the first common electrode Vcom1. Typically, the first common electrode Vcom1 is grounded.

[0064] The electronic ink layer 222 includes multiple microcapsules or multiple microcups, each of which is provided with a number of charged particles 222a, and the charged particles 222a include multiple colors; the pixel driving circuit 21 in each pixel unit 2 is electrically connected to the first electrode 221 of the display unit 22 therein to drive the display unit 22 to display the target image.

[0065] Of course, a number of charged magnetic particles or plasma can also be set in the microcapsule or microcup, and are not limited to charged particles. The embodiments of the present disclosure are described with charged particles.

[0066] By applying a voltage to the first electrode 221 and the second electrode 223 to form an electric field, the charged particles 222a of different colors are driven to move according to the current applied voltage, thereby displaying different colors on the surface of the electronic paper. For example, in the case of a microcapsule structure, when a negative electric field is applied to both ends of the microcapsule, the negatively charged white particles move to the top of the microcapsule under the action of the electric field. At the same time, the positively charged black particles move to the bottom of the microcapsule and "hide" there, and the surface will appear white. When a positive electric field is applied to both sides of the adjacent microcapsules, the black particles will move to the top of the microcapsule under the action of the electric field, and the surface will appear black. Simply put, the microcapsule structure uses the charged particles to form a bistability under the action of the electric field, so that the electronic paper can still display the state before the power is turned off after the power is turned off.

[0067] As shown in Figures 3 to 5 , each pixel driving circuit 21 in the same column of pixel units 2 is connected to the same data line Data, while each pixel driving circuit 21 in different columns of pixel units 2 is connected to different data lines Data. The data line Data is electrically connected to a source driver chip (Source IC). The source driver chip (Source IC) provides a data signal (Data signal) to the connected pixel driving circuit 21 via the data line Data, thereby providing a driving voltage to the pixel electrode ITO, thereby forming a vertical electric field between the pixel electrode ITO and the first common electrode Vcom1.

[0068] As shown in Figures 3 to 5, multiple pixel units 2 are divided into multiple pixel unit groups 3 arranged in an array. Each pixel driving circuit 21 in the same pixel unit group 3 is connected to a different gate line Gate. The gate line Gate is electrically connected to a gate driver chip (Gate IC). The gate driver chip (Gate IC) provides a gate signal (Gate signal) to the connected pixel driving circuit 21 through the gate line Gate, thereby controlling the on / off of the transistor TFT.

[0069] Exemplarily, each pixel unit group 3 may include multiple pixel units 2 arranged side by side along the row direction X and / or the column direction Y. For example, as shown in FIG3 to FIG5 , a pixel unit group 3 includes three pixel units 2 arranged side by side along the row direction X.

[0070] The electronic paper includes a plurality of first connection pads located on a base substrate 1; data lines connected to at least two columns of pixel drive circuits 21 connected to different gate lines (Gate) are connected to the same first connection pad. The first connection pad is also known as an IC pin. For an EPD panel with a resolution of M (Data) × N (Gate), compared to the traditional 1G1D drive method, the disclosed embodiment can reduce at least M / 3 source IC pins (first connection pads), saving the cost of source driver chips and, therefore, the manufacturing cost of the electronic paper.

[0071] For example, as shown in FIG3 , two first connection pads are shown. The data lines Data connected to the pixel driver circuits 21 in every three columns, each connected to a different gate line Gate, are connected to the same first connection pad. For an EPD panel with a resolution of M(Data)×N(Gate), compared to the traditional 1G1D drive method, the disclosed embodiment can reduce 2M / 3 Source IC pins, saving the cost of source driver chips and, therefore, the manufacturing cost of the electronic paper.

[0072] For example, as shown in Figures 4 and 5, three first connection pads are shown. The data lines Data connected to pixel driver circuits 21 in every two columns, connected to different gate lines Gate, are connected to the same first connection pad. For an EPD panel with a resolution of M(Data) x N(Gate), compared to the traditional 1G1D drive method, the disclosed embodiment can reduce M / 3 Source IC pins, saving the cost of source driver chips and, therefore, the manufacturing cost of the electronic paper.

[0073] In addition, by utilizing the electrophoretic display characteristics of electronic paper (that is, after the electronic paper is powered off, it can still display the state before power failure), multiple gate lines Gate are scanned in sequence. For the pixel driving circuit 21 connected to the same first connecting pad and connected to different gate lines Gate, different driving voltages can be provided to the pixel electrode ITO of the display unit 22 connected thereto, so that the corresponding display units 22 can display different pictures respectively, thereby reducing the number of Source IC pins while improving the fineness of the electronic paper display picture.

[0074] In some embodiments, the pixel unit group 3 includes n pixel units 2 arranged side by side along the row direction X, n≥2, and n is a positive integer; for the pixel units 2 located in the same row, the pixel driving circuit 21 in the i-th pixel unit 2 in each pixel unit group 3 is electrically connected to the same gate line Gate; i is 1 to n, and i is a positive integer.

[0075] Exemplarily, as shown in FIG3 and FIG4 , the pixel unit group 3 includes three pixel units 2 arranged side by side along the row direction X.

[0076] Exemplarily, as shown in FIG5 , the pixel unit group 3 includes two pixel units 2 arranged side by side along the row direction X.

[0077] In this embodiment, the pixel units 2 located at the same position in each pixel unit group 3 are connected to the same gate line Gate, and the unified structure facilitates wiring and saves wiring space.

[0078] In some embodiments, as shown in FIG. 3 to FIG. 5 , the pixel driving circuits 21 in the pixel unit group 3 are staggered along the column direction Y.

[0079] In some embodiments, the base substrate 1 includes a first side surface and a second side surface disposed opposite each other along a column direction Y. As shown in FIG3 to FIG5 , the pixel driving circuit 21 is located in a non-display area BB of the pixel unit 2; a first distance H1 from the center of the non-display area BB where the i-th pixel driving circuit 21 in the pixel unit group 3 is located to the first side surface S is less than a second distance H2 from the center of the area where the i+1-th pixel driving circuit 21 is located to the first side surface S.

[0080] In some embodiments, as shown in Figures 3 to 5, the pixel driving circuit 21 is located in the non-display area BB of the pixel unit 2; for the pixel units 2 located in the same row, the centers of the non-display areas BB where the pixel driving circuits 21 connected to the same gate line Gate are located are located on the same straight line L2, and the extension direction of the straight line L1 is the row direction X.

[0081] In some embodiments, as shown in FIG. 3 and FIG. 5 , the data lines Data connected to the pixel driving circuits 21 in the pixel unit group 3 in the same column are connected to the same first connection pad.

[0082] In combination with the various embodiments of the arrangement of the pixel driving circuit 21 and the gate line Gate described above, when the same pixel unit group 3 uses the same first connection pad, the above-mentioned arrangement of the pixel driving circuit 21 and the gate line Gate is adopted, so that different pixel units 2 located in the same pixel unit group 3 can display different pictures.

[0083] Exemplarily, a plurality of pixel units 2 are divided into a plurality of pixel unit groups 3 arranged in an array; the data lines Data connected to the pixel driving circuits 21 in the pixel unit group 3 in the same column are connected to the same first connection pad; and the pixel driving circuits 21 in the same pixel unit group 3 are connected to different gate lines Gate. In this example, for a group of pixel unit groups 3, by scanning a plurality of gate lines Gate in sequence, the pixel driving circuits 21 in the same pixel unit group 3 connected to different gate lines Gate can provide different driving voltages to the pixel electrodes ITO of the display units 22 connected thereto. At the same time, by utilizing the bistable characteristics of the charged particles 222a under the action of the electric field (that is, after the electronic paper is powered off, it can still display the state before the power is turned off), during the gate line Gate scanning process, the plurality of pixel units 2 in a group of pixel unit groups 3 can respectively display different images, thereby reducing the number of Source IC pins while making the displayed image more delicate.

[0084] In some embodiments, as shown in FIG. 4 , parts of the data lines Data connected to the pixel driving circuits 21 in the pixel unit group 3 in the same column are connected to the same first connection pad.

[0085] In some embodiments, as shown in FIG. 4 , every two data lines Data adjacent to each other in the row direction X are connected to the same first connection pad.

[0086] Exemplarily, a group of pixel unit groups 3 includes three pixel units 2 arranged side by side along the row direction X, wherein the data lines Data connected to the pixel driving circuits 21 in two adjacent pixel units 2 are connected to the same first connection pad, and the data line Data connected to the pixel driving circuit 21 in another pixel unit 2 is connected to the same first connection pad as the data line Data connected to the adjacent pixel driving circuit 21 in the adjacent group of pixel unit groups 3.

[0087] Figure 6 is a plan schematic diagram of a pixel driving circuit provided in an embodiment of the present disclosure, Figure 7 is a plan schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure, Figure 8 is a plan schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure, Figure 9 is a plan schematic diagram of another pixel driving circuit provided in an embodiment of the present disclosure, Figure 10 is a cross-sectional view of the pixel driving circuits shown in Figures 6 and 8, and Figure 11 is a cross-sectional view of the pixel driving circuits shown in Figures 7 and 9.

[0088] In some embodiments, in combination with the above embodiments, as shown in Figures 6 to 11 , the pixel driving circuit 21 includes at least one transistor and a storage capacitor Cst; the storage capacitor Cst includes a first plate Cst_1 and a second plate Cst_2 disposed opposite each other. For any pixel unit 2, the first electrode 221 of the display unit 22 is electrically connected to the first plate Cst_1 of the storage capacitor Cst. Exemplarily, the first electrode 221 of the display unit 22 can be electrically connected to the first plate Cst_1 of the storage capacitor Cst via a first connection via Via1.

[0089] Exemplarily, the second plate Cst_2 of the storage capacitor Cst may be the second common electrode Vcom2 .

[0090] Exemplarily, the second common electrode Vcom2 may be grounded.

[0091] It should be noted that the transistors used in the embodiments of the present disclosure can be thin-film transistors (TFTs) or field-effect transistors (FETs) or other devices with the same characteristics. Since the source and drain of the transistors used are symmetrical, there is no difference between the source and drain. In the embodiments of the present disclosure and the subsequent description, to distinguish the source and drain of the transistor, one of the electrodes is referred to as the first electrode TFT_a, the other electrode is referred to as the second electrode TFT_b, and the gate is referred to as the control electrode TFT_c. In addition, according to the characteristics of the transistor, transistors can be divided into N-type and P-type. When a P-type transistor is used, the first electrode TFT_a is the source of the P-type transistor, and the second electrode TFT_b is the drain of the P-type transistor. When a low-level signal is input to the gate, the source and drain are turned on. When an N-type transistor is used, the first electrode TFT_a is the source of the N-type transistor, and the second electrode TFT_b is the drain of the N-type transistor. When a high-level signal is input to the gate, the source and drain are turned on. The embodiments of the present disclosure are specifically described using an N-type transistor as an example.

[0092] For example, the pixel driving circuit 21 includes only one thin-film transistor (TFT) and one storage capacitor (Cst). The thin-film transistor (TFT) includes a first electrode (TFT_a), a second electrode (TFT_b), and a control electrode (TFT_c). The first electrode (TFT_a) is electrically connected to the data line (Data). The second electrode (TFT_b) is electrically connected to the first electrode plate (Cst_1) of the storage capacitor (Cst). The control electrode (TFT_c) is electrically connected to the gate line (Gate).

[0093] As shown in Figures 6 to 11, taking the pixel driving circuit 21 as an example, which includes a first thin-film transistor TFT1, a second thin-film transistor TFT2, and a storage capacitor Cst, the first thin-film transistor TFT1 and the second thin-film transistor TFT2 each include a first electrode TFT_a, a second electrode TFT_b, and a control electrode TFT_c. The first electrode TFT_a of the first thin-film transistor TFT1 is electrically connected to the data line Data, the second electrode TFT_b of the first thin-film transistor TFT1 is electrically connected to the first electrode TFT_a of the second thin-film transistor TFT1, the control electrodes TFT_c of the first thin-film transistor TFT1 and the second thin-film transistor TFT2 are both electrically connected to the gate line Gate, and the second electrode TFT_b of the second thin-film transistor TFT2 is electrically connected to the first electrode plate Cst_1 of the storage capacitor Cst.

[0094] In some embodiments, as shown in Figures 10 and 11, the electronic paper includes a first conductive layer M1, a semiconductor layer Active, and a second conductive layer M2 arranged in sequence on a base substrate 1; for any pixel unit 2, the control electrode TFT_c of the thin film transistor TFT is located in the first conductive layer M1; the active layer TFT_d of the transistor is located in the semiconductor layer Active; the first electrode TFT_a and the second electrode TFT_b of the thin film transistor TFT are located in the second conductive layer M2.

[0095] The electronic paper also includes a first insulating layer R1 disposed on the side of the first conductive layer M1 close to the semiconductor layer Active. This first insulating layer R1 can serve as a gate insulating layer, isolating the gate of the thin-film transistor from the active layer TFT_d. The electronic paper also includes a second insulating layer R2 disposed on the side of the second conductive layer M2 facing away from the semiconductor layer Active. This third insulating layer R2 can serve as a passivation layer. The electronic paper also includes a third insulating layer R3 disposed on the side of the second insulating layer R2 facing away from the second conductive layer M2. This third insulating layer R3 can be an organic film layer to reduce power consumption.

[0096] In some embodiments, as shown in FIG6 , FIG8 and FIG10 , for any pixel unit 2 , the first plate Cst_1 of the storage capacitor Cst is located in the second conductive layer M2 ; the second plate Cst_2 of the storage capacitor Cst is located in the first conductive layer M1 .

[0097] In combination with the above embodiments, the preparation order of each film layer process is, for example: forming a first conductive layer M1 including a control electrode TFT_c of a thin film transistor TFT and a second electrode Cst_2 of a storage capacitor Cst through a composition process; depositing an insulating layer material to form a first insulating layer R1; forming a semiconductor layer Active including an active layer TFT_d of a thin film transistor TFT through a composition process; forming a second conductive layer M2 including a first electrode TFT_a, a second electrode TFT_b and a first electrode Cst_1 of a storage capacitor Cst through a composition process; depositing an insulating layer material to form a second insulating layer R2; and depositing an insulating layer material to form a third insulating layer R3.

[0098] In some embodiments, in combination with the above embodiments, as shown in Figure 6, for any pixel unit 2, the second plate Cst_2 of the storage capacitor Cst is divided into a first sub-portion Cst_2a and a second sub-portion Cst_2b; for the pixel units 2 located in the same row, the first sub-portion Cst_2a of the second plate Cst_2 of each storage capacitor Cst is an integrally formed structure; the second sub-portion Cst_2b of the second plate Cst_2 of each storage capacitor Cst is an integrally formed structure; for each pixel unit 2, the integrally formed first sub-portion Cst_2a and the integrally formed second sub-portion Cst_2b are both connected to the same first common signal line.

[0099] Here, the first sub-section Cst_2a and the second sub-section Cst_2b are arranged in parallel along the column direction Y, so that the second electrode Cst_2 of the storage capacitor Cst approximately covers the display area of ​​the display unit 22, thereby increasing the storage capacitor Cst and facilitating the maintenance of the display image.

[0100] Exemplarily, the second plate Cst_2 of the storage capacitor Cst in each pixel driving circuit 21 is connected to the same first common signal line. The first common signal line can be directly grounded or electrically connected to the first common electrode Vcom1 and grounded through the first common electrode Vcom1.

[0101] In some embodiments, as shown in FIG8 , for pixel units 2 in the same row, the second electrode plate Cst_2 of each storage capacitor Cst is an integrally formed structure; for each pixel unit 2 , the integrally formed second electrode plate Cst_2 is connected to the same second common signal line.

[0102] Exemplarily, as shown in FIG8 , the second electrode Cst_2 of the storage capacitor Cst approximately covers the display area of ​​the display unit 22 , thereby increasing the storage capacitor Cst and facilitating the maintenance of the display image.

[0103] Exemplarily, the second plate Cst_2 of the storage capacitor Cst in each pixel driving circuit 21 is connected to the same second common signal line. The second common signal line can be directly grounded or electrically connected to the first common electrode Vcom1 and grounded through the first common electrode Vcom1.

[0104] In some embodiments, as shown in FIG7 , FIG9 and FIG11 , for any pixel unit 2 , the first plate Cst_1 of the storage capacitor Cst is located in the first conductive layer M1 ; the second plate Cst_2 of the storage capacitor Cst is located in the second conductive layer M2 .

[0105] In combination with the above embodiments, the preparation order of each film layer process is, for example: forming a first conductive layer M1 including a control electrode TFT_c of a thin film transistor TFT and a first electrode Cst_1 of a storage capacitor Cst through a composition process; depositing an insulating layer material to form a first insulating layer R1; forming a semiconductor layer Active including an active layer TFT_d of a thin film transistor TFT through a composition process; forming a second conductive layer M2 including a first electrode TFT_a, a second electrode TFT_b and a second electrode Cst_2 of a storage capacitor Cst through a composition process; depositing an insulating layer material to form a second insulating layer R2; and depositing an insulating layer material to form a third insulating layer R3.

[0106] In some embodiments, as shown in FIG7 and FIG9 , the second electrode plate Cst_2 of each storage capacitor Cst in the pixel units 2 in the same column is an integrally formed structure; for each pixel unit 2 , the integrally formed second electrode plate Cst_2 is connected to the same third common signal line.

[0107] In some embodiments, as shown in Figures 6, 8 and 10, the coverage areas of the positive projections of the first plate Cst_1 and the second plate Cst_2 of the storage capacitor Cst are approximately equal, and can approximately cover the display area of ​​the display unit 22, thereby increasing the storage capacitor Cst and facilitating the maintenance of the display image.

[0108] In some embodiments, the electronic paper further includes a third conductive layer M3 disposed on a side of the second conductive layer M2 facing away from the base substrate 1 ; for any pixel unit 2 , the first electrode 221 of the display unit 22 is located on the third conductive layer M3 .

[0109] Continuing with the above preparation sequence, for example, a third conductive layer M3 including the first electrode 221 of the display unit 22 is formed on the side of the third insulating layer R3 facing away from the base substrate 1 through a patterning process. An electronic ink layer 222 is formed on the side of the third conductive layer M3 facing away from the base substrate 1. A fourth conductive layer including the second electrode 223 of the display unit 22 is formed on the side of the electronic ink layer 222 facing away from the base substrate 1 through a patterning process.

[0110] Exemplarily, the first conductive layer M1 further includes a gate line Gate, and the second conductive layer M2 further includes a data line Data.

[0111] In some embodiments, for any pixel unit 2, the second electrode 223 of the display unit 22 is arranged on the side of the first electrode 221 away from the base substrate 1, and the second electrode 223 of the display unit 22 can be electrically connected to the second plate Cst_2 of the storage capacitor Cst through the second connection via Via2.

[0112] In some embodiments, for the pixel units 2 located in the same row, the second electrodes 223 of the display units 22 are in the same layer and form an integrated structure.

[0113] For example, the first common electrode Vcom1 and the second common electrode Vcom2 may be electrically connected via a silver glue point penetrating the connection via hole and grounded using a signal line.

[0114] In some embodiments, the first connection line connecting the gate line Gate and the control electrode TFT_c of the thin film transistor TFT is thinned to reduce the overlapping capacitance between the first connection line and the conductive layer in the pixel unit 2, thereby reducing leakage current and power consumption.

[0115] In some embodiments, the second connection line at the connection between the data line Data and the first electrode TFT_a of the thin film transistor is thinned to reduce the overlapping capacitance between the second connection line and the conductive layer in the pixel unit 2, thereby reducing leakage current and power consumption.

[0116] In addition, an embodiment of the present disclosure further provides a display device, which includes the electronic paper in any of the above embodiments.

[0117] In addition, an embodiment of the present disclosure further provides a display control method, which is mainly applied to the display control of the electronic paper in any of the above embodiments.

[0118] In some embodiments, for pixel units 2 located in the same row, each gate line Gate is scanned in sequence, and a first voltage is applied to each gate line Gate, and when one of the gate lines Gate is scanned, a third voltage is applied to other gate lines Gate; the other gate lines Gate are gate lines Gate scanned before the gate line Gate currently being scanned; when scanning different gate lines Gate, different second voltages are applied to the data lines Data connected to the pixel driving circuits 21 connected to different gate lines Gate, so that the first electrode 221 of the display unit 22 receives the second voltage, driving the charged particles 222a with the same charging properties as the second voltage to move toward the second electrode 223.

[0119] Figure 12 is an equivalent circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in Figure 12, taking the pixel driving circuit 21 including a first thin film transistor (TFT1), a second thin film transistor (TFT2) and a storage capacitor Cst as an example, the load of the fanout lead in Figure 12 is equivalent to the model 4R3C (that is, 4 resistors R and 3 equivalent capacitors Cgs, where Cgs represents the overlapping capacitance between the gate line and the source), the TFT is equivalent to an N-type A-Si TFT, and the storage capacitor Cst and the capacitance of the TFT itself (that is, the overlapping capacitance Cgd between the gate line and the data line) are characterized by an equivalent capacitor structure. Among them, the Data signal is triggered by the same Data signal, and the Vcom signal is also triggered by the same Vcom signal. The Vcom signal is a common signal emitted by the electrically connected first common electrode Vcom1 and the second common electrode Vcom2, which can be a GND signal.

[0120] FIG13 is a timing control diagram of a pixel driving circuit provided by an embodiment of the present disclosure. As shown in FIG13 , it shows timing control waveforms in which the pixel driving circuit 21 drives the display unit 22 to display black, white, and red, respectively.

[0121] As shown in FIG3 , the data lines Data connected to the pixel drive circuits 21 in the pixel unit group 3 in the same column are connected to the same first connection pad. A pixel unit group 3 includes three pixel units 2 arranged side by side along the row direction X. For the pixel units 2 in the same row, S1 represents the second voltage applied to the first connection pad corresponding to each column of the pixel unit group 3; G1 represents the first voltage applied to the first gate line Gate1, G2 represents the first voltage applied to the second gate line Gate2, and G3 represents the first voltage applied to the third gate line Gate3.

[0122] As shown in FIG13 , the working process of the pixel driving circuit 21 is divided into: a first scanning phase t1 , a second scanning phase t2 and a third scanning phase t3 .

[0123] In the first scanning stage t1: the first voltage m4 is applied to the first gate line Gate1, the thin film transistor TFT is turned on, and the second voltage m1 is applied to the first connection pad corresponding to each column of pixel unit group 3. At the same time, the data line Data connected to each pixel driving circuit 21 in each column of pixel unit group 3 is written with the second voltage m1, so that the pixel units 2 in the same column will display the first target image.

[0124] Exemplarily, the first voltage m4 is a turn-on voltage, and the voltage range of the first voltage m4 is between 10V and 20V.

[0125] For example, when the second voltage m1 is in the range of 10 V to 15 V, the first target image is a black image, and the charged particles 222 a having the same charge property as the second voltage m1 are black balls.

[0126] In the second scanning stage t2: the first voltage m4 is applied to the second gate line Gate2, and at the same time, the third voltage m5 is applied to the first gate line Gate1; and the second voltage m3 is applied to the first connection pad corresponding to each column of pixel unit group 3, and at the same time, the data line Data connected to each pixel driving circuit 21 in each column of pixel unit group 3 is written with the second voltage m3, so that the pixel units 2 located in the same column will display the second target picture.

[0127] Exemplarily, the first voltage m4 is a turn-on voltage, and the voltage range of the first voltage m4 is between 10 V and 20 V. The third voltage m5 is a turn-off voltage, and the voltage range of the third voltage m5 is between -10 V and -20 V.

[0128] For example, when the second voltage m3 is in the range of -10 V to -15 V, the second target image is a white image, and the charged particles 222a having the same charge property as the second voltage m3 are white balls.

[0129] In this stage t2, one column of pixel units 2 will display a white image. Since the third voltage m5 is the off voltage, the other column of pixel units 2 maintains the original black image by utilizing the bistability of the charged particles 222a under the action of the electric field. Therefore, during the gate line Gate scanning process, multiple columns of pixel units 2 can respectively display different images, while reducing the number of Source IC pins and making the display image more detailed.

[0130] In the second scanning stage t3: the first voltage m4 is applied to the third gate line Gate3, and at the same time, the third voltage m5 is applied to the second gate line Gate2; and the second voltage m2 is applied to the first connection pad corresponding to each column of pixel unit group 3, and at the same time, the data line Data connected to each pixel driving circuit 21 in each column of pixel unit group 3 is written with the second voltage m2, so that the pixel units 2 located in the same column will display the third target picture.

[0131] For example, when the second voltage m2 is in the range of 5V to 8V, the third target image is a red image, and the charged particles 222a having the same charge property as the second voltage m2 are red balls.

[0132] In this stage t3, one column of pixel units 2 will display a red image. Since the third voltage m5 is the off voltage, the other two columns of pixel units 2 respectively utilize the bistability of the charged particles 222a under the action of the electric field to maintain the original black and white images. Therefore, during the gate line Gate scanning process, multiple columns of pixel units 2 can respectively display different images, while reducing the number of Source IC pins and making the display image more detailed.

[0133] In this way, the electrophoretic display characteristics of electronic paper are utilized: that is, the image before power failure can still be maintained after power failure. In this way, multiple columns of pixels controlled by the same data signal can display different images, reducing the number of Source IC pins and making the image display more delicate.

[0134] Of course, a voltage range different from the second voltage can also be selected to drive charged particles 222a with the same charging properties as the second voltage to display colors different from the above, forming a more delicate display screen such as a checkerboard, thereby improving the display effect.

[0135] For example, the specific signal transmission process of the pixel driving circuit 21 of the present disclosure is as follows: the thin-film transistor (TFT) is turned on or off by gate signals and data signals. When the gate signal turns on the TFT, the data signal is transmitted to the pixel electrode (ITO). A vertical electric field is formed between the pixel electrode (ITO) and the first common electrode (Vcom1), controlling the movement of the multi-colored charged particles 222a in the electronic ink layer 222.

[0136] For multiple columns of pixel units 2 connected to the same first connection pad, as shown in Figure 4, two adjacent columns of pixel units 2 are connected to the same first connection pad. S1 represents the application of a second voltage to each first connection pad; G1 represents the first voltage applied to the first gate line Gate1, G2 represents the first voltage applied to the second gate line Gate2, and G3 represents the first voltage applied to the third gate line Gate3. Similar to the control timing of the pixel drive circuit 21 shown in Figure 13, it can drive the display unit 22 in the pixel unit group to display black, white, and red, respectively.

[0137] For multiple columns of pixel units 2 connected to the same first connection pad, as shown in Figure 5 , two adjacent columns of pixel units 2 are connected to the same first connection pad. S1 represents the application of a second voltage to each first connection pad; G1 represents the application of a first voltage to the first gate line Gate1, and G2 represents the application of a first voltage to the second gate line Gate2. Similar to the control timing of the pixel drive circuit 21 shown in Figure 13 , the display units 22 in the pixel unit group can be driven to display any two colors among black, white, and red.

[0138] It is understood that the above embodiments are merely exemplary embodiments for illustrating the principles of the present disclosure, and the present disclosure is not limited thereto. Those skilled in the art may make various modifications and improvements without departing from the spirit and substance of the present disclosure, and such modifications and improvements are also considered to be within the scope of protection of the present disclosure.

Claims

1. An electronic paper, comprising a substrate, a plurality of pixel units arranged in an array on the substrate; each of the pixel units comprises a pixel driving circuit and a display unit; the display unit comprises a first electrode, an electronic ink layer, and a second electrode arranged in a stacked manner; the electronic ink layer comprises a plurality of microcapsules or a plurality of microcups, wherein a plurality of charged particles are arranged in the microcapsules or the microcups, and the charged particles comprise a plurality of colors; the pixel driving circuit in each pixel unit is electrically connected to the first electrode of the display unit therein; wherein, The pixel driving circuits in the pixel units in the same column are connected to the same data line, and the pixel driving circuits in the pixel units in different columns are connected to different data lines; The plurality of pixel units are divided into a plurality of pixel unit groups arranged in an array; the pixel driving circuits in the same pixel unit group are connected to different gate lines; The electronic paper comprises a plurality of first connection pads located on the base substrate; at least two columns of data lines connected to the pixel driving circuits connected to different gate lines are connected to the same first connection pad.

2. The electronic paper according to claim 1, wherein: The pixel unit group includes n pixel units arranged side by side along a row direction, n≥2, and n is a positive integer; For the pixel units located in the same row, the pixel driving circuit in the i-th pixel unit in each pixel unit group is electrically connected to the same gate line; i ranges from 1 to n, and i is a positive integer.

3. The electronic paper according to claim 1, wherein: The pixel driving circuits in the pixel unit group are arranged alternately along the column direction.

4. The electronic paper according to claim 3, wherein: The pixel driving circuit is located in a non-display area of ​​the pixel unit; For the pixel units located in the same row, the centers of the non-display areas where the pixel driving circuits connected to the same gate line are located are located on the same straight line, and the extension direction of the straight line is the row direction.

5. The electronic paper according to claim 1, wherein: The data lines connected to the pixel driving circuits in the pixel unit group located in the same column are connected to the same first connection pad.

6. The electronic paper according to claim 1, wherein: Part of the data lines connected to the pixel driving circuits in the pixel unit group located in the same column is connected to the same first connection pad.

7. The electronic paper according to claim 6, wherein: Every two of the data lines adjacently arranged in the row direction are connected to the same first connecting pad.

8. The electronic paper according to any one of claims 1 to 7, wherein: The pixel driving circuit includes at least one transistor and a storage capacitor; the storage capacitor includes a first electrode plate and a second electrode plate arranged opposite to each other; For any of the pixel units, the first electrode of the display unit is electrically connected to the first plate of the storage capacitor.

9. The electronic paper according to claim 8, wherein: The electronic paper comprises a first conductive layer, a semiconductor layer and a second conductive layer sequentially arranged on the base substrate; For any of the pixel units, the control electrode of the transistor is located in the first conductive layer; the active layer of the transistor is located in the semiconductor layer; the first electrode and the second electrode of the transistor are located in the second conductive layer.

10. The electronic paper according to claim 9, wherein: For any of the pixel units, the first plate of the storage capacitor is located on the second conductive layer; and the second plate of the storage capacitor is located on the first conductive layer.

11. The electronic paper according to claim 10, wherein: For any of the pixel units, the second plate of the storage capacitor is divided into a first sub-portion and a second sub-portion; For the pixel units located in the same row, the first sub-portion of the second electrode plate of each storage capacitor is an integrally formed structure; the second sub-portion of the second electrode plate of each storage capacitor is an integrally formed structure; For each of the pixel units, the first sub-portion formed in one piece and the second sub-portion formed in one piece are both connected to the same first common signal line.

12. The electronic paper according to claim 10, wherein: For the pixel units located in the same row, the second electrode plates of the storage capacitors are integrally formed structures; For each of the pixel units, the second electrode plate formed in one piece is connected to the same second common signal line.

13. The electronic paper according to claim 9, wherein: For any of the pixel units, the first plate of the storage capacitor is located on the first conductive layer; and the second plate of the storage capacitor is located on the second conductive layer.

14. The electronic paper according to claim 13, wherein: The second electrode plates of the storage capacitors in the pixel units in the same column are integrally formed; For each of the pixel units, the second electrode plate formed in one piece is connected to the same third common signal line.

15. The electronic paper according to claim 8, wherein: For any of the pixel units, the second electrode of the display unit is arranged on a side of the first electrode away from the base substrate, and the second electrode of the display unit is electrically connected to the second electrode plate of the storage capacitor through a second connecting via.

16. The electronic paper according to claim 9, wherein: The electronic paper further comprises a third conductive layer arranged on a side of the second conductive layer away from the base substrate; For any of the pixel units, the first electrode of the display unit is located in the third conductive layer.

17. The electronic paper according to any one of claims 1 to 7, wherein: For the pixel units located in the same row, the second electrodes of the display units are in the same layer and are an integrated structure.

18. A display device comprising the electronic paper according to any one of claims 1 to 17.

19. A display control method, applied to the electronic paper according to any one of claims 1 to 17; wherein: Display control methods include: For the pixel units located in the same row, each gate line is scanned in sequence, a first voltage is applied to each gate line, and when one of the gate lines is scanned, a third voltage is applied to other gate lines; the other gate lines are gate lines that have been scanned before the gate line currently being scanned; When scanning different gate lines, the data connected to the pixel driving circuit connected to the different gate lines are A different second voltage is applied to the line, so that the first electrode of the display unit receives the second voltage, and the charged particles with the same charging property as the second voltage are driven to move toward the second electrode. 20 . The display control method according to claim 19 , wherein the different second voltages include voltages within at least three different voltage ranges of 10V to 15V, 5V to 8V, and −10V to −15V.

Images