Method and device for reducing sudden drop of power supply

Abstract

Methods and apparatus for reducing or removing sags in a power supply are disclosed. The disclosed teachings may serve various applications, such as applications that implement RF switches. Using such teachings, integration methods may benefit from two different modes of operation, where an external or internal charge pump may be used to provide a desired negative voltage to various components within the integrated circuit. This can be accomplished by disposing a larger load capacitor outside the integrated circuit and without compromising any die space requirements.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. Non-Provisional Application No. 17 / 893,677, filed on August 23, 2022, entitled “POWER SUPPLY SLUMP REDUCTION METHODS AND DEVICES,” the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to methods and apparatus for reducing or removing sags in a power supply. The disclosed methods can serve various applications, more particularly applications implementing RF switches. Background Art

[0004] The performance of various components implemented as part of an electronic circuit may be negatively affected by a temporary voltage sag at the output of a power supply used to bias such components. The term "voltage sag" or "power sag" is used to denote a temporary and undesirable low voltage condition that does not reflect the true condition of the power supply. A typical example is a radio frequency (RF) circuit having a power switch implemented, for example, using a field effect transistor (FET). When in the off state, the power handling of such a switch depends on the bias voltage applied to their gate terminal. As an example, depending on the overall circuit requirements, a certain negative voltage, such as -3.5V, may be required at the FET gate terminal when a switch transition from the on state to the off state occurs. However, the gate terminal of the switch generally requires a certain amount of time to stabilize to the required value. FIG. 1A shows a prior art graph (100A) illustrating such a settling time. Curve (101A) represents a control signal indicating a switching event occurring at time (T1) when the switch begins to transition from the on state to the off state. Curve (102A) represents the voltage at the gate terminal of the switch which is at a positive voltage (Vp) when the switch is turned on and stabilizes to a negative voltage (Vn) and completely turns off after the switch stabilizes (i.e., at and after time (T2)). It can be seen that the settling time before the gate terminal voltage reaches the voltage (Vn) is equal to ΔT=T 2 -T 1 .

[0005] 1A, the settling time as described above depends on the RC time constant at the switch gate terminal, where the resistance R depends on the biasing scheme, and the capacitor C is essentially the off capacitance of the switch, which depends on the switch size. Another factor affecting such a settling time is the possible power sag that occurs during the switching event when the switch transitions from the on state to the off state.

[0006] To further illustrate the effect of power sag on the switch settling time as described above, reference is made to FIG. 1B , which shows an integrated circuit (105) including a power block (110) for biasing other components (not shown) of the integrated circuit (105). The power block (110) includes a (LDO) low dropout voltage regulator (120) and a negative power supply (130). In an embodiment, a positive charge pump can be implemented instead of the LDO (120). The power block (110) is configured to receive a positive power supply voltage from a first external power supply (P1) and a negative power supply voltage from a second external power supply (P2). The negative power supply (130) also includes a negative charge pump (131) and two switches (S1, S2). FIG. 1B also shows a load capacitor (CL) coupled to the terminal (N2). The LDO (120) regulates the positive power supply voltage to provide a regulated positive voltage (VDD) at the terminal (N1). Such a positive voltage can be used to bias the remaining circuits implemented inside the integrated circuit (105). For example, referring to Figures 1A to 1B, and referring to the example of the power switch mentioned above, when the power switches (not shown) inside the integrated circuit (105) are in the on state, a positive voltage (VDD) can be used to provide the required voltage (Vp) at the gate terminals of these switches.

[0007] With further reference to FIG. 1B , the negative power supply (130) provides a negative bias voltage (VSS) at the terminal (N2). This can be accomplished by an internal negative charge pump (131) or by a second external power supply (P2). That is, by turning on (closing) the switch (S1) and turning off (opening) the switch (S2), the internal negative charge pump (131) is selected to provide the negative bias voltage (VSS). On the other hand, by turning off the switch (S1) and turning on the switch (S2), the charge pump will be cut off and the external power supply (P2) is used to generate the negative bias voltage (VSS).

[0008] With further reference to FIG. 1B , as described above, there are applications where an external power supply (P2) is not available or cannot be used. Therefore, the internal charge pump will act as a provider of a negative bias voltage (VSS). In this case, the load capacitor (CL) is charged by the charge pump (131) to generate the negative charge required by the rest of the circuit. In most applications, die space requirements are stringent, and therefore, implementing a larger size load capacitor may be prohibitive due to such die space requirements. This means that due to the small size of the load capacitor (CL), the amount of negative charge across the load capacitor may not be sufficient when charged by the negative charge pump (131), and therefore, a sag will occur across the load capacitor (CL). Such a sag may occur whenever there is a high demand for the negative charge required for the bias (e.g., a large RF switch). Therefore, there is a delay before the charge pump is able to provide all the negative charge required by other circuit components across the load capacitor. This may result in an undesirable negative impact on the performance of the rest of the circuit. Now returning to the example of the RF power switch as described above, in the case of transitioning from the on state to the off state, the lack of negative charge across the load capacitor during the transition may result in a larger switching time. This is shown in FIG1C . Similar to that described with respect to FIG1A , curve ( 101C ) represents a control signal indicating a switching event occurring at time (T1′) when the switch begins to transition from an on state to an off state. Curve ( 102C ) represents the voltage at the switch gate terminal which is at a positive voltage (Vp) when the switch is on, and the voltage at the switch gate terminal which stabilizes to a negative voltage (Vn) and is completely off after the switch stabilizes (i.e., at time (T2′) and after time (T2′)). Curve ( 103C ) represents the voltage seen at terminal (N2) of FIG1B during the transition. As shown, a dip (i.e., a sag toward the positive voltage direction) occurs during the transition, slowing down the switch's settling time, which in this case is equal to ΔT′=T 2 ′-T 1 The smaller the load capacitor size, the larger the droop and the slower the transition of the RF switch.

[0009] Referring now back to FIG. 1B , in applications where an external power supply (P2) can be used, the presence of the load capacitor is optional and the external power supply can provide essentially all the negative charge required without any problems. This is illustrated in FIG. 1D , which shows a faster transition, namely curve ( 102D ), because in this case the sag on the power supply, as shown by curve ( 103D ), is almost negligible. Summary of the invention

[0010] In view of the above, a solution is needed to overcome supply voltage sags in applications using negative power supplies inside integrated circuits. This will help avoid undesirable performance degradation (e.g., slower transitions in power switches) caused by such voltage sags.

[0011] The disclosed method and apparatus solve the above-mentioned voltage sag problem in integrated circuits implementing internal negative voltage power blocks such as charge pumps.

[0012] According to a first aspect of the present disclosure, an integrated circuit is provided, comprising: an internal negative power supply inside the integrated circuit; a detector and a control circuit, wherein the detector and the control circuit are configured to connect the internal negative power supply to a negative bias voltage terminal inside the integrated circuit, and disconnect the internal negative power supply from the negative bias voltage terminal inside the integrated circuit, wherein, in a first mode, upon detecting the presence of an external negative power supply outside the integrated circuit, the detector and the control circuit are configured to disconnect the internal negative power supply from the negative bias voltage terminal; and in a second mode, upon detecting the absence of an external negative power supply outside the integrated circuit, the detector and the control circuit are configured to connect the internal negative power supply to the negative bias voltage terminal to provide a negative bias voltage originating from within the integrated circuit.

[0013] According to a second aspect of the present disclosure, an integrated circuit is provided, comprising: an internal negative power supply inside the integrated circuit; a detector and a control circuit, wherein the detector and the control circuit are configured to connect the internal negative power supply or the external negative power supply to a negative bias voltage terminal inside the integrated circuit, and disconnect the internal negative power supply or the external negative power supply from the negative bias voltage terminal inside the integrated circuit, wherein, in a first mode, upon detecting the presence of an external negative power supply outside the integrated circuit and connectable to the integrated circuit, the detector and the control circuit are configured to disconnect the internal negative power supply from the negative bias voltage terminal, and connect the external negative power supply to the negative bias voltage terminal to provide a negative bias voltage originating from the outside to the integrated circuit; and in a second mode, upon detecting the absence of an external negative power supply outside the integrated circuit, the detector and the control circuit are configured to connect the internal negative power supply to the negative bias voltage terminal to provide a negative bias voltage originating from the inside to the integrated circuit.

[0014] According to a third aspect of the present disclosure, a method for providing a negative bias voltage to a negative bias voltage terminal of an integrated circuit is disclosed, the negative bias voltage terminal being inside the integrated circuit, the integrated circuit including an internal negative power supply, the method comprising: in a first mode: detecting the presence of an external negative power supply outside the integrated circuit; disconnecting the negative internal power supply from the internal negative bias voltage terminal; and connecting the external negative power supply to the negative bias voltage terminal, and in a second mode: detecting the absence of the external negative power supply; coupling the negative bias voltage terminal to ground via an external load capacitor, the external load capacitor being arranged outside the integrated circuit; connecting the internal negative power supply to the negative bias voltage terminal, thereby charging the external load capacitor with a negative charge as the negative bias voltage.

[0015] Other aspects of the disclosure are provided in the description, drawings and claims of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] FIG. 1A shows a prior art graph illustrating a timing diagram associated with a transition of a radio frequency switch from an on state to an off state.

[0017] FIG. 1B shows a prior art integrated circuit.

[0018] 1C to 1D show timing diagrams associated with power sags.

[0019] FIG. 2A to FIG. 2C An exemplary integrated circuit according to an implementation of the present disclosure is shown.

[0020] FIG. 3A to FIG. 3B An exemplary timing diagram associated with the functionality of the detector and control module according to an embodiment of the present disclosure is shown.

[0021] FIG. 4A to FIG. 4B An exemplary implementation according to the teachings of the present disclosure is shown, illustrating how to detect the presence / absence of an external power source and how to set the operating mode accordingly.

[0022] Like reference numbers and numerals in the various drawings indicate like elements. DETAILED DESCRIPTION

[0023] Figure 2AAn integrated circuit (205) according to an embodiment of the present disclosure is shown. The integrated circuit (205) includes a power block (210) for biasing other components (not shown) of the integrated circuit (205). The power block (210) includes an optional (LDO) low dropout voltage regulator (220) and a negative power supply circuit or module (230). Similar to what is described with respect to the integrated circuit (105) of FIG. 1B, the power block (210) is configured to receive a positive power supply voltage from a first external power supply (P1) and a negative power supply voltage from a second external power supply (P2). The negative power supply (230) also includes a negative charge pump (231), a detector and control circuit or module (232), and switches (S3, S4). In contrast to the integrated circuit (105) of FIG. 1B, the load capacitor (CL) is now provided at a terminal (N3) external to the integrated circuit (205). The operating principle and function of the optional LDO (220) are similar to the principles described with respect to the LDO (120) of FIG. 1B.

[0024] According to the teachings of this disclosure, Figure 2A The embodiment of can operate in two modes. In the first mode corresponding to an application in which an external power supply (P2) can be used, the detector and control module (232) has the function of detecting the presence of the external power supply (P2). After such detection, the detector and control module (232) will issue a control signal to disconnect (open) the switch (S3) and connect (close) the switch (S4). Therefore, the negative charge pump (231) is disconnected and turned off, and the negative bias voltage (VSS) is directly provided from the connected external power supply (P2). In the first mode, the load capacitor (CL) is optional, and the problem of voltage sag does not actually exist because the external power supply (P2) is able to provide all the negative charge required to generate the negative bias voltage (VSS). That is, returning to the exemplary application in which the integrated circuit (205) includes an RF power switch, when transitioning from the on state to the off state, the settling time of such a switch will not be impaired due to the problem of power supply voltage sag as described above. According to the teachings of the present disclosure, the switch (S4) is optional. That is, it is also conceivable to implement the above two modes without the switch ( S4 ).

[0025] Figure 2BIndicates a second operating mode of the integrated circuit (205). The second mode corresponds to an application where an external power supply is not available or cannot be used. In this case, upon detecting that the external power supply is not present, the detector and control module (232) will provide a control signal to turn on (close) the two switches (S3, S4). That is, in this mode, the internal negative charge pump (231) will be used to provide the negative bias voltage (VSS) required by the remaining circuits. According to the teachings of the present disclosure, by arranging the load capacitor (CL) outside the integrated circuit (205), a larger size capacitor (e.g., 7nF to 20nF) can now be implemented without compromising the die space and circuit performance within the integrated circuit. The reason for this is that due to the large size of the load capacitor (CL), the negative charge required by the components within the integrated circuit (205) can now be provided without any voltage sag issues. That is, when the user selects the second mode, at the start of operation, the load capacitor (CL) will be charged by the negative charge pump (231). Due to the large size of the load capacitor (CL), such negative charge will remain largely fixed throughout operation, and more specifically during transition times or switching events where the rest of the circuit requires a large negative charge for short durations for biasing purposes. Those skilled in the art will recognize that by providing two corresponding operating modes, the integrated circuit (205) can now serve both applications with and without external power being present, without compromising overall integrated circuit performance or die area. Figure 2C An integrated circuit (205') according to an embodiment of the present disclosure is shown. Figure 2C The operating principle of the integrated circuit (205') is similar to that of Figure 2B The principle described in the integrated circuit (205) is different in that Figure 2C The optional switch (S4) is replaced by a wire.

[0026] Figure 3A Shown with FIG. 2A to FIG. 2B An exemplary timing diagram of the detector and the functions of the control module (232) is shown. Signal (301A) indicates when FIG. 2A to FIG. 2B The start pulse is generated inside the IC when the power supply (P1) is applied to the IC, and it will exist in the two operating modes mentioned above. The width of such a pulse indicates the waiting time (ΔT w ), during which the presence or absence of the external power supply (P2) will be determined by FIG. 2A to FIG. 2B The detector and control module (232) detects to determine which of the first operating mode or the second operating mode is enabled. Then, the detector and control module (232) will send a signal to the controller according to the detected operating mode. FIG. 2A to FIG. 2B The control switches (S3, S4) send appropriate control signals.

[0027] Figure 3A This corresponds to the first operating mode as described above (i.e., connected to external power). Figure 2A When the power source (P2) is connected to the terminal (N3), the voltage of such terminal changes from 0V to a negative value (e.g. -3.5V), as shown by the signal (302A). Such a change occurs during the waiting time (ΔT w ) is detected by the detector and control module (232). Such module indicates detection by issuing a signal (303A) from, for example, a low level to a high level (rising edge). Signal (304A) represents a control signal for activating or deactivating the charge pump (231). In this exemplary embodiment, the low level / high level state of such a control signal indicates activation / deactivation of the negative charge pump (231). Figure 2A As shown, in this case as the first operating mode, the negative charge pump (231) is deactivated. Signal (305) represents the voltage at terminal (N2), which is stabilized to a negative bias voltage (VSS), such as -3.5V, and will be used by the rest of the circuit as required.

[0028] Figure 3B shows that when operating in the second mode FIG. 2A to FIG. 2B An exemplary timing diagram of the functions associated with the detector and control module (232) is shown. The waveforms shown from top to bottom represent the functions associated with Figure 3A In the second mode as shown in the figure, no external power supply is connected to the terminal (N3), so during the waiting time (ΔT) shown by the signal (301B), w ), no negative voltage is detected at terminal (N3). This means that the negative charge pump (231) will be used. Signal (304B) is active during the waiting time (ΔT) of activating the charge pump. w ) immediately after the high level changes to the low level. Signal (306) indicates that the output of the negative charge pump (231) changes from the high level to the low level after the waiting time (ΔT w ) and in response to the transition of signal (304B) from high to low. As shown, the charge pump output will settle to a negative voltage (VSS), such as -3.5V, after a duration (Tc). Such duration, which is essentially the charge pump startup time, depends on the load capacitor (CL), the fly capacitor that is usually implemented as part of the charge pump, and the charge pump frequency. Signal (303B) is similar to Figure 3A As can be noted, the rising edge of signal (303B) now occurs within the waiting time (ΔT) which is an indication of the second operating mode. w ). Signal (305B) indicates Figure 2BThe voltage at the terminal (N2) of the charge pump stabilizes to the required negative bias voltage (VSS) after a duration equal to the charge pump startup time.

[0029] FIG. 4A to FIG. 4B An exemplary implementation according to the teachings of the present disclosure is shown, illustrating how to detect the presence / absence of an external power source and how to set the operating mode accordingly. FIG. 4A to FIG. 4B The detector and control module (432) is similar to FIG. 2A to FIG. 2B The detector and module (232) of the present invention comprises a sensing and control module (433), resistors (R1, R2) and a switch (S5). The combination of the series resistors (R1, R2) and the switch (S5) couples the positive bias voltage (VDD) to the terminal (N3). FIG. 2A to FIG. 2B As shown, a positive bias voltage (VDD) is provided via a positive external power supply (P1). Figure 4A Corresponding to the first operating mode, the external power source (P2) is connected at the terminal (N3). Therefore, a negative voltage, for example -3.5V, appears at the terminal (N3). During the startup and during the waiting time (ΔT w ), the switch (S5) is closed and the resistors (R1, R2) are selected so that the voltage at the terminal (N4) sensed by the sensing and control module (433) is a negative voltage. Therefore, the sensing and control module (433) issues a control signal to close the switch (S4') and open the switch (S3'). That is, the charge pump (431) is cut off and the negative voltage required by the rest of the circuit is provided by the external power supply (P2). In the first mode, the load capacitor (CL) is optional and, if implemented, such a load capacitor can be used for the purpose of filtering the output of the external power supply (P2).

[0030] Figure 4B Corresponding to the second mode, in which the terminal (N3) remains open and has no connection to the external power supply. Therefore, during the waiting time (ΔT w ), the switch (S5) is closed and the positive voltage at the sensing terminal (N4) is sensed so that the sensing and control module (433) will issue the time control signal to close both switches (S3', S4). In this way, at start-up, the external load capacitor (CL) is charged using the charge pump, and the stored negative charge can be used later during normal operation to provide the required negative voltage required by the rest of the circuit. Since it is possible to provide a larger load capacitor (CL) external to the integrated circuit, sufficient negative charge will be stored during operation, and this will overcome the power sag problem as described above.

[0031] As used in this disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and encompasses insulated gates having metal or metalloid, insulator, and / or semiconductor structures. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper or other metal, or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0032] As used in this disclosure, the term "radio frequency" (RF) refers to oscillation frequencies in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves or alternating voltage or current in an electrical circuit.

[0033] With respect to the drawings cited in this disclosure, the dimensions of the various elements are not drawn to scale; some dimensions are greatly exaggerated vertically and / or horizontally for clarity or emphasis. In addition, references to orientations and directions (e.g., "top," "bottom," "above," "below," "lateral," "vertical," "horizontal," etc.) are relative to the exemplary drawings and are not necessarily absolute orientations or directions.

[0034] Various embodiments of the present invention can be implemented to meet a variety of specifications. Unless otherwise specified above, the selection of suitable component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structure), or in hybrid or discrete circuit form. Integrated circuit implementations can be manufactured using any suitable substrate and process, including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon on insulator (SOI) and silicon on sapphire (SOS). Unless otherwise specified above, embodiments of the present invention can be implemented in other transistor technologies, such as bipolar, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAs pHEMT and MESFET technology. However, embodiments of the present invention are particularly useful when manufactured using SOI or SOS-based processes, or when manufactured using processes with similar characteristics. Fabrication in CMOS using SOI or SOS processes enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity and high frequency operation (i.e., radio frequencies up to and exceeding 300GHz). Monolithic IC implementations are particularly useful because parasitic capacitances can usually be kept low by careful design (or at least, kept uniform across all cells to allow them to be compensated for).

[0035] Depending on the particular specifications and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices), voltage levels may be adjusted, and / or voltage and / or logic signal polarity inversion may be achieved. Some disclosed devices detect the presence / absence of a negative bias voltage while implementing a positive supply voltage. Some other disclosed devices detect the presence / absence of a positive bias voltage while implementing a negative supply voltage. Component voltage, current, and power handling capabilities may be adapted as needed, for example, by adjusting device size, "stacking" components (particularly FETs) in series to withstand larger voltages, and / or using multiple components in parallel to handle larger currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0036] Circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. Embodiments of the present invention can be manufactured as integrated circuits (ICs), which can be packaged in IC packages and / or modules for ease of processing, manufacturing and / or improved performance. In particular, IC embodiments of the present invention are often used in such modules, in which one or more such ICs are combined with other circuit blocks (e.g., filters, amplifiers, passive components and possible additional ICs) into a package. Then, the IC and / or module are usually combined with other components, usually on a printed circuit board, to form a part of a final product (e.g., a cellular phone, a laptop computer or an electronic tablet), or to form a more advanced module that can be used in a variety of products (e.g., vehicles, test equipment, medical devices, etc.). Through various configurations of modules and components, such ICs usually implement communication modes, usually wireless communications.

[0037] A number of embodiments of the present invention have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the above steps may be order-independent and therefore may be performed in a different order than described. In addition, some of the above steps may be optional. The various activities described with respect to the above method may be performed in a repetitive, serial and / or parallel manner.

[0038] It should be understood that the foregoing description is intended to illustrate rather than limit the scope of the invention, which is defined by the scope of the appended claims, and other embodiments are also within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more methods, machines, manufactures, or compositions of matter set forth in the following claims. (Note that parenthetical markings of claim elements are for ease of reference to such elements and do not themselves indicate a specific desired ordering or enumeration of elements; furthermore, such markings may be reused in dependent claims as references to additional elements without being considered as conflicting marking sequences).

Claims

1. An integrated circuit, comprising: an internal negative power supply within the integrated circuit; a detector and control circuit configured to connect and disconnect the internal negative power supply to and from a negative bias voltage terminal inside the integrated circuit, in, In a first mode, upon detecting the presence of an external negative power supply external to the integrated circuit, the detector and control circuitry is configured to disconnect the internal negative power supply from the negative bias voltage terminal; In a second mode, upon detecting the absence of an external negative power supply external to the integrated circuit, the detector and control circuit is configured to connect the internal negative power supply to the negative bias voltage terminal to provide an internally sourced negative bias voltage to the integrated circuit; indicating detection of the presence of the external negative power supply at a first time within a set waiting period during startup of the integrated circuit; and Detection of the absence of the external negative power source is indicated at a second time greater than the first time and outside the set waiting period.

2. The integrated circuit according to claim 1, wherein: The internal negative power supply includes a negative charge pump.

3. The integrated circuit of claim 1 , further comprising a first switch controllable by the detector and the control circuit, the first switch being configured to connect the negative charge pump to the negative bias voltage terminal and disconnect the negative charge pump from the negative bias voltage terminal.

4. The integrated circuit of claim 3 further comprising a second switch controllable by the detector and the control circuit, the second switch being configured to connect a terminal of the external power supply to the negative bias voltage terminal and disconnect a terminal of the external power supply from the negative bias voltage terminal.

5. A circuit device comprising the integrated circuit according to claim 1 and an external positive power supply outside the integrated circuit, wherein the external positive power supply is configured to be connected to a positive bias voltage terminal inside the integrated circuit to provide a positive bias voltage originating from the outside to the integrated circuit.

6. A circuit arrangement comprising the integrated circuit according to claim 1 and an external load capacitor coupled between the negative bias voltage terminal and a reference voltage.

7. The integrated circuit according to claim 6, wherein: The external load capacitor is external to the integrated circuit and has a capacitance in the range of 7 nF to 20 nF.

8. The integrated circuit according to claim 5, wherein: The detector and control circuit includes a series combination of a first resistor, a second resistor, and a third switch, the series combination selectively coupling the external negative power supply to the negative bias voltage terminal.

9. An integrated circuit comprising an internal negative power supply within the integrated circuit; a detector and control circuit configured to connect the internal negative power supply or the external negative power supply to a negative bias voltage terminal inside the integrated circuit and disconnect the internal negative power supply or the external negative power supply from the negative bias voltage terminal inside the integrated circuit, in, In a first mode, upon detecting the presence of the external negative power supply external to the integrated circuit and connectable to the integrated circuit, the detector and control circuit is configured to disconnect the internal negative power supply from the negative bias voltage terminal and connect the external negative power supply to the negative bias voltage terminal to provide an externally derived negative bias voltage to the integrated circuit; as well as In a second mode, upon detecting the absence of the external negative power supply external to the integrated circuit, the detector and control circuit is configured to connect the internal negative power supply to the negative bias voltage terminal to provide an internally derived negative bias voltage to the integrated circuit, in, indicating detection of the presence of the external negative power supply at a first time within a set waiting period during startup of the integrated circuit, and Detection of the absence of the external negative power source is indicated at a second time greater than the first time and outside the set waiting period.

10. The integrated circuit of claim 9, wherein: The internal negative power supply includes a negative charge pump.

11. The integrated circuit of claim 10, further comprising a first switch controllable by the detector and control circuit, the first switch being configured to connect the negative charge pump to the negative bias voltage terminal and disconnect the negative charge pump from the negative bias voltage terminal.

12. The integrated circuit of claim 11 , further comprising a second switch controllable by the detector and control circuit, the second switch being configured to connect a terminal of the external power supply to the negative bias voltage terminal and disconnect a terminal of the external power supply from the negative bias voltage terminal.

13. A circuit device comprising the integrated circuit according to claim 9 and an external positive power supply outside the integrated circuit, wherein the external positive power supply is configured to be connected to a positive bias voltage terminal inside the integrated circuit to provide a positive bias voltage originating from the outside to the integrated circuit.

14. A circuit arrangement comprising the integrated circuit of claim 9 and an external load capacitor, the external load capacitor being external to the integrated circuit and coupling the negative bias voltage terminal to ground.

15. The circuit arrangement according to claim 14, wherein: The external load capacitor has a capacitance in the range of 7nF to 20nF.

16. The circuit arrangement according to claim 13, wherein: The detector and control circuit includes a series combination of a first resistor, a second resistor, and a third switch, the series combination selectively coupling the external negative power supply to the negative bias voltage terminal.

17. A method of providing a negative bias voltage to a negative bias voltage terminal of an integrated circuit, the negative bias voltage terminal being inside the integrated circuit, the integrated circuit comprising an internal negative power supply, the method comprising: In the first mode: detecting the presence of an external negative power source external to the integrated circuit at a first time within a set waiting period during startup of the integrated circuit; disconnecting the negative internal power supply from the internal negative bias voltage terminal; as well as connecting the external negative power supply to the negative bias voltage terminal, as well as In the second mode: detecting the absence of the external negative power source at a second time greater than the first time and outside the set waiting period; coupling the negative bias voltage terminal to ground via an external load capacitor, the external load capacitor being disposed external to the integrated circuit; as well as The internal negative power supply is connected to the negative bias voltage terminal, thereby charging the external load capacitor with negative charge as the negative bias voltage.

18. The method according to claim 17, wherein: The internal negative power supply is a charge pump.

19. The method according to claim 17, wherein: The external load capacitor has a capacitance in the range of 7nF to 20nF.

20. The method of claim 17, further comprising connecting an external positive power supply to a positive bias voltage terminal inside the integrated circuit.

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