Modulating power consumption from power source supplying power to data dependent power consumer

Abstract

A method may include setting a data mode state signal to a data mode state indicating a data mode to be received by a data dependent power consumer; and modulating power consumption from a power source providing power to the data dependent power consumer based at least in part on the set data mode state signal.

Description

[0001] Priority declaration

[0002] This application claims the benefit of the priority date of U.S. Provisional Patent Application Serial No. 63 / 376,864, filed on September 23, 2022, entitled “IDLE PATTERN DETECTION AND CURRENT COMPENSATION, METHOD AND APPARATUS FOR REDUCING DATADEPENDENT POWER SOURCE CURRENT VARIATION,” under 35 U.S.C. §119(e), the contents and disclosure of which are incorporated herein by reference in their entirety. Technical Field

[0003] One or more examples involve modulating power consumption from a power source that supplies power to one or more data-dependent power consumers. One or more examples involve determining that an idle data pattern exists. One or more examples involve compensating for a reduction in power consumption of a data-dependent power consumer caused by an idle data pattern. Background Art

[0004] Electronic communications systems and computer buses and their interfaces are used in a variety of operating environments. BRIEF DESCRIPTION OF THE DRAWINGS

[0005] To easily identify the discussion of any particular element or act, the most significant digit(s) in a reference number refers to the figure number in which the element is first introduced.

[0006] Figure 1 is a block diagram illustrating an apparatus for compensating for reduced power consumption caused by data-dependent power consumption according to one or more examples.

[0007] Figure 2 is a block diagram illustrating a system for compensating for reduced power consumption caused by data-dependent power consumers according to one or more examples.

[0008] Figure 3 is a block diagram illustrating an apparatus for determining a data mode status of a data mode 106 according to one or more examples.

[0009] Figure 4 is a block diagram of an apparatus for determining data pattern status using autocorrelation according to one or more examples.

[0010] Figure 5 is a block diagram of an apparatus for regulating power modulation with respect to data mode status signals of a plurality of data mode detectors according to one or more examples.

[0011] Figure 6 is a block diagram of an apparatus for aligning power modulation in a sequential manner according to one or more examples.

[0012] Figure 7 is a schematic diagram of a current sink activated in response to a detection signal generated by an idle mode detector according to one or more examples.

[0013] Figure 8 is a block diagram illustrating a system for compensating for reduced power consumption caused by data dependent power consumers of a serial interface according to one or more examples.

[0014] Fig. 9 is a flow chart depicting a process of compensating for reduced power consumption caused by data-dependent power consumption according to one or more examples.

[0015] Fig.10 is a flow chart depicting a process of setting a data mode state signal to a data mode state indicating a data mode to be received by a data dependent power consumer according to one or more examples.

[0016] Fig.11 is a flow diagram depicting a process for determining a data pattern state for a data pattern based at least in part on symbolic relationships of the data pattern according to one or more examples.

[0017] Fig.12 is a flow chart depicting a process of determining a data schema state of a data schema based at least in part on a frequency of identified relationship changes according to one or more examples.

[0018] Fig.13 is a flow chart depicting a process of determining a data pattern status of a data pattern based on autocorrelation according to one or more examples.

[0019] Fig.14 An example process for determining a data pattern status of a data pattern based on autocorrelation according to one or more examples is illustrated.

[0020] Fig.15 are block diagrams of circuit systems that, in some examples, may be used to implement various functions, operations, acts, processes, or methods disclosed herein. DETAILED DESCRIPTION

[0021] In the following detailed description, reference is made to the accompanying drawings which form a part of the present disclosure, and in the accompanying drawings are shown by way of illustration specific examples in which the present disclosure may be practiced. These examples are described in sufficient detail to enable one of ordinary skill in the art to practice the present disclosure. However, other examples may be utilized, and changes in structure, material, and process may be made without departing from the scope of the present disclosure.

[0022] The illustrations presented herein are not intended to be actual views of any particular method, system, device, or structure, but are merely idealized representations used to describe examples of the present disclosure. The drawings presented herein are not necessarily drawn to scale. For the convenience of the reader, similar structures or components in the various drawings may retain the same or similar numbering; however, the similarity of numbering does not mean that the structure or component must be the same in size, composition, configuration, or any other attribute.

[0023] The following description may include examples to help enable a person of ordinary skill in the art to practice the disclosed examples. The use of the terms "exemplary," "such as," and "for example" means that the related description is illustrative, and while the scope of the present disclosure is intended to encompass the examples and legal equivalents, the use of such terms is not intended to limit the examples or the scope of the present disclosure to the specified components, steps, features, functions, etc.

[0024] It should be readily understood that the components of the examples as generally described herein and illustrated in the accompanying drawings may be arranged and designed in a variety of different configurations. Therefore, the following description of various examples is not intended to limit the scope of the present disclosure, but is merely representative of various examples. Although various aspects of these examples may be presented in the accompanying drawings, the drawings are not necessarily drawn to scale unless otherwise indicated.

[0025] In addition, the specific implementations shown and described are only examples and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. Elements, circuits, and functions can be shown in block diagram form so as not to obscure the present disclosure with unnecessary details. On the contrary, the specific implementations shown and described are only exemplary and should not be understood as the only way to implement the present disclosure, unless otherwise specified herein. Additionally, the partitioning of logic between block definitions and individual blocks is an example of a specific implementation. It will be apparent to those of ordinary skill in the art that the present disclosure can be practiced through many other partitioning solutions. In most cases, details about timing considerations, etc. have been omitted, where such details are not required to obtain a complete understanding of the present disclosure and are within the capabilities of those of ordinary skill in the relevant art.

[0026] Those of ordinary skill in the art will appreciate that information and signals may be represented using any of a variety of different technologies and techniques. For clarity of presentation and description, some of the figures may illustrate a signal as a single signal. Those of ordinary skill in the art will appreciate that a signal may represent a signal bus, where the bus may have a variety of bit widths, and that the present disclosure may be implemented on any number of data signals, including a single data signal.

[0027] The various illustrative logic blocks, modules, and circuits described in conjunction with the examples disclosed herein may be implemented or executed with a general purpose processor, a special purpose processor, a digital signal processor (DSP), an integrated circuit (IC), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, or any combination thereof designed to perform the functions described herein. A general purpose processor (also referred to herein as a host processor or simply a host) may be a microprocessor, but in an alternative, the processor may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration. A general purpose computer is considered a special purpose computer when it includes or executes computing instructions (e.g., software code) associated with the examples disclosed herein.

[0028] Examples may be described in terms of processes depicted as flow charts, flow diagrams, structure diagrams, or block diagrams. Although flow charts may describe operable actions as continuous processes, many of these actions may be performed in another sequence, in parallel, or substantially simultaneously. In addition, the order of the actions may be rearranged. A process may correspond to a method, a thread, a function, a procedure, a subroutine, a subprogram, but is not limited thereto. In addition, the methods disclosed herein may be implemented by hardware, software, or both. If implemented in software, a function may be stored or sent to a computer-readable medium as one or more instructions or codes. Computer-readable media include both computer storage media and communication media, which include any media that facilitates transferring a computer program from one location to another.

[0029] Any reference to elements herein using names such as "first," "second," etc. does not limit the quantity or order of those elements unless such limitations are explicitly stated. Rather, these names may be used herein as a convenient method of distinguishing between two or more elements or instances of elements. Thus, reference to a first element and a second element does not mean that only two elements may be employed there, or that the first element must precede the second element in some manner. Furthermore, unless otherwise indicated, a group of elements may include one or more elements.

[0030] As used herein, the term "substantially" in reference to a given parameter, attribute, or condition refers to and includes the degree to which a person of ordinary skill in the art would understand that the given parameter, attribute, or condition is satisfied with a small degree of variance, such as, for example, within acceptable manufacturing tolerances. By way of example, depending on the particular parameter, attribute, or condition that is substantially satisfied, the parameter, attribute, or condition may be satisfied by at least 90%, by at least 95%, or even by at least 99%.

[0031] As used herein, any relative terms (such as "above", "below", "on", "below", "upper", "lower", but not limited to) are used for clarity and convenience in understanding the present disclosure and the drawings, and do not imply or depend on any particular preference, orientation, or order unless the context clearly indicates otherwise.

[0032] In this description, the term "coupled" and its derivatives may be used to indicate that two elements cooperate or interact with each other. When an element is described as being "coupled" to another element, then the elements may be in direct physical or electrical contact, or there may be intervening elements or layers. In contrast, when an element is described as being "directly coupled" to another element, then there are no intervening elements or layers. The term "connected" may be used interchangeably with the term "coupled" in this specification and have the same meaning, unless otherwise expressly indicated or the context would indicate otherwise to one of ordinary skill in the art.

[0033] As used herein, the term "assert" when used with "signal" means to set a signal to an active state. As used herein, the term "disable" when used with "signal" means to set a signal to an inactive or default state. For example, a signal may be active high and inactive low, or active low and inactive high.

[0034] A "clock signal" is a signal that oscillates between two discrete states (a low state and a high state) in a reliable and predictable manner. As a non-limiting example, one or more circuits may coordinate actions in response to the rising edge or the falling edge of a clock. The terms "clock signal" and "clock" are used interchangeably herein to refer to a "clock signal."

[0035] A "data pattern" is a sequence of symbols. The corresponding symbols of the data pattern may represent one or more data bits, such as one data bit (e.g., a pulse amplitude modulation (PAM)2) symbol, a binary phase shift keying (binary PSK or BPSK) symbol, a binary frequency shift keying (binary FSK or BFSK) symbol, but not limited thereto), two data bits (e.g., a PAM-4 symbol, a quadrature PSK (QPSK) symbol, a 4-FSK symbol, but not limited thereto), three data bits (e.g., a PAM-8 symbol, but not limited thereto), or four data bits (e.g., a 16-QAM (quadrature amplitude modulation) symbol, but not limited thereto), but not limited thereto.

[0036] It is desirable that a data pattern on a serial link (e.g., on a serial interface for communicating via a computer bus, but not limited thereto) exhibit a uniform distribution of data values, sometimes referred to as "statistical randomness" or "pseudo-randomness." Data patterns that exhibit statistical randomness are referred to herein as "random data patterns." When the desire for statistical randomness depends on a particular technical or operational goal, non-limiting examples include: reducing electromagnetic interference or preventing longer runs of the same value that make synchronization more difficult (e.g., due to lost clocks, baseline drift, or error propagation, but not limited thereto). Scrambling is often used to randomize the data, i.e., to enhance the uniform distribution of data values ​​exhibited by the data pattern on the serial link.

[0037] An "idle data pattern" is a repeated, aligned data pattern of valid symbols. An idle data pattern may exist on a serial link (e.g., on a data path of a serial interface, but not limited thereto). In the case of a multi-channel serial link, an idle data pattern may exist on some or all of the corresponding channels of the serial link. In the case of a multi-channel serial link, an idle data pattern may exist on some or all of the corresponding channels of the serial link. An idle data pattern may exhibit repeated variations of symbols having a constant data pattern (e.g., variations in signal levels, but not limited thereto). An idle data pattern may reduce the uniformity of the distribution of data values ​​on the serial link, i.e., the data values ​​lack randomness.

[0038] There are multiple sources of idle data patterns, non-limiting examples being control and management data patterns. PCIe (Peripheral Component Interconnect Express) and other serial communication interfaces (high speed or otherwise) implement control and management functions using predetermined data patterns, sometimes also referred to as "ordered sets". Non-limiting examples of control and management data patterns include Skip Ordered Sets (SKP) and Training Sequence 1 (TS1). SKPs are periodically inserted by the transmitter to allow the receiver to maintain synchronization in a high-speed serial link by skipping SKPs or using them to align a local clock. TS1 is used for link initialization and training processes to, for example, enable the receiver to set its equalization settings and establish a link. Corresponding cases of control and management data patterns (such as SKP and TS1, but not limited thereto) include substantially the same symbol sequences, and many cases of control and management data patterns may occur when performing these functions. Control and management data patterns are non-limiting examples of sources of idle data patterns.

[0039] A data converter (e.g., an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a data rate converter, but not limited thereto) may operate in a data path (a single data path in the case of a single channel and multiple data paths (or "channels") in the case of a multi-channel) of a serial interface. The power consumption profile of a data converter processing an idle data pattern (e.g., a time-interleaved data converter, but not limited thereto) may be substantially different from the power consumption profile of the same data converter processing a random data pattern. When the data pattern repeats, the power consumption of the data converter is less than the power consumption when the data pattern is random. Dynamic power consumption is at least partially responsive to frequency and transition density. For example, when the data pattern is random, there are more transitions that cause the internal node capacitance of the circuit to charge or discharge. The average power consumption of the data converter typically increases in response to a change from an idle data pattern to a random data pattern. The average power consumption of the data converter typically decreases in response to a change from a random data pattern to an idle data pattern, sometimes by a large amount. In an integrated circuit (IC), large variations in average power consumption together with any parasitic inductance in the power delivery network can result in large voltage noise on the power source (e.g., but not limited to, >250 millivolts peak-to-peak (mVpp) for a supply voltage of <1 volt), which can degrade IC performance, sometimes significantly.

[0040] In the case of both receivers and transmitters, the reduced IC performance may reduce the jitter tolerance of the internal receiver and the margin in the transmit eye. In the case of the transmitter, the degradation may be directly observed by the shape of the transmit eye. In some cases, a filter such as a decoupling capacitor may be used to filter out such voltage noise. In some cases, a highly sensitive regulator such as a low dropout (LDO) may be used (e.g., in cascade with a decoupling capacitor, but not limited thereto) so that the data converter can process the data pattern in the presence of voltage noise (even if filtered by the decoupling capacitor).

[0041] Devices and circuits that exhibit a different power consumption profile for idle data patterns as compared to random data patterns may be referred to herein as exhibiting "data-dependent power consumption," and such devices or circuits may be referred to herein as "data-dependent power consumers."

[0042] One or more examples relate to compensating for reduced power consumption caused by data dependent power consumption at a serial interface. In one or more examples, a data mode detector is provided that receives a data pattern, determines a data mode state of the data pattern, and sets a data mode state signal to indicate the determined data mode state.

[0043] Figure 1 is a block diagram illustrating an apparatus 100 for compensating for reduced power consumption caused by data-dependent power consumption, according to one or more examples.

[0044] The apparatus 100 includes a data pattern detector 102 and a power modulator 104 .

[0045] Generally speaking, device 100 dynamically adjusts power consumption in response to a change in the state of a data pattern exhibited by data pattern 106. Data pattern 106 may be a copy of a data pattern to be processed by a data-dependent power consumer, or otherwise indicate a data pattern to be processed by a data-dependent power consumer. A corresponding adjustment to the power consumption of device 100 may correspond to a change in the power consumption of the data-dependent power consumer. In the event that the power consumption of the data-dependent power consumer will be reduced in response to data pattern 106, the corresponding adjustment of the power consumption of device 100 may compensate for some or all of the reduction in the power consumption of the data-dependent power consumer. Therefore, device 100 may also be referred to herein as "data-dependent power compensator 100".

[0046] The data pattern detector 102 receives the data pattern 106, determines a data pattern state of the data pattern 106, and sets the data pattern state signal 108 to indicate the determined data pattern state of the data pattern 106, as described below. The corresponding data pattern state determined by the data pattern detector 102 may include one or more of the presence of an idle data pattern or the absence of an idle data pattern.

[0047] In one or more examples, a first value of the data mode state signal 108 set by the data pattern detector 102 may indicate the presence of an idle data pattern, while a second, different value of the data mode state signal 108 set by the data pattern detector 102 may indicate the absence of an idle data pattern. In another example, the second value of the data mode state signal 108 set by the data pattern detector 102 may indicate a lack of positive confirmation of the presence of an idle data pattern rather than indicating its absence.

[0048] In one or more examples, a first value of the data mode state signal 108 set by the data mode detector 102 may indicate the presence of an idle data pattern, a second value of the data mode state signal 108 set by the data mode detector 102 may indicate the absence of an idle data pattern, and a third value of the data mode state signal 108 set by the data mode detector 102 may indicate a lack of positive confirmation of the presence, absence, or both of an idle data pattern.

[0049] In one or more examples, the data pattern detector 102 may determine a degree of certainty and, if the degree of certainty is greater than a predetermined threshold, set the data pattern status signal 108 to indicate the presence of an idle data pattern, and, if the degree of certainty is less than or equal to the predetermined threshold, set the data pattern status signal 108 to indicate a lack of positive confirmation of the presence, absence, or both of an idle data pattern.

[0050] Additionally or alternatively, in one or more examples, the data pattern detector 102 may set the data mode state signal 108 to a value indicating a degree of certainty based at least in part on the degree of certainty determined by the data pattern detector 102, and this value may be used by the power modulator 104 to set the amount of current drawn, as described below.

[0051] The power modulator 104 receives the data mode state signal 108 and sets its power state based at least in part on this. The corresponding power state of the power modulator 104 may include one or more power states in which it consumes power 110, and a power state in which it consumes no power or consumes negligible power. The power modulator 104 may set its power state to a first power state in which it consumes power in response to the data mode state signal 108 indicating the presence of an idle data mode. The power modulator 104 may set its power state to a second power state in which it does not consume power in response to the data mode state signal 108 indicating the absence of an idle data mode. In some cases, when the power modulator 104 sets its power state to its first state in which it consumes power, the amount of power 110 it consumes is set to compensate for the reduction in power consumption at the data-dependent power consumer, which operates the data mode 106.

[0052] In one or more examples, the power modulator 104 may include one or more controlled current sinks that may be selectively turned on or off to set a power state of the power modulator 104 and optionally set the power 110 consumed by the power modulator 104. When a controlled current sink is turned on, it actively sinks current (draws current) and may present a low impedance path, and when a controlled current sink is turned off, it is inactive (does not draw current) and may present an open or high impedance path.

[0053] In one or more examples, the corresponding controlled current sink of the power modulator 104 can be or include one or more analog or digital circuits for performing the function of sinking current, such as, but not limited to: a switch-controlled current sink, such as a bipolar junction transistor (BJT) or metal oxide semiconductor field effect transistor (MOSFET) controlled current sink, which sinks an amount of current set by a resistor from a node; an operational amplifier (op-amp) controlled current sink, which is used in conjunction with a switch-controlled current sink to accurately set and maintain the amount of current sunk from a node; a transistor-controlled current sink, which uses a digital potentiometer to set the amount of current sunk from a node (the digital potentiometer controls the amount of current sunk based on the digital setting); a pulse width modulation (PWM) controlled current sink, which quickly turns the switch-controlled current sink on and off and by changing the duty cycle of the switching waveform, and thereby controls the average current sunk.

[0054] In one or more examples, the value of the power 110 set by the power modulator 104 may be based at least in part on the expected change in the power consumption of the data-dependent power consumer. In one or more examples, the value of the power 110 set by the power modulator 104 may be predetermined based on the expected reduction in the power consumed by the data-dependent power consumer in response to the presence of one or more idle data patterns. In one or more examples, the amount of power compensation (i.e., the value of the power 110 set by the power modulator 104) may be based at least in part on one or more power consumption profiles associated with the data-dependent power consumer. Such power consumption profiles describe the change in the power consumption of the data-dependent power consumer based on the content and length of the data pattern, and the data pattern includes but is not limited to the idle data pattern being processed. As a non-limiting example, a power consumption profile can be obtained from a manufacturer, via testing, or both.

[0055] In one or more examples, the power modulator 104 may set the power 110 to a value that is proportional to the value of the data mode state signal 108. As a non-limiting example, the greater the value of the data mode state signal 108, the greater the amount of power 110 set by the power modulator 104, and the smaller the value of the data mode state signal 108, the smaller the amount of power 110 set by the power modulator 104. As a non-limiting example, if the data mode detector 102 sets the data mode state signal 108 to a value indicating the presence of an idle data pattern and low certainty, the power modulator 104 may set the power 110 to a value that is smaller than if the value of the data mode state signal 108 indicates the presence of an idle data pattern and high certainty. The power modulator 104 may set the power 110 to a larger value and a smaller value to indicate high certainty or low certainty in response to changing the value of the data mode state signal 108.

[0056] Figure 2is a block diagram illustrating a system 200 that compensates for reduced power consumption caused by data-dependent power consumers according to one or more examples.

[0057] System 200 includes a data converter 202 and a power source 204, and further includes Figure 1 The data pattern detector 102 and the power modulator 104 are shown in FIG. 1 . In this example, the data pattern detector 102 and the power modulator 104 operate as the data dependent power compensator 100, as described above.

[0058] Generally speaking, the system 200 dynamically maintains power consumption through various data pattern state changes exhibited by the data pattern 206 received by the system 200. The data pattern detector 102 and the power modulator 104 cooperate to respond to the data pattern state changes exhibited by the data pattern 206 and dynamically adjust the power consumption of the data converter 202 (a data dependent power consumer in this example) by an amount corresponding to a reduction in the power consumption of the data converter 202.

[0059] The data converter 202 receives the data pattern 206 and generates a converted data pattern 208 in response thereto, at least in part. The data converter 202 converts data from one form to another different form, such as converting between analog and digital forms, converting between voltage levels or current levels used to represent a signal, converting between data rates, changing the bit depth of a value (e.g., between 8 bits and 16 bits, 2 bits and 4 bits, but not limited thereto), and combinations and sub-combinations thereof, but not limited thereto. In one or more examples, the data converter 202 can be an electronic device that performs functions related to a data session, such as an analog-to-digital converter (ADC), a digital-to-analog converter (DAC), a serial-to-parallel converter (e.g., a serial peripheral interface (SPI), but not limited thereto), a parallel-to-serial converter (e.g., a PSI), a protocol converter (e.g., an inter-integrated circuit (I 2 C) to SPI converter, but not limited to), voltage level shifter, and their combinations and sub-combinations, but not limited to.

[0060] The power source 204 provides power (eg, current, voltage, but not limited thereto) that is utilized by the data converter 202 , the power modulator 104 , and optionally the data pattern detector 102 .

[0061] The value of power 110 consumed by power modulator 104 corresponds to a change in the value of power 210 consumed by data converter 202 that is caused by the presence of an idle data pattern in data pattern 106 compared to the absence of such an idle pattern in data pattern 106. Thus, the relationship between power 210 and power 110 is indirectly proportional. For a corresponding negative change (decrease) in power 210, there is a corresponding positive change (increase) in power 110, and for a corresponding positive change (increase) in power 210, there is a corresponding negative change (decrease) in power 110.

[0062] Data pattern detector 102 may utilize any suitable process to determine the data pattern status of data pattern 106, including determining the presence or absence of an idle data pattern, including but not limited to filtering-based techniques, non-filtering-based techniques, and combinations thereof.

[0063] Figure 3 is a block diagram illustrating an apparatus 300 for determining a data pattern state of a data pattern 106 according to one or more examples.

[0064] The apparatus 300 includes a shift register 302, an exclusive-OR (XOR) gate 304, and a filter 306, respectively, for idle mode detection. The apparatus 300 may optionally include a controlled current sink 308 for current draw compensation.

[0065] XOR gate 304 and filter 306 operate as a data pattern detector such as data pattern detector 102. Controlled current sink 308 operates as a power modulator such as power modulator 104. Shift register 302 is a source of the signs of data pattern 320 such as the signs of data pattern 106 provided to XOR gate 304.

[0066] Generally, the apparatus 300 utilizes difference detection to identify symbol changes in the symbols of the data pattern 320, and utilizes the identified symbol changes to determine the data pattern state of the data pattern 320, as described below. As a non-limiting example, using symbol changes in the symbols of the data pattern 320 can enhance noise immunity.

[0067] Shift register 302 is a first-in, first-out (FIFO) shift register that receives the symbols of data pattern 320 and sequentially shifts (moves) the symbols one symbol position toward its output in response to being triggered by clock 318 .

[0068] XOR gate 304 is coupled to shift register 302 to perform difference detection between a symbol stored at a first symbol position of shift register 302 and a symbol stored at a second different symbol position of shift register 302. In one or more examples, as a non-limiting example, by feeding the symbols through shift register 302, the detection interval can be approximately aligned with a clock cycle of clock 318. Respective inputs of XOR gate 304 are coupled (e.g., via taps, but not limited thereto) to corresponding bit positions of shift register 302 to receive the bits stored in the corresponding bit positions. One of the inputs of XOR gate 304 is coupled to receive historical symbols 310, and the other of the inputs is coupled to receive current symbols 312.

[0069] In one or more examples, the historical symbol 310 can be the current symbol 312 in the immediately previous detection interval. In one or more examples, any two symbol positions of the shift register 302 can be coupled to the inputs of the XOR gate 304 as long as the inputs for the historical symbol 310 are coupled to a bit position that is earlier in time than the bit position coupled to the current symbol 312. In one or more examples, the bit positions of the shift register 302 can be adjacent or can be stored in intervening bit positions.

[0070] When the current symbol 312 is identical to the historical symbol 310, the output of the XOR gate 304 is a first value indicating that the current symbol 312 is identical to the historical symbol 310 in response to the XOR action of the XOR gate 304. When the current symbol 312 is different from the historical symbol 310, the output of the XOR gate 304 is a second different value indicating that the current symbol 312 is different from the historical symbol 310 in response to the XOR action of the XOR gate 304. The output of the XOR gate 304 is coupled to the input filter 306.

[0071] Filter 306 receives the output of XOR gate 304, processes the output, and in response to the processing sets data pattern status signal 108. Using the output of XOR gate 304 effectively uses the indication of a sign change to determine the presence of an idle data pattern.

[0072] By way of non-limiting example, assume that Y represents the output of XOR gate 304 when historical symbol 310 and current symbol 312 are different, and N represents the output of XOR gate 304 when historical symbol 310 and current symbol 312 are the same. In the case of a random data pattern, the frequency of the change in the output of XOR gate 304 (e.g., from Y to N or from N to Y) should appear to change, i.e., the output of XOR gate 304 should appear to be frequency modulated. For an idle data pattern, the frequency of the change in the output of XOR gate 304 should appear to be approximately constant or within a narrow frequency band, i.e., frequency stable.

[0073] In one or more examples, filter 306 can detect a frequency-stable output of XOR gate 304 and conversely can detect a frequency-modulated output of XOR gate 304. Filter 306 can utilize any suitable digital signal processing (DSP) technique to determine whether the output of XOR gate 304 is frequency-stable or frequency-modulated, such as, but not limited to, bandpass filtering, moving average filtering, or Kalman filtering.

[0074] In the case of bandpass filtering, filter 306 may include one or more bandpass filters that only pass frequencies within a corresponding predetermined range. The frequency range of the stable frequency associated with the repetitive pattern can be predetermined and used to configure the corresponding bandpass filter. If the output of any filter in the bandpass digital filter bank remains constant, this indicates a stable frequency and an idle data pattern. The output of the bandpass filter can be directly or, for example, via an AND gate or an OR gate to set a data mode state signal 314.

[0075] In the case of moving average filtering, filter 306 may include a moving average filter that smoothes rapid changes in the signal to appear more gradual changes. If the smoothed signal remains consistent over time, this will indicate a stable frequency, and filter 306 sets data pattern state signal 314 to indicate the presence of an idle data pattern.

[0076] In the case of Kalman filtering, filter 306 comprises a Kalman filter that estimates the frequency and rate of change of the output of XOR gate 304. If the rate of change approaches zero for some predetermined duration, the frequency is considered stable, indicating an idle data pattern, and filter 306 sets data pattern status signal 314 to indicate the presence of an idle data pattern.

[0077] In another example, the filter 306 may include a phase detector (e.g., a time-to-digital converter (TDC), but not limited thereto) that stores samples of the output of the XOR gate 304 and compares the stored samples to a current sample of the output of the XOR gate 304 to determine if a phase difference exists. If the determined phase difference is zero (i.e., the phase difference is zero or close to zero), optionally for some predetermined duration, this indicates a stable frequency, and the filter 306 may set the data pattern state signal 314 to indicate the presence of an idle data pattern.

[0078] In one or more examples, data pattern states may be determined using non-filtering based digital signal processing techniques, including but not limited to autocorrelation. In digital signal processing (DSP), an autocorrelator calculates the autocorrelation of a signal. Autocorrelation measures the similarity of a signal to a delayed version of the signal within a certain delay range.

[0079] In one or more examples, an autocorrelation of the data pattern is calculated over a predetermined time interval. If the autocorrelation is above a predetermined threshold, this indicates the presence of an idle data pattern, and if the autocorrelation is less than or equal to the predetermined threshold, this indicates the absence of an idle data pattern.

[0080] Figure 4 is a block diagram of an apparatus 400 for determining a data pattern state using autocorrelation according to one or more examples.

[0081] The apparatus 400 includes one or more delays 402 , a binary multiplier 404 , an accumulator 410 , and a threshold detector 412 .

[0082] One or more delays 402 receive the data pattern 406 and generate one or more delayed data patterns 408 at least partially in response thereto. In one or more examples, the one or more delays 402 may generate corresponding delayed data patterns 408 for a range of delays. The one or more delays 402 may include a plurality of corresponding delays 402 and may generate corresponding delayed data patterns 408 for each delay. Non-limiting examples of delays include delaying one symbol, two symbols, three symbols, or four symbols. Other numbers of delays may be utilized without exceeding the scope of the present disclosure.

[0083] Binary multiplier 404 receives data pattern 406 and corresponding delayed data pattern 408 , computes a product of data pattern 406 and corresponding delayed data pattern 408 , and provides the computed product to accumulator 410 .

[0084] The accumulator 410 receives the calculated products from the binary multiplier 404 and sums the calculated products over one or more predetermined time intervals. The accumulated value stored at the accumulator 410 is an autocorrelation value 414 representing the instantaneous autocorrelation of the data pattern 406 for the corresponding delay. The autocorrelation value 414 may change over time, thereby representing the change in the instantaneous autocorrelation over time.

[0085] Equation 1 provides the autocorrelation value for a particular delay m. For a discrete sequence, the autocorrelation value 414 will be generated as an array (or sequence) of values, where each value corresponds to a particular delay.

[0086] R[m]=∑nx[n]·x[n+m] Formula 1

[0087] Where R[m] represents the autocorrelation value at delay m, x[n] is the signal value at index n, and x[n+m] is the signal value at index n offset by m.

[0088] Threshold detector 412 receives autocorrelation value 414 from accumulator 410 and determines whether autocorrelation value 414 is less than a predetermined threshold or greater than or equal to a predetermined threshold. If autocorrelation value 414 is less than the predetermined threshold, this indicates that there is no idle data pattern. If autocorrelation value 414 is greater than or equal to the predetermined threshold, this indicates that there is an idle data pattern.

[0089] In this manner, device 400 utilizes autocorrelation to determine the mode state of data pattern 406 (ie, the presence or absence of an idle data pattern) and sets data mode state signal 416 to indicate the determined mode state.

[0090] In a multi-channel serial interface, each channel of the serial interface may include a data dependent power consumer, such as a data converter that is affected by the presence of an idle data pattern. In one or more examples, a corresponding data dependent power compensator, such as data dependent power compensator 100, may be provided to some or all of such data dependent power consumers.

[0091] In one or more examples, the respective data dependent power compensators of each channel may modulate power consumption independently (from each other), as described above. In some cases, it may be desirable to align power modulations performed on the various data dependent power compensators.

[0092] Figure 5 is a block diagram depicting an apparatus 500 for regulating power modulation with respect to data pattern status signals of a plurality of data pattern detectors according to one or more examples.Regulating power modulation with respect to data pattern status signals of respective data pattern detectors monitoring respective data patterns of respective data-dependent power compensators may also be referred to herein as a "majority voting mechanism."

[0093] In one or more examples, the corresponding data pattern detectors 502 can receive the corresponding data patterns 508 from the corresponding channels of the multi-channel serial interface. Alternatively, some data pattern detectors 502 can receive the corresponding data patterns 508 from the corresponding channels of the multi-channel serial interface, and other data pattern detectors 502 can receive the corresponding data patterns 508 from data paths of other data-dependent power consumers.

[0094] The device 500 includes a data pattern detector 502 and a multi-input AND gate 504. The device 500 optionally also includes a controlled current sink 506. When the device 500 does not include the controlled current sink 506, it can be referred to as a set of data pattern detectors 502. When the device 500 includes the controlled current sink 506, it can be referred to as a data-dependent power compensator 500 regulated by a majority voting mechanism.

[0095] The corresponding data pattern detector 502 receives the corresponding data pattern 508 and generates, at least in part in response thereto, a corresponding data pattern status signal 510. In one or more examples, the corresponding data pattern 508 can be from a corresponding channel of a multi-channel serial interface.

[0096] The multi-input AND gate 504 receives the data mode state signals 510 generated by the data pattern detector 502 and sets the control signal 512 at least partially in response thereto. The multi-input AND gate 504 sets the control signal 512 to activate the controlled current sink 506 in response to all of the data mode state signals 510 asserted by the data pattern detector 502. The multi-input AND gate 504 sets the control signal 512 to a first value that turns on the controlled current sink 506 in response to all of the data mode state signals 510 being asserted, and sets the control signal 512 to a second value that turns off the controlled current sink 506 in response to any of the data mode state signals 510 being de-asserted.

[0097] In this way, the compensation current draw is activated only when all data mode state signals 510 are asserted.

[0098] Figure 6 6 is a block diagram of an apparatus 600 for aligning power modulation in a sequential manner according to one or more examples. The respective data dependent power compensators or data pattern detectors of the apparatus 600 are configured to align sequential power modulation, i.e., the adjustment of the power modulation or the setting of the data pattern state signal by at least some of the data dependent power compensators is based on the power modulation of one or more other data dependent power compensators or the data pattern state signal of one or more other data pattern detectors.

[0099] The apparatus 600 includes 1 to N idle mode detectors and optionally 1 to N controlled current sinks. The 1 to N idle mode detectors include a first idle mode detector 602, a second idle mode detector 604, and an Nth idle mode detector 606. The optional 1 to N controlled current sinks include a controlled current sink 614, a controlled current sink 616, and a controlled current sink 618.

[0100] The first idle mode detector 602 receives the first data pattern 620 and generates a first data mode state signal 608 in response, at least in part, thereto. The second idle mode detector 604 receives the second data pattern 622 and is coupled to receive the first data mode state signal 608 from the first idle mode detector 602. The second idle mode detector 604 generates a second data mode state signal 610 in response, at least in part, to the second data pattern 622 and the first data mode state signal 608. The Nth idle mode detector 606 receives the third data pattern 624 and is coupled to receive the second data mode state signal 610 from the second idle mode detector 604. The Nth idle mode detector 606 generates a third data mode state signal 612 in response, at least in part, to the third data pattern 624 and the second data mode state signal 610.

[0101] More specifically, only when the second idle mode detector 604 detects that an idle mode exists in the second data pattern 622 and the first data mode state signal 608 is asserted, that is, the first idle mode detector 602 detects that an idle mode exists in the first data pattern 620, the second idle mode detector asserts the second data mode state signal 610. Only when the Nth idle mode detector 606 detects that an idle data pattern exists in the third data pattern 624 and the second data mode state signal 610 is asserted, the Nth idle mode detector asserts the third data mode state signal 612.

[0102] By way of non-limiting example, if the Nth idle mode detector 606 detects the presence of an idle data pattern earlier in time than the second idle mode detector 604, and thus the second data mode state signal 610 is deasserted when the Nth idle mode detector 604 detects the idle data pattern, then the Nth idle mode detector 606 will not assert the third data mode state signal 612 unless or until the second idle mode detector 606 asserts the second data mode state signal 610. Similarly, the second idle mode detector 604 will not assert the second data mode state signal 610 unless or until the first idle mode detector 602 asserts the first data mode state signal 608.

[0103] Figure 7 is a schematic diagram of a current sink 700 activated in response to a detection signal generated by an idle pattern detector or in response to a control signal generated by a plurality of data pattern detectors according to one or more examples.

[0104] The current sink 700 includes a plurality of complementary metal oxide semiconductor (CMOS) inverters ( Figure 7700 , when turned on, can be set based on the number of CMOS inverters present.

[0105] The corresponding CMOS inverter is selectively coupled to VSUP and ground respectively through switch 702 and switch 704. When switch 702 and switch 704 are turned on, they allow current to flow between the CMOS inverter and VSUP and ground. When switch 702 and switch 704 are turned off, they are high impedance or open circuit and they do not allow current to flow.

[0106] The switches 702 and 704 are controlled by (i.e., switched on and off in response to) a data mode state signal 706. In one or more examples, the data mode state signal 706 can be generated by any of the idle mode detectors described herein including the detector 102, the device 300, the device 400, the data mode detector 502, the first idle mode detector 602, the second idle mode detector 604, or the Nth idle mode detector 606.

[0107] When switch 702 and switch 704 are turned on, clock gating logic 708 can selectively provide gated clock 716 based on clock 718. Any one or more sources of clock 718 can be utilized. In one or more examples, clock 718 can be or be based on a clock utilized by a data-dependent power consumer such as data converter 202, but is not limited thereto, such that power modulation by current sink 700 is temporally aligned with changes in power consumption by the data-dependent power consumer.

[0108] Figure 8 is a block diagram depicting a system 800 that compensates for reduced power consumption caused by a data dependent power consumer of a serial interface according to one or more examples. As a non-limiting example, the data dependent power consumer may be a data converter such as an ADC or DAC.

[0109] System 800 includes a serial interface 802, a data pattern detector 812, one or more power modulators 814, and a power source 816. Serial interface 802 includes an equalizer 804 and a data dependent power consumer 810. Equalizer 804 includes a comparator 806 and a shift register 808, respectively.

[0110] The equalizer 804 performs equalization on the data pattern 818 and generates an equalized data pattern 820 in response thereto. Equalization reduces channel-induced impairments in high-speed serial links, such as inter-symbol interference (ISI), but not limited thereto. The equalizer 804 may be a corresponding example of a decision feedback equalizer (DFE) in the case of a receiver, or a corresponding example of a feed-forward equalizer (FFE) in the case of a transmitter. The corresponding shift register 808 of the equalizer 804 is coupled to the data pattern detector 812 to provide the equalized data pattern 820 or a portion thereof (e.g., historical symbols and current symbols, but not limited thereto) to the data pattern detector 812 and the data-dependent power consumer 810. It is noteworthy that although the data-dependent power consumer 810 is depicted as a separate box from the equalizer 804, some or all of the data-dependent power consumer 810 may be the equalizer 804 or a portion thereof.

[0111] In one or more examples, equalization taps (e.g., DFE taps, FFE taps, but not limited to) may store historical symbols, and these taps may be available, and the data pattern detector 812 may receive historical symbols of the data pattern 820 from these taps.

[0112] Data pattern detector 812 determines the data pattern state of equalized data pattern 820 as described above and generates corresponding data pattern state signal 830 to indicate the determined data pattern state. One or more power modulators 814 modulate power from power source 816 at system 800 based on corresponding data pattern state signal 830.

[0113] Fig. 9 900 is a flow chart depicting a process 900 for compensating for reduced power consumption caused by data-dependent power consumption according to one or more examples. As non-limiting examples, some or all of the operations of process 900 may be performed by device 100, system 200, device 300, device 400, device 500, device 600, or device 800.

[0114] Although the example process 900 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 900. In other examples, different components of an example device or system implementing the process 900 may perform functions substantially simultaneously or in a particular order.

[0115] According to one or more examples, process 900 includes, at operation 902 , setting a data mode state signal to a data mode state indicative of a data mode to be received by a data dependent power consumer.

[0116] According to one or more examples, process 900 includes, at operation 904 , modulating power consumption from a power source providing power to a data dependent power consumer based at least in part on the set data mode state signal.

[0117] Fig.10 1 is a flow chart depicting a process 1000 of setting a data mode state signal to a data mode state indicating a data mode to be received by a data-dependent power consumer according to one or more examples. As non-limiting examples, some or all of the operations of process 1000 may be performed by device 100, system 200, device 300, device 400, device 500, device 600, or system 800.

[0118] Although the example routines depict a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without substantially affecting the functionality of the routines. In other examples, different components of the example devices or systems implementing the routines may perform functions substantially simultaneously or in a particular order.

[0119] According to one or more examples, process 1000 includes determining a data mode state of a data mode at operation 1002 .

[0120] According to one or more examples, process 1000 includes, at operation 1004 , setting a data mode state signal to indicate a determined data mode state of a data mode.

[0121] Fig.11 1 is a flow chart depicting a process 1100 for determining a data pattern state for a data pattern based at least in part on a symbolic relationship of the data pattern according to one or more examples. As non-limiting examples, some or all of the operations of process 1100 may be performed by device 100, system 200, device 300, device 500, device 600, or device 800.

[0122] Although the example process 1100 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 1100. In other examples, different components of an example device or system implementing the process 1100 may perform functions substantially simultaneously or in a particular order.

[0123] According to one or more examples, process 1100 optionally includes determining whether the historical symbol and the current symbol are the same or different at operation 1104. The relationship between the symbols of the data pattern determined in operation 1102 can be based on the determination made in optional operation 1104. If the historical symbol and the current symbol are the same, then the relationship can be determined to be that the current symbol is the same as the historical symbol. If the historical symbol and the current symbol are different, then the relationship can be determined to be that the historical symbol is different from the current symbol.

[0124] According to one or more examples, process 1100 includes determining whether the historical symbol and the current symbol are the same or different at operation 1104 .

[0125] According to one or more examples, process 1100 optionally includes indicating, at operation 1106, a determination of a relationship between symbols used to identify the data pattern. In one or more examples, such indication can be a value in a series (e.g., a time series) of values ​​representing the relationship between the symbols. In one or more examples, a corresponding value in such a series can indicate whether the corresponding current symbol and the historical symbol are the same or different. According to one or more examples, process 1100 includes determining, at operation 1108, a data pattern state of the data pattern based at least in part on a frequency of changes in the identified relationship.

[0126] Fig.12 1 is a flow chart depicting a process 1200 of determining a data pattern state of a data pattern based at least in part on a frequency of identified relationship changes according to one or more examples. As non-limiting examples, some or all of the operations of process 1200 may be performed by device 100, system 200, device 400, device 500, device 600, or device 800.

[0127] Although the example process 1200 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 1200. In other examples, different components of an example device or system implementing the process 1200 may perform functions substantially simultaneously or in a particular order.

[0128] According to one or more examples, process 1200 includes determining, at operation 1202 , that an idle data pattern exists in response at least in part to determining that the frequency of the identified relationship changes of operation 1102 is frequency stable.

[0129] According to one or more examples, process 1200 includes determining, at operation 1204 , that an idle data pattern is present in response, at least in part, to determining that the frequency of the identified relationship change of operation 1102 is frequency modulated.

[0130] Fig.13 1 is a flow chart depicting a process 1300 for determining a data pattern state of a data pattern based on autocorrelation according to one or more examples. As non-limiting examples, some or all of the operations of process 1300 may be performed by device 100, system 200, device 400, device 500, device 600, or device 800.

[0131] Although the example process 1300 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 1300. In other examples, different components of an example device or system implementing the process 1300 may perform functions substantially simultaneously or in a particular order.

[0132] According to one or more examples, process 1300 includes, at operation 1302 , determining an autocorrelation of a data pattern.

[0133] According to one or more examples, process 1300 includes determining a data mode state based at least in part on the determined autocorrelation at operation 1304 .

[0134] Fig.14 An example process 1400 for determining a data pattern state of a data pattern based on autocorrelation according to one or more examples is illustrated. As non-limiting examples, some or all of the operations of process 1400 may be performed by device 100, system 200, device 400, device 500, device 600, or device 800.

[0135] Although the example process 1400 depicts a particular order of operations, this order may be changed without departing from the scope of the present disclosure. For example, some of the operations depicted may be performed in parallel or in a different order without materially affecting the functionality of the process 1400. In other examples, different components of an example device or system implementing the process 1400 may perform functions substantially simultaneously or in a particular order.

[0136] According to one or more examples, process 1400 includes determining, at operation 1402 , that an idle data pattern is present, at least in part in response to determining that the determined autocorrelation of operation 1302 exceeds a predetermined threshold.

[0137] According to one or more examples, process 1400 includes determining, at operation 1404 , that an idle mode state does not exist in response at least in part to determining that the determined autocorrelation of operation 1302 does not exceed a predetermined threshold.

[0138] Those of ordinary skill in the art will appreciate that the functional elements (eg, functions, operations, actions, processes or methods) of the examples disclosed herein may be implemented in any suitable hardware, software, firmware or a combination thereof. Fig.15 Non-limiting examples illustrating specific implementations of the functional elements disclosed herein. In some examples, some or all of the functional elements disclosed herein may be performed by hardware specifically designed to perform the functional elements.

[0139] Fig.15 15 is a block diagram of a circuit system 1500 that can be used to implement various functions, operations, actions, processes, or methods disclosed herein in some examples. The circuit system 1500 includes one or more processors 1502 (sometimes referred to herein as "processor 1502") that are operably coupled to one or more data storage devices 1504 (sometimes referred to herein as "storage device 1504"). The storage device 1504 includes machine executable code 1506 stored thereon, and the processor 1502 includes logic circuitry 1508. The machine executable code 1506 describes information of functional elements that can be implemented (e.g., executed) by the logic circuitry 1508. The logic circuitry 1508 is suitable for implementing (e.g., executing) the functional elements described by the machine executable code 1506. When the functional elements described by the machine executable code 1506 are executed, the circuit system 1500 should be regarded as dedicated hardware for performing the functional elements disclosed herein. In some examples, processor 1502 may execute the functional elements described by machine executable code 1506 sequentially, concurrently (eg, on one or more different hardware platforms), or in one or more parallel process flows.

[0140] When implemented by logic circuitry 1508 of processor 1502, machine executable code 1506 adapts processor 1502 to perform operations of the examples disclosed herein. By way of non-limiting example, machine executable code 1506 may adapt processor 1502 to perform some or all operations of one or more of data mode state determination, idle data pattern detection, and data dependent power compensation as described herein. By way of non-limiting example, machine executable code 1506 may adapt processor 1502 to perform some or all operations of one or more of process 900, process 1000, process 1100, process 1200, process 1300, process 1400.

[0141] Likewise, by way of non-limiting example, the machine executable code 1506 may adapt the processor 1502 to perform some or all of the features, functions, or operations disclosed herein for one or more of the device 100, the system 200, the device 300, the device 400, the device 500, the device 600, the current sink 700, or the system 800. More specifically, the features, functions, or operations disclosed herein are for one or more of the following: the data pattern detector 102, the power modulator 104, the data converter 202, the power source 204, the shift register 302, the XOR gate 304, the filter 306, the controlled current sink 308; one or more delays 402, the binary multiplier 404, the data pattern 406, the accumulator 410, the threshold detector 412; the data pattern detector 502, the multi-input AND gate 504, the controlled current sink 506 ; a first idle mode detector 602, a second idle mode detector 604, an Nth idle mode detector 606, a controlled current sink 614, a controlled current sink 616, a controlled current sink 618; a switch 702, a switch 704, a clock gating logic 708, a CMOS inverter; a serial interface 802, an equalizer 804, a comparator 806, a shift register 808, a data dependent power consumer 810, a data pattern detector 812, one or more power modulators 814 or a power source 816.

[0142] Processor 1502 may include a general-purpose processor, a special-purpose processor, a central processing unit (CPU), a microcontroller, a programmable logic controller (PLC), a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic, a discrete hardware component, other programmable devices, or any combination thereof designed to perform the functions disclosed herein. When a general-purpose computer including a processor executes a functional element corresponding to a machine executable code 1506 (e.g., software code, firmware code, hardware description) related to the examples of the present disclosure, the general-purpose computer is considered a special-purpose computer. It should be noted that a general-purpose processor (also referred to as a host processor or simply a host in this article) can be a microprocessor, but in an alternative, processor 1502 may include any conventional processor, controller, microcontroller, or state machine. Processor 1502 may also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration.

[0143] In some examples, storage device 1504 includes volatile data storage device (e.g., random access memory (RAM)), non-volatile data storage device (e.g., flash memory, hard disk drive, solid state drive, erasable programmable read-only memory (EPROM), but not limited thereto). In some examples, processor 1502 and storage device 1504 may be implemented as a single device (e.g., semiconductor device product, system on chip (SOC), but not limited thereto). In some examples, processor 1502 and storage device 1504 may be implemented as independent devices.

[0144] In some examples, machine executable code 1506 may include computer readable instructions (e.g., software code, firmware code). By way of non-limiting example, the computer readable instructions may be stored by storage device 1504, directly accessed by processor 1502, and executed by processor 1502 using at least logic circuit 1508. Also by way of non-limiting example, the computer readable instructions may be stored on storage device 1504, transferred to a memory device (not shown) for execution, and executed by processor 1502 using at least logic circuit 1508. Thus, in some examples, logic circuit 1508 includes electrically configurable logic circuit 1508.

[0145] In some examples, machine executable code 1506 may describe hardware (e.g., circuitry) to be implemented in logic circuit 1508 to perform a functional element. The hardware may be described at any of a variety of abstraction levels, from low-level transistor layout to a high-level description language. At a high level of abstraction, a hardware description language (HDL) may be used, such as an IEEE standard hardware description language (HDL). By way of non-limiting example, a S YSTEM V ERILOG TM or Very Large Scale Integration (VLSI) Hardware Description Language (VHDL).

[0146] The HDL description may be converted into a description at any of a variety of other abstraction levels as desired. As a non-limiting example, the high-level description may be converted into a logic-level description such as a register transfer language (RTL), a gate-level (GL) description, a layout-level description, or a mask-level description. As a non-limiting example, the micro-operations performed by the hardware logic circuits (e.g., gates, flip-flops, registers, but not limited thereto) of the logic circuit 1508 may be described in RTL and then converted into a GL description by a synthesis tool, and the GL description may be converted into a layout-level description by a placement and routing tool, which corresponds to the physical layout of an integrated circuit, a discrete gate or transistor logic element, a discrete hardware component, or a combination thereof of a programmable logic device. Therefore, in some examples, the machine executable code 1506 may include an HDL, RTL, GL description, a mask-level description, other hardware descriptions, or any combination thereof.

[0147] In examples where the machine executable code 1506 includes a hardware description (at any level of abstraction), a system (not shown, but including the storage device 1504) may implement the hardware description described by the machine executable code 1506. By way of non-limiting example, the processor 1502 may include a programmable logic device (e.g., an FPGA or a PLC), and the logic circuit 1508 may be electrically controlled to implement circuitry corresponding to the hardware description into the logic circuit 1508. Also by way of non-limiting example, the logic circuit 1508 may include hard-wired logic manufactured by a manufacturing system (not shown, but including the storage device 1504) according to the hardware description of the machine executable code 1506.

[0148] Regardless of whether the machine executable code 1506 includes computer readable instructions or a hardware description, the logic circuit 1508 is adapted to perform the functional elements described by the machine executable code 1506 when implementing the functional elements of the machine executable code 1506. It should be noted that although the hardware description may not directly describe the functional elements, the hardware description indirectly describes the functional elements that the hardware elements described by the hardware description are capable of performing.

[0149] As used in this disclosure, the term "module" or "component" may refer to a specific hardware implementation that performs the actions of a module or component and / or software object or software routine that may be stored on and / or executed by general-purpose hardware of a computing system (e.g., a computer-readable medium, a processing device, but not limited thereto). In some examples, the different components, modules, engines, and services described in this disclosure may be implemented as objects or processes executed on a computing system (e.g., as separate threads). Although some of the systems and methods described in this disclosure are generally described as being implemented in software (stored on and / or executed by general-purpose hardware), specific hardware implementations or combinations of software and specific hardware implementations are also possible and contemplated.

[0150] As used in this disclosure, the term "combination" referring to a plurality of elements may include any combination of all elements or various subcombinations of certain elements. For example, the phrase "A, B, C, D, or a combination thereof" may refer to any one of A, B, C, or D; a combination of each of A, B, C, and D; and any subcombination of A, B, C, or D, such as A, B, and C; A, B, and D; A, C, and D; B, C, and D; A and B; A and C; A and D; B and C; B and D; or C and D.

[0151] The terms used in this disclosure and in particular in the appended claims (e.g., the body of the appended claims, but not limited thereto) are generally intended to be "open" terms (e.g., the term "comprising" should be interpreted as "including but not limited to," the term "having" should be interpreted as "having at least," but not limited thereto). As used herein, the term "each" means "some or all." As used herein, the terms "each and every" mean "all."

[0152] Additionally, if a specific number of introduced claim expressions is intended, such intent will be expressly recited in the claim, and in the absence of such a recitation, no such intent is present. For example, as an aid to understanding, the following appended claims may include the use of the introductory phrases "at least one" and "one or more" to introduce claim expressions. However, the use of such phrases should not be construed to imply that a claim expression introduced by the indefinite article "a" or "an" will limit any particular claim containing such introduced claim expression to an example containing only one such expression, even when the same claim includes the introductory phrases "one or more" or "at least one" and an indefinite article, such as "a" or "a kind" (e.g., "a" and / or "a" may be interpreted to mean "at least one" or "one or more", but not limited to such); the same is true when a claim expression is introduced using a definite article.

[0153] Furthermore, even if a specific number of an introduced claim recitation is explicitly recited, one skilled in the art will recognize that such recitation should be interpreted as intending at least the recited number (e.g., the unmodified recitation "two recitations" without other modifiers intends at least two recitations, or two or more recitations, but is not limited thereto). Furthermore, in those instances where a convention similar to "at least one of, but not limited to, A, B, and C" or "one or more of, but not limited to, A, B, and C" is used, such constructions are generally intended to include A alone, B alone, C alone, A and B together, A and C together, B and C together, or A, B, and C together, but are not limited thereto.

[0154] In addition, any separate word or phrase presenting two or more alternative terms, whether in the specification, claims or drawings, should be understood to include the possibility of one of the terms, any one of the terms, or both of the terms. For example, the phrase "A or B" should be understood to include the possibility of "A" or "B" or "A and B".

[0155] Additional non-limiting examples include:

[0156] Embodiment 1: A device comprising: a data mode detector, the data mode detector being used to set a data mode state signal to a data mode state indicating a data mode to be received by a data-dependent power consumer; and a power modulator, the power modulator being used to set a power state of the power modulator based at least in part on the data mode state signal.

[0157] Embodiment 2: The apparatus of embodiment 1, wherein the data pattern state determined by the data pattern detector comprises the presence of an idle data pattern.

[0158] Embodiment 3: The apparatus of any one of Embodiments 1 and 2, wherein the data pattern detector comprises an autocorrelator, and the data pattern detector sets the data pattern state signal based at least in part on an output of the autocorrelator.

[0159] Embodiment 4: An apparatus according to any one of Embodiments 1 to 3, wherein the signal pattern detector comprises: an XOR gate for continuously comparing symbols presented at its input in each clock cycle and generating an output indicating the difference between the symbols; and a filter for processing the output of the XOR gate and setting the output of the filter to indicate the frequency stability of the output of the XOR gate.

[0160] Embodiment 5: According to the device described in any one of embodiments 1 to 4, the device comprises: a shift register, and the shift register is used to continuously present the sign of the data pattern to the input of the XOR gate through the action of the shift register.

[0161] Embodiment 6: The apparatus of any one of Embodiments 1 to 5, wherein the corresponding symbol of the data pattern presented to the input of the XOR gate comprises a current symbol and a historical symbol.

[0162] Embodiment 7: According to the device described in any one of embodiments 1 to 6, the device comprises: a power source, which is used to provide power to the power modulator, wherein the power consumed by the power modulator from the power source is at least partially based on the power state of the power modulator.

[0163] Embodiment 8: The apparatus of any one of Embodiments 1 to 7, wherein the power source provides power to the data dependent power consumer.

[0164] Embodiment 9: The apparatus of any one of Embodiments 1 to 8, wherein the data dependent power consumer comprises a data converter.

[0165] Embodiment 10: A device according to any one of embodiments 1 to 9, wherein the data pattern detector comprises: a multi-input AND gate; and a plurality of data pattern detectors, respective outputs of the plurality of data pattern detectors being coupled to respective inputs of the multi-input AND gate.

[0166] Embodiment 11: The apparatus of any one of Embodiments 1 to 10, wherein the power modulator comprises a current sink.

[0167] Embodiment 12: The apparatus of any one of Embodiments 1 to 11, wherein the current sink is one or more CMOS inverters.

[0168] Embodiment 13: A method, comprising: setting a data mode state signal to a data mode state indicating a data mode to be received by a data-dependent power consumer; and modulating power consumption from a power source based at least in part on the set data mode state signal, wherein the power source provides power to the data-dependent power consumer.

[0169] Embodiment 14: The method according to embodiment 13 comprises: determining a data mode state of the data mode; and setting the data mode state signal to indicate the determined data mode state of the data mode.

[0170] Embodiment 15: A method according to any one of Embodiments 13 and 14, wherein determining the data pattern state of the data pattern comprises: identifying a relationship between symbols of the data pattern; and determining the data pattern state of the data pattern based at least in part on a frequency of changes in the identified relationship.

[0171] Embodiment 16: A method according to any one of embodiments 13 to 15, wherein identifying the relationship between symbols of the data pattern comprises: determining whether a historical symbol and a current symbol are the same or different; and indicating the determination.

[0172] Embodiment 17: A method according to any one of Embodiments 13 to 16, wherein determining the data mode state of the data mode based at least in part on the frequency of the identified relationship changes includes: determining the existence of an idle data mode at least in part in response to determining that the frequency of the identified relationship changes is frequency stable.

[0173] Embodiment 18: A method according to any one of Embodiments 13 to 17, wherein determining the data mode state of the data mode based at least in part on the frequency of the identified relationship change includes: determining that an idle data mode does not exist at least in part in response to determining that the frequency of the identified relationship change is frequency modulated.

[0174] Embodiment 19: A method according to any one of Embodiments 13 to 18, wherein determining the data pattern state of the data pattern comprises: determining an autocorrelation of the data pattern; and determining the data pattern state based at least in part on the determined autocorrelation.

[0175] Embodiment 20: A method according to any one of embodiments 13 to 19, wherein determining the data pattern state based at least in part on the determined autocorrelation includes: determining the presence of an idle data pattern at least in part in response to determining that the autocorrelation of the data pattern exceeds a predetermined threshold.

[0176] Embodiment 21: A method according to any one of embodiments 13 to 20, wherein determining the data mode state based at least in part on the determined autocorrelation includes: determining that the idle mode state does not exist at least in part in response to determining that the determined autocorrelation does not exceed the predetermined threshold.

[0177] Embodiment 22: A system, comprising: a serial interface, the serial interface comprising multiple channels and multiple data-dependent power consumers; a power source, the power source being used to provide power to the multiple data-dependent power consumers; multiple data mode detectors, the multiple data mode detectors being used to set corresponding data mode state signals to data mode states indicating data modes received at corresponding channels among the multiple channels of the serial interface; and one or more power modulators, the one or more power modulators being used to set the power consumed by the one or more power modulators from the power source based at least in part on the data mode state signals.

[0178] Although the present disclosure describes the present invention with respect to certain illustrative examples, those of ordinary skill in the art will recognize and understand that the present invention is not so limited. Rather, many additions, deletions, and modifications may be made to the illustrative examples and the examples described without departing from the scope of the present invention as claimed below and its legal equivalents. Furthermore, features from one example may be combined with features from another example while still being included within the scope of the present invention as contemplated by the inventor.

Claims

1. A device, comprising: a data mode detector for setting a data mode state signal to a data mode state indicative of a data mode to be received by the data dependent power consumer; and A power modulator is configured to set a power state of the power modulator based at least in part on the data mode state signal.

2. The apparatus of claim 1, wherein the data pattern state determined by the data pattern detector comprises the presence of an idle data pattern.

3. The apparatus of claim 1, wherein the data pattern detector comprises an autocorrelator, and wherein the data pattern detector sets the data pattern state signal based at least in part on an output of the autocorrelator.

4. The apparatus of claim 1, wherein the data pattern detector comprises: an XOR gate for continuously comparing the symbols presented at its inputs at each clock cycle and generating an output indicative of a difference between the symbols; and A filter is provided for processing the output of the XOR gate and setting the output of the filter to indicate the frequency stability of the output of the XOR gate.

5. The device according to claim 4, comprising: A shift register for successively presenting the sign of the data pattern to the input of the XOR gate via action of the shift register.

6. The apparatus of claim 5, wherein the corresponding symbols of the data pattern presented to the input of the XOR gate include a current symbol and a historical symbol.

7. The device according to claim 1, comprising: A power source is provided for providing power to the power modulator, wherein the power consumed by the power modulator from the power source is based at least in part on the power state of the power modulator.

8. The apparatus of claim 7, wherein the power source provides power to the data dependent power consumer.

9. The apparatus of claim 8, wherein the data dependent power consumer comprises a data converter.

10. The apparatus of claim 1, wherein the data pattern detector comprises: Multi-input AND gate; and A plurality of data pattern detectors, respective outputs of the plurality of data pattern detectors being coupled to respective inputs of the multi-input AND gate.

11. The apparatus of claim 1, wherein the power modulator comprises a current sink.

12. The apparatus of claim 11, wherein the current sink comprises one or more CMOS inverters.

13. A method comprising: setting a data mode state signal to a data mode state indicative of a data mode to be received by the data dependent power consumer; as well as Power consumption from a power source is modulated based at least in part on the set data mode state signal, wherein the power source provides power to the data dependent power consumer.

14. The method according to claim 13, comprising: determining the data mode state of the data mode; as well as The data mode state signal is set to indicate the determined data mode state of the data mode.

15. The method of claim 14, wherein determining the data mode state of the data mode comprises: identifying relationships between symbols of the data pattern; as well as The data pattern state of the data pattern is determined based at least in part on a frequency of the identified relationship changes.

16. The method of claim 15, wherein identifying the relationship between symbols of the data pattern comprises: Determine whether the historical symbol and the current symbol are the same or different; as well as The determination is indicated.

17. The method of claim 15, wherein determining the data pattern state of the data pattern based at least in part on the frequency of the identified relationship changes comprises: The presence of an idle data pattern is determined at least in part in response to determining that the frequency of the identified relationship change is frequency stable.

18. The method of claim 15, wherein determining the data pattern state of the data pattern based at least in part on the frequency of the identified relationship changes comprises: An absence of an idle data pattern is determined at least in part in response to determining that the frequency of the identified relationship change is frequency modulated.

19. The method of claim 14, wherein determining the data mode state of the data mode comprises: determining an autocorrelation of the data pattern; as well as The data mode state is determined based at least in part on the determined autocorrelation.

20. The method of claim 19, wherein determining the data mode state based at least in part on the determined autocorrelation comprises: The presence of an idle data pattern is determined at least in part in response to determining that the autocorrelation of the data pattern exceeds a predetermined threshold.

21. The method of claim 20, wherein determining the data mode state based at least in part on the determined autocorrelation comprises: An absence of an idle mode state is determined at least in part in response to determining that the determined autocorrelation does not exceed the predetermined threshold.

22. A system, comprising: a serial interface comprising a plurality of channels and a plurality of data dependent power consumers; a power source for providing power to the plurality of data dependent power consumers; a plurality of data pattern detectors for setting respective data mode state signals to data mode states indicative of data patterns received at respective ones of the plurality of lanes of the serial interface; and One or more power modulators configured to set power consumed by the one or more power modulators from the power source based at least in part on the data mode status signal.

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