Method and device for generating code, electronic equipment and program product

Abstract

The embodiment of the invention provides a method and device for generating codes, electronic equipment and a program product. The method includes generating a multi-layer intermediate representation of source code based on the source code of a target language. The method further includes generating a low-level virtual machine intermediate representation of the source code based on the multi-level intermediate representation. The method further comprises the step of generating an executable file package of the target language in response to the situation that the low-layer virtual machine intermediate representation meets a preset condition. In addition, the method also includes regenerating a multi-layer intermediate representation of the source code in response to the low-layer virtual machine intermediate representation not satisfying the predetermined condition. According to the embodiment of the invention, through the backtraceable iterative compiling process, the process which does not meet the preset condition in the compiling process can be adjusted in time, so that the compiling cost is reduced, and the development efficiency of developers is improved.

Description

Technical Field

[0001] The present disclosure relates generally to the field of computers, and more particularly, to methods, apparatuses, electronic devices, and program products for generating codes. Background Art

[0002] Both Multi-Level Intermediate Representation (MLIR) and Low-Level Virtual Machine Intermediate Representation (LLVM-IR) enhance the efficiency and flexibility of compilers, promote code optimization and cross-platform compatibility, and are important technologies in modern software development and high-performance computing. The multi-level intermediate representation in the compilation process is a high-level abstraction concept that aims to simplify and unify program representation and optimization across multiple levels of abstraction. It allows developers to operate at different levels of abstraction, from high-level function call graphs to low-level instruction sequences, thereby achieving more sophisticated code optimization.

[0003] The low-level virtual machine intermediate representation is a core component of the LLVM compiler infrastructure. It is a statically typed, control-flow-oriented intermediate language used to represent the intermediate state of the compilation process. It can be optimized at compile time, link time, load time, and even runtime, and converted into native code for the target machine. The design of the low-level virtual machine intermediate representation complements the multi-layer intermediate representation, and together they provide strong support for efficient code generation and optimization of the compiler. Summary of the invention

[0004] Embodiments of the present disclosure provide a method, an apparatus, an electronic device, and a program product for generating codes.

[0005] According to a first aspect of the present disclosure, a method for generating code is provided. The method includes generating a multi-layer intermediate representation of the source code based on the source code of the target language. The method also includes generating a low-level virtual machine intermediate representation of the source code based on the multi-layer intermediate representation. The method also includes generating an executable file package in the target language in response to the low-level virtual machine intermediate representation satisfying a predetermined condition. In addition, the method also includes regenerating the multi-layer intermediate representation of the source code in response to the low-level virtual machine intermediate representation not satisfying the predetermined condition.

[0006] In a second aspect of the present disclosure, a device for generating code is provided. The device includes a multi-layer intermediate representation generating device, which is configured to generate a multi-layer intermediate representation of the source code based on the source code of the target language. The device also includes a low-level virtual machine intermediate representation generating module, which is configured to generate a low-level virtual machine intermediate representation of the source code based on the multi-layer intermediate representation. The device also includes an executable file package generating module, which is configured to generate an executable file package in the target language in response to the low-level virtual machine intermediate representation satisfying a predetermined condition. In addition, the device also includes a multi-layer intermediate representation regeneration module, which is configured to regenerate the multi-layer intermediate representation of the source code in response to the low-level virtual machine intermediate representation not satisfying the predetermined condition.

[0007] In a third aspect of the present disclosure, an electronic device is provided, comprising a processor and a memory coupled to the processor, wherein the memory has instructions stored therein, and when the instructions are executed by the processor, the electronic device executes the method according to the first aspect.

[0008] In a fourth aspect of the present disclosure, a computer program product is provided, on which computer executable instructions are stored, wherein the computer executable instructions are executed by a processor to implement the method of the first aspect.

[0009] The purpose of this Summary is to introduce a selection of concepts in a simplified form that are further described in the Detailed Description below. This Summary is not intended to identify key features or essential features of the claimed subject matter, nor is it intended to limit the scope of the claimed subject matter. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] The above and other features, advantages and aspects of the embodiments of the present disclosure will become more apparent with reference to the following detailed description in conjunction with the accompanying drawings. In the accompanying drawings, the same or similar reference numerals represent the same or similar elements, wherein:

[0011] Figure 1 A schematic diagram illustrating an example environment in which some embodiments of the present disclosure may be implemented;

[0012] Figure 2 A flowchart of a method for generating code according to some embodiments of the present disclosure is shown;

[0013] Figure 3 A schematic diagram showing a process for generating an executable file package according to some embodiments of the present disclosure is shown;

[0014] Figure 4 A schematic diagram showing a compilation process for performing bidirectional deduction in the process of generating target code according to some embodiments of the present disclosure;

[0015] Figure 5A block diagram showing an apparatus for generating code according to some embodiments of the present disclosure; and

[0016] Figure 6 A block diagram of an electronic device according to some embodiments of the present disclosure is shown.

[0017] Throughout the drawings, the same or similar reference numbers denote the same or similar elements. DETAILED DESCRIPTION

[0018] It is understandable that the data involved in this technical solution (including but not limited to the data itself, the acquisition or use of the data) shall comply with the requirements of relevant laws, regulations and relevant provisions.

[0019] Embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although some embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be construed as being limited to the embodiments described herein, but rather these embodiments are provided for a more thorough and complete understanding of the present disclosure. It should be understood that the drawings and embodiments of the present disclosure are only for exemplary purposes and are not intended to limit the scope of protection of the present disclosure.

[0020] In the description of the embodiments of the present disclosure, the term "including" and similar terms should be understood as open inclusion, that is, "including but not limited to". The term "based on" should be understood as "based at least in part on". The term "one embodiment" or "the embodiment" should be understood as "at least one embodiment". The terms "first", "second", etc. may refer to different or the same objects, unless explicitly stated. Other explicit and implicit definitions may also be included below.

[0021] As mentioned above, multi-layer intermediate representation and low-level virtual machine intermediate representation play an extremely important role in the compilation process. In related technologies, the compilation process usually follows a linear, one-way execution mode, which means that the compilation process can only be carried out in a predetermined order, from source code analysis, syntax parsing, semantic analysis, to the generation of target code. This process is particularly evident in the conversion from multi-layer intermediate representation to low-level virtual machine intermediate representation. When the compiler converts from multi-layer intermediate representation to low-level virtual machine intermediate representation, it will perform a series of checks and verifications on the generated low-level virtual machine intermediate representation to ensure the correctness and efficiency of the code.

[0022] However, if an error is found at this stage, the traditional approach is to stop the entire compilation process and not try to "backtrack" or "reverse" the error, that is, not try to go back to the multi-layer intermediate representation level to correct the problem and then re-convert it. Instead, the entire compilation process needs to be re-executed from the beginning, starting with source code analysis until the entire compilation process is completed. Although this approach can ensure the quality and reliability of the executable file, it undoubtedly increases the cost of compilation. Moreover, it is not convenient for developers to debug flexibly, which reduces the development efficiency of developers.

[0023] According to an embodiment of the present disclosure, a multi-layer intermediate representation is generated by analyzing the source code of the target language. Then, based on the generated multi-layer intermediate representation, a low-level virtual machine intermediate representation of the source code is further generated to lay the foundation for the subsequent compilation and execution process. After the low-level virtual machine intermediate representation is generated, it is verified to ensure that it can meet the predetermined conditions (such as optimization conditions). If the generated low-level virtual machine intermediate representation meets the predetermined conditions, the executable file package can continue to be generated. If the generated low-level virtual machine intermediate representation cannot meet the predetermined conditions, it will return to the generation stage of the multi-layer intermediate representation and re-iterate the process to further optimize the compilation process.

[0024] Through this traceable continuous iteration and optimization process, it is eventually possible to generate a low-level virtual machine intermediate representation that meets the predetermined conditions, and then generate an executable file package in the target language. This not only ensures the efficient operation and reliability of the program, but also reduces the compilation cost and improves the development efficiency of developers.

[0025] Figure 1 1 is a schematic diagram of an example environment 100 in which some embodiments of the present disclosure may be implemented. Figure 1 As shown, the compilation process is the process of converting a high-level language source code 110 (e.g., Python language) into a low-level language (usually a machine language or assembly language) so that the computer hardware can directly execute it. During the compilation process, the front end of the compiler mainly focuses on the analysis and conversion of the source code 110. It is responsible for reading the source code, performing lexical analysis, syntax analysis, semantic analysis, etc., until an intermediate representation (e.g., a multi-layer intermediate representation 130 and / or a low-level virtual machine intermediate representation 140) is generated. The back end of the compiler mainly focuses on how to convert the intermediate representation into a target code 150, which is also called a target machine code.

[0026] like Figure 1As shown, source code 110 is a human-readable program text written by a programmer using a certain high-level programming language. The process of converting source code 110 into an abstract syntax tree (AST) 120 usually occurs in the front-end analysis stage of a compiler or interpreter. The abstract syntax tree is a tree structure in which the nodes represent various syntax elements in the source code, such as variable declarations, function calls, loop structures, etc.

[0027] refer to Figure 1 , during the compilation process, involves converting the abstract syntax tree 120 into an intermediate representation. The intermediate representation is an internal representation used for optimization and analysis during the compilation process. The compiler can generate one or more intermediate representations for deeper analysis and optimization. For example, a common intermediate representation is a three-address code, which simplifies complex expressions into a sequence of simple instructions, each with a maximum of three operands. There are other types of intermediate representations, such as SSA (static single assignment) form, which helps eliminate duplicate calculations and optimize control flow.

[0028] like Figure 1 As shown, the abstract syntax tree 120 can be first converted into a multi-layer intermediate representation 130, and then converted into a low-level virtual machine intermediate representation 140 that is closer to the target code. The existence of the multi-layer intermediate representation 130 can enable the compiler to gradually refine the source code 110, which is a representation that gradually descends from high-level abstraction to close to the target machine. The multi-layer intermediate representation 130 can encapsulate multiple domain dialects (Dialects), which are designed to optimize the compilation process. For example, the Linalg domain dialect can be encapsulated, which is specially designed to represent and optimize linear algebra and array operations. In the multi-layer intermediate representation 130, multiple domain dialects can be converted to each other, that is, from one domain dialect to another, thereby helping the compiler to implement a pipeline process from high-level abstraction to low-level hardware optimization. The domain dialect specifically encapsulated in the multi-layer intermediate representation 130 can be specifically determined according to the specific compilation and optimization tasks.

[0029] Continue to refer Figure 1 , unlike the multi-layer intermediate representation 130, the low-level virtual machine intermediate representation 140 is closer to the machine language, and still maintains a certain degree of independence, and can achieve cross-platform execution. For example, the Java compiler generates bytecode, which is a low-level intermediate representation that can be interpreted and executed by the Java virtual machine (JVM) or further compiled into local machine code. It can be understood that the multi-layer intermediate representation and low-level virtual machine intermediate representation mentioned in this article are both an intermediate representation, which is a narrow concept. For example, the abstract syntax tree is also a broad multi-layer intermediate representation.

[0030] Continue to refer Figure 1 After the source code 110 is converted into an abstract syntax tree 120, and then converted into a multi-layer intermediate representation 130 and then into a low-level virtual machine intermediate representation 140, the low-level virtual machine intermediate representation 140 can be checked and verified to determine whether the entire compilation process has reached the predetermined compilation target or predetermined conditions. For example, if a developer wants to generate a low-level virtual machine intermediate representation of a target code for a certain hardware platform, some hardware information is required. However, during the compilation process, this hardware information is lost, and then the compilation process does not reach the predetermined compilation conditions. At this time, the low-level virtual machine intermediate representation 140 can be traced back to the multi-layer intermediate representation 130 through 162 for verification and inspection. If it is found that the predetermined optimization conditions are still not met, the abstract syntax tree 120 can be traced back through 164 for inspection and verification analysis to regenerate the multi-layer intermediate representation 130 of the source code 110, and then the compilation process is repeated in sequence. If the generated low-level virtual machine intermediate representation 140 meets the predetermined compilation conditions after verification and inspection, the target code 150 can be generated with the help of the low-level virtual machine intermediate representation 140.

[0031] Through this continuous iteration and optimization compilation process including the backtracking mechanism, it is finally possible to generate a low-level virtual machine intermediate representation that meets the predetermined conditions, and then generate an executable file package based on it. This process not only ensures the efficient operation and reliability of the program, but also effectively reduces the compilation cost, thereby improving the development efficiency of developers.

[0032] The following will combine Figures 2 to 6 The process according to the embodiment of the present disclosure is described in detail. For ease of understanding, the specific data mentioned in the following description are exemplary and are not intended to limit the scope of protection of the present disclosure. It is understood that the embodiments described below may also include additional actions not shown and / or the actions shown may be omitted, and the scope of the present disclosure is not limited in this respect.

[0033] Figure 2 FIG. 2 is a flowchart of a method 200 for generating code according to some embodiments of the present disclosure. Figure 2 , method 200 includes box 202, box 204, box 206 and box 208. The execution subject of method 200 may be a device for generating code, and the device may be a server, such as a computing system, a single server, a distributed server, or a system of servers configured in the cloud, or an independent device or system. The device may be implemented in software and / or hardware. The method 200 will be described below with the execution subject being a device for generating code.

[0034] In block 202, a multi-layer intermediate representation of the source code is generated based on the source code of the target language. Figure 1, source code 110 is a human-readable program text written by a programmer using a certain high-level programming language. For example, it can be a source code with Python as the target language. In some embodiments, source code 110 is a code that can be used to describe the process orchestration code of the orchestration process and the process node of the task in the orchestration process, and these codes describe the user-defined orchestration process. In order to compile source code 110 into target code 150 to be suitable for machine recognition and operation, source code 110 can be first converted into an intermediate representation for deeper analysis and optimization. For example, it can be first converted into a multi-layer intermediate representation 130, which is usually closer to machine language than source code, but still maintains a certain level of abstraction, so that the rules of conversion optimization can be more universal.

[0035] In block 204, a low-level virtual machine intermediate representation of the source code is generated based on the multi-layer intermediate representation. Figure 1 After lowering the abstraction level through the multi-layer intermediate representation 130, the multi-layer intermediate representation 130 can be further converted into a low-level virtual machine intermediate representation 140, because it is closer to the code structure of the target machine and also contains more information related to the target architecture. This enables the compiler to optimize for different target architectures, thereby improving the running efficiency of the program.

[0036] In block 206, in response to the low-level virtual machine intermediate representation satisfying a predetermined condition, an executable file package in the target language is generated. Figure 1 When the generated low-level virtual machine intermediate representation 140 meets the predetermined optimization conditions, the low-level virtual machine intermediate representation 140 can then be smoothly converted into a target code 150, and then an executable file package can be generated. In some embodiments, it can be an executable file package related to a platform (such as x86, etc.).

[0037] In block 208, in response to the low-level virtual machine intermediate representation not satisfying the predetermined condition, the multi-layer intermediate representation of the source code is regenerated. Figure 1 If the generated low-level virtual machine intermediate representation 140 does not meet the predetermined optimization conditions, then the multi-layer intermediate representation 130 from which the low-level virtual machine intermediate representation 140 is derived will be traced back, and the multi-layer intermediate representation 130 will be regenerated, so that the compilation process can continue in a cyclical reciprocating manner until the generated low-level virtual machine intermediate representation 140 meets the predetermined optimization conditions.

[0038] In this embodiment, a multi-layer intermediate representation is generated by analyzing the source code of the target language. Then, based on the generated multi-layer intermediate representation, a low-level virtual machine intermediate representation of the source code is further generated to lay the foundation for the subsequent compilation and execution process. After the low-level virtual machine intermediate representation is generated, it is verified to ensure that it can meet the predetermined conditions. If the generated low-level virtual machine intermediate representation meets the predetermined conditions, the executable file package can continue to be generated. If the generated low-level virtual machine intermediate representation cannot meet the predetermined conditions, it will return to the generation stage of the multi-layer intermediate representation and repeat the process to further adjust the compilation process.

[0039] Through this traceable continuous iteration and optimization process, it is eventually possible to generate a low-level virtual machine intermediate representation that meets the predetermined conditions, and then generate an executable file package in the target language. This not only ensures the efficient operation and reliability of the program, but also reduces the compilation cost and improves the development efficiency of developers.

[0040] Figure 3 FIG. 3 is a schematic diagram of a process 300 for generating an executable file package according to some embodiments of the present disclosure. Figure 3 In the data structure 310, the serialized file 312 in the middle layer of the front end and the back end is obtained. In some embodiments, the orchestration process expressed by the user through the front-end canvas can be stored in the data structure of the middle layer in a digital and serialized form. For example, data in JSON format can be stored in the BFF (Backend for Frontends) data structure, where BFF is a backend service designed specifically for the front end. As an middle layer, it can process and convert data to adapt to different system components.

[0041] Continue to refer Figure 3 , the serialized files 312 obtained from the middle layer of the front end and the back end are converted into the process orchestration code 322 and process node code 324 of the target language (for example, Python). For example, the serialized files in JSON format can be converted into the process orchestration code 322 and process node code 324 presented in Python language, so that the generated process orchestration code 322 and process node code 324 can form an orchestration paradigm 320, thereby ensuring that the corresponding generated code is credible. In some embodiments, in the process of generating the orchestration paradigm 320, the generated code can also be optimized, thereby ensuring that the generated code is executable.

[0042] like Figure 3As shown, in order to make effective use of the generated code, the generated code needs to be compiled into a machine language that can be recognized and run by the machine. During the compilation process, in order to optimize the compilation process as much as possible, thereby improving the efficiency of the compilation, the generated target language code can be first converted into a multi-layer intermediate representation 332. In some embodiments, a variety of different domain dialects can be encapsulated in the multi-layer intermediate representation 332, and these different domain dialects can be converted into each other according to the rules defined by the developer to achieve the purpose of optimizing the compilation process. By converting the source code into part of the compilation process of the multi-layer intermediate representation, the compiler can separate the stages of source code parsing, optimization and target code generation, and each layer of the intermediate representation can represent different levels of abstraction. In addition, it can also enable the compiler to independently develop and optimize the various parts of the multi-layer intermediate representation, thereby improving modularity and maintainability.

[0043] Continue to refer Figure 3 Although the multi-layer intermediate representation 332 can represent various levels of abstraction from high-level language features to low-level machine instructions, it usually does not directly generate machine code, but needs to rely on the low-level virtual machine intermediate representation 334 or other backends to complete this process. In some embodiments, tools such as the Clang compiler front end, LLVMLinker, and LLVM Assembler can be used to convert the multi-layer intermediate representation 332 into a low-level virtual machine intermediate representation 334, so that the code can be easily integrated into the existing build and deployment process, so that cross-platform execution can be achieved with the help of LLVM.

[0044] In order to more clearly describe the bidirectional derivation compilation process of the present disclosure with excellent reduction in compilation cost to generate low-level virtual machine intermediate representation, the following will be combined with Figure 4 describe. Figure 4 FIG. 4 is a schematic diagram showing a compilation process 400 for performing bidirectional deduction in the process of regenerating target code according to some embodiments of the present disclosure. Figure 4 As shown, source code 410 describes in Python the method for printing all numbers in the Fibonacci sequence that are less than a given value n (n=1000). During the compilation process, an abstract syntax tree 420 can then be gradually constructed. Before constructing the abstract syntax tree 420, the source code 410 can be subjected to lexical analysis and grammatical analysis. After lexical analysis (also called scanning), which converts the source code character stream into a series of meaningful tokens, Table 1 can be obtained:

[0045]

[0046]

[0047] Continue to refer Figure 4Then, after lexical analysis, syntax analysis (also called parsing) can be performed, the purpose of which is to check whether the token sequence conforms to the grammatical specification of the language and construct a syntax tree, usually an abstract syntax tree. The abstract syntax tree 420 is a tree-shaped data structure that ignores irrelevant details in the source code and only retains its grammatical structure. Based on the above code, the general structure of the abstract syntax tree 420 is as follows:

[0048]

[0049] Among them, each node type such as FunctionDef, Assign, While, Expr, Call, BinOp, etc. corresponds to a specific grammatical structure identified in the grammatical analysis. Here, Module is the root node of the entire abstract syntax tree 420, which contains all top-level statements. The FunctionDef node represents a function definition, the Assign node represents an assignment statement, the While node represents a loop structure, and the Expr node is usually used to represent an expression statement, such as a function call. The Call node represents a function call, the BinOp node represents a binary operation (such as addition), and the Compare node represents a comparison operation. In the Python language, the abstract syntax tree of the source code can be directly obtained.

[0050] Continue to refer Figure 4 In some embodiments, after the abstract syntax tree 420 of the source code 410 is generated, it is necessary to perform other important analyses on the source code 420, namely type checking 430. Type checking 430 can ensure the type safety and consistency of the program, thereby preventing some errors that may occur during the operation of the program code, such as preventing illegal operations such as trying to add a string and an integer. In some embodiments, the abstract syntax tree 420 can be traversed to check variable declarations, function definitions, type consistency, etc., and the abstract syntax tree 420 can also be annotated to add type information and other metadata. For example, for "a, b = 0, 1", variables a and b are declared and initialized as integers. The type checker will record that the types of a and b are int. For "a, b = b, a + b", it will be checked whether the type of b is consistent with the type of a, and whether the operation of a + b is legal. Because a and b are both integers, there is no problem with addition. In some embodiments, when the type check 430 is correct, the abstract syntax tree 420 can be converted into a multi-layer intermediate representation at 440. This separation of type checking from code transformation allows each part of the compiler to focus on its own task, thereby increasing the flexibility of the compiler.

[0051] Continue to refer Figure 4In some embodiments, the multi-layer intermediate representation can be optimized from dialect A to dialect B, and then to dialect C. Among them, dialect A can be the representation closest to the source code, retaining the original structure and semantics of the source code, and can therefore be used for preliminary syntax analysis and semantic checking. Dialect B can be a domain dialect that focuses more on improving code execution efficiency and resource consumption, and dialect C can be a domain dialect that is closer to the target machine code, which ensures that the final generated code is suitable for the target platform. Developers can select and optimize domain dialects according to their development needs. In this way, professional programmers can write high-performance code in an intuitive, advanced, and familiar way.

[0052] Continue to refer Figure 4 As shown, as described above, in order to make the multi-layer intermediate representation closer to the machine language, the multi-layer intermediate representation can be converted into the low-level virtual machine intermediate representation at 450. In this way, after the converted low-level virtual machine intermediate representation is checked and verified to be qualified, the converted low-level virtual machine intermediate representation can be converted into the target code required by the developer at 460. If it is found through verification and inspection that the converted low-level virtual machine intermediate representation does not meet the expected requirements or predetermined conditions, the multi-layer intermediate representation of the low-level virtual machine intermediate representation can be re-derived by tracing back to 440 at 470, so as to regenerate a new abstract syntax tree and multi-layer intermediate representation about the source code 410 by performing type checking on the syntax tree 420 again at 430 at 480, so as to convert it into a new low-level virtual machine intermediate representation again at 450 for verification. If the verification result still does not meet the predetermined conditions, the process of generating the multi-layer intermediate representation can be iterated again until the generated low-level virtual machine intermediate representation meets the predetermined conditions.

[0053] Through this multi-layer static bidirectional compilation method, dynamic languages ​​​​(such as Python) can be converted into (C / Rust-like) static languages ​​​​and static inference can be achieved without using any runtime type information, eliminating the overhead of interpreted execution, reducing the pre-compilation AOT (Ahead-of-Time) time, and improving the overall compilation performance.

[0054] return Figure 3When the generated low-level virtual machine intermediate representation meets the predetermined conditions, the low-level virtual machine intermediate representation that meets the predetermined conditions can be converted into an executable file, for example, a native file can be directly generated to directly implement cross-platform operation at 340. In some embodiments, the low-level virtual machine intermediate representation that meets the predetermined conditions can also generate an orchestration process file package 336 related to the orchestration process. For example, if the orchestration process is presented in Python language, a Python package can be generated, and then a third-party package of Python can be combined at 340 to implement cross-platform execution. In some embodiments, if the generated low-level virtual machine intermediate representation does not meet the predetermined optimization conditions, it can be retraced to the multi-layer intermediate representation 332 through 338 to re-iterate compilation.

[0055] Through this traceable continuous iteration and optimization process, it is eventually possible to generate a low-level virtual machine intermediate representation that meets the predetermined conditions, and then generate an executable file package in the target language. This not only ensures the efficient operation and reliability of the program, but also reduces the compilation cost and improves the development efficiency of developers.

[0056] Figure 5 FIG. 5 is a block diagram of an apparatus 500 for generating code according to some embodiments of the present disclosure. Figure 5 As shown, the apparatus 500 includes a multi-layer intermediate representation generation module 502, which is configured to generate a multi-layer intermediate representation of the source code based on the source code of the target language. The apparatus 500 also includes a low-level virtual machine intermediate representation generation module 504, which is configured to generate a low-level virtual machine intermediate representation of the source code based on the multi-layer intermediate representation. The apparatus 500 also includes an executable file package generation module 506, which is configured to generate an executable file package in the target language in response to the low-level virtual machine intermediate representation satisfying a predetermined condition. In addition, the apparatus 500 also includes a multi-layer intermediate representation regeneration module 508, which is configured to regenerate the multi-layer intermediate representation of the source code in response to the low-level virtual machine intermediate representation not satisfying the predetermined condition.

[0057] In some embodiments, the multi-layer intermediate representation generation module 502 includes: a first generation module, configured to generate an abstract syntax tree corresponding to the source code based on the source code, the abstract syntax tree being a tree representation of the source code; and a second generation module, configured to generate a multi-layer intermediate representation of the source code based on the abstract syntax tree.

[0058] In some embodiments, the second generation module includes: a first determination module, traversing and checking the types of nodes in the abstract syntax tree to determine the check result of the abstract syntax tree; and a first derivation module, configured to derive a multi-layer intermediate representation corresponding to the source code layer by layer in response to the determined check result of the abstract syntax tree being correct.

[0059] In some embodiments, the first derivation module includes: a second derivation module, configured to derive a first layer of intermediate representation of the multi-layer intermediate representation from the abstract syntax tree; and a third derivation module, configured to derive a second layer of intermediate representation of the multi-layer intermediate representation from the first layer of intermediate representation of the multi-layer intermediate representation.

[0060] In some embodiments, the low-level virtual machine intermediate representation generation module 504 includes: a third generation module generates a low-level virtual machine intermediate representation based on the second-level intermediate representation of the multi-level intermediate representation.

[0061] In some embodiments, the executable file package generation module 506 includes: a fourth generation module, configured to generate machine code corresponding to the source code based on the low-level virtual machine intermediate representation; and a fifth generation module, configured to generate an executable file package based on the machine code.

[0062] In some embodiments, the multi-layer intermediate representation regeneration module 508 includes: a backtracking module, configured to backtrack to the abstract syntax tree in response to the low-level virtual machine intermediate representation not satisfying a predetermined condition; and a sixth generation module, configured to regenerate the multi-layer intermediate representation of the source code based on the abstract syntax tree.

[0063] In some embodiments, the apparatus 500 further includes: an acquisition module configured to acquire an orchestration process drawn by a user on a canvas of a graphical user interface; and a seventh generation module configured to generate source code in a target language based on the orchestration process, wherein the source code includes a process orchestration code representing process semantics and a process node code representing a task in the orchestration process.

[0064] In some embodiments, the seventh generation module further includes a second determination module configured to determine a serialization file corresponding to the orchestration process based on the orchestration process; and an eighth generation module configured to generate source code in a target language based on the serialization file.

[0065] Figure 6 1 is a block diagram of an electronic device 600 of some embodiments of the present disclosure, and the device 600 may be a device or apparatus described in the embodiments of the present disclosure. Figure 6As shown, the device 600 includes a central processing unit (CPU) and / or a graphics processing unit (GPU) 601, which can perform various appropriate actions and processes according to computer program instructions stored in a read-only memory (ROM) 602 or loaded from a storage unit 608 to a random access memory (RAM) 603. In the RAM 603, various programs and data required for the operation of the device 600 can also be stored. The CPU / GPU 601, the ROM 602, and the RAM 603 are connected to each other via a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604. Although not shown in FIG. Figure 6 As shown in FIG. 6 , device 600 may also include a co-processor.

[0066] A number of components in the device 600 are connected to the I / O interface 605, including: an input unit 606, such as a keyboard, a mouse, etc.; an output unit 607, such as various types of displays, speakers, etc.; a storage unit 608, such as a disk, an optical disk, etc.; and a communication unit 609, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0067] The various methods or processes described above may be performed by the CPU / GPU 601. For example, in some embodiments, the methods may be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as a storage unit 608. In some embodiments, part or all of the computer program may be loaded and / or installed on the device 600 via the ROM 602 and / or the communication unit 609. When the computer program is loaded into the RAM 603 and executed by the CPU / GPU 601, one or more steps or actions in the methods or processes described above may be performed.

[0068] In some embodiments, the methods and processes described above may be implemented as a computer program product. The computer program product may include a computer-readable storage medium carrying computer-readable program instructions for executing various aspects of the present disclosure.

[0069] Computer readable storage medium can be a tangible device that can hold and store instructions used by an instruction execution device. Computer readable storage medium can be, for example, but not limited to, an electrical storage device, a magnetic storage device, an optical storage device, an electromagnetic storage device, a semiconductor storage device, or any suitable combination thereof. More specific examples (non-exhaustive list) of computer readable storage medium include: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a static random access memory (SRAM), a portable compact disk read-only memory (CD-ROM), a digital versatile disk (DVD), a memory stick, a floppy disk, a mechanical encoding device, for example, a punch card or a convex structure in a groove on which instructions are stored, and any suitable combination thereof. The computer readable storage medium used here is not interpreted as a transient signal itself, such as a radio wave or other freely propagating electromagnetic wave, an electromagnetic wave propagated by a waveguide or other transmission medium (for example, a light pulse by an optical fiber cable), or an electrical signal transmitted by a wire.

[0070] The computer-readable program instructions described herein can be downloaded from a computer-readable storage medium to each computing / processing device, or downloaded to an external computer or external storage device via a network, such as the Internet, a local area network, a wide area network, and / or a wireless network. The network can include copper transmission cables, optical fiber transmissions, wireless transmissions, routers, firewalls, switches, gateway computers, and / or edge servers. The network adapter card or network interface in each computing / processing device receives the computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in the computer-readable storage medium in each computing / processing device.

[0071] The computer program instructions for performing the disclosed operation may be assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source code or object code written in any combination of one or more programming languages, programming languages ​​including object-oriented programming languages, and conventional procedural programming languages. Computer-readable program instructions may be executed completely on a user's computer, partially on a user's computer, executed as an independent software package, partially on a user's computer, partially on a remote computer, or completely on a remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., utilizing an Internet service provider to connect via the Internet). In certain embodiments, by utilizing the state information of a computer-readable program instruction to customize an electronic circuit, such as a programmable logic circuit, a field programmable gate array (FPGA), or a programmable logic array (PLA), the electronic circuit may execute a computer-readable program instruction, thereby realizing various aspects of the present disclosure.

[0072] These computer-readable program instructions can be provided to a processing unit of a general-purpose computer, a special-purpose computer, or other programmable data processing device, thereby producing a machine, so that when these instructions are executed by the processing unit of the computer or other programmable data processing device, a device that implements the functions / actions specified in one or more boxes in the flowchart and / or block diagram is generated. These computer-readable program instructions can also be stored in a computer-readable storage medium, and these instructions cause the computer, programmable data processing device, and / or other equipment to work in a specific manner, so that the computer-readable medium storing the instructions includes a manufactured product, which includes instructions for implementing various aspects of the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0073] Computer-readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other device so that a series of operating steps are performed on the computer, other programmable data processing apparatus, or other device to produce a computer-implemented process, thereby causing the instructions executed on the computer, other programmable data processing apparatus, or other device to implement the functions / actions specified in one or more boxes in the flowchart and / or block diagram.

[0074] The flow chart and block diagram in the accompanying drawings show the possible architecture, function and operation of the equipment, method and computer program product according to multiple embodiments of the present disclosure. In this regard, each frame in the flow chart or block diagram can represent a part of a module, program segment or instruction, and a part of the module, program segment or instruction includes one or more executable instructions for realizing the specified logical function. In some alternative implementations, the function marked in the frame can also occur in a sequence different from that marked in the accompanying drawings. For example, two continuous frames can actually be executed substantially in parallel, and they can also be executed in the opposite order sometimes, depending on the functions involved. It should also be noted that each frame in the block diagram and / or flow chart, and the combination of frames in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or action, or can be implemented with a combination of dedicated hardware and computer instructions.

[0075] The embodiments of the present disclosure have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The choice of terms used herein is intended to best explain the principles of the embodiments, practical applications, or technical improvements to the technology in the market, or to enable other persons of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for generating code, comprising: Based on the source code of the target language, generate a multi-layer intermediate representation of the source code; Based on the multi-layer intermediate representation, generating a low-level virtual machine intermediate representation of the source code; In response to the low-level virtual machine intermediate representation satisfying a predetermined condition, generating an executable file package in the target language; and In response to the low-level virtual machine intermediate representation not satisfying the predetermined condition, regenerating the multi-layer intermediate representation of the source code.

2. The method according to claim 1, wherein generating a multi-layer intermediate representation of the source code based on the source code of the target language comprises: Based on the source code, generating an abstract syntax tree corresponding to the source code, wherein the abstract syntax tree is a tree representation of the source code; as well as Based on the abstract syntax tree, the multi-layer intermediate representation of the source code is generated.

3. The method according to claim 2, wherein generating the multi-layer intermediate representation of the source code based on the abstract syntax tree comprises: Traversing and checking the types of nodes in the abstract syntax tree to determine a check result for the abstract syntax tree; as well as In response to the determined checking result for the abstract syntax tree being correct, the multi-layer intermediate representation corresponding to the source code is derived layer by layer.

4. The method according to claim 3, wherein in response to the determined checking result for the abstract syntax tree being correct, deriving the multi-layer intermediate representation corresponding to the source code layer by layer comprises: Derived a first-layer intermediate representation of the multi-layer intermediate representation from the abstract syntax tree; as well as A second-layer intermediate representation of the multi-layer intermediate representation is derived from the first-layer intermediate representation of the multi-layer intermediate representation.

5. The method according to claim 4, wherein generating a low-level virtual machine intermediate representation of the source code based on the multi-layer intermediate representation comprises: The low-level virtual machine intermediate representation is generated based on the second-level intermediate representation of the multi-level intermediate representation.

6. The method according to claim 5, wherein in response to the low-level virtual machine intermediate representation satisfying the predetermined condition, generating the executable file package in the target language comprises: Based on the low-level virtual machine intermediate representation, generate machine code corresponding to the source code; as well as Based on the machine code, the executable file package is generated.

7. The method according to claim 6, wherein in response to the low-level virtual machine intermediate representation not satisfying the predetermined condition, regenerating the multi-layer intermediate representation of the source code comprises: In response to the low-level virtual machine intermediate representation not satisfying the predetermined condition, backtracking to the abstract syntax tree; as well as The multi-layer intermediate representation of the source code is regenerated based on the abstract syntax tree.

8. The method according to claim 1, further comprising: Get the orchestration flow drawn by the user on the canvas of the graphical user interface; as well as Based on the choreography process, the source code in the target language is generated, wherein the source code includes a process choreography code representing process semantics and a process node code representing a task in the choreography process.

9. The method according to claim 8, wherein generating the source code of the target language based on the editing process comprises: Based on the orchestration process, determining a serialization file corresponding to the orchestration process; as well as Based on the serialization file, the source code in the target language is generated.

10. A device for generating a code, comprising: A multi-layer intermediate representation generating device is configured to generate a multi-layer intermediate representation of the source code based on the source code of the target language; A low-level virtual machine intermediate representation generation module, configured to generate a low-level virtual machine intermediate representation of the source code based on the multi-layer intermediate representation; an executable file package generation module, configured to generate an executable file package in the target language in response to the low-level virtual machine intermediate representation satisfying a predetermined condition; and The multi-layer intermediate representation regeneration module is configured to regenerate the multi-layer intermediate representation of the source code in response to the low-layer virtual machine intermediate representation not satisfying the predetermined condition.

11. An electronic device, comprising: processor; as well as A memory coupled to the processor, the memory having instructions stored therein, wherein when the instructions are executed by the processor, the electronic device executes the method according to any one of claims 1 to 9.

12. A computer program product comprising computer executable instructions, wherein the computer executable instructions are executed by a processor to implement the method according to any one of claims 1 to 9.

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