Pixel circuit, driving method, display substrate and display device

Abstract

The invention provides a pixel circuit, a driving method, a display substrate and a display device. The pixel circuit comprises a data write-in sub-circuit which is coupled with a data signal end, a scanning signal end and a fourth node; the first light-emitting control sub-circuit is coupled with a first voltage end, a first light-emitting control end and a second node; the driving sub-circuit is coupled with the first node, the second node and the third node; the storage sub-circuit is coupled with the first node and the fourth node; the compensation sub-circuit is coupled with a compensation signal end, the first node and the third node; the second light-emitting control sub-circuit is coupled with the third node, a second light-emitting control end and an electrode of the light-emitting element; the first initialization sub-circuit is coupled with a first reset signal end, a first initialization signal end and a fourth node; the second initialization sub-circuit is coupled with a second reset signal end, a second initialization signal end and an electrode of the light-emitting element; and the third initialization sub-circuit is coupled with a third reset signal end, a third initialization signal end and a third node.

Description

Pixel circuit, driving method, display substrate and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and particularly to a pixel circuit, a driving method, a display substrate, and a display device. Background Art

[0002] With the advancement of display technology, display products are experiencing diverse application requirements, such as high-frequency displays and large-size displays. However, high-frequency display products suffer from insufficient drive voltage compensation time due to the compressed time required for circuit image writing and compensation, which impacts display quality. Large-size display products, on the other hand, experience significant voltage drops due to the high drive current, resulting in insufficient drive voltage and impacting display quality.

[0003] How to optimize the pixel circuit of display products and ensure stable driving voltage is one of the important research topics for R&D personnel.

[0004] The above information disclosed in this section is only for understanding the background of the technical concept of the present disclosure and therefore the above information may contain information that does not constitute the prior art.

[0005] Summary of the Invention

[0006] In one aspect, a pixel circuit is provided, characterized in that the pixel circuit includes: a data writing subcircuit, the data writing subcircuit is coupled to a data signal terminal, a scan signal terminal and a fourth node, the data writing subcircuit is configured to write a data signal received at the data signal terminal to the fourth node in response to a scan signal received at the scan signal terminal; a first light-emitting control subcircuit, the first light-emitting control subcircuit is coupled to a first voltage terminal, a first light-emitting control terminal and a second node, the first light-emitting control subcircuit is configured to write a first voltage received at the first voltage terminal to the second node in response to a first light-emitting control signal received at the first light-emitting control terminal; a driving subcircuit, the driving subcircuit The driver subcircuit is coupled to the first node, the second node, and the third node, and the driver subcircuit is configured to generate a driving current in response to the voltage of the first node; the storage subcircuit is coupled between the first node and the fourth node, and the storage subcircuit is configured to store a voltage; the compensation subcircuit is coupled to the compensation signal terminal, the first node, and the third node, and the compensation subcircuit is configured to transmit the first voltage from the first voltage terminal and the threshold voltage of the driver subcircuit to the first node in response to the compensation control signal received at the compensation signal terminal; the second light-emitting control subcircuit is coupled to the third node, the second light-emitting control terminal, and the light-emitting control terminal. The first electrode of the light-emitting element is coupled to the first electrode of the light-emitting element, the second light-emitting control subcircuit is configured to output the driving current transmitted to the third node to the light-emitting element in response to the second light-emitting control signal received at the second light-emitting control terminal; the first initialization subcircuit is coupled to the first reset signal terminal, the first initialization signal terminal and the fourth node, the first initialization subcircuit is configured to transmit the first initialization signal received at the first initialization signal terminal to the fourth node in response to the first reset signal received at the first reset signal terminal, so as to initialize the potential of the fourth node; the second initialization subcircuit is coupled to the second reset signal terminal, the second initialization signal terminal and the fourth node. The first initialization sub-circuit is coupled to the first electrode of the light-emitting element, the second initialization sub-circuit is configured to transmit the second initialization signal received at the second initialization signal terminal to the first electrode of the light-emitting element in response to the second reset signal received at the second reset signal terminal, so as to initialize the potential of the first electrode of the light-emitting element; and a third initialization sub-circuit, the third initialization sub-circuit is coupled to the third reset signal terminal, the third initialization signal terminal and the third node, the third initialization sub-circuit is configured to transmit the third initialization signal received at the third initialization signal terminal to the third node in response to the third reset signal received at the third reset signal terminal, so as to initialize the potential of the third node.

[0007] According to some exemplary embodiments, the pixel circuit further includes: a potential maintaining sub-circuit, the potential maintaining sub-circuit being coupled between the first voltage terminal and the fourth node, the potential maintaining sub-circuit being configured to maintain the potential of the first node.

[0008] According to some exemplary embodiments, the pixel circuit is configured to transmit the first voltage from the first voltage terminal and the threshold voltage of the driving sub-circuit to the first node in response to the first light-emitting control signal, the first reset signal and the compensation control signal.

[0009] According to some exemplary embodiments, the third initialization sub-circuit and the compensation sub-circuit are further configured to: in response to a third reset signal received at the third reset signal terminal and in response to a second control signal received at the compensation signal terminal, transmit the third initialization signal received at the third initialization signal terminal to the first node to initialize the potential of the first node.

[0010] According to some exemplary embodiments, the second initialization sub-circuit includes a first transistor, a control electrode of the first transistor is coupled to the second reset signal terminal, a first electrode of the first transistor is coupled to the second initialization signal terminal, and a second electrode of the first transistor is coupled to the first electrode of the light-emitting element.

[0011] According to some exemplary embodiments, the compensation sub-circuit includes a second transistor, a control electrode of the second transistor is coupled to the compensation signal terminal, a first electrode of the second transistor is coupled to the first node, and a second electrode of the second transistor is coupled to the third node.

[0012] According to some exemplary embodiments, the driving sub-circuit includes a third transistor, a control electrode of the third transistor coupled to the first node, a first electrode of the third transistor coupled to the second node, and a second electrode of the third transistor coupled to the third node.

[0013] According to some exemplary embodiments, the data writing sub-circuit includes a fourth transistor, the control electrode of the fourth transistor is coupled to the scan signal terminal, the first electrode of the fourth transistor is coupled to the data signal terminal, and the second electrode of the fourth transistor is coupled to the fourth node.

[0014] According to some exemplary embodiments, the first light-emitting control subcircuit includes a fifth transistor, a control electrode of the fifth transistor is coupled to the first light-emitting control terminal, a first electrode of the fifth transistor is coupled to the first voltage terminal, and a second electrode of the fifth transistor is coupled to the second node.

[0015] According to some exemplary embodiments, the second light-emitting control subcircuit includes a sixth transistor, the control electrode of the sixth transistor is coupled to the second light-emitting control terminal, the first electrode of the sixth transistor is coupled to the third node, and the second electrode of the sixth transistor is coupled to the first electrode of the light-emitting element.

[0016] According to some exemplary embodiments, the first initialization sub-circuit includes a seventh transistor, a control electrode of the seventh transistor is coupled to the first reset signal terminal, a first electrode of the seventh transistor is coupled to the first initialization signal terminal, and a second electrode of the seventh transistor is coupled to the fourth node.

[0017] According to some exemplary embodiments, the third initialization sub-circuit includes an eighth transistor, the control electrode of the eighth transistor is coupled to the third reset signal terminal, the first electrode of the eighth transistor is coupled to the third initialization signal terminal, and the second electrode of the eighth transistor is coupled to the third node.

[0018] According to some exemplary embodiments, the storage sub-circuit includes a first capacitor, a first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to the fourth node.

[0019] According to some exemplary embodiments, the potential maintaining sub-circuit includes a second capacitor, a first terminal of the second capacitor is coupled to the first voltage terminal, and a second terminal of the second capacitor is coupled to the fourth node.

[0020] According to some exemplary embodiments, the second reset signal terminal and the third reset signal terminal are the same reset signal terminal.

[0021] On the other hand, a driving method for a pixel circuit is provided, which is applied to the pixel circuit as described in any one of the above items, wherein the driving method includes: in the compensation stage of an image frame, the first light-emitting control subcircuit writes the first voltage received at the first voltage terminal to the second node in response to the first light-emitting control signal; in response to the first reset signal and the compensation control signal, the first initialization subcircuit and the compensation subcircuit are both turned on so that the first voltage from the first voltage terminal and the threshold voltage of the driving subcircuit are transmitted to the first node, wherein the time of the compensation stage is adjusted by the first light-emitting control signal, the first reset signal and the compensation control signal.

[0022] According to some exemplary embodiments, the driving method further includes: in a reset phase of an image frame, the first initialization sub-circuit transmits the first initialization signal received at the first initialization signal terminal to the fourth node in response to the first reset signal received at the first reset signal terminal, so as to initialize the potential of the fourth node; after a preset time interval, the third initialization sub-circuit transmits the third initialization signal received at the third initialization signal terminal to the third node in response to the third reset signal received at the third reset signal terminal, and the compensation sub-circuit is turned on in response to the compensation control signal received at the compensation signal terminal, so that the third initialization signal is transmitted to the first node to initialize the potential of the first node.

[0023] On the other hand, a display substrate is provided, wherein the display substrate includes: a base substrate; a pixel circuit as described in any one of the above items arranged on the base substrate; and a light-emitting element arranged on the base substrate, the light-emitting element being coupled to the pixel circuit.

[0024] On the other hand, a display substrate is provided, wherein the display substrate includes: a base substrate; a first semiconductor layer arranged on the base substrate; a first conductive layer arranged on a side of the first semiconductor layer away from the base substrate; a second conductive layer arranged on a side of the first conductive layer away from the base substrate; a second semiconductor layer arranged on a side of the second conductive layer away from the base substrate, wherein the second semiconductor layer includes an oxide semiconductor; a third conductive layer arranged on a side of the second semiconductor layer away from the base substrate; a fourth conductive layer arranged on a side of the third conductive layer away from the base substrate; and a fifth conductive layer arranged on a side of the fourth conductive layer away from the base substrate, wherein the display substrate further includes a a pixel circuit on the substrate, the pixel circuit including a data writing subcircuit, a driving subcircuit, a compensation subcircuit, a first light emitting control subcircuit, a second light emitting control subcircuit, a first initialization subcircuit, a second initialization subcircuit, and a third initialization subcircuit, the second initialization subcircuit including a first transistor, the compensation subcircuit including a second transistor, the driving subcircuit including a third transistor, the data writing subcircuit including a fourth transistor, the first light emitting control subcircuit including a fifth transistor, the second light emitting control subcircuit including a sixth transistor, the first initialization subcircuit including a seventh transistor, and the third initialization subcircuit including an eighth transistor; the display substrate further comprising: a second complex circuit located on the first conductive layer; a first light-emitting control line and a second light-emitting control line; a third initialization signal line, a first sub-line of a compensation signal line, a first sub-line of a first reset signal line and a first sub-line of a scan signal line located in the second conductive layer; a second initialization signal line, a first initialization signal line, a second sub-line of a compensation signal line, a second sub-line of a first reset signal line and a second sub-line of a scan signal line located in the third conductive layer; an orthographic projection of the first sub-line of the compensation signal line on the substrate at least partially overlaps with an orthographic projection of the second semiconductor layer on the substrate, an orthographic projection of the second sub-line of the compensation signal line on the substrate at least partially overlaps with an orthographic projection of the second semiconductor layer on the substrate, and The overlapping portion of the semiconductor layer is the first sub-control electrode of the second transistor, and the overlapping portion of the second sub-line of the compensation signal line and the second semiconductor layer is the second sub-control electrode of the second transistor; the orthographic projection of the first sub-line of the scan signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the substrate, and the orthographic projection of the second sub-line of the scan signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the substrate, the overlapping portion of the first sub-line of the scan signal line and the second semiconductor layer is the first sub-control electrode of the fourth transistor, and the overlapping portion of the second sub-line of the scan signal line and the second semiconductor layer is the second sub-control electrode of the fourth transistor;The orthographic projection of the first sub-line of the first reset signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the substrate, and the orthographic projection of the second sub-line of the first reset signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the substrate. The portion where the first sub-line of the first reset signal line overlaps with the second semiconductor layer serves as the first sub-control electrode of the seventh transistor, and the portion where the second sub-line of the first reset signal line overlaps with the second semiconductor layer serves as the second sub-control electrode of the seventh transistor.

[0025] According to some exemplary embodiments, the display substrate further includes a plurality of connecting signal lines located in the fourth conductive layer; at least one of the first initialization signal line, the second initialization signal line, and the third initialization signal line extends along a first direction, and the plurality of connecting signal lines extend along a second direction respectively, and at least one of the first initialization signal line, the second initialization signal line, and the third initialization signal line is electrically connected to the plurality of connecting signal lines to form a mesh structure.

[0026] According to some exemplary embodiments, the pixel circuit further includes a storage subcircuit and a potential holding subcircuit, the storage subcircuit includes a first capacitor, and the potential holding subcircuit includes a second capacitor; the display substrate further includes a first conductive portion located in the first conductive layer, a second conductive portion located in the second conductive layer, a third conductive portion located in the fourth conductive layer, and a first voltage signal line located in the fifth conductive layer, the first voltage signal line includes a widened portion; the first conductive portion is the first end of the first capacitor, the second conductive portion and the third conductive portion electrically connected to each other are the second end of the first capacitor and the second end of the second capacitor, and the widened portion of the first voltage signal line is the first end of the second capacitor; and the orthographic projection of the widened portion of the first voltage signal line on the base substrate covers the orthographic projection of each of the first conductive portion, the second conductive portion and the third conductive portion on the base substrate.

[0027] In yet another aspect, a display device is provided, comprising the display substrate as described in any one of the above items. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Features and advantages of the present disclosure will become more apparent by describing in detail exemplary embodiments of the present disclosure with reference to the accompanying drawings.

[0029] FIG1 is a schematic plan view of a display device according to some embodiments of the present disclosure;

[0030] FIG2 is a schematic plan view of a display substrate included in a display device according to some embodiments of the present disclosure;

[0031] FIG3 is a structural diagram of a sub-pixel according to some embodiments of the present disclosure;

[0032] FIG4 is a structural block diagram of a pixel circuit according to some embodiments of the present disclosure;

[0033] FIG5 is a structural block diagram of a pixel circuit according to some other embodiments of the present disclosure;

[0034] FIG6 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure;

[0035] FIG7 is an operation timing diagram of at least one embodiment of a driving method for the pixel circuit shown in FIG6 ;

[0036] FIG8 is a schematic structural diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] 9 is a schematic diagram illustrating a planar structure of a first semiconductor layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0038] 10 is a schematic diagram illustrating a planar structure of a first conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0039] 11 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer and a first conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0040] 12 is a schematic diagram illustrating a planar structure of a second conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0041] 13 is a schematic diagram illustrating a planar structure of a second semiconductor layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0042] 14 is a schematic diagram illustrating a planar structure of a third conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0043] 15 is a schematic diagram illustrating a planar structure of a combination of a second conductive layer, a second semiconductor layer, and a third conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0044] 16 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0045] FIG17 is a schematic diagram showing a via hole in the insulating layer formed on the structure of FIG16;

[0046] 18 is a schematic diagram illustrating a planar structure of a fourth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0047] FIG19 is a schematic diagram showing a via hole in the insulating layer formed on the structure of FIG18;

[0048] 20 is a schematic diagram illustrating a planar structure of a fifth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure;

[0049] 21 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0050] To make the purpose, technical solutions, and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0051] It should be noted that in the drawings, the sizes and relative sizes of elements may be exaggerated for clarity and / or descriptive purposes. Thus, the sizes and relative sizes of the individual elements are not necessarily limited to those shown in the drawings. In the specification and drawings, the same or similar reference numerals indicate the same or similar parts.

[0052] When an element is described as being "on" another element, "connected to" another element, or "bound to" another element, the element may be directly on the other element, directly connected to the other element, or directly bound to the other element, or there may be an intermediate element. However, when an element is described as being "directly on" another element, "directly connected to" another element, or "directly bound to" another element, there is no intermediate element. Other terms and / or expressions used to describe the relationship between elements should be interpreted in a similar manner, for example, "between" versus "directly between", "adjacent" versus "directly adjacent", or "on" versus "directly on", etc. In addition, the term "connected" may refer to a physical connection, an electrical connection, a communication connection, and / or a fluid connection. In addition, the X-axis, Y-axis, and Z-axis are not limited to the three axes of a rectangular coordinate system, and may be interpreted in a broader sense. For example, the X-axis, Y-axis, and Z-axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0053] It should be noted that although the terms "first," "second," etc. may be used herein to describe various parts, components, elements, regions, layers, and / or portions, these parts, components, elements, regions, layers, and / or portions should not be limited by these terms. Rather, these terms are used to distinguish one part, component, element, region, layer, and / or portion from another. Thus, for example, the first part, first member, first element, first region, first layer, and / or first portion discussed below may be referred to as a second part, second member, second element, second region, second layer, and / or second portion without departing from the teachings of the present disclosure.

[0054] For ease of description, spatially relative terms, such as "upper," "lower," "left," "right," etc., may be used herein to describe the relationship of one element or feature to another element or feature as shown in the figures. It should be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" or "over" the other elements or features.

[0055] As used herein, the terms "substantially," "about," "approximately," "roughly," and other similar terms are used as terms of approximation rather than as terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that would be recognized by one of ordinary skill in the art. To account for factors such as process fluctuations, measurement problems, and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "about" or "approximately" as used herein are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0056] It should be noted that, in this article, the term "the same layer" refers to a layer structure formed by using the same film-forming process to form a film layer used to form a specific pattern, and then patterning the film layer using the same mask through a single patterning process. Depending on the specific pattern, a single patterning process may include multiple exposure, development, or etching processes, and the specific pattern in the resulting layer structure may be continuous or discontinuous. In other words, multiple elements, components, structures, and / or parts located in the "same layer" are composed of the same material and are formed through the same patterning process. Typically, multiple elements, components, structures, and / or parts located in the "same layer" have approximately the same thickness.

[0057] Those skilled in the art should understand that, in this article, unless otherwise specified, the expression "height" or "thickness" refers to the dimension of the surface of each film layer arranged perpendicular to the display substrate, that is, the dimension along the light emitting direction of the display substrate, or the dimension along the normal direction of the display device.

[0058] In this document, the term "transistor" may refer to a triode, a thin-film transistor, a field-effect transistor, or other device with similar characteristics. In the embodiments of the present disclosure, to distinguish the two electrodes of a transistor other than the control electrode, one electrode is referred to as the first electrode, and the other electrode is referred to as the second electrode. In actual operation, when the transistor is a thin-film transistor or a field-effect transistor, the first electrode may be the drain electrode, and the second electrode may be the source electrode; alternatively, the first electrode may be the source electrode, and the second electrode may be the drain electrode.

[0059] An embodiment of the present disclosure provides at least one pixel circuit, the pixel circuit comprising: a data writing subcircuit, the data writing subcircuit being coupled to a data signal terminal, a scan signal terminal, and a fourth node, the data writing subcircuit being configured to write a data signal received at the data signal terminal to the fourth node in response to a scan signal received at the scan signal terminal; a first light-emitting control subcircuit, the first light-emitting control subcircuit being coupled to a first voltage terminal, a first light-emitting control terminal, and a second node, the first light-emitting control subcircuit being configured to write a first voltage received at the first voltage terminal to the second node in response to a first light-emitting control signal received at the first light-emitting control terminal; a driving subcircuit, the driving subcircuit The circuit is coupled to a first node, a second node, and a third node, the driving sub-circuit being configured to generate a driving current in response to a voltage at the first node; a storage sub-circuit being coupled between the first node and the fourth node, the storage sub-circuit being configured to store a voltage; a compensation sub-circuit being coupled to a compensation signal terminal, the first node, and the third node, the compensation sub-circuit being configured to transmit a first voltage from the first voltage terminal and a threshold voltage of the driving sub-circuit to the first node in response to a compensation control signal received at the compensation signal terminal; a second light-emitting control sub-circuit being coupled to the third node, the second light-emitting control terminal, and the light-emitting element The first initialization subcircuit is coupled to the first electrode of the light-emitting element, the second light-emitting control subcircuit is configured to output the driving current transmitted to the third node to the light-emitting element in response to the second light-emitting control signal received at the second light-emitting control terminal; the first initialization subcircuit is coupled to the first reset signal terminal, the first initialization signal terminal and the fourth node, the first initialization subcircuit is configured to transmit the first initialization signal received at the first initialization signal terminal to the fourth node in response to the first reset signal received at the first reset signal terminal, so as to initialize the potential of the fourth node; the second initialization subcircuit is coupled to the second reset signal terminal, the second initialization signal terminal and the second initialization signal terminal. The first terminal is coupled to the first electrode of the light-emitting element, the second initialization sub-circuit is configured to transmit the second initialization signal received at the second initialization signal terminal to the first electrode of the light-emitting element in response to the second reset signal received at the second reset signal terminal, so as to initialize the potential of the first electrode of the light-emitting element; and a third initialization sub-circuit, the third initialization sub-circuit is coupled to the third reset signal terminal, the third initialization signal terminal and the third node, the third initialization sub-circuit is configured to transmit the third initialization signal received at the third initialization signal terminal to the third node in response to the third reset signal received at the third reset signal terminal, so as to initialize the potential of the third node.By controlling the on or off state of the first light-emitting control subcircuit, the first initialization subcircuit and the compensation subcircuit and their respective on or off times, the writing time of the first voltage received at the first voltage terminal can be flexibly adjusted to fully compensate for the voltage of the first node coupled to the control terminal of the driving subcircuit, thereby ensuring that the light-emitting element obtains a stable driving voltage, thereby improving the display effect of the display product.

[0060] FIG1 is a schematic plan view of a display device according to some embodiments of the present disclosure. For example, the display device may be an OLED display device. Referring to FIG1 , the display device may include a display panel 1000, a gate driver 1200, a data driver 1300, a controller 1400, and a voltage generator 1500. The display panel 1000 may include a display substrate 1100 and a plurality of pixels PX. The array substrate 1000 may include a display area AA and a non-display area NA, with the plurality of pixels PX arranged in an array within the display area AA. The signal generated by the gate driver 1200 may be applied to the pixels PX via a signal line, such as a scan signal line GL, and the signal generated by the data driver 1300 may be applied to the pixels PX via a signal line, such as a data line DL. A first voltage, such as VDD, and a second voltage, such as VSS, may be applied to the pixels PX. The first voltage, such as VDD, may be higher than the second voltage, such as VSS. Alternatively, the first voltage, such as VDD, may be applied to the anode of a light-emitting element (e.g., an OLED), and the second voltage, such as VSS, may be applied to the cathode of the light-emitting element, thereby causing the light-emitting element to emit light.

[0061] For example, each pixel PX may include a plurality of sub-pixels, eg, a red sub-pixel, a green sub-pixel, and a blue sub-pixel, or may include a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel.

[0062] 2 is a schematic plan view of a display substrate included in a display device according to some embodiments of the present disclosure. For example, the display substrate may be an array substrate for an OLED display panel.

[0063] Referring to Figure 2 , the display substrate may include a display area AA and a non-display area NA. For example, the display area AA and the non-display area NA may include multiple boundaries, such as AAS1, AAS2, AAS3, and AAS4 as shown in Figure 2 . The display substrate may also include a driver located within the non-display area NA. For example, the driver may be located on at least one side of the display area AA. In the embodiment shown in Figure 2 , the driver is located on the left and right sides of the display area AA, respectively. It should be noted that the left and right sides may be the left and right sides of the display substrate (screen) as viewed by the human eye during display. The driver may be used to drive each pixel in the display substrate for display. For example, the driver may include the gate driver 1200 and data driver 1300 described above. The data driver 1300 is used to sequentially latch input data according to a clock signal, convert the latched data into analog signals, and then input them to the data lines of the display substrate. The gate driver 1200 is typically implemented by a shift register, which converts the clock signal into on / off voltages and outputs them to the scan signal lines of the display substrate.

[0064] It should be noted that, although FIG. 2 shows that the drivers are located on the left and right sides of the display area AA, the embodiments of the present disclosure are not limited thereto, and the driving circuits may be located at any appropriate position in the non-display area NA.

[0065] For example, the driver can adopt GOA technology, i.e., Gate Driver on Array (GDA). In GOA technology, the gate driver circuit is directly arranged on the array substrate to replace the external driver chip. Each GOA unit acts as a shift register, and each shift register is connected to a gate line. The shift registers at each level sequentially output the turn-on voltage to achieve row-by-row scanning of pixels. In some embodiments, each shift register can also be connected to multiple gate lines. In this way, it can adapt to the development trend of high-resolution and narrow-frame display substrates.

[0066] Referring to Figure 2 , the display substrate includes a left-side GOA circuit DA1, multiple subpixels P located in the display area AA, and a right-side GOA circuit DA2. The left-side GOA circuit DA1 and the right-side GOA circuit DA2 are each electrically connected to a display IC via signal lines. The display IC controls the supply of GOA signals. The display IC is, for example, located on the lower side of the display substrate (the direction of human viewing). The left-side GOA circuit DA1 and the right-side GOA circuit DA2 are also electrically connected to each pixel via signal lines (e.g., scan signal lines GL) to supply drive signals to each pixel.

[0067] It should be noted that the figure exemplifies that the orthographic projection of the sub-pixel on the substrate is a rounded rectangle, but the embodiments of the present disclosure are not limited to this. For example, the orthographic projection of the sub-pixel on the substrate can be a rectangle, hexagon, pentagon, square, circle, or other shapes. Moreover, the arrangement of the three sub-pixels in a pixel unit is not limited to that shown in Figures 1 and 2.

[0068] 1 and 2 , each pixel unit may include a plurality of sub-pixels P, for example, a first sub-pixel, a second sub-pixel, and a third sub-pixel. For ease of understanding, the first sub-pixel, the second sub-pixel, and the third sub-pixel may be described as a red sub-pixel, a green sub-pixel, and a blue sub-pixel, respectively. However, the embodiments of the present disclosure are not limited thereto.

[0069] The plurality of sub-pixels are arranged in an array on the base substrate 1 along the row direction X and the column direction Y. It should be noted that although the row direction X and the column direction Y are perpendicular to each other in the illustrated embodiment, the embodiments of the present disclosure are not limited thereto.

[0070] It should be understood that in the embodiments of the present disclosure, each sub-pixel includes a pixel circuit and a light-emitting element. For example, the light-emitting element may be an OLED light-emitting element, including a stacked anode, a light-emitting layer, and a cathode. The pixel circuit may include multiple thin-film transistors and at least one storage capacitor.

[0071] FIG3 is a schematic structural diagram of a sub-pixel according to some embodiments of the present disclosure.

[0072] 3 , each sub-pixel P includes a light emitting element L and a pixel circuit 101 coupled to the light emitting element L. The pixel circuit 101 is configured to provide a driving current to the light emitting element L to drive the light emitting element L to operate (ie, emit light).

[0073] For example, referring to FIG3 , a first electrode of the light-emitting element L is coupled to the pixel circuit 101, and a second electrode of the light-emitting element L is coupled to a second voltage terminal VSS. The second voltage terminal VSS is configured to transmit a second voltage. The second voltage can be a DC reference voltage, for example, the second voltage Vss is -3V. Alternatively, the second voltage Vss is 0V, i.e., the second voltage terminal VSS is grounded. The second voltage terminal VSS only needs to provide 0V or a negative voltage to the second electrode of the light-emitting element L.

[0074] Exemplarily, the light-emitting element L includes a current-driven element. Further, the light-emitting element L can be a current-driven light-emitting diode, such as a micro light-emitting diode (Micro LED), a mini light-emitting diode (Mini LED), a quantum dot light-emitting diode (Quantum Light Emitting Diode, QLED), or an organic light-emitting diode (Organic Light Emitting Diode, OLED). Exemplarily, the first electrode and the second electrode of the light-emitting element L are the anode and cathode of the light-emitting diode, respectively.

[0075] FIG4 is a block diagram of a pixel circuit according to some embodiments of the present disclosure. As shown in FIG4 , the pixel circuit includes: a light emitting control subcircuit 200 , a data writing subcircuit 310 , a driving subcircuit 410 , a compensation subcircuit 510 , and a storage subcircuit 610 .

[0076] The data writing sub-circuit 530 is coupled to the data signal terminal Vdata, the scan signal terminal GN1 and the fourth node N4 and is configured to write the data signal received at the data signal terminal Vdata into the fourth node N4 in response to the scan signal received at the scan signal terminal GN1.

[0077] The driving sub-circuit 410 is coupled to the first voltage terminal VDD, the first node N1, and the third node N3. The driving sub-circuit 410 is configured to generate a driving current I in response to the voltage of the first node N1.

[0078] The storage sub-circuit 610 is coupled between the first node N1 and the fourth node N4 and is configured to store a voltage.

[0079] The compensation sub-circuit 510 is coupled to the compensation signal terminal GN2, the first node N1, and the third node N3. The compensation sub-circuit 510 is configured to transmit the first voltage Vdd from the first voltage terminal VDD and the threshold voltage Vth of the driver sub-circuit 410 to the first node N1 in response to a control signal received at the compensation signal terminal GN2.

[0080] The light emitting control subcircuit 200 is coupled to the light emitting control terminal EM, the third node N3, and the first electrode of the light emitting element L. The light emitting control subcircuit 200 is configured to transmit the driving current I transmitted to the third node N3 to the light emitting element L in response to a control signal received at the light emitting control terminal EM.

[0081] The second electrode of the light emitting element L is coupled to the second voltage terminal VSS.

[0082] It should be understood that in the pixel circuit 101 provided in the embodiments of the present disclosure, the first node N1, the second node N2, the third node N3, and the fourth node N4 do not necessarily represent actual components. In some embodiments, these nodes represent the junction points of related couplings (i.e., electrical connections) in the equivalent circuit diagram of the pixel circuit. In other words, these nodes are nodes formed by equivalent junction points of related electrical connections in the circuit diagram.

[0083] For example, the light emitting element L is an OLED, and the threshold voltage of the light emitting element L is the threshold voltage V o1ed-th .

[0084] The following describes the working process of the above-mentioned pixel circuit 101 by taking the light-emitting element L as OLED as an example. It should be understood that the light-emitting element can also be other current-driven elements such as Micro LED, Mini LED or QLED, and the embodiments of the present disclosure are not limited to this.

[0085] In the compensation phase of an image frame F, the compensation sub-circuit 510 transmits the first voltage (e.g., power supply voltage Vdd) from the first voltage terminal VDD and the threshold voltage Vth of the driving sub-circuit 410 to the first node N1 in response to the control signal received at the compensation signal terminal GN2. Therefore, the voltage V N1 Equal to Vdd+Vth. Exemplarily, the first voltage Vdd from the first voltage terminal VDD is a DC voltage, for example, a DC high-level voltage, for example, the first voltage Vdd is 5V.

[0086] In the writing phase of the image frame F, the data writing sub-circuit 310 responds to the scanning signal received at the scanning signal terminal GN1 and writes the data signal V received at the data signal terminal Vdata to the data signal terminal Vdata. data Write to the fourth node N4, so that the voltage V N4 Directly changes to V data , that is, V N4 =V data .

[0087] Since the storage sub-circuit 610 relies on the capacitor to store voltage, the bootstrap effect of the capacitor (i.e., the voltage across the capacitor cannot change suddenly, and when the voltage at one end increases, the other end remains at the voltage difference with the previous end) is utilized. N4 becomes V data After that, the voltage V N1 Finally stabilized at V N1 =V data +Vdd+Vth.

[0088] Since the voltage difference (V data +Vth) is greater than the threshold voltage Vth of the driving sub-circuit 410. Therefore, the driving sub-circuit 410 responds to the voltage V N1 It is turned on and generates a driving current I. The driving circuit satisfies the following formula: I = 1 / 2·K·(Vgs-Vth) 2 =1 / 2·K·(V N1 -Vdd-Vth) 2 =1 / 2·K·V data 2

[0089] Wherein, K is a fixed constant related to the process parameters and geometric dimensions of the driver sub-circuit 410. Vgs is the gate-source voltage difference of the driver transistor in the driver sub-circuit 410.

[0090] During the light-emitting phase of the image frame F, the light-emitting control subcircuit 200 outputs the driving current I transmitted to the third node N3 to the light-emitting element L in response to the control signal received at the light-emitting control terminal EM, so as to drive the light-emitting element L to emit light.

[0091] Since the driving current I ultimately flowing through the light-emitting element L is independent of the first voltage Vdd and the threshold voltage Vth of the driving sub-circuit 410, the driving current I of the light-emitting element L is not affected by the voltage drop of the first power line transmitting the first voltage Vdd and the threshold voltage Vth of the driving sub-circuit 410. In this way, the above-mentioned pixel circuit 101 can improve the uniformity of the driving current flowing through the light-emitting element L and achieve uniform luminous brightness.

[0092] Figure 5 is a block diagram of a pixel circuit according to other embodiments of the present disclosure, and Figure 6 is an equivalent circuit diagram of a pixel circuit according to some embodiments of the present disclosure. It should be noted that in the following description, an 8T2C pixel circuit is used as an example to describe the structure of the pixel circuit in detail. However, the embodiments of the present disclosure are not limited to the 8T2C pixel circuit. Other known pixel circuit structures can be applied to the embodiments of the present disclosure unless there is a conflict.

[0093] As shown in Figure 5, the pixel circuit includes: a first light-emitting control sub-circuit 210, a second light-emitting control circuit 220, a data writing sub-circuit 310, a driving sub-circuit 410, a compensation sub-circuit 510, a storage sub-circuit 610, a potential holding sub-circuit 620 and at least one of the first initialization sub-circuit 110, the second initialization sub-circuit 120 and the third initialization sub-circuit 130.

[0094] For example, referring to FIG5 , a pixel circuit according to an embodiment of the present disclosure is used to drive a light-emitting element L. The pixel circuit includes a first initialization subcircuit 110 for resetting the voltage of the fourth node N4 during a reset phase. The first initialization subcircuit 110 is electrically connected to the first initialization signal terminal Vi1, the first reset signal terminal GN3, and the fourth node N4, respectively, and is configured to control the connection between the first initialization signal terminal Vi1 and the fourth node N4 under the control of a first reset signal provided by the first reset signal terminal GN3, thereby resetting the voltage of the fourth node N4 and clearing the data voltage V of the fourth node N4 in the previous image frame. data , to avoid signal interference. The first initialization signal provided by the first initialization signal terminal can be selected according to actual conditions and is not limited here. For example, the third initialization signal is a low-level signal. For example, the third initialization signal is -3V.

[0095] The pixel circuit further includes a second initialization sub-circuit 120 for resetting the voltage of the first electrode of the light-emitting element L during a reset phase. The second initialization sub-circuit 120 is electrically connected to the second reset signal terminal GN4, the second initialization signal terminal Vi2, and the first electrode of the light-emitting element L. The second initialization sub-circuit 120 is configured to control the connection between the second initialization signal terminal Vi2 and the first electrode of the light-emitting element L under the control of a reset signal provided by the second reset signal terminal GN4, thereby initializing the potential of the first electrode of the light-emitting element L, i.e., lowering the potential of the first electrode of the light-emitting element L.

[0096] During the reset stage, the voltage of the first electrode of the light-emitting element L is cleared by the second initialization sub-circuit 120, so that the potential of the first electrode of the light-emitting element L is initialized, thereby preventing the light-emitting element L from emitting light in a dark state due to the influence of the leakage current of the second light-emitting control circuit 220, thereby improving the display quality of the display device having the pixel circuit.

[0097] The pixel circuit further includes a third initialization sub-circuit 130 and a compensation sub-circuit 510, which can be used to reset the voltages of the third node N3 and the first node N1 during a reset phase. The compensation sub-circuit 510 is electrically connected to the compensation signal terminal GN2, the first node N1, and the third node N3, respectively, and is configured to control the connection between the first node N1 and the third node N3 under the control of a compensation signal provided by the compensation signal terminal GN2. The third initialization sub-circuit 130 is electrically connected to the third reset signal terminal GN5, the third initialization signal terminal Vi3, and the third node N3, respectively, and is configured to control the connection between the third initialization signal terminal Vi3 and the third node N3 under the control of a third reset signal provided by the third reset signal terminal GN5, thereby resetting the voltage of the third node N3. Since the first node N1 and the third node N3 are now connected, the voltage of the first node N1 is also reset, i.e., the potential of the first node is lowered.

[0098] 5 , the pixel circuit further includes a first light emitting control subcircuit 210 for performing voltage compensation on the first node N1 during the compensation phase. The first light emitting control subcircuit 210 is electrically connected to the first voltage terminal VDD, the first light emitting control terminal EM1, and the second node N2, respectively, and is configured to control the connection between the first voltage terminal VDD and the second node N2 under the control of the first light emitting control signal provided by the first light emitting control terminal EM1, thereby writing the first voltage Vdd provided by the first voltage terminal VDD into the second node N2. At this time, V N2 =Vdd. In this stage, the compensation sub-circuit 510 controls the connection between the first node N1 and the third node N3 in response to the compensation control signal received at the compensation signal terminal GN2, thereby transmitting the voltage Vdd of the second node N2 and the threshold voltage Vth of the driving sub-circuit 410 to the first node N1. Therefore, the voltage V N1 Equal to Vdd+Vth. Exemplarily, the first voltage Vdd from the first voltage terminal VDD is a DC voltage, for example, a DC high-level voltage, for example, the first voltage Vdd is 5V.

[0099] The pixel circuit can transmit the first voltage from the first voltage terminal and the threshold voltage of the driving sub-circuit to the first node in response to the first light-emitting control signal, the first reset signal, and the compensation control signal. By adjusting the on / off timing of the first light-emitting control sub-circuit 210, the compensation sub-circuit 510, and the first initialization sub-circuit 110, the voltage compensation time during the compensation phase can be flexibly adjusted to ensure sufficient voltage compensation at the first node N1, thereby improving the driving effect of the pixel circuit on the light-emitting element L.

[0100] In Figure 5, the node labeled N1 is the first node electrically connected to the control end of the driving sub-circuit 410, the node labeled N2 is the second node electrically connected to the first end of the driving sub-circuit 410, and the node labeled N3 is the third node electrically connected to the second end of the driving sub-circuit 410.

[0101] Continuing with FIG5 , the pixel circuit further includes a data write sub-circuit 310 for writing a data signal provided by the data signal terminal Vdata into the fourth node N4 during a data write phase. Before the data write phase begins, the compensation sub-circuit 510 controls the disconnection between the first node N1 and the third node N3 in response to a control signal received at the compensation signal terminal GN2, and the first initialization sub-circuit 110 controls the disconnection between the first initialization signal terminal Vi1 and the fourth node N4 in response to a first reset signal received at the first reset signal terminal GN3. The data write sub-circuit 310 is electrically connected to the data signal terminal Vdata, the scan signal terminal GN1, and the fourth node N4, respectively. During the data write phase, under control of a scan signal provided by the scan signal terminal GN1, the data signal terminal Vdata is controlled to connect to the fourth node N4, thereby writing the data signal Vdata provided by the data signal terminal Vdata into the fourth node N4.

[0102] 5 and 6 , the pixel circuit further includes a storage subcircuit 610 and a potential holding subcircuit 620. The potential holding subcircuit 620 is configured to hold the potential of the first node N1. The storage subcircuit 610 may include a first capacitor C1, which may include a first plate C1a and a second plate C1b. The potential holding subcircuit 620 may include a second capacitor C2, which may include a first plate C2a and a second plate C2b. The first plate C1a of the first capacitor C1 is electrically connected to the first node N1, and the second plate C1b of the first capacitor C1 is electrically connected to the fourth node N4. The first plate C2a of the second capacitor C2 is electrically connected to the fourth node N4, and the second plate C2b of the second capacitor C2 is electrically connected to the first voltage terminal VDD. In response to a voltage change at the fourth node N4 electrically connected to the second plate C1b of the first capacitor C1, the capacitance of the first capacitor C1 changes by: ΔV N4 =V data +V i1 .

[0103] Since the storage sub-circuit 610 relies on the capacitor to store voltage, the bootstrap effect of the capacitor is utilized (i.e., the voltage across the capacitor cannot change suddenly. When the voltage at one end increases, the other end remains at the voltage difference with the previous end).N4 V data +V i1 When the voltage of the first node N1 is V N1 Finally stabilized at V N1 =V data +V i1 +Vdd+Vth.

[0104] Since the voltage difference (V data +V i1 +Vth) is greater than the threshold voltage Vth of the driving sub-circuit 410. Therefore, the driving sub-circuit 410 responds to the voltage V N1 It is turned on and generates a driving current I. The driving circuit satisfies the following formula: I = 1 / 2·K·(Vgs-Vth) 2 =1 / 2·K·(V N1 -Vdd-Vth) 2 =1 / 2·K·(V data +V i1 ) 2

[0105] Wherein, K is a fixed constant related to the process parameters and geometric dimensions of the driver sub-circuit 410. Vgs is the gate-source voltage difference of the driver transistor in the driver sub-circuit 410.

[0106] Continuing with reference to FIG5 , the pixel circuit further includes a second light-emitting control subcircuit 220, which is configured to output the driving current I transmitted to the third node N3 to the light-emitting element L in response to the light-emitting control signal received at the second light-emitting control terminal EM2 during the light-emitting phase of the image frame, so as to drive the light-emitting element L to emit light.

[0107] Since the driving current I ultimately flowing through the light-emitting element L is independent of the first voltage Vdd and the threshold voltage Vth of the driving sub-circuit 410, the driving current I of the light-emitting element L is not affected by the voltage drop of the first power line transmitting the first voltage Vdd and the threshold voltage Vth of the driving sub-circuit 410. In this way, the above-mentioned pixel circuit can improve the uniformity of the driving current flowing through the light-emitting element L and achieve uniform luminous brightness.

[0108] For example, in some embodiments of the present disclosure, referring to FIG6 , the first initialization subcircuit 110 includes a seventh transistor T7, the second initialization subcircuit 120 includes a first transistor T1, the third initialization subcircuit 130 includes an eighth transistor T8, the first emission control subcircuit 210 includes a fifth transistor T5, the second emission control subcircuit 220 includes a sixth transistor T6, the driving subcircuit 410 includes a third transistor T3, the compensation subcircuit 510 includes a second transistor T2, the data writing subcircuit 310 includes a fourth transistor T4, the storage subcircuit 610 includes a first capacitor C1, and the potential maintaining subcircuit 620 includes a second capacitor C2. The light-emitting element L may be an organic light-emitting diode.

[0109] Each transistor includes a control electrode of the transistor, that is, a gate; a first electrode of the transistor, that is, one of a source or a drain; and a second electrode of the transistor, that is, the other of the source or the drain.

[0110] The first capacitor C1 may include a first plate C1a and a second plate C1b. The first plate C1a of the first capacitor C1 is electrically connected to the first node N1, that is, the first plate C1a of the first capacitor C1 is electrically connected to the gate of the third transistor and the first electrode of the second transistor. The second plate C1b of the first capacitor C1 is electrically connected to the fourth node N4, that is, the second plate C1b of the first capacitor C1 is electrically connected to the second plate C2b of the second capacitor C2, the first electrode of the fourth transistor, and the first electrode of the seventh transistor.

[0111] The second capacitor C2 may include a first plate C2a and a second plate C2b. The first plate C2a of the second capacitor C2 is electrically connected to the fourth node N4, and the second plate C2b of the second capacitor C2 is electrically connected to the second electrode of the fifth transistor T5. That is, the second plate C2b of the second capacitor is electrically connected to the first voltage terminal VDD.

[0112] The control electrode (gate) of the first transistor T1 is electrically connected to the second reset signal terminal GN4, the first electrode of the first transistor T1 is electrically connected to the second initialization signal terminal Vi2, and the second electrode of the first transistor T1 is electrically connected to the first electrode of the light-emitting element L. For example, the second initialization signal terminal Vi2 is used to provide a second initialization signal.

[0113] The control electrode (gate) of the second transistor T2 is electrically connected to the compensation signal terminal GN2, the first electrode of the second transistor T2 is electrically connected to the first node N1, and the second electrode of the second transistor T2 is electrically connected to the third node N3. That is, the first electrode of the second transistor T2 is electrically connected to the gate of the third transistor T3 and the first electrode plate C1a of the first capacitor C1, and the second electrode of the second transistor T2 is electrically connected to the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the first electrode of the eighth transistor T8.

[0114] A control electrode (gate) of the third transistor T3 is electrically connected to the first node N1 , a first electrode of the third transistor T3 is electrically connected to the second node N2 , and a second electrode of the third transistor T3 is electrically connected to the node N3 .

[0115] A control electrode (gate) of the fourth transistor T4 is electrically connected to the scan signal terminal GN1 , a second electrode of the fourth transistor T4 is electrically connected to the data signal terminal Vdata, and a first electrode of the fourth transistor T4 is electrically connected to the fourth node N4 .

[0116] The control electrode (gate) of the fifth transistor T5 is electrically connected to the first light emitting control terminal EM1, the first electrode of the fifth transistor T5 is electrically connected to the first voltage terminal VDD, and the second electrode of the fifth transistor T5 is electrically connected to the first electrode of the third transistor T3. The first voltage terminal VDD is used to provide a high voltage Vdd.

[0117] The control electrode (gate) of the sixth transistor T6 is electrically connected to the second light-emitting control terminal EM2; the first electrode of the sixth transistor T6 is electrically connected to the node N3, that is, the first electrode of the sixth transistor T6 is electrically connected to the second electrode of the third transistor T3 and the second electrode of the second transistor T2; the second electrode of the sixth transistor T6 is electrically connected to the first electrode of the light-emitting element L, and the first electrode of the light-emitting element L can be an anode.

[0118] The control electrode (gate) of the seventh transistor T7 is electrically connected to the first reset signal terminal GN3, the second electrode of the seventh transistor T7 is electrically connected to the first initialization signal terminal Vi1, and the first electrode of the seventh transistor T7 is electrically connected to the fourth node N4. That is, the first electrode of the seventh transistor T7 is electrically connected to the first electrode of the fourth transistor T4, the second plate C1b of the first capacitor C1, and the first plate C2a of the second capacitor C2. For example, the first initialization signal terminal Vi1 is used to provide a first initialization signal.

[0119] A control electrode (gate) of the eighth transistor T8 is electrically connected to the third reset signal terminal GN5 , a first electrode of the eighth transistor T8 is electrically connected to the third node N3 , and a second electrode of the eighth transistor T8 is electrically connected to the third initialization signal terminal Vi3 .

[0120] The first electrode of the light emitting element L is electrically connected to the second electrode of the sixth transistor, and the second electrode of the light emitting element L is electrically connected to the second voltage terminal VSS. The second voltage terminal VSS is used to provide a low voltage Vss.

[0121] In the embodiment of the present disclosure, any two of Vi1, Vi2, and Vi3 may be the same or different.

[0122] In an embodiment of the present disclosure, the second reset signal terminal GN4 and the third reset signal terminal GN5 are the same reset signal terminal.

[0123] In the embodiment of the present disclosure, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 may be oxide thin film transistors, and other transistors such as the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the eighth transistor T8 may be low-temperature polysilicon thin film transistors. However, the embodiment of the present disclosure is not limited thereto.

[0124] In at least one embodiment of the pixel circuit described in the present disclosure, the voltage value of Vi1 may be greater than or equal to -6V and less than or equal to -2V. For example, the voltage value of Vi1 may be -2V, -3V, -4V, -5V, or -6V, but is not limited thereto.

[0125] The threshold voltage Vth of the transistor may be greater than or equal to -5V and less than or equal to -0.5V; for example, Vth may be -2.5V or -3V;

[0126] The voltage value of the high voltage Vdd provided by the first voltage terminal VDD may be greater than or equal to 3V and less than or equal to 6V. For example, the voltage value of Vdd may be 4.6V, but is not limited thereto.

[0127] The absolute value of the high voltage Vdd may be greater than 1.5 times the absolute value of Vth. For example, the absolute value of the high voltage Vdd may be 1.6 times, 1.8 times, or 2 times the absolute value of Vth.

[0128] Optionally, the voltage value of the low voltage Vss provided by the second voltage terminal VSS may be greater than or equal to -6V and less than or equal to -3V; for example, the voltage value of Vss may be -5V, -4V or -3V.

[0129] In at least one embodiment of the present disclosure, the voltage value of Vi2 may be greater than or equal to -7 V and less than or equal to 0 V. For example, the voltage value of the second initialization voltage may be -6 V, -5 V, -4 V, -3 V, or -2 V, but is not limited thereto.

[0130] Optionally, the voltage difference between the voltage value of Vi2 and the voltage value of VSS needs to be smaller than the turn-on voltage of the light-emitting element, so that when the first electrode of the light-emitting element is connected to Vi2, the light-emitting element does not emit light.

[0131] FIG7 is an operating timing diagram of at least one embodiment of a driving method for the pixel circuit shown in FIG6. With reference to FIG5 to FIG7 , when the pixel circuit according to an embodiment of the present disclosure is in operation, a display cycle may include a reset phase t1, a compensation phase t2, a data writing phase t3, and a light emitting phase t4, which are sequentially arranged.

[0132] In the reset phase t1, the potential of the first light control signal provided by the first light control terminal EM1 changes from the low voltage Vgl to the high voltage Vgh, controlling the fifth transistor T5 to turn off. The second light control signal provided by the second light control terminal EM2 changes from the low voltage Vgl to the high voltage Vgh, controlling the sixth transistor T6 to turn off. After a short interval, the first reset signal provided by the first reset signal terminal GN3 changes from the low voltage Vgl to the high voltage Vgh, controlling the seventh transistor to turn on, and the first initialization voltage V i1 Write to the fourth node N4, at this time V N4 =V i1 Then, after a certain period of time, the compensation signal provided by the compensation signal terminal GN2 is converted from the low voltage Vgl to the high voltage Vgh, controlling the second transistor T2 to turn on. At the same time, the third reset signal provided by the third reset signal terminal GN5 is converted from the high voltage Vgh to the low voltage Vgl, controlling the eighth transistor T8 to turn on, and the third initialization voltage V i3 Write to the first node N1.

[0133] For example, in the reset phase of an image frame, the first initialization sub-circuit 110 responds to the first reset signal received at the first reset signal terminal GN3, and transmits the first initialization signal received at the first initialization signal terminal Vi1 to the fourth node N4 to initialize the potential of the fourth node N4; after a preset time interval, the third initialization sub-circuit 130 responds to the third reset signal received at the third reset signal terminal GN5, and transmits the third initialization signal received at the third initialization signal terminal Vi3 to the third node N3, and the compensation sub-circuit 510 responds to the compensation control signal received at the compensation signal terminal GN2, and the compensation sub-circuit 510 is turned on, so that the third initialization signal Vi3 is transmitted to the first node N1 to initialize the potential of the first node N1.

[0134] In the compensation phase t2, the third reset signal provided by the third reset signal terminal GN5 is converted from the low voltage Vgl to the high voltage Vgh, controlling the eighth transistor T8 to turn off, the compensation signal provided by the compensation signal terminal GN2 continues to maintain a high voltage, controlling the second transistor T2 to continue to turn on, and the first reset signal provided by the first reset signal terminal GN3 continues to maintain a high voltage, controlling the seventh transistor T7 to turn on. At this time, the first light-emitting control signal provided by the first light-emitting control terminal EM1 is converted from the high voltage Vgh to the low voltage Vgl, controlling the fifth transistor T5 to turn on, and the first voltage Vdd provided by the first voltage terminal VDD is sequentially written into the second node N2, the third node N3 and the first node N1. At this time, the voltage V N1 =Vdd+Vth.

[0135] Exemplarily, in combination with reference to Figures 5 to 7, in the compensation stage of an image frame, the first light-emitting control sub-circuit 210 writes the first voltage received at the first voltage terminal VDD into the second node N2 in response to the first light-emitting control signal; in response to the first reset signal and the compensation control signal, the first initialization sub-circuit 120 and the compensation sub-circuit 510 are both turned on, so that the first voltage Vdd from the first voltage terminal VDD and the threshold voltage Vth of the driving sub-circuit 410 are transmitted to the first node N1, wherein the time of the compensation stage can be adjusted by the first light-emitting control signal, the first reset signal and the compensation control signal to ensure sufficient voltage compensation for the first node N1 and improve the driving effect of the pixel circuit on the light-emitting element L.

[0136] 5-7 , before the data writing phase t3, the first reset signal provided by the first reset signal terminal GN3 is converted from the high voltage Vgh to the low voltage Vgl, controlling the seventh transistor T7 to be turned off; in the data writing phase t3, the compensation signal provided by the compensation signal terminal GN2 is converted from the high voltage Vgh to the low voltage Vgl, controlling the second transistor T2 to be turned off, and the scan signal provided by the scan signal terminal GN1 is converted from the low voltage Vgl to the high voltage Vgh, controlling the fourth transistor T4 to be turned on, and writing the data signal provided by the data signal terminal Vdata to the fourth node N4, thereby causing the capacitance change ΔV of the first capacitor C1 to be ΔV. N4 =V data +V i1 .

[0137] Due to the bootstrap effect of the capacitor (i.e., the voltage across the capacitor cannot change suddenly, when the voltage at one end increases, the other end remains at the voltage difference with the previous end), when the voltage of the fourth node N4 changes by ΔV N4 V data +V i1When the voltage of the first node N1 is V N1 Finally stabilized at V N1 =V data +V i1 +Vdd+Vth.

[0138] In the light-emitting stage t4, the scan signal provided by the scan signal terminal GN1 is converted from the high voltage Vgh to the low voltage Vgl, controlling the fourth transistor T4 to turn off; the reset signal provided by the second reset signal terminal GN4 is converted from the high voltage Vgh to the low voltage Vgl, controlling the first transistor T1 to turn on, and writing Vi2 into the first electrode of the light-emitting element L. Subsequently, the reset signal provided by the second reset signal terminal GN4 is converted from the low voltage Vgl to the high voltage Vgh, controlling the first transistor T1 to turn off; then, the first light-emitting control signal provided by the first light-emitting control terminal EM1 is converted from the high voltage Vgh to the low voltage Vgl, controlling the fifth transistor T5 to turn on, and the second light-emitting control signal provided by the second light-emitting control terminal EM2 is converted from the high voltage Vgh to the low voltage Vgl, controlling the sixth transistor T6 to turn on. At this time, due to the voltage difference (V data +V i1 +Vth) is greater than the threshold voltage Vth of the driving sub-circuit 410. Therefore, the third transistor T3 responds to the voltage V N1 It is turned on and generates a driving current I. The driving circuit satisfies the following formula: I = 1 / 2·K·(Vgs-Vth) 2 =1 / 2·K·(V N1 -Vdd-Vth) 2 =1 / 2·K·(V data +V i1 ) 2

[0139] Wherein, K is a fixed constant related to the process parameters and geometric dimensions of the driver sub-circuit 410. Vgs is the gate-source voltage difference of the driver transistor in the driver sub-circuit 410.

[0140] The light emitting element L emits light due to the driving action of the driving current I.

[0141] In an embodiment of the present disclosure, the second transistor T2 included in the compensation subcircuit, the fourth transistor T4 included in the data writing subcircuit, and the seventh transistor T7 included in the first initialization subcircuit can be oxide thin-film transistors. This can reduce leakage at the control terminal of the driver circuit, ensure the stability of the voltage at the control terminal of the driver circuit, and help improve display quality, enhance display uniformity, and reduce flicker.

[0142] In an embodiment of the present disclosure, the first transistor T1 may be controlled by a separate GOA, which is electrically connected to the second reset signal terminal GN4, so that the light emitting element L may be reset at a specific frequency, such as 240 Hz.

[0143] In the embodiments of the present disclosure, the second reset signal provided by the second reset signal terminal GN4 can be a high-frequency signal. By increasing the frequency of the second reset signal provided by the second reset signal terminal GN4, the refresh frequency of resetting the first electrode of the light-emitting element L can be increased, so that the brightness build-up time of the light-emitting element L during the refresh phase and the hold phase remains consistent. This can reduce the low-frequency component of the light-emission hold phase, reduce visible brightness changes, improve flicker levels, and reduce load and power consumption.

[0144] It should be noted that, in the embodiments of the present disclosure, each thin film transistor T1, T2, T3, T4, T5, T6, T7 and T8 may be a p-channel field effect transistor, but the embodiments of the present disclosure are not limited thereto, and at least some of the thin film transistors T1, T2, T3, T4, T5, T6, T7 and T8 may be an n-channel field effect transistor.

[0145] FIG. 8 is a schematic structural diagram of a display substrate according to some exemplary embodiments of the present disclosure.

[0146] 8 , the present disclosure illustratively provides a display substrate 1100 , including a base substrate 1 , a pixel circuit 101 disposed on the base substrate 1 , and a light-emitting element L disposed on the base substrate 1 , wherein the pixel circuit 101 includes any of the pixel circuits described above. The light-emitting element L is coupled to the pixel circuit 101 .

[0147] FIG9 is a schematic diagram illustrating a planar structure of a first semiconductor layer of a pixel circuit according to an exemplary embodiment of the present disclosure. FIG10 is a schematic diagram illustrating a planar structure of a first conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure. FIG11 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer and a first conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure. FIG12 is a schematic diagram illustrating a planar structure of a second conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure. FIG13 is a schematic diagram illustrating a planar structure of a second semiconductor layer of a pixel circuit according to an exemplary embodiment of the present disclosure. FIG14 is a schematic diagram illustrating a planar structure of a third conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure. FIG15 is a schematic diagram illustrating a planar structure of a combination of a second conductive layer, a second semiconductor layer, and a third conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure. FIG16 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure. FIG17 is a schematic diagram illustrating a via hole formed in an insulating layer on the structure of FIG16. FIG18 is a schematic diagram illustrating a planar structure of a fourth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure. FIG19 is a schematic diagram illustrating a via hole formed in an insulating layer on the structure of FIG18 . FIG20 is a schematic diagram illustrating a planar structure of a fifth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure. FIG21 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure.

[0148] For example, with reference to Figures 9 to 21, in some embodiments of the present disclosure, a display substrate includes a base substrate and multiple film layers disposed on the base substrate. In some embodiments, the multiple film layers include at least a first semiconductor layer 2, a first conductive layer 3, a second conductive layer 4, a second semiconductor layer 5, a third conductive layer 6, a fourth conductive layer 7, and a fifth conductive layer 8. The first semiconductor layer 2, the first conductive layer 3, the second conductive layer 4, the second semiconductor layer 5, the third conductive layer 6, the fourth conductive layer 7, and the fifth conductive layer 8 are sequentially disposed away from the base substrate.

[0149] 5 and 6 , the display substrate further includes a pixel circuit disposed on the base substrate, the pixel circuit including a data writing subcircuit 310, a driving subcircuit 410, a compensation subcircuit 510, a first light-emitting control subcircuit 210, a second light-emitting control subcircuit 220, a first initialization subcircuit 110, a second initialization subcircuit 120, and a third initialization subcircuit 130. The second initialization subcircuit 120 includes a first transistor T1, the compensation subcircuit 510 includes a second transistor T2, the driving subcircuit 410 includes a third transistor T3, the data writing subcircuit 310 includes a fourth transistor T4, the first light-emitting control subcircuit 210 includes a fifth transistor T5, the second light-emitting control subcircuit 220 includes a sixth transistor T6, the first initialization subcircuit 110 includes a seventh transistor T7, and the third initialization subcircuit 130 includes an eighth transistor T8.

[0150] For example, the first semiconductor layer 2 can be formed of a semiconductor material such as low-temperature polysilicon, and its film thickness can be in the range of 400 to 800 angstroms, for example, 500 angstroms. The second semiconductor layer 5 can be formed of an oxide semiconductor material, such as a polycrystalline silicon oxide semiconductor material such as IGZO, and its film thickness can be in the range of 300 to 600 angstroms, for example, 400 angstroms. The first conductive layer 3, the second conductive layer 4, and the third conductive layer 6 can be formed of a conductive material that forms the gate of a thin film transistor, for example, the conductive material can be Mo, and its film thickness can be in the range of 2000 to 3000 angstroms, for example, 2500 angstroms. The fourth conductive layer 7 and the fifth conductive layer 8 can be formed of a conductive material that forms the source and drain of a thin film transistor, for example, the conductive material can include Ti, Al, etc. The fourth conductive layer 7 and the fifth conductive layer 8 can have a stacked structure formed of Ti / Al / Ti, and their film thickness can be in the range of 7000 to 9000 angstroms. For example, in the case where the fourth conductive layer 7 and the fifth conductive layer 8 have a stacked-layer structure formed of Ti / Al / Ti, the thickness of each layer of Ti / Al / Ti may be approximately 500 angstroms, 5500 angstroms, and 500 angstroms, respectively.

[0151] In an embodiment of the present disclosure, the first transistor T1, the third transistor T3, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T8 may be formed along the first semiconductor layer 2 as shown in FIG9 . The second transistor T2, the fourth transistor T4, and the seventh transistor T7 may be formed along the second semiconductor layer 5 as shown in FIG13 .

[0152] As shown in Figure 9, the first semiconductor layer 2 may have a curved or bent shape and may include a first active layer 20a corresponding to the first transistor T1, a third active layer 20c corresponding to the third transistor T3, a fifth active layer 20e corresponding to the fifth transistor T5, a sixth active layer 20f corresponding to the sixth transistor T6, and an eighth active layer 20h corresponding to the eighth transistor T8.

[0153] For example, the first semiconductor layer 2 may include polycrystalline silicon, such as low-temperature polycrystalline silicon. The active layer of each transistor may include a channel region, a source region, and a drain region. The channel region may not be doped or may have a different doping type from the source region and the drain region, and thus have semiconductor properties. The source region and the drain region are respectively located on either side of the channel region and are doped with impurities, and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0154] 9-11 , the first transistor T1 includes a first active layer 20a and a first gate G1. The first active layer 20a includes a first source region 203a, a first drain region 205a, and a first channel region 201a connecting the first source region 203a and the first drain region 205a. The first source region 203a and the first drain region 205a extend in opposite directions relative to the first channel region 201a.

[0155] The third transistor T3 includes a third active layer 20c and a third gate G3. The third active layer 20c includes a third source region 203c, a third drain region 205c, and a third channel region 201c connecting the third source region 203c and the third drain region 205c. The third source region 203c and the third drain region 205c extend in two opposite directions relative to the third channel region 201c.

[0156] The fifth transistor T5 includes a fifth active layer 20e and a fifth gate G5. The fifth active layer 20e includes a fifth source region 203e, a fifth drain region 205e, and a fifth channel region 201e connecting the fifth source region 203e and the fifth drain region 205e. The fifth source region 203e and the fifth drain region 205e extend in two opposite directions relative to the fifth channel region 201e.

[0157] The sixth transistor T6 includes a sixth active layer 20f and a sixth gate G6. The sixth active layer 20f includes a sixth source region 203f, a sixth drain region 205f, and a sixth channel region 201f connecting the sixth source region 203f and the sixth drain region 205f. The sixth source region 203f and the sixth drain region 205f extend in two opposite directions relative to the sixth channel region 201f.

[0158] The eighth transistor T8 includes an eighth active layer 20h and an eighth gate G8. The eighth active layer 20h includes an eighth source region 203h, an eighth drain region 205h, and an eighth channel region 201h connecting the eighth source region 203h and the eighth drain region 205h. The eighth source region 203h and the eighth drain region 205h extend in opposite directions relative to the eighth channel region 201h.

[0159] As shown in Figures 10 and 11, the first emission control line EM1, the second emission control line EM2, the second reset signal line GN4, the third reset signal line GN5, and the first conductive portion CG1 are all located in the first conductive layer 3. The portion of the third reset signal line GN5 that overlaps with the first semiconductor layer 2 forms the eighth gate G8 of the eighth transistor T8. The portion of the first emission control line EM1 that overlaps with the first semiconductor layer 2 forms the fifth gate G5 of the fifth transistor T5. The portion of the first conductive portion CG1 that overlaps with the first semiconductor layer 2 forms the third gate G3 of the third transistor T3. The portion of the second emission control line EM2 that overlaps with the first semiconductor layer 2 forms the sixth gate G6 of the sixth transistor T6. The portion of the second reset signal line GN4 that overlaps with the first semiconductor layer 2 forms the first gate G1 of the first transistor T1.

[0160] The first conductive portion CG1 also forms a plate of the first capacitor C1, for example, the first plate C1a. That is, the first conductive portion CG1 serves as the gate of the third transistor T3 and a plate of the first capacitor C1 at the same time.

[0161] 12 , the third initialization signal line Vi3, the compensation signal line first sub-line GN21, the scan signal line first sub-line GN11, the first reset signal line first sub-line GN31, and the second conductive portion CG2 are all located in the second conductive layer 4. The second conductive portion CG2 forms another plate of the first capacitor C1, for example, the second plate C1b.

[0162] 13 , the second semiconductor layer 5 may have a curved or bent shape and may include a second active layer 20 b corresponding to the second transistor T2 , a fourth active layer 20 d corresponding to the fourth transistor T4 , and a seventh active layer 20 g corresponding to the seventh transistor T7 .

[0163] The second active layer 20b includes a second source region 203b, a second drain region 205b, and a second channel region 201b connecting the second source region 203b and the second drain region 205b. The second source region 203b and the second drain region 205b extend in two opposite directions relative to the second channel region 201b.

[0164] The fourth active layer 20d includes a fourth source region 203d, a fourth drain region 205d, and a fourth channel region 201d connecting the fourth source region 203d and the fourth drain region 205d. The fourth source region 203d and the fourth drain region 205d extend in two opposite directions relative to the fourth channel region 201d.

[0165] The seventh active layer 20g includes a seventh source region 203g, a seventh drain region 205g, and a seventh channel region 201g connecting the seventh source region 203g and the seventh drain region 205g. The seventh source region 203g and the seventh drain region 205g extend in two opposite directions relative to the seventh channel region 201g.

[0166] For example, the second semiconductor layer 5 may include an oxide semiconductor material. The active layer of each transistor may include a channel region, a source region, and a drain region. The channel region may not be doped or may have a different doping type from the source region and the drain region, and thus have semiconductor properties. The source region and the drain region are located on either side of the channel region, respectively, and are doped with impurities, and thus have conductivity. The impurities may vary depending on whether the TFT is an N-type or P-type transistor.

[0167] As shown in FIG. 14 , the second initialization signal line Vi2 , the first initialization signal line Vi1 , the compensation signal line second sub-line GN22 , the scan signal line second sub-line GN12 and the first reset signal line second sub-line GN32 are all located in the third conductive layer 6 .

[0168] For example, the first compensation signal line sub-line GN21 located in the second conductive layer 4 and the second compensation signal line sub-line GN22 located in the third conductive layer 6 can both transmit compensation signals. The first scan signal line sub-line GN11 located in the second conductive layer 4 and the second scan signal line sub-line GN12 located in the third conductive layer 6 can both transmit scan signals. The first reset signal line first sub-line GN31 located in the second conductive layer 4 and the second reset signal line second sub-line GN32 located in the third conductive layer 6 can both transmit first reset signals.

[0169] 15 , the orthographic projection of the first compensation signal line sub-line GN21 on the base substrate at least partially overlaps with the orthographic projection of the second semiconductor layer 5 on the base substrate, and the orthographic projection of the second compensation signal line sub-line GN22 on the base substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the base substrate. The portion where the first compensation signal line sub-line GN21 overlaps with the second semiconductor layer is the first sub-control electrode G21 of the second transistor T2, and the portion where the second compensation signal line sub-line GN22 overlaps with the second semiconductor layer is the second sub-control electrode G22 of the second transistor T2.

[0170] The orthographic projection of the first scan signal line sub-line GN11 on the base substrate at least partially overlaps with the orthographic projection of the second semiconductor layer 5 on the base substrate, the orthographic projection of the second scan signal line sub-line GN12 on the base substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the base substrate, the portion where the first scan signal line sub-line GN11 overlaps with the second semiconductor layer 5 is the first sub-control electrode G41 of the fourth transistor T4, and the portion where the second scan signal line sub-line GN12 overlaps with the second semiconductor layer 5 is the second sub-control electrode G42 of the fourth transistor T4;

[0171] The orthographic projection of the first sub-line GN31 of the first reset signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer 5 on the substrate, and the orthographic projection of the second sub-line GN32 of the first reset signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer 5 on the substrate. The part where the first sub-line GN31 of the first reset signal line overlaps with the second semiconductor layer 5 is the first sub-control electrode G71 of the seventh transistor T7, and the part where the second sub-line GN32 of the first reset signal line overlaps with the second semiconductor layer 5 is the second sub-control electrode G72 of the seventh transistor T7.

[0172] Exemplarily, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 have a dual-gate structure. In the embodiment of the present disclosure, the second transistor T2, the fourth transistor T4, and the seventh transistor T7 are configured as oxide semiconductor transistors, and the second transistor T2, the fourth transistor T4, and the seventh transistor T7 have a dual-gate structure, which is beneficial for reducing the leakage current of the first node N1 and the fourth node N4, thereby facilitating the potential stability of the first node N1 and the fourth node N4.

[0173] FIG16 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, and a third conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure, showing a first gate G1 of a first transistor, a first sub-control electrode G21 and a second sub-control electrode G22 of a second transistor, a third gate G3 of a third transistor, a first sub-control electrode G41 and a second sub-control electrode G42 of a fourth transistor, a fifth gate G5 of a fifth transistor, a sixth gate G6 of a sixth transistor, a first sub-control electrode G71 and a second sub-control electrode G72 of a seventh transistor, an eighth gate G8 of an eighth transistor, and a first capacitor C1. FIG17 is a schematic diagram illustrating vias formed in an insulating layer on the structure of FIG16 , showing a first via VH1.

[0174] As shown in FIG18 , the display substrate further includes a fourth conductive layer 7 and a plurality of connection signal lines 76 located within the fourth conductive layer 7. The plurality of connection signal lines 76 extend along the second direction Y. The fourth conductive layer 7 further includes a third conductive portion CG3. Referring again to FIG16 and FIG17 , the third conductive portion CG3 can be electrically connected to the second conductive portion CG2 via a first via VH1. The fourth conductive portion 7 further includes a first initialization signal line transition portion 71, a second initialization signal line transition portion 72, a third initialization signal line transition portion 73, a first power line transition portion 74, and a data signal line transition portion 75.

[0175] FIG. 19 is a schematic diagram illustrating via holes in an insulating layer formed on the structure of FIG. 18 , showing a second via hole VH2 , a first node N1 , a third node N3 , and a fourth node N4 .

[0176] 20 is a schematic diagram illustrating a planar structure of a fifth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure, showing a data signal line Vdata and a first voltage signal line VDD, wherein the first voltage signal line includes a widened portion VDDL.

[0177] 21 is a schematic diagram illustrating a planar structure of a combination of a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer of a pixel circuit according to an exemplary embodiment of the present disclosure.

[0178] With reference to Figures 9 to 21 , the pixel circuit includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, and a second capacitor C2. The gate of the third transistor T3, the first electrode of the second transistor T2, and one plate of the first capacitor C1 are coupled at a first node N1. The second electrode of the second transistor T2, the second electrode of the third transistor T3, the first electrode of the sixth transistor T6, and the first electrode of the eighth transistor T8 are coupled at a third node N3. The first electrode of the fourth transistor T4, the first electrode of the seventh transistor T7, the second plate of the first capacitor C1, and the first plate of the second capacitor C2 are coupled at a fourth node N4. The second electrode of the first transistor T1 is electrically connected to the second initialization signal line Vi2 through the second initialization signal line adapter 72, the second electrode of the fourth transistor T4 is electrically connected to the data signal line Vdata through the data signal line adapter 75, the first electrode of the fifth transistor T5 is electrically connected to the first power line VDD through the first power line adapter 74, the second electrode of the seventh transistor T7 is electrically connected to the first initialization signal line Vi1 through the first initialization signal line adapter 71, and the second electrode of the eighth transistor T8 is electrically connected to the third initialization signal line Vi3 through the third initialization signal line adapter 73.

[0179] The conductive layers in different film layers can be electrically connected through vias. For example, the data signal line Vdata is electrically connected to the data signal line transition portion 75 through the second via VH2, and then the data signal is written into the pixel circuit through the fourth transistor T4.

[0180] With reference to Figures 12, 14, and 21, the first initialization signal line Vi1 and the second initialization signal line Vi2 are located in the third conductive layer 6, and the third initialization signal line Vi3 is located in the second conductive layer 4. At least one of the first initialization signal line Vi1, the second initialization signal line Vi2, and the third initialization signal line Vi3 extends along the first direction X. At least one of the first initialization signal line Vi1, the second initialization signal line Vi2, and the third initialization signal line Vi3 is electrically connected to the plurality of connection signal lines 76 to form a mesh structure. This mesh structure design allows any two of the first initialization signal line Vi1, the second initialization signal line Vi2, and the third initialization signal line Vi3 to be electrically connected, thereby saving wiring space and improving the aperture ratio of the pixel.

[0181] 5 and 6 , the pixel circuit further includes a storage sub-circuit 610 and a potential holding sub-circuit 620. The storage sub-circuit 610 includes a first capacitor C1, and the potential holding sub-circuit 620 includes a second capacitor C2. With reference to FIG10 , FIG12 , FIG18 , FIG20 , and FIG21 , the display substrate further includes a first conductive portion CG1 located in the first conductive layer 3, a second conductive portion CG2 located in the second conductive layer 4, a third conductive portion CG3 located in the fourth conductive layer 7, and a first voltage signal line VDD located in the fifth conductive layer. The first voltage signal line includes a widened portion VDDL. The first conductive portion CG1 is a first end of the first capacitor C1. The second conductive portion CG2 and the third conductive portion CG3, which are electrically connected to each other, are second ends of the first capacitor C1 and second ends of the second capacitor C2. The widened portion VDDL of the first voltage signal line is a first end of the second capacitor C2. The orthographic projection of the widened portion VDDL of the first voltage signal line on the substrate covers the orthographic projection of each of the first conductive portion CG1, the second conductive portion CG2, and the third conductive portion CG3 on the substrate.

[0182] For example, the widened portion VDDL of the first power signal line may completely cover the first capacitor C1 and the second capacitor C2 , meeting the requirement of capacitor shielding.

[0183] 1 , at least some embodiments of the present disclosure further provide a display device, which may include the display substrate described above.

[0184] The display device may include any device or product with a display function. For example, the display device may be a smart phone, a mobile phone, an e-book reader, a desktop computer (PC), a laptop PC, a netbook PC, a personal digital assistant (PDA), a portable multimedia player (PMP), a digital audio player, a mobile medical device, a camera, a wearable device (such as a head-mounted device, electronic clothing, an electronic bracelet, an electronic necklace, an electronic accessory, an electronic tattoo, or a smart watch), a television, etc.

[0185] It should be understood that the display panel and display device according to the embodiments of the present disclosure have all the features and advantages of the display substrate described above. For details, please refer to the above description and will not be repeated here. Although some embodiments of the overall technical concept of the present disclosure have been shown and described, those skilled in the art will understand that changes can be made to these embodiments without departing from the principles and spirit of the overall technical concept. The scope of the present disclosure is defined by the claims and their equivalents.

Claims

1. A pixel circuit, characterized in that: The pixel circuit comprises: a data writing subcircuit coupled to the data signal terminal, the scan signal terminal and the fourth node, the data writing subcircuit being configured to write a data signal received at the data signal terminal into the fourth node in response to a scan signal received at the scan signal terminal; a first light-emitting control subcircuit, the first light-emitting control subcircuit being coupled to a first voltage terminal, a first light-emitting control terminal, and a second node, the first light-emitting control subcircuit being configured to write a first voltage received at the first voltage terminal into the second node in response to a first light-emitting control signal received at the first light-emitting control terminal; a driving subcircuit, the driving subcircuit being coupled to the first node, the second node and the third node, the driving subcircuit being configured to generate a driving current in response to a voltage at the first node; a storage subcircuit, the storage subcircuit being coupled between the first node and the fourth node, the storage subcircuit being configured to store a voltage; a compensation subcircuit coupled to a compensation signal terminal, the first node, and the third node, the compensation subcircuit being configured to transmit a first voltage from the first voltage terminal and a threshold voltage of the driving subcircuit to the first node in response to a compensation control signal received at the compensation signal terminal; a second light emitting control subcircuit, the second light emitting control subcircuit being coupled to the third node, the second light emitting control terminal and the first electrode of the light emitting element, the second light emitting control subcircuit being configured to output the driving current transmitted to the third node to the light emitting element in response to a second light emitting control signal received at the second light emitting control terminal; a first initialization subcircuit, the first initialization subcircuit being coupled to the first reset signal terminal, the first initialization signal terminal and the fourth node, the first initialization subcircuit being configured to transmit the first initialization signal received at the first initialization signal terminal to the fourth node in response to the first reset signal received at the first reset signal terminal, so as to initialize the potential of the fourth node; a second initialization subcircuit, the second initialization subcircuit being coupled to the second reset signal terminal, the second initialization signal terminal, and the first electrode of the light-emitting element, the second initialization subcircuit being configured to transmit the second initialization signal received at the second initialization signal terminal to the first electrode of the light-emitting element in response to the second reset signal received at the second reset signal terminal, so as to initialize the potential of the first electrode of the light-emitting element; and A third initialization sub-circuit is coupled to a third reset signal terminal, a third initialization signal terminal and the third node, and the third initialization sub-circuit is configured to respond to a third reset signal received at the third reset signal terminal, transmit the third initialization signal received at the third initialization signal terminal to the third node to initialize the potential of the third node.

2. The pixel circuit according to claim 1, wherein: The pixel circuit further comprises: A potential holding sub-circuit is coupled between the first voltage terminal and the fourth node, and is configured to hold the potential of the first node.

3. The pixel circuit according to claim 1 or 2, wherein: The pixel circuit is configured to transmit the first voltage from the first voltage terminal and the threshold voltage of the driving sub-circuit to the first node in response to the first light emission control signal, the first reset signal and the compensation control signal.

4. The pixel circuit according to any one of claims 1 to 3, wherein: The third initialization sub-circuit and the compensation sub-circuit are also configured to: in response to a third reset signal received at the third reset signal terminal and in response to a second control signal received at the compensation signal terminal, transmit the third initialization signal received at the third initialization signal terminal to the first node to initialize the potential of the first node.

5. The pixel circuit according to any one of claims 1 to 4, wherein: The second initialization subcircuit includes a first transistor, a control electrode of the first transistor is coupled to the second reset signal terminal, a first electrode of the first transistor is coupled to the second initialization signal terminal, and a second electrode of the first transistor is coupled to the first electrode of the light-emitting element.

6. The pixel circuit according to claim 5, wherein: The compensation subcircuit includes a second transistor, a control electrode of the second transistor is coupled to the compensation signal terminal, a first electrode of the second transistor is coupled to the first node, and a second electrode of the second transistor is coupled to the third node.

7. The pixel circuit according to claim 5 or 6, wherein: The driving sub-circuit includes a third transistor, a control electrode of the third transistor is coupled to the first node, a first electrode of the third transistor is coupled to the second node, and a second electrode of the third transistor is coupled to the third node.

8. The pixel circuit according to any one of claims 5 to 7, wherein: The data writing subcircuit includes a fourth transistor, a control electrode of the fourth transistor is coupled to the scan signal terminal, a first electrode of the fourth transistor is coupled to the data signal terminal, and a second electrode of the fourth transistor is coupled to the fourth node.

9. The pixel circuit according to any one of claims 5 to 8, wherein: The first light-emitting control subcircuit includes a fifth transistor, a control electrode of the fifth transistor is coupled to the first light-emitting control terminal, a first electrode of the fifth transistor is coupled to the first voltage terminal, and a second electrode of the fifth transistor is coupled to the second node.

10. The pixel circuit according to any one of claims 5 to 9, wherein: The second light-emitting control subcircuit includes a sixth transistor, a control electrode of the sixth transistor is coupled to the second light-emitting control terminal, a first electrode of the sixth transistor is coupled to the third node, and a second electrode of the sixth transistor is coupled to the first electrode of the light-emitting element.

11. The pixel circuit according to any one of claims 5 to 10, wherein: The first initialization subcircuit includes a seventh transistor, a control electrode of the seventh transistor is coupled to the first reset signal terminal, a first electrode of the seventh transistor is coupled to the first initialization signal terminal, and a second electrode of the seventh transistor is coupled to the fourth node.

12. The pixel circuit according to any one of claims 5 to 11, wherein: The third initialization subcircuit includes an eighth transistor, a control electrode of the eighth transistor is coupled to the third reset signal terminal, a first electrode of the eighth transistor is coupled to the third initialization signal terminal, and a second electrode of the eighth transistor is coupled to the third node.

13. The pixel circuit according to any one of claims 5 to 12, wherein: The storage sub-circuit includes a first capacitor, a first end of the first capacitor is coupled to the first node, and a second end of the first capacitor is coupled to the fourth node.

14. The pixel circuit according to any one of claims 5 to 13, wherein: The potential holding subcircuit includes a second capacitor, a first end of the second capacitor is coupled to the first voltage end, and a second end of the second capacitor is coupled to the fourth node.

15. The pixel circuit according to any one of claims 1 to 14, wherein: The second reset signal terminal and the third reset signal terminal are the same reset signal terminal.

16. A method for driving a pixel circuit, applied to the pixel circuit according to any one of claims 1 to 15, wherein: The driving method comprises: In a compensation phase of an image frame, the first light-emitting control subcircuit writes the first voltage received at the first voltage terminal into the second node in response to the first light-emitting control signal; in response to the first reset signal and the compensation control signal, the first initialization subcircuit and the compensation subcircuit are both turned on, so that the first voltage from the first voltage terminal and the threshold voltage of the driving subcircuit are transmitted to the first node, The time of the compensation stage is adjusted by the first light-emitting control signal, the first reset signal and the compensation control signal.

17. The method of claim 16, wherein: The driving method further includes: In the reset phase of an image frame, the first initialization sub-circuit responds to the first reset signal received at the first reset signal terminal, and transmits the first initialization signal received at the first initialization signal terminal to the fourth node to initialize the potential of the fourth node; after a preset time interval, the third initialization sub-circuit responds to the third reset signal received at the third reset signal terminal, and transmits the third initialization signal received at the third initialization signal terminal to the third node, and the compensation sub-circuit responds to the compensation control signal received at the compensation signal terminal, and the compensation sub-circuit is turned on, so that the third initialization signal is transmitted to the first node to initialize the potential of the first node.

18. A display substrate, wherein: The display substrate comprises: substrate substrate; A pixel circuit according to any one of claims 1 to 15 disposed on the substrate; and A light emitting element is disposed on the base substrate, and the light emitting element is coupled to the pixel circuit.

19. A display substrate, wherein: The display substrate comprises: substrate substrate; A first semiconductor layer disposed on the substrate; A first conductive layer disposed on a side of the first semiconductor layer away from the substrate; A second conductive layer disposed on a side of the first conductive layer away from the base substrate; A second semiconductor layer disposed on a side of the second conductive layer away from the substrate, wherein the second semiconductor layer comprises an oxide semiconductor; A third conductive layer disposed on a side of the second semiconductor layer away from the substrate; A fourth conductive layer disposed on a side of the third conductive layer away from the base substrate; and A fifth conductive layer is disposed on a side of the fourth conductive layer away from the base substrate, Wherein, the display substrate further includes a pixel circuit disposed on the base substrate, the pixel circuit includes a data writing subcircuit, a driving subcircuit, a compensation subcircuit, a first light-emitting control subcircuit, a second light-emitting control subcircuit, a first initialization subcircuit, a second initialization subcircuit and a third initialization subcircuit, the second initialization subcircuit includes a first transistor, the compensation subcircuit includes a second transistor, the driving subcircuit includes a third transistor, the data writing subcircuit includes a fourth transistor, the first light-emitting control subcircuit includes a fifth transistor, the second light-emitting control subcircuit includes a sixth transistor, the first initialization subcircuit includes a seventh transistor, and the third initialization subcircuit includes an eighth transistor; The display substrate further includes: a second reset signal line, a first light-emitting control line and a second light-emitting control line located in the first conductive layer; a third initialization signal line, a first sub-line of a compensation signal line, a first sub-line of a first reset signal line and a first sub-line of a scan signal line located in the second conductive layer; a second initialization signal line, a first initialization signal line, a second sub-line of a compensation signal line, a second sub-line of a first reset signal line and a second sub-line of a scan signal line located in the third conductive layer; The orthographic projection of the first sub-line of the compensation signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the substrate, the orthographic projection of the second sub-line of the compensation signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the substrate, the portion where the first sub-line of the compensation signal line overlaps with the second semiconductor layer is the first sub-control electrode of the second transistor, and the portion where the second sub-line of the compensation signal line overlaps with the second semiconductor layer is the second sub-control electrode of the second transistor; The orthographic projection of the first sub-line of the scanning signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the substrate, the orthographic projection of the second sub-line of the scanning signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the substrate, the portion where the first sub-line of the scanning signal line overlaps with the second semiconductor layer is the first sub-control electrode of the fourth transistor, and the portion where the second sub-line of the scanning signal line overlaps with the second semiconductor layer is the second sub-control electrode of the fourth transistor Extreme; and The orthographic projection of the first sub-line of the first reset signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the substrate, the orthographic projection of the second sub-line of the first reset signal line on the substrate at least partially overlaps with the orthographic projection of the second semiconductor layer on the substrate, the portion where the first sub-line of the first reset signal line overlaps with the second semiconductor layer is the first sub-control electrode of the seventh transistor, and the portion where the second sub-line of the first reset signal line overlaps with the second semiconductor layer is the second sub-control electrode of the seventh transistor.

20. The display substrate according to claim 19, wherein: The display substrate further comprises a plurality of connection signal lines located in the fourth conductive layer; At least one of the first initialization signal line, the second initialization signal line and the third initialization signal line extends along a first direction, the multiple connection signal lines extend along a second direction respectively, and at least one of the first initialization signal line, the second initialization signal line and the third initialization signal line is electrically connected to the multiple connection signal lines to form a mesh structure.

21. The display substrate according to claim 19 or 20, wherein: The pixel circuit further includes a storage subcircuit and a potential holding subcircuit, the storage subcircuit includes a first capacitor, and the potential holding subcircuit includes a second capacitor; The display substrate further includes a first conductive portion located in the first conductive layer, a second conductive portion located in the second conductive layer, a third conductive portion located in the fourth conductive layer, and a first voltage signal line located in the fifth conductive layer, wherein the first voltage signal line includes a widened portion; The first conductive portion is a first end of the first capacitor, the second conductive portion and the third conductive portion electrically connected to each other are a second end of the first capacitor and a second end of the second capacitor, and the widened portion of the first voltage signal line is a first end of the second capacitor; as well as The orthographic projection of the widened portion of the first voltage signal line on the base substrate covers the orthographic projection of each of the first conductive portion, the second conductive portion, and the third conductive portion on the base substrate.

22. A display device comprising the display substrate according to any one of claims 18 to 21.

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