Circuit board and semiconductor package including same

Abstract

A circuit board according to an embodiment includes an insulating layer; and a circuit layer disposed on the insulating layer and having a lower surface contacting the insulating layer and an upper surface facing the lower surface, in which the circuit layer includes a plurality of through-holes passing through the upper surface and the lower surface, and wherein a diameter of each of the plurality of through holes is equal to or greater than a separation distance between two of the plurality of through holes disposed adjacent to each other.

Description

Technical Field

[0001] Embodiments relate to a circuit board and a semiconductor package including the same. Background Art

[0002] As the performance of electrical / electronic products advances, technologies for arranging a greater number of semiconductor devices on a semiconductor package substrate of limited size are being proposed and studied. However, since general semiconductor packaging is based on mounting a single semiconductor device, there are limitations in achieving desired performance.

[0003] Therefore, a semiconductor package for mounting a plurality of semiconductor devices using a plurality of circuit boards has recently been provided. This semiconductor package has a structure in which a plurality of semiconductor devices are connected to each other in a horizontal direction and / or a vertical direction on a circuit board. Therefore, the semiconductor package has the advantages of effectively using the mounting area of ​​the semiconductor device and transmitting a high-speed signal through a short signal transmission path between the semiconductor devices.

[0004] Moreover, as the number of semiconductor devices and / or the size of each semiconductor device increases in accordance with the trend of high integration, or as the functional components of semiconductor devices are divided, semiconductor packaging used in products providing the Internet of Things (IoT), self-driving cars, and high-performance servers is expanding the concept to semiconductor chiplets.

[0005] On the other hand, as the number of semiconductor devices and / or semiconductor chiplets mounted on the semiconductor package increases, the area of ​​the circuit board and the semiconductor package tends to increase. Moreover, as the area of ​​the circuit board and the semiconductor package increases, the area and / or wiring density of the circuit layer arranged on the circuit board also increases. When the area and / or wiring density of the circuit layer increases, a problem arises that the gas generated from the insulating layer in contact with the circuit layer is not fully discharged, and therefore the surface of the insulating layer and / or the circuit layer may swell due to the gas that has not been discharged. Therefore, mechanical reliability problems of peeling of the insulating layer and / or the circuit layer may occur. Summary of the invention

[0006] Technical issues

[0007] The embodiment provides a circuit board having a new structure and a semiconductor package including the same.

[0008] Furthermore, embodiments provide a circuit board having improved adhesion between an insulating layer and a circuit layer, and a semiconductor package including the circuit board.

[0009] Furthermore, embodiments provide a circuit board having improved gas exhaust characteristics and a semiconductor package including the same.

[0010] Technical problems to be solved by the proposed embodiments are not limited to the above-mentioned technical problems, and other unmentioned technical problems may be clearly understood by those skilled in the art to which the embodiments pertain from the following description.

[0011] Technical Solution

[0012] According to an embodiment, a circuit board includes an insulating layer; and a circuit layer, which is arranged on the insulating layer and has a lower surface contacting the insulating layer and an upper surface facing the lower surface, wherein the circuit layer includes a plurality of through holes passing through the upper surface and the lower surface, and wherein a diameter of each of the plurality of through holes is equal to or greater than a separation distance between two through holes arranged adjacent to each other among the plurality of through holes.

[0013] In addition, the diameter of each of the multiple through holes is different from each other, the separation distance between two through holes arranged adjacent to each other in the multiple through holes is different from each other, and the diameter of the smallest through hole in the multiple through holes is equal to or greater than the maximum separation distance among the separation distances between two through holes arranged adjacent to each other.

[0014] Furthermore, a ratio of a diameter of the through hole to a plane area of ​​the insulating layer satisfies a range of 0.0000825 to 0.000147.

[0015] Furthermore, a ratio of a plane area of ​​the through hole to a plane area of ​​the insulating layer satisfies a range of 0.00025905 to 0.0004605.

[0016] In addition, the plane area of ​​the insulation layer is 1500mm 2 Up to 2000mm 2 .

[0017] Furthermore, at least one of the plurality of through holes has a diameter of 165 μm to 220 μm.

[0018] In addition, at least one of the plurality of through holes has a plane area satisfying 518.1 μm 2 To 690.8μm 2 range.

[0019] Furthermore, the circuit layer includes a plurality of circuit patterns spaced apart in a horizontal direction, a plurality of through holes are respectively disposed in the plurality of circuit patterns, and a space between the plurality of circuit patterns is smaller than a diameter of the through hole.

[0020] In addition, the circuit board further includes a through electrode penetrating the insulating layer and connected to the circuit layer, and wherein a diameter of the through hole is greater than a width of the through electrode in a horizontal direction.

[0021] Furthermore, each of the plurality of through holes is not connected to the outer surface of the circuit layer and does not overlap with the through electrode in the vertical direction.

[0022] Furthermore, the diameter of the through hole is 2.5 times or more the width of the through electrode.

[0023] Furthermore, the insulating layer is composed of a plurality of layers, the circuit layer is disposed at the uppermost layer, and the through-holes of the circuit layer are filled with a protective layer disposed on the circuit layer.

[0024] Furthermore, the insulating layer includes a first insulating layer and a second insulating layer disposed on the first insulating layer, the circuit layer is disposed between the first insulating layer and the second insulating layer, and the through hole is filled with a second insulating material.

[0025] Furthermore, the circuit board includes a plurality of circuit layers spaced apart in a vertical direction, and each of the ratios is a ratio of through holes provided in any one of the circuit layers.

[0026] In addition, the circuit board of the embodiment includes an insulating layer; and a first circuit layer arranged on the upper surface of the insulating layer; the first circuit layer is divided into a first area and a second area along a horizontal direction; the first area of ​​the first circuit layer includes a plurality of first through holes passing through the upper surface and the lower surface of the first circuit layer; the second area of ​​the first circuit layer includes a plurality of second through holes passing through the upper surface and the lower surface of the first circuit layer; and the diameter of each of the plurality of first through holes is smaller than the diameter of each of the plurality of second through holes.

[0027] In addition, the circuit board also includes a second circuit layer arranged on the lower surface of the insulating layer, the second circuit layer includes a first circuit pattern vertically overlapping with the first area of ​​the first circuit layer and a second circuit pattern vertically overlapping with the second area of ​​the first circuit layer, and the wiring density of the first circuit pattern is different from the wiring density of the second circuit pattern.

[0028] Furthermore, the wiring density of the second circuit pattern is greater than the wiring density of the first circuit pattern.

[0029] Furthermore, the second circuit pattern includes an impedance matching circuit pattern for impedance matching.

[0030] Furthermore, a separation distance between two closest first through-holes among the plurality of first through-holes is greater than a separation distance between two closest second through-holes among the plurality of second through-holes.

[0031] In addition, the first circuit layer is further divided into a third area corresponding to an edge area of ​​an upper surface of the first circuit layer, and the third area of ​​the first circuit layer includes a plurality of third through holes passing through the upper and lower surfaces of the first circuit layer.

[0032] Furthermore, a diameter of the third through hole is smaller than a diameter of each of the first through hole and the second through hole.

[0033] Furthermore, a separation distance between two closest third through holes is greater than a separation distance between two closest first through holes and a separation distance between two closest second through holes.

[0034] Furthermore, a diameter of each of the plurality of first through holes is greater than or equal to a separation distance between two of the plurality of first through holes that are disposed closest to each other.

[0035] Furthermore, the two first through holes disposed closest to each other are two first through holes located diagonally to each other in the horizontal direction in the first circuit layer.

[0036] In addition, the diameters of the multiple first through holes are different from each other, the diameter of each of the first through holes is different from the separation distance between two first through holes arranged adjacent to each other, and the minimum diameter of the multiple first through holes is greater than the maximum separation distance between two first through holes arranged adjacent to each other.

[0037] In addition, a ratio of a diameter of the first through hole to a plane area of ​​the insulating layer satisfies a range of 0.0000825 to 0.000147.

[0038] In addition, a ratio of a plane area of ​​the first through hole to a plane area of ​​the insulating layer satisfies a range of 0.00025905 to 0.0004605.

[0039] Furthermore, the ratio is a ratio to the first through-hole provided in a single circuit layer disposed on the insulating layer.

[0040] In addition, the plane area of ​​the insulation layer is 1500mm 2 Up to 2000mm 2 .

[0041] Furthermore, at least one of the plurality of first through holes has a diameter of 165 μm to 220 μm.

[0042] In addition, a plane area of ​​at least one of the plurality of first through holes satisfies 518.1 μm 2 To 690.8μm 2 range.

[0043] Furthermore, the circuit board further includes a through electrode passing through the insulating layer, and a width of the through electrode is different from a diameter of each of the first to third through holes.

[0044] Furthermore, the through electrode has an inclination whose width gradually changes from the upper surface toward the lower surface of the insulating layer, and a diameter of each of the first to third through holes is larger than a width of a region having a maximum width in the through electrode.

[0045] Furthermore, each of the first to third through holes does not vertically overlap with the through-electrode.

[0046] In addition, the first circuit layer includes a fourth through hole vertically overlapping the through electrode; and a pad disposed in the fourth through hole, and a diameter of the fourth through hole is smaller than a diameter of each of the first through holes to the third through holes.

[0047] Furthermore, the circuit pattern is not provided in the inner regions of the first to third through holes, and the inner regions of the first to third through holes are filled with another insulating layer or a protective layer provided on the insulating layer.

[0048] Beneficial Effects

[0049] The semiconductor package of the embodiment may include an insulating layer and a circuit layer disposed on the insulating layer. In this case, the circuit layer may include at least one through hole. That is, the circuit layer may include a plurality of circuit patterns spaced apart in a horizontal direction. In addition, the through hole may have a different meaning from the space between the plurality of circuit patterns. That is, the through hole may refer to a through hole passing through the upper surface and the lower surface of each circuit pattern.

[0050] Therefore, the embodiment can use the through hole provided in the circuit layer to allow the gas generated in the insulating layer to be discharged well onto the circuit layer. In this way, the embodiment can prevent the insulating layer and / or the circuit layer from expanding due to the gas. Therefore, the embodiment can improve the adhesion between multiple insulating layers and the adhesion between the insulating layer and the circuit layer. In this way, the embodiment can improve the physical reliability of the circuit board.

[0051] In addition, the circuit layer of the embodiment may be provided with a plurality of through holes. At this time, the diameter W3 of each of the plurality of through holes provided in the circuit layer may be greater than or equal to the separation distance between two mutually adjacent through holes in the plurality of through holes. In other words, the diameter of each of the plurality of through holes provided in the circuit layer may be equal to or greater than the separation distance between two mutually adjacent through holes in the plurality of through holes.

[0052] At this time, if the diameter of each of the plurality of through holes is smaller than the separation distance between two mutually adjacent through holes among the plurality of through holes, the gas generated in the insulating layer may not be easily discharged to the outside of the circuit board. In other words, the fact that the diameter is smaller than the separation distance may mean that, based on the area in which the through hole is set in the circuit layer, the area in which the gas cannot be discharged via the through hole is larger than the area in which the gas can be discharged. In addition, if the diameter of the through hole is smaller than the separation distance between the plurality of through holes, the gas may not be discharged well and may remain in the insulating layer, which may cause degradation of physical properties.

[0053] Therefore, the embodiment allows each diameter of the plurality of through holes provided in the circuit layer to be equal to or greater than the separation distance between two adjacent through holes in the plurality of through holes. Therefore, the embodiment can completely discharge the gas without residual gas in the insulating layer. Therefore, the embodiment can further improve the physical properties of the circuit board and the semiconductor package.

[0054] At the same time, at this time, the diameter of at least one of the multiple through holes can be different from at least one other diameter. The separation distances of multiple through holes adjacent to each other can be different from each other. At this time, the embodiment allows the diameter of the through hole with the smallest diameter in the multiple through holes to be equal to or greater than the maximum separation distance in the multiple adjacent through holes. In this way, the embodiment can further improve the physical reliability of the circuit board and the semiconductor package by allowing better discharge of the gas generated in the insulating layer.

[0055] In addition, the circuit layer of the embodiment is provided with a plurality of through holes. In this case, the diameter of at least one of the plurality of through holes may be determined based on the plane area of ​​the circuit board and / or the insulating layer.

[0056] For example, the ratio of the diameter of the through hole to the plane area of ​​the insulating layer may satisfy the range of 0.0000825 to 0.000147. In addition, the ratio of the plane area of ​​the through hole to the plane area of ​​the insulating layer may satisfy the range of 0.00025905 to 0.0004605. In this case, the plane area of ​​the insulating layer may be 1500 mm 2 Up to 2000mm 2 In addition, at least one of the plurality of through holes may have a diameter of 165 μm to 220 μm. In addition, a plane area of ​​at least one of the plurality of through holes may satisfy 518.1 μm 2 To 690.8μm 2 range. In addition, the embodiment allows the diameter of at least one of the multiple through holes provided in the circuit layer to be 165μm or greater. In this case, the diameter of at least one of the multiple through holes provided in the circuit layer may be 165μm or greater. That is, if the diameter of the through hole is less than 165μm, the gas generated by the insulating layer having a planar area may not be properly discharged to the upper side of the circuit layer. In addition, when the gas is not discharged, the adhesion may be reduced due to the expansion of the circuit layer and / or the insulating layer. Therefore, the embodiment can ensure that at least one of the multiple through holes has a diameter of 165μm or greater, so that the gas generated from the insulating layer can be properly discharged, and thereby the physical properties can be further improved.

[0057] In addition, the diameter of the through hole may be 220 μm or less. Preferably, if the diameter of the through hole exceeds 220 μm, the impedance characteristics between multiple circuit layers may change. In addition, if the diameter of the through hole exceeds 220 μm, the density and / or area of ​​the circuit layer may be reduced, and thus the circuit board and the semiconductor package may be significantly warped in a specific direction. Therefore, by making the diameter of the through hole 220 μm or less, the embodiment can improve the rigidity of the circuit board and the semiconductor package while preventing the impedance characteristics between multiple circuit layers from changing.

[0058] In addition, the through hole of the circuit layer may not vertically overlap with the through electrode passing through the insulating layer. In other words, the through electrode may refer to a through electrode directly connected to the circuit layer. In addition, the through electrode directly connected to the circuit layer may not vertically overlap with the through hole. Therefore, the embodiment can allow the gas generated in the insulating layer to be well discharged without deteriorating the electrical signal transmission characteristics of the through electrode.

[0059] In addition, the through hole of the circuit layer may be larger than the width of the region having the largest width in the through electrode. In this way, the embodiment may further improve the gas exhaust characteristics through the through hole of the circuit layer.

[0060] At the same time, the circuit layer of the embodiment may include a first circuit layer disposed on the insulating layer and a second circuit layer disposed under the insulating layer. At this time, the first circuit layer may be divided into a plurality of regions. For example, the first circuit layer may include a first and a second region. The first region of the first circuit layer may be a region vertically overlapping with the first electrode pattern of the second circuit layer. The second region of the second circuit layer may be a region vertically overlapping with the second electrode pattern of the second circuit layer. In addition, the first circuit layer may include a third region closer to the edge of the first circuit layer than the first and second regions.

[0061] At this time, the first to third regions of the first circuit layer may each be provided with a through hole. For example, the first region of the first circuit layer may be provided with a plurality of first through holes. For example, the second region of the first circuit layer may be provided with a plurality of second through holes. For example, the third region of the first circuit layer may be provided with a plurality of third through holes. At this time, the diameter of the first through hole provided in the first circuit pattern, the diameter of the second through hole provided in the second circuit pattern, and the diameter of the third through hole provided in the third circuit pattern may be different from each other.

[0062] Preferably, the second electrode pattern of the second circuit layer may have a higher wiring density than other circuit patterns of the second circuit layer. For example, the second circuit pattern of the second circuit layer may include a circuit pattern for impedance matching.

[0063] Therefore, the diameter of the second through hole provided in the second area of ​​the first circuit layer can be larger than the diameter of each of the first and third through holes. In this way, in an embodiment, a smoother gas discharge can be achieved in an area vertically overlapping with the second circuit pattern of the second circuit layer, and the second circuit pattern of the second circuit layer has a high wiring density in the entire area of ​​the insulating layer. In addition, in an embodiment, the diameter of the second through hole provided in the second area of ​​the second circuit layer is made larger than the diameter of other through holes, so that the metal ratio of the second area can be reduced. In this way, the embodiment can prevent the impedance characteristics of the second circuit pattern of the second circuit layer from being changed due to the first circuit layer. In this way, the embodiment can further improve the physical reliability and / or electrical characteristics of the semiconductor package.

[0064] At the same time, the third region of the first circuit layer can be arranged on the edge region of the insulating layer. At this time, the diameter of the third through hole arranged in the third region of the first circuit layer can be smaller than each diameter of the first through hole and the second through hole. In this way, the embodiment can ensure the rigidity of the circuit board and the semiconductor package through the third region of the first circuit layer. In this way, the embodiment can further improve the physical and electrical properties of the circuit board.

[0065] At this time, the diameter of each of the first through hole, the second through hole and the third through hole can be greater than the width of the through electrode passing through the insulating layer. In this way, the embodiment can completely remove the gas that may remain in the insulating layer, and thus can further improve the adhesion between the insulating layer and the circuit layer.

[0066] In addition, the separation distance between two adjacent second through holes in the plurality of second through holes can be respectively smaller than the separation distance between two adjacent first through holes in the plurality of first through holes and the separation distance between two adjacent third through holes in the plurality of third through holes. In addition, the separation distance between two adjacent third through holes in the plurality of third through holes can be greater than the separation distance between two adjacent first through holes in the plurality of first through holes and the separation distance between two adjacent second through holes in the plurality of second through holes. Therefore, the embodiment can further improve the adhesion between the insulating layer and the circuit layer without changing the characteristics (e.g., impedance characteristics) of the circuit layer, while preventing the circuit board from warping in a specific direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0067] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment.

[0068] Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment.

[0069] Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment.

[0070] Figure 1d is a cross-sectional view showing a semiconductor package according to a fourth embodiment.

[0071] Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment.

[0072] Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment.

[0073] Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0074] Figure 2 is a cross-sectional view showing a circuit board according to the first embodiment.

[0075] Figure 3 It is shown Figure 2 A plan view of some of the layers of a circuit board.

[0076] Figure 4 It is used to explain Figure 3 A plan view of the relationship between the through-electrode and the through-hole in a plan view.

[0077] Figure 5 and Figure 6 : is a graph for explaining the adhesion characteristics of the circuit boards of the comparative example and the first embodiment.

[0078] Figure 7 It is used to explain Figure 3 A plan view of a modified example of a circuit board.

[0079] Figure 8 is a diagram showing a method according to the second embodiment Figure 2 A plan view of some of the layers of a circuit board.

[0080] Fig. 9 is a diagram showing a method according to the third embodiment Figure 2 A plan view of some of the layers of a circuit board.

[0081] Fig.10 It is used to explain Figure 8 A plan view of the relationship between the through-electrode and the through-hole in a plan view.

[0082] Fig.11 According to the fourth embodiment Figure 2 A magnified view of some of the layers of the circuit board.

[0083] Fig.12 is used to explain the settings in Fig.11 A plan view of diameters of a plurality of through holes in a first circuit layer.

[0084] Fig.13 It is used to explain Fig.11 A plan view of the wiring density of the second circuit layer.

[0085] Fig.14 It is used to explain Fig.12 A plan view of the relationship between the through-electrode and the through-hole in a plan view. DETAILED DESCRIPTION

[0086] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0087] However, the spirit and scope of the present disclosure are not limited to a part of the described embodiments and may be implemented in various other forms, and one or more of the elements in the embodiments may be selectively combined and re-presented within the spirit and scope of the present disclosure.

[0088] In addition, unless otherwise clearly defined and described, the terms (including technical and scientific terms) used in the embodiments of the present disclosure may be interpreted as having the same meaning as that generally understood by a person of ordinary skill in the art to which the present disclosure belongs, and terms such as those defined in commonly used dictionaries may be interpreted as having meanings consistent with their meanings in the context of the relevant technology. In addition, the terms used in the embodiments of the present disclosure are used to describe the embodiments and are not intended to limit the present disclosure.

[0089] In the present specification, unless otherwise specified in a phrase, a singular form may also include a plural form, and when described as "at least one (or more) of A (and), B, and C", the singular form may include at least one of all combinations that can be combined with A, B, and C. In addition, when describing elements of the embodiments of the present disclosure, terms such as first, second, A, B, (a), and (b) may be used.

[0090] These terms are only used to distinguish an element from other elements, and these terms are not limited to the nature, order or sequence of the elements. In addition, when an element is described as being "connected", "coupled" or "in contact with" another element, it may include not only the case when the element is directly "connected", "coupled" or "in contact with" the other element, but also the case where the element is "connected", "coupled" or "in contact with" the element through another element between the element and the other elements.

[0091] Furthermore, when described as being formed or disposed “on (above)” or “below (below)” of each element, “on (above)” or “below (below)” may include not only the case when two elements are directly connected to each other but also the case when one or more other elements are formed or disposed between the two elements. Furthermore, when expressed as “on (above)” or “below (below)”, it may include not only an upper direction based on one element but also a lower direction.

[0092] The terms used in this application are only used to describe specific embodiments and are not intended to limit the present invention. Unless the context clearly indicates otherwise, the singular forms "one", "one" and "said" used herein are also intended to include plural forms. It should also be understood that the terms "include", "comprise", "include" and / or "include" are used in this article to specify the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or their groups.

[0093] Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as those commonly understood by ordinary technicians in the field to which the present invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with the meaning in the relevant technical background, and unless clearly defined in this application, they cannot be interpreted in an ideal or overly formal sense.

[0094] Hereinafter, the embodiments will be described in detail with reference to the accompanying drawings. However, regardless of the reference numerals, the same or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0095] Before describing the embodiment, an electronic device to which the semiconductor package of the embodiment is applied will be briefly described. The electronic device may be a smartphone, a personal digital assistant, a digital video camera, a digital still camera, a vehicle, a high-performance server, a network system, a computer, a monitor, a tablet computer, a laptop computer, a netbook, a television, a video game, a smart watch, an automobile, etc. However, the embodiment is not limited thereto, and may be any other electronic device that processes data other than these.

[0096] The electronic device includes a mainboard (not shown). The mainboard can be physically and / or electrically connected to various components. For example, the mainboard can be connected to the semiconductor package of the embodiment. In addition, the semiconductor package includes a circuit board, a semiconductor chip, a bonding portion that electrically connects the semiconductor device to the circuit board, a resin portion that fills the space between the semiconductor device and the circuit board, and a molded portion that covers the semiconductor device as a whole.

[0097] Semiconductor devices may include active devices and / or passive devices, and may have various functions. Active devices may be in the form of integrated circuits (ICs), in which hundreds to millions of transistors are integrated into one semiconductor device, and may be, for example, logic chips or memory chips. For example, a logic chip may be an application processor (AP) device including at least one of a central processing unit (CPU), a graphics processing unit (GPU), a digital signal processor, an encryption processor, a microprocessor, a microprocessor, or a microcontroller, or an analog-data converter, an application specific integrated chip (application specific IC, ASIC), or may be a device set including a specific combination of those listed so far. The memory chip may be a stacked memory, such as HBM. In addition, the memory chip may include memory chips such as volatile memory (such as DRAM), non-volatile storage (such as ROM), or flash memory.

[0098] The semiconductor package of the embodiment can be any one of CSP (Chip Scale Package), FC-CSP (Flip Chip-Chip Scale Package), FC-BGA (Flip Chip-Chip Scale Package), POP (Package on Package) and SIP (System in Package), but is not limited to these.

[0099] Hereinafter, a semiconductor package including a circuit board according to an embodiment will be described. The semiconductor package according to the embodiment may have various types of package structures including a circuit board to be described later. In addition, the circuit board described in the embodiment may be Figures 1a to 1g Any one of the first circuit board and the second circuit board shown in any one of .

[0100] Figure 1a is a cross-sectional view showing a semiconductor package according to a first embodiment, Figure 1b is a cross-sectional view showing a semiconductor package according to a second embodiment, Figure 1c is a cross-sectional view showing a semiconductor package according to a third embodiment, Figure 1dis a cross-sectional view showing a semiconductor package according to a fourth embodiment, Figure 1e is a cross-sectional view showing a semiconductor package according to a fifth embodiment, Figure 1f is a cross-sectional view showing a semiconductor package according to a sixth embodiment, and Figure 1g is a cross-sectional view showing a semiconductor package according to a seventh embodiment.

[0101] refer to Figure 1a , the semiconductor package according to the first embodiment may include a first circuit board 1100 , a second circuit board 1200 , and a semiconductor device 1300 .

[0102] The first circuit board 1100 refers to a semiconductor package substrate. For example, the first circuit board 1100 may provide a space to which at least one external circuit board is coupled. The external circuit board may refer to a second circuit board 1200 coupled to the first circuit board 1100. In addition, the external circuit board may refer to a main board included in an electronic device coupled to the lower portion of the first circuit board 1100.

[0103] In addition, although not shown in the drawings, the first circuit board 1100 may provide a space in which at least one semiconductor device is mounted.

[0104] The first circuit board 1100 includes at least one insulating layer, a circuit layer disposed on the at least one insulating layer, and a through-electrode passing through the at least one insulating layer.

[0105] The second circuit board 1200 is disposed on the first circuit board 1100. The second circuit board 1200 may be an interposer. For example, the second circuit board 1200 may provide a space in which at least one semiconductor device is installed. The second circuit board 1200 may be connected to at least one semiconductor device 1300. For example, the second circuit board 1200 may provide a space in which a first semiconductor device 1310 and a second semiconductor device 1320 are installed. The second circuit board 1200 may electrically connect the first semiconductor device 1310 and the second semiconductor device 1320 and the first circuit board 1100, and at the same time electrically connect the first semiconductor device 1310 and the second semiconductor device 1320. That is, the second circuit board 1200 may perform a horizontal connection function between a plurality of semiconductor devices and a vertical connection function between a semiconductor device and a package circuit substrate.

[0106] Figure 1a It is shown that the first semiconductor device 1310 and the second semiconductor device 1320 are disposed on the second circuit board 1200, but is not limited thereto. For example, one semiconductor device may be disposed on the second circuit board 1200, or alternatively, three or more semiconductor devices may be disposed.

[0107] The second circuit board 1200 may be disposed between at least one semiconductor device 1300 and the first circuit board 1100. In one embodiment, the second circuit board 1200 may be an active interposer used as a semiconductor device. When the second circuit board 1200 is used as a semiconductor device, the semiconductor package of the embodiment may have a structure vertically stacked on the first circuit board 1100, and may have the functions of multiple logic chips. Having the function of a logic chip may mean that it may have the functions of an active device and a passive device. In the case of an active device, unlike a passive device, the characteristics of current and voltage may not be linear, and in the case of an active interposer, it may have the function of an active device. In addition, the active interposer may perform the function of a corresponding logic chip while performing a signal transmission function between the second logic chip disposed thereon and the first circuit board 1100. The second circuit board 1200 according to another embodiment may be a passive interposer. For example, the second circuit board 1200 may perform a signal relay function between the semiconductor device 1300 and the first circuit board 1100, and may have a passive device function such as a resistor, a capacitor, an inductor, and the like. For example, due to 5G, Internet of Things (IoT), improved image quality, increased communication speed, etc., the number of terminals of the semiconductor device 1300 is gradually increasing. That is, the number of terminals provided in the semiconductor device 1300 is increasing, so the width of the terminal or the interval between the plurality of terminals is decreasing. In this case, the first circuit board 1100 can be connected to the mainboard of the electronic device. Therefore, in order to have a width and interval for connecting the electrodes provided on the first circuit board 1100 to the semiconductor device 1300 and the mainboard respectively, there is a problem that the thickness of the first circuit board 100 increases or the layer structure of the first circuit board 1000 is complicated. Therefore, in the first embodiment, the second circuit board 1200 can be provided on the first circuit board 1100 and the semiconductor device 1300. In addition, the second circuit board 1200 may include electrodes having a fine width and interval corresponding to the terminals of the semiconductor device 1300.

[0108] The first connection portion 1410 is disposed between the first circuit board 1100 and the second circuit board 1200. The first connection portion 1410 electrically connects the first circuit board 1100 and the second circuit board 1200 while bonding the second electrical substrate 1200 to the first circuit board 1100. The second connection portion 1420 is disposed between the second circuit board 1200 and the semiconductor device 1300. The second connection portion 1420 can electrically connect the semiconductor device 1300 and the second circuit board 1200 while bonding the semiconductor device 1300 to the second circuit board 1200. The third connection portion 1430 is disposed on the lower surface of the first circuit board 1100. The third connection portion 1430 can electrically connect the first circuit board 1100 and the main board while bonding the first circuit board 1100 to the main board.

[0109] At this time, the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 can be electrically connected between multiple components by using at least one bonding method of wire bonding, solder bonding, and metal-to-metal direct bonding. That is, since the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 have the function of electrically connecting multiple components, when metal-to-metal direct bonding is used, the connection portion of the semiconductor package can be understood as an electrical connection portion, rather than solder or wire.

[0110] The wire bonding method may refer to electrically connecting multiple components using a wire such as gold (Au). In addition, the solder bonding method may electrically connect multiple components using a material containing at least one of Sn, Ag, and Cu. In addition, the metal-to-metal direct bonding method may refer to recrystallization by applying heat and pressure between multiple components without the presence of solder, wires, conductive adhesives, etc. In addition, multiple components can be directly bonded. In addition, the metal-to-metal direct bonding method may refer to a bonding method through the second connection portion 1420. In this case, the second connection portion 1420 may refer to a metal layer formed between multiple components by recrystallization.

[0111] The first connection part 1410, the second connection part 1420 and the third connection part 1430 may couple the plurality of components to each other by a thermal compression (TC) bonding method. Thermocompression bonding may refer to a method of directly bonding the plurality of components by applying heat and pressure to the first connection part 1410, the second connection part 1420 and the third connection part 1430.

[0112] In this case, at least one of the first circuit board 1100 and the second circuit board 1200 may include a protrusion disposed in an electrode, and the first connection portion 1410, the second connection portion 1420, and the third connection portion 1430 are disposed on the electrode. The protrusion may protrude outward from the first circuit board 1100 or the second circuit board 1200. The protrusion may be referred to as a bump, a pillar, or a post. Preferably, the protrusion may refer to an electrode provided with a second connection portion 1420 for bonding with the semiconductor device 1300 in an electrode of the second circuit board 1200. That is, as the pitch of the terminal of the semiconductor device 1300 becomes thinner, a short circuit may occur between the plurality of second connection portions 1420 respectively connected to the plurality of terminals of the semiconductor device 1300 by a conductive adhesive such as solder. Therefore, in an embodiment, thermal compression bonding may be performed to reduce the volume of the second connection portion 1420. In addition, in order to ensure diffusion prevention and alignment to prevent the intermetallic compound (IMC) formed between the conductive adhesive such as solder and the protrusion from diffusing into the inserter and / or the circuit board, the protrusion may be included in an electrode of the second circuit board 1200 on which the second connection portion 1420 is provided.

[0113] At the same time, reference Figure 1b, the semiconductor package of the second embodiment is different from the semiconductor package of the first embodiment in that the connecting member 1210 is disposed on the second circuit board 1200. The connecting member 1210 may be called a bridge. For example, the connecting member 1210 may include a redistribution layer. The connecting member 1210 may perform the function of electrically connecting a plurality of semiconductor devices horizontally to each other. For example, since the semiconductor device should generally have a too large area, the connecting member 1210 may include a redistribution layer. Since there are large differences between the semiconductor package and the semiconductor device in terms of the width or spacing of the circuit pattern, the circuit pattern is required to buffer the electrical connection. The buffering effect may mean having a size between the width or spacing of the circuit pattern of the semiconductor package and the width or spacing of the circuit pattern of the semiconductor device, and the redistribution layer may include the function of performing the buffering effect. In one embodiment, the connecting member 1210 may be a silicon bridge. That is, the connecting member 1210 may include a silicon substrate and a redistribution layer disposed on the silicon substrate. In another embodiment, the connecting member 1210 may be an organic bridge. For example, the connecting member 1210 may include an organic material. For example, the connecting member 1210 may include an organic substrate instead of a silicon substrate, the organic substrate including an organic material. In particular, when the connecting member 1210 includes an organic material, the structure of the circuit board according to the following embodiment can more stably protect the connecting member 1210 from stress caused by thermal cycles (such as contraction and / or expansion of the semiconductor package). The connecting member 1210 can be an organic bridge that can smoothly supply power from the lower side to the upper side and minimize the power loss of the supply. In this case, in the case of an inorganic bridge including a silicon substrate, power can be supplied through silicon vias (Through Silicon Via, TSV), but there is a problem of increased process cost of TSV processing and reduced product yield. Therefore, preferably, the connecting member 1210 according to the embodiment is an organic bridge.

[0114] The connecting member 1210 may be embedded in the second circuit board 1200, but is not limited thereto. For example, the connecting member 1210 may be disposed on the second circuit board 1200 to have a protruding structure. In addition, the second circuit board 1200 may include a cavity, and the connecting member 1210 may be disposed in the cavity of the second circuit board 1200. The connecting member 1210 may horizontally connect a plurality of semiconductor devices disposed on the second circuit board 1200.

[0115] refer to Figure 1c , the semiconductor package according to the third embodiment may include a second circuit board 1200 and a semiconductor device 1300. In this case, the semiconductor package of the third embodiment may have a structure in which the first circuit board 1100 is removed, compared with the semiconductor package of the second embodiment.

[0116] That is, the second circuit board 1200 of the third embodiment can be used as a semiconductor package substrate while performing an interposer function. The first connection portion 1410 provided on the lower surface of the second circuit board 1200 can couple the second circuit board 1200 to a main board of an electronic device.

[0117] refer to Figure 1d , the semiconductor package according to the fourth embodiment may include a first circuit board 1100 and a semiconductor device 1300. In this case, compared with the semiconductor package of the second embodiment, the package of the fourth embodiment may have a structure in which the second circuit board 1200 is removed. That is, the first circuit board 1100 of the fourth embodiment may be used as a packaging circuit board while also performing the function of connecting the semiconductor device 1300 and the main board. To this end, the first circuit board 1100 may include a connecting member 1110 for connecting a plurality of semiconductor devices. The connecting member 1110 may be a silicon bridge or an organic material bridge connecting a plurality of semiconductor devices.

[0118] refer to Figure 1e , compared with the semiconductor package of the fourth embodiment, the package of the fifth embodiment may further include a third semiconductor device 1330. To this end, the fourth connection portion 1440 may be provided on the lower surface of the first circuit board 1100. In addition, the third semiconductor device 33 may be provided on the fourth connection portion 1440. That is, the semiconductor package of the fifth embodiment may have a structure in which semiconductor devices are mounted on the upper side and the lower side, respectively. In this case, the third semiconductor device 1330 may have a structure provided on the lower side. Figure 1c The structure on the lower surface of the second circuit board 1200 in the semiconductor package.

[0119] refer to Figure 1f, the semiconductor package according to the sixth embodiment may include a first circuit board 1100. The first semiconductor device 1310 may be disposed on the first circuit board 1100. To this end, the first connection portion 1410 may be disposed between the first circuit board 1100 and the first semiconductor device 1310. In addition, the first circuit board 1100 includes a conductive bonding portion 1450. The conductive bonding portion 1450 may also protrude from the first circuit board 1100 toward the second semiconductor device 1320. The conductive bonding portion 1450 may be referred to as a bump, or may also be referred to as a column. The conductive bonding portion 1450 may be provided to have a protruding structure on an electrode disposed on the uppermost side of the first circuit board 1100. The second semiconductor device 1320 may be provided on the conductive bonding portion 1450. In this case, the second semiconductor device 1320 may be connected to the first circuit board 1100 through the conductive bonding portion 1450. In addition, the second connection portion 1420 may be provided on the first semiconductor device 1310 and the second semiconductor device 1320. Therefore, the second semiconductor device 1320 may be electrically connected to the first semiconductor device 1310 through the second connection portion 1420.

[0120] That is, the second semiconductor device 1320 can be connected to the first circuit board 1100 through the conductive bonding portion 1450, and can also be connected to the first semiconductor device 1310 through the second connection portion 1420. In this case, the second semiconductor device 1320 can receive a power signal and / or power through the conductive bonding portion 1450. In addition, the second semiconductor device 1320 can send and receive communication signals with the first semiconductor device 1310 through the second connection portion 1420. The semiconductor package according to the sixth embodiment provides a power signal and / or power to the second semiconductor device 1320 through the conductive bonding portion 1450, thereby providing sufficient power to drive the second semiconductor element 1320 or to achieve smooth control of power operation. Therefore, the embodiment can improve the driving characteristics of the second semiconductor device 1320. That is, the embodiment can solve the problem of insufficient power provided to the second semiconductor device 1320. In addition, in the embodiment, at least one of the power signal, power and communication signal of the second semiconductor device 1320 is provided through different paths of the conductive bonding portion 1450 and the second connection portion 1420. In this way, the embodiment can solve the problem of loss of communication signal due to power signal. For example, embodiments may minimize mutual interference between communication signals of power signals.

[0121] Meanwhile, the second semiconductor device 1320 in the sixth embodiment may have a POP (Package On Package) structure in which a plurality of semiconductor package substrates are stacked, and may be disposed on the first circuit board 1100. For example, the second semiconductor device 1320 may be a memory package including a memory chip. In addition, the memory package may be coupled to the conductive bonding portion 1450. In this case, the memory package may not be connected to the first semiconductor device 1310.

[0122] refer to Figure 1g , the semiconductor package according to the seventh embodiment may include a first circuit board 1100 , a first connection portion 1410 , a first connection portion 1410 , a semiconductor device 1300 , and a third connection portion 1430 .

[0123] In this case, the semiconductor package of the seventh embodiment is different from that of the fourth embodiment in that the first circuit board 1100 includes a plurality of substrate layers, while the connection member 1110 is removed.

[0124] The first circuit board 1100 includes a plurality of circuit board layers. For example, the first circuit board 1100 may include a first substrate layer 1100A corresponding to the package substrate and a second substrate layer 1100B corresponding to the redistribution layer of the connection member. For example, the semiconductor package of the seventh embodiment may include a first substrate layer 1100A and a second substrate layer 1100B, wherein Figure 1a The first circuit board (semiconductor package substrate 1100) and the second circuit board (interposer 1200) disclosed in the seventh embodiment are formed integrally. The material of the insulating layer of the second substrate layer 1100B may be different from the material of the insulating layer of the first substrate layer 1100A. For example, the material of the insulating layer of the second substrate layer 1100B may include a photocurable material. For example, the second substrate layer 1100B may be a photoimageable dielectric (PID). In addition, since the second substrate layer 1100B includes a photocurable material, the electrode can be miniaturized. Therefore, in the seventh embodiment, the second substrate layer 1100B can be formed by sequentially stacking insulating layers of photocurable material on the first substrate layer 1100A and forming miniaturized electrodes on the insulating layers of photocurable material. Therefore, the second substrate layer 1100B may include a redistribution layer function, the redistribution layer function includes microelectrodes, and the second substrate layer 1100B may include a function of horizontally connecting multiple semiconductor devices 1310 and 1320.

[0125] Figure 2 is a sectional view showing a circuit board according to a first embodiment, Figure 3 It is shown Figure 2 A plan view of some layers in a circuit board. Figure 4It is used to explain Figure 3 A plan view of the relationship between the through-electrode and the through-hole in the plan view, Figure 5 and Figure 6 is a diagram for explaining the adhesion characteristics of the circuit boards of the comparative example and the first embodiment, Figure 7 It is used to explain Figure 3 A plan view of a modified example of a circuit board, Figure 8 is a diagram showing a method according to the second embodiment Figure 2 A plan view of some layers of a circuit board, Fig. 9 is a diagram showing a method according to the third embodiment Figure 2 A plan view of some layers of a circuit board, Fig.10 It is used to explain Figure 8 A plan view of the relationship between the through-electrode and the through-hole in the plan view, Fig.11 According to the fourth embodiment Figure 2 A magnified view of some layers of the circuit board. Fig.12 is used to explain the settings in Fig.11 A plan view of the diameters of a plurality of through holes in the first circuit layer, Fig.13 It is used to explain Fig.11 A plan view of the wiring density of the second circuit layer, and Fig.14 It is used to explain Fig.12 A plan view of the relationship between the through-electrode and the through-hole in a plan view.

[0126] In the following, reference will be made to Figures 2 to 14 A circuit board according to an embodiment is described in detail. Hereinafter, the embodiment will be described in detail with reference to the accompanying drawings. However, regardless of the reference numerals, the same or corresponding components are given the same reference numerals, and redundant descriptions thereof will be omitted.

[0127] refer to Figure 2 , the circuit board 100 according to the embodiment may include an insulating substrate 110 , a first protective layer 116 , a second protective layer 117 , a circuit layer 120 , a through electrode 130 , an insulating member 140 , and a bonding part 150 .

[0128] The insulating substrate 110 may be provided with a plurality of layers. For example, the insulating substrate 110 may include a core layer 111, upper buildup insulating layers 112 and 113 provided on one surface of the core layer, and lower buildup insulating layers 114 and 115 provided on another surface of the core layer 111. In addition, each of the upper buildup layers 112 and 113 and the lower buildup layers 114 and 115 may be provided as a single layer, or may have a structure in which a plurality of layers are stacked in a vertical direction. The core layer 111 is composed of a resin such as an epoxy resin or BT (bismaleimide triazine) and a reinforcing material such as glass fiber, and has a function of improving the rigidity of the circuit board 100. Recently, with the increase in the number of terminals of the semiconductor device provided on the circuit board 100, the wiring has become more complicated, and therefore, the thickness of the circuit board 100 has also increased. Therefore, the core layer 110 of the embodiment may have a thickness of 400 μm to 1200 μm to improve the overall rigidity of the circuit board 100 and prevent excessive signal loss. A via may be formed in the core layer 111 passing through one surface and the other surface. The vias in the core layer 111 can be drilled mechanically or by CO 2 When mechanical drilling is used to form the via hole of the core layer 111, the inclination of the inner wall of the via hole may be perpendicular to one surface and / or the other surface of the core layer 111, while when CO 2 When the via hole of the core layer 110 is formed by laser, the inner wall of the via hole may have a plurality of concave portions and / or convex portions alternately stacked in the vertical direction. Here, the concave portion may refer to a concave area that is recessed in a direction away from the center in the horizontal direction of the via hole set in the core layer 111, and the convex portion may refer to an area that protrudes and / or bulges toward the center in the horizontal direction of the via hole set in the core 111. In the case of forming the via hole using a mechanical drilling process, the path for transmitting the electrical signal can be shortened, which can be beneficial to the electrical characteristics, but the process cost may increase. In addition, when using CO 2 When the laser forms the concave and convex portions on the inner wall of the via hole, the thickness of the core through electrode 131 disposed on the inner wall of the via hole of the core layer 111 can be thickened in the subsequent process, which can have the advantages of reducing impedance and reducing process costs. Therefore, the processing method of the via hole disposed in the core layer 111 can be freely and selectively used depending on the application field of the semiconductor package.

[0129] The core through electrode 131 may be disposed in a via hole of the core layer 111. The core through electrode 131 has a function of electrically connecting a circuit layer disposed in the upper build-up insulating layers 112 and 113 with a circuit layer disposed in the lower build-up insulating layers 114 and 115. Therefore, for the function of resistance or heat dissipation, it is desirable that the core through electrode 131 densely fills the via hole. However, when the thickness of the core layer 111 becomes thicker as described above, it may be difficult to densely fill the via hole with the core through electrode 131. For example, when attempting to fill a via hole disposed in a thick core layer 111 as described above according to a plating process, a void may appear inside the core through electrode 131. The void expands due to the heat generated during the operation of the semiconductor package, which is a factor that reduces the mechanical reliability of the circuit board. Therefore, a core through electrode 131 having a predetermined thickness is disposed on the inner wall of the via hole of the core layer 111. The thickness of the core through electrode 131 refers to the thickness in the horizontal direction perpendicular to the vertical direction, rather than the thickness in the vertical direction of the stacked upper build-up insulating layers 112 and 113, the core layer 111, and the lower build-up insulating layers 114 and 115. The thickness of the core through electrode 131 can be set to have a thickness of 5μm to 20μm to prevent voltage drop and prevent voids from occurring as the thickness of the core layer 111 increases. It is difficult to densely fill the inside of the core through electrode 131 with metal through a process such as plating, thereby generating a blank space. The blank space may cause a problem in which it is difficult to evenly arrange the upper build-up insulating layers 112 and 113, the circuit layer 120, and the lower build-up insulating layers 114 and 115.

[0130] Therefore, the insulating member 140 may be disposed on the inner side of the core through electrode 131, thereby ensuring the flatness of the core layer 111. The upper surface of the insulating member 140 may be on the same plane as the upper surface of the core layer 111, or may be closer to the upper build-up insulating layers 112 and 113 than the upper surface of the core layer 111 in the vertical direction. The lower surface of the insulating member 140 may be on the same plane as the lower surface of the core layer 111, or may be closer to the lower build-up insulating layers 114 and 115 than the lower surface of the core layer 111 in the vertical direction. This may be freely designed to address the flatness when stacking the upper build-up insulating layers 112 and 113, the lower build-up insulating layers 114 and 115, and the circuit layer 120, or to ensure the flatness of the first circuit layer 121 and / or the fourth circuit layer 124 described later.

[0131] The upper build-up insulating layers 112 and 113 , the plurality of circuit layers 121 , 122 , and 123 , the plurality of through electrodes 132 and 133 , and the first protective layer 116 may be disposed on one surface of the core layer 111 .

[0132] Multiple circuit layers 121, 122 and 123 arranged on a surface of the core layer 111 may include a first circuit layer 121 closest to the core layer 111 in the vertical direction, a second circuit layer 122 farther away from the core layer 111 than the first circuit layer 121 in the vertical direction, and a third circuit layer 123 farther away from the core layer 111 than the second circuit layer 122 in the vertical direction.

[0133] The first to third circuit layers 121, 122, and 123 may have a function of being electrically connected to a semiconductor device disposed on the circuit board 100. Each of the first to third circuit layers 121, 122, and 123 may be freely designed in consideration of impedance. In addition, through electrodes 132 and 133 may be provided to connect each of the first to third circuit layers 121, 122, and 123. For example, the first through electrode 132 is provided between the first circuit layer 121 and the second circuit layer 122, and the second through electrode 133 is provided between the second circuit layer 122 and the third circuit layer 123, thereby electrically connecting the first to third circuit layers 121, 122, and 123. The first to third circuit layers 121, 122, and 123 may include at least one through hole. For example, the third circuit layer 123 may be provided with a through hole 120a, and the through hole 120a passes through the upper surface and the lower surface of the third circuit layer 123. The through hole 120a provided in the first circuit layer 121, the second circuit layer 122 and the third circuit layer 123 may have a different meaning from the separation area between the multiple circuit patterns of each of the first circuit layer 121, the second circuit layer 122 and the third circuit layer 123. Specifically, the separation area may be connected to the outer surface of each circuit pattern and may be provided between the outer surfaces of the multiple circuit patterns. Differently, the through hole 120a may be provided to pass through the upper and lower surfaces of each circuit pattern and may not be connected to each circuit pattern. In this way, the through hole 120a and the separation area may be distinguished. For example, each of the first to third circuit layers 121, 122 and 123 may have multiple pads and multiple traces connecting the multiple pads. In addition, the through hole 120a may have a different meaning from the separation area between the multiple pads, the separation area between the pad and the trace, and the separation area between the multiple traces. The through hole 120a may allow the gas generated during the curing process of the first insulating layer 112 and the second insulating layer 113 to be easily discharged. This will be described later.

[0134] In the process of arranging the second circuit layer 122 and the third circuit layer 123, the first through electrode 132 and the second through electrode 133 may be simultaneously implemented. For example, in the process of arranging the second circuit layer 122 on the first circuit layer 121, a through hole may be formed in the first insulating layer 112 of the upper build-up insulating layer to expose a portion of the first circuit layer 122, and the second circuit layer 122 may be arranged together with the first through electrode 132 to fill the through hole of the first insulating layer 112 of the upper build-up insulating layer. Therefore, the first through electrode 132 may be distinguished by the protrusion of the second circuit layer 122. Similarly, the second through electrode 133 may be distinguished by the protrusion of the third circuit layer 123 and connected to another circuit layer arranged below the corresponding circuit layer.

[0135] The first circuit layer 121 may be in contact with one surface of the core layer 111. In this case, a portion of the first circuit layer 121 may be arranged to cover the above-mentioned insulating member 140. A portion of the first circuit layer 121 covering the insulating member 140 may be thinner than the remaining portion that does not overlap vertically with the insulating member 140. Here, the thickness of the first circuit layer 121 refers to the thickness along the vertical direction. When the first circuit layer 121 is designed, the insulating member 140 may be covered or not covered depending on the degree of freedom of wiring, thereby increasing the degree of freedom of wiring connection. When the first circuit layer 121 does not cover the insulating member 140, the insulating member 140 may be in direct contact with the first insulating layer 112 of the upper build-up insulating layer. When the first circuit layer 121 and the first insulating layer 112 of the upper build-up insulating layer are in contact with each other, the bonding strength may be better and the heat dissipation may be more favorable than when the insulating member 140 and the first insulating layer 112 of the upper build-up insulating layer are in direct contact. However, in order to reduce the process cost, the first circuit layer 121 may be arranged not to cover the insulating member 140. In addition, the first circuit layer 121 may or may not cover the insulating member 140, depending on the design of the first through electrode 132. For example, when the first through electrode 132 is provided to overlap with the first circuit layer 121 in the vertical direction, the first circuit layer 121 may be provided to cover the insulating member 140 to ensure electrical connection and / or mechanical coupling between the first circuit layer 121 and the first through electrode 132. In addition, if the first through electrode 132 overlapping with the first circuit layer 121 in the vertical direction is not provided, the first circuit layer 121 may be provided without covering the insulating member 140.

[0136] The upper build-up insulating layers 112 and 113 may have a structure in which a plurality of layers are stacked in a vertical direction. The upper build-up insulating layers 112 and 113 may include a first insulating layer 112 closest to the core layer 111 in the vertical direction and a second insulating layer 113 farther from the core layer 111 than the first insulating layer 112 in the vertical direction.

[0137] The first insulating layer 112 and the second insulating layer 113 are provided for vertical insulation between the above-mentioned first circuit layer 121, the second circuit layer 122, and the third circuit layer 123. For example, the first insulating layer 112 and the second insulating layer 113 may be formed using a thermosetting insulating material containing an inorganic filler contained in a resin, and Ajinomoto Build-up Film (ABF) from Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photocurable insulating material (photoimageable dielectric, PID) for forming a fine pattern may be used.

[0138] The first protective layer 116 can protect the third circuit layer 123 from external moisture or contaminants. In addition, when a semiconductor device is provided on the circuit board 100 using a material such as solder, the first protective layer 116 is used to prevent a short circuit between the solders due to low wettability with the solder. The first protective layer 116 can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0139] Lower build-up insulating layers 114 and 115 , a plurality of circuit layers 124 , 125 , and 126 , a plurality of through electrodes 134 and 135 , and a second protective layer 117 may be disposed on the other surface of the core layer 111 .

[0140] Multiple circuit layers 124, 125 and 126 arranged on the other surface of the core layer 111 may include a fourth circuit layer 124 closest to the core layer 111 in the vertical direction, a fifth circuit layer 125 farther away from the core layer 111 than the fourth circuit layer 124 in the vertical direction, and a sixth circuit layer 126 farther away from the core layer 111 than the fifth circuit layer 125 in the vertical direction.

[0141] The fourth to sixth circuit layers 124, 125 and 126 can electrically connect the main board (not shown) of the electronic device and the semiconductor device arranged on the circuit board 100. Each of the fourth to sixth circuit layers 124, 125 and 126 can be freely designed in consideration of impedance. The fourth to sixth circuit layers 124, 125 and 126 can have at least one through hole. In addition, similar to the through hole 120a arranged in the first to third circuit layers 121, 122 and 123 described above, the through hole arranged in the fourth to sixth circuit layers 124, 125 and 126 can have a different meaning from the separation area between the multiple circuit patterns of each of the fourth to sixth circuit layers 124, 125 and 126. For example, each of the fourth to sixth circuit layers 124, 125 and 126 can have a plurality of pads and a plurality of traces connecting the plurality of pads. In addition, the through holes provided in the fourth to sixth circuit layers 124, 125, and 126 may have a different meaning from the intervals between the plurality of pads, the intervals between the pads and the traces, and the intervals between the plurality of traces of each of the fourth to sixth circuit layers 124, 125, and 126. The through holes provided in the fourth to sixth circuit layers 124, 125, and 126 may allow easy discharge of gas generated during the curing of the third and fourth insulating layers 114 and 115. This will be described later.

[0142] In addition, through electrodes 134 and 135 may be provided to connect each of the fourth to sixth circuit layers 124, 125, and 126. For example, the third through electrode 134 is provided between the fourth circuit layer 124 and the fifth circuit layer 125, and the fourth through electrode 135 is provided between the fifth circuit layer 125 and the sixth circuit layer 126, thereby electrically connecting the fourth to sixth circuit layers 124, 125, and 126.

[0143] As described above with respect to the first through electrode 132 and the second through electrode 133, the third through electrode 134 and the fourth through electrode 135 may also be simultaneously implemented in the process of arranging the fifth circuit layer 125 and the sixth circuit layer 126. For example, as described above, the third through electrode 134 may be distinguished by the protrusion of the fifth circuit layer 125. In addition, the fourth through electrode 135 may be distinguished by the protrusion of the sixth circuit layer 126. The layers disposed on the upper side of the core layer 111 and the layers disposed on the lower side of the core layer 111 are stacked in different directions, and the inclination direction of the third and fourth through electrodes 134 and 135 may have a direction opposite to the inclination direction of the first and second through electrodes 132 and 133. For example, the first through electrode 132 and the second through electrode 133 may have an inclination that narrows as the first through electrode 132 and the second through electrode 133 approach the core layer 111, and the third through electrode 134 and the fourth through electrode 135 may also have an inclination that narrows as the third through electrode 134 and the fourth through electrode 135 approach the core layer 111. The inclination of the first through electrode 132 and the second through electrode 133 may be symmetrical with the inclination of the third through electrode 134 and the fourth through electrode 135 with respect to the core layer 111.

[0144] The fourth circuit layer 124 may be in contact with the other surface of the core layer 111. In this case, a portion of the fourth circuit layer 124 may be arranged to cover the above-mentioned insulating member 140. A portion of the fourth circuit layer 124 covering the insulating member 140 may be thinner than the remaining portion that does not overlap vertically with the insulating member 140. Here, the thickness of the fourth circuit layer 124 refers to the thickness along the vertical direction. When designing the fourth circuit layer 124, the insulating member 140 may be covered or not covered depending on the degree of freedom of wiring, thereby increasing the degree of freedom of wiring connection. When the fourth circuit layer 124 does not cover the insulating member 140, the insulating member 140 may be in direct contact with the third insulating layer 114. Compared with the case where the insulating member 140 and the third insulating layer 114 are in direct contact, the case where the fourth circuit layer 124 and the third insulating layer 114 are in contact may have better bonding strength and may be conducive to heat dissipation. However, in order to reduce process costs, the fourth circuit layer 124 may be arranged not to cover the insulating member 140. In addition, the fourth circuit layer 124 may cover or not cover the insulating member 140, depending on the design of the third through electrode 134. For example, when the third through electrode 134 is disposed to vertically overlap with the fourth circuit layer 124, the fourth circuit layer 124 may be disposed to cover the insulating member 140 to ensure electrical connection and / or mechanical coupling between the fourth circuit layer 124 and the third through electrode 134. In addition, when the third through electrode 134 overlapping with the fourth circuit layer 124 in the vertical direction is not disposed, the fourth circuit layer 124 may be disposed without covering the insulating member 140.

[0145] Lower build-up insulating layers 114 and 115 may have a structure in which a plurality of layers are stacked in a vertical direction. Lower build-up insulating layers 114 and 115 may include a third insulating layer 114 closest to core layer 111 in a vertical direction, and a fourth insulating layer 115 farther from core layer 111 than third insulating layer 114 in a vertical direction.

[0146] The third insulating layer 114 and the fourth insulating layer 115 are provided for vertical insulation between the fourth to sixth circuit layers 124, 125, and 126. For example, the third insulating layer 114 and the fourth insulating layer 115 may be formed using a thermosetting insulating material containing an inorganic filler in a resin, and Ajinomoto Build-up Film (ABF) from Ajinomoto Co., Ltd. may be used. However, the embodiment is not limited thereto, and a photocurable insulating material (photoimageable dielectric, PID) for forming a fine pattern may be used.

[0147] The second protective layer 117 can protect the sixth circuit layer 126 from external moisture or contaminants. In addition, when a semiconductor device is provided on the circuit board 100 using a material such as solder, the second protective layer 117 is used to prevent a short circuit between the solders due to low wettability with the solder. The second protective layer 117 can be formed using a photocurable insulating material, and for example, a solder resist can be used.

[0148] Some areas of the third circuit layer 123 may include pad portions exposed from the first protective layer 116. In addition, as the terminal density of the semiconductor device increases, conventional solder bonding may cause a short circuit problem of the solder between adjacent pad portions. Therefore, in order to reduce the amount of solder used as the terminal density of the semiconductor device increases, the semiconductor device and the circuit board 100 may be bonded to each other by a thermal compression bonding method. When using thermal compression bonding, the circuit board 100 may include a bonding portion 150 protruding on the first protective layer 116. The bonding portion 150 may have a protrusion 151 protruding on the first protective layer 116 and a through portion 152 passing through the first protective layer 116 and contacting the third circuit layer 123. In addition, when the circuit board 100 and the semiconductor device are bonded by the thermal compression bonding method, cracks may occur in the through portion 152 of the bonding portion 150 due to the load generated thereby. Therefore, the through-portion 152 of the joint 150 can prevent cracks by arranging a material having an elasticity higher than that of the third circuit layer 123 in a portion adjacent to the third circuit layer 123. This material may be nickel (Ni), but a copper layer having a low grain density may be arranged by electroless plating. At this time, the protrusion 151 and the through-portion 152 of the joint 150 may be arranged in various ways. For example, a process may be performed in which the first protective layer 116 is exposed and developed to form an opening in the first protective layer 116, and then the protrusion 151 and the through-portion 152 of the joint 150 are arranged in the opening. In addition, a process may be performed in which an opening is formed in the first protective layer 116 using a laser, and then the protrusion 151 and the through-portion 152 of the joint 150 are arranged in the opening. In addition, by using DFR (Dry Film resist), DFR is first disposed in the region where the through portion 152 is to be disposed, and then the first protective layer 116 is disposed to cover the DFR, and then a portion of the first protective layer 116 is etched with a chemical solution to expose the DFR, and then the DFR is peeled off to form an opening in the first protective layer 116, and then the protrusion 151 and the through portion 152 of the joint 150 can be disposed. Therefore, depending on the process method, the through portion 152 of the joint 150 can have various shapes.For example, when the opening of the first protective layer 116 is formed by an exposure process, the side surface of the through portion 152 of the bonding portion 150 may have a structure in which the width gradually narrows toward the third circuit layer 123, when the opening of the first protective layer 116 is formed by a laser process, the side surface of the through portion 152 may have a vertical side surface and a curved side surface adjacent to the third circuit layer 123, and when the opening of the first protective layer 116 is formed using a DFR, the side surface of the through portion 152 may have only a vertical side surface. As described above, when the semiconductor device is bonded to the circuit board 100 by thermal compression bonding, a load may be applied to the through portion 152, and in the case of using a DFR in the through portion 152, stress may be uniformly applied, thereby improving the manufacturing yield.

[0149] The structure of the circuit board 100 described above is merely an example for explaining the present invention, and the technical concept of the present invention is not limited to the stacked structure of the embodiment.

[0150] In addition, the third circuit layer 123 and the sixth circuit layer 126 disposed on the uppermost and lowermost sides of the circuit layer 120 of the circuit board 100 have been described as having a structure protruding from the upper surface of the second insulating layer 113 and the lower surface of the fourth insulating layer 115, but the embodiment is not limited thereto. For example, at least one of the third circuit layer 123 and the sixth circuit layer 126 may have an ETS (Embedded Trace Substrate) structure. For example, the third circuit layer 123 may be disposed in a recess disposed on the upper surface of the second insulating layer 113. The above-mentioned ETS structure may also be referred to as an embedded structure. Compared with a circuit layer having a general protruding structure, the ETS structure is conducive to miniaturization. Therefore, the embodiment is capable of forming a circuit layer corresponding to the size and spacing of the terminals provided in the semiconductor device. In this way, the embodiment can improve the circuit integration. In addition, the embodiment can minimize the transmission distance of the signal transmitted through the semiconductor device, thereby minimizing the signal transmission loss.

[0151] The above-mentioned circuit board 100 may generate gas during the process, which may reduce the adhesion between the first to fourth insulating layers 112, 113, 114 and 115 and the first to sixth circuit layers 121, 122, 123, 124, 125 and 126. In addition, when the adhesion is reduced, the interface between the first to fourth insulating layers 112, 113, 114 and 115 and the first to sixth circuit layers 121, 122, 123, 124, 125 and 126 may peel off, which may cause mechanical reliability and / or electrical reliability problems. Therefore, at least one of the first to sixth circuit layers 121, 122, 123, 124, 125 and 126 may be provided with a through hole 120a. At this time, a through hole 120a may be provided in each of the first to sixth circuit layers 121, 122, 123, 124, 125, and 126, and thus, gas generated during the curing process of the first to fourth insulating layers 112, 113, 114, and 115 may be easily discharged.

[0152] refer to Figure 2 , the circuit board may include an insulating layer 210 and a circuit layer 220 disposed on the insulating layer 210. At this time, the insulating layer 210 may refer to any one of the first to fourth insulating layers 112, 113, 114, and 115 described in FIG. 1, and the circuit layer 220 may refer to any one of the first to sixth circuit layers 121, 122, 123, 124, 125, and 126.

[0153] The circuit layer 220 may include a plurality of circuit patterns spaced apart from each other in the horizontal direction. In this case, the through hole 220a may have a different meaning from the separation region between the plurality of circuit patterns. The circuit layer 220 may include a plurality of circuit patterns disposed on the same plane of the insulating layer 210 and spaced apart from each other in the horizontal direction. In addition, the separation region between the plurality of circuit patterns may have a different meaning from the through hole 220a. The separation region may refer to a hole disposed between a plurality of circuit patterns that must be electrically separated from each other. In addition, the through hole 220a may refer to a hole passing through the upper and lower surfaces of a circuit pattern. In addition, the separation region may also be expressed as the interval between the plurality of circuit patterns. For the miniaturization of the circuit layer 220, the interval may have a range of 20 μm or less, 18 μm or less, 15 μm or less, or 12 μm or less.

[0154] The through hole 220a is provided in the circuit layer 220, and may be used as a gas discharge hole for discharging gas generated in the insulating layer 210. Therefore, the through hole 220a may also be functionally referred to as a degassing hole.

[0155] In one embodiment, the planar shape of the through hole 220a may be circular. However, the embodiment is not limited thereto. In another embodiment, the planar shape of the through hole 220a may have a triangle, a square, an ellipse, a rhombus, or a polygon. In addition, at least one of the plurality of through holes 220a provided in the circuit layer 220 may have a first planar shape, and at least one other through hole 220a may have a second planar shape different from the first planar shape.

[0156] The through hole 220 a of the circuit layer 220 may be used as a gas discharge hole for discharging gas generated in the insulating layer 210 .

[0157] For example, to briefly explain the manufacturing process of the circuit board 100, the insulating layer 210 may be provided in a semi-cured state. Then, the circuit layer 220 may be disposed on the insulating layer 210 in a semi-cured state. In this case, a process of completely curing the insulating layer 210 may be performed after the circuit layer 220 is disposed.

[0158] At this time, when the process of completely curing the insulating layer 210 is performed, gas may be generated in the insulating layer 210. At this time, the generated gas must be discharged from the insulating layer 210 to the outside of the circuit board 100. At this time, the circuit layer 220 is provided on the insulating layer 210. Therefore, a problem may occur that the gas generated from the insulating layer 210 is not discharged to the outside of the circuit board 100 by the circuit layer 220.

[0159] Therefore, the circuit layer 220 of the embodiment may have a through hole 220a passing through the upper surface and the lower surface. The through hole 220a of the circuit layer 220 may be used as a gas discharge hole, which discharges the gas generated by the insulating layer 210 to the outside of the circuit board 100 (for example, in the upper direction of the circuit layer away from the insulating layer 210). The embodiment is provided with a through hole 220a in the circuit layer 220 so that the gas generated in the insulating layer 210 can be easily discharged to the outside of the circuit board 100. In this way, the embodiment can solve the physical reliability problem caused by the residual gas in the insulating layer 210. For example, if the gas generated in the insulating layer 210 is not discharged, there may be a problem that at least one of the insulating layer 210 and the circuit layer 220 expands due to the gas.

[0160] For example, refer to Figure 5(a), the circuit layer of the circuit board of the comparative example is not provided with a through hole. As a result, the circuit board of the comparative example may have a problem in which the gas generated in the insulating layer 10 is not discharged to the upper side of the circuit layer 20. Therefore, the circuit board of the comparative example may include a portion in which the insulating layer 10 and the circuit layer 20 expand due to the gas. For example, the insulating layer 10 of the circuit board of the comparative example may include a convex area 10P in which one area bulges upward and / or a concave area (A) in which a concave shape is sunken to correspond to the convex area 10P. In addition, the circuit layer 20 of the circuit board of the comparative example may include a convex area 20P in which one area bulges upward to correspond to the convex area 10P. In the convex areas 10P and 20P, the adhesion between the insulating layer 10 and the circuit layer 20 is reduced, and therefore, physical reliability problems such as peeling between the circuit layer 20 and the insulating layer 10 may occur. In addition, the adhesion between the multiple insulating layers is reduced by the concave area (A), and therefore, the adhesion problem of multiple insulating layers being physically separated from each other may occur.

[0161] In addition, reference Figure 5 (b), the circuit board of the comparative example includes a portion in which the insulating layer 10 and / or the circuit layer 20 expands due to the gas. For example, the circuit layer 20 of the circuit board of the comparative example may include a convex area 20P in which one area expands upward from the insulating layer 10. In addition, the surface (B) corresponding to the convex area 20P of the circuit layer 20 may not contact the insulating layer 10. As a result, due to the convex area 20P, the adhesion between the circuit layer 20 and the insulating layer 10 may be reduced, and therefore, a physical reliability problem of the circuit layer 20 being separated from the insulating layer 10 may occur.

[0162] In contrast, reference Figure 6 , the circuit layer 220 of the embodiment is provided with a through hole 220a, and the gas generated in the insulating layer 210 can be smoothly discharged to the outside of the circuit board 100 through the through hole 220a. In this way, the embodiment can prevent the insulating layer 210 and / or the circuit layer 220 from including an area that expands due to the gas. Therefore, the embodiment can improve the adhesion between multiple insulating layers, and the adhesion between the insulating layer and the circuit layer. In this way, the embodiment can improve the physical reliability of the circuit board.

[0163] At this time, the through hole 220a of the circuit layer 220 may be filled with an insulating material. That is, the through hole 220a of the circuit layer 220 may be filled with another insulating layer and / or a protective layer stacked on the circuit layer 220 during the lamination process of the circuit board 110.

[0164] It may be difficult to improve the gas discharge characteristics by only providing the through hole 220a in the circuit layer 220 without any conditions. In addition, if the through hole 220a is provided in the circuit layer 220, the wiring density of the circuit layer 220 may be reduced, which may cause a problem that the circuit board 100 is significantly warped in a specific direction. For example, the gas discharge characteristics and / or the warpage characteristics of the circuit board 100 may be determined according to the diameter W3 of the through hole 220a provided in the circuit layer 220.

[0165] For example, if the diameter W3 of the through hole 220a is too small, gas generated in the insulating layer 210 may not be properly discharged to the outside of the circuit board 200, and thus the effect of improving adhesion between the insulating layer 210 and the circuit layer 220 may be insufficient.

[0166] For example, if the diameter W3 of the through hole 220a is too large, the area or wiring density of the circuit layer 220 on the single layer of the insulating layer 210 may be reduced. In addition, if the area or density of the circuit layer 220 is reduced, the warping characteristics of the circuit board 100 may deteriorate, and as a result, the circuit board 100 may be severely warped in a specific direction. If the circuit board 100 is severely warped in a specific direction, it may be difficult to ensure a uniform contact surface when the semiconductor package is mounted on the main board. Alternatively, when the circuit board 100 is bent due to the heat generated during the operation of the semiconductor device, it may be difficult to smoothly operate the semiconductor device, and it may be difficult to smoothly operate the server or electronic product. Therefore, the diameter W3 of the through hole 220a relative to the plane area of ​​the circuit board 100 can be directly related to the reliability of electronic products such as servers to which the semiconductor package is applied, so that technical interoperability or functional integrity can be achieved. In addition, if the circuit board 100 is significantly bent in a specific direction, a process error may occur during the manufacturing process of the circuit board 100, which may cause a problem of reduced yield.

[0167] Therefore, the embodiment determines the diameter W3 of the through hole 220a based on the plane area of ​​the circuit board 100. Therefore, the embodiment solves the problem of bending of the circuit board 100 and allows the gas generated from the insulating layer 210 to be well discharged to the outside of the circuit board 100.

[0168] The plane area of ​​the circuit board 100 may refer to the plane area of ​​the insulating layer 210. The insulating layer 210 may have a first width W1 in a first horizontal direction (e.g., an x-axis direction or a horizontal direction). In addition, the insulating layer 210 may have a second width W2 in a second horizontal direction (e.g., a y-axis direction or a vertical direction) perpendicular to the first horizontal direction.

[0169] In addition, the plane area of ​​the circuit board 100 having the first width W1 and the second width W2 may be 1500 mm2 Up to 2000mm 2 Preferably, the plane area of ​​the circuit board 100 having the first width W1 and the second width W2 may be 1550 mm 2 Up to 1950mm 2 More preferably, the plane area of ​​the circuit board 100 having the first width W1 and the second width W2 may be 1580 mm 2 Up to 1900mm 2 .

[0170] Furthermore, when the circuit board 100 has a plane area as described above, the minimum value of the diameter W3 of the through hole 220 a provided in the circuit layer 220 must have a certain level so that the gas generated in the insulating layer 210 can be smoothly discharged to the outside of the circuit board 100 .

[0171] For example, a plurality of through holes 220a may be provided in the circuit layer 220. In addition, at least one of the plurality of through holes 220a must have a diameter W3 of a predetermined level or higher, and since at least one through hole 220b has the diameter W3, gas generated in the insulating layer 210 may be easily discharged to the outside.

[0172] The diameter W3 of the through hole 220a may be at least 165 μm or more. If the diameter W3 of the through hole 220a is less than 165 μm, the gas generated from the insulating layer 210 having the plane area may not be properly discharged to the upper side of the circuit layer 220. In addition, if the gas is not discharged, the circuit layer 220 and / or the insulating layer 210 may expand. As a result, the adhesion between the circuit layer 220 and the insulating layer 210 may be reduced.

[0173] At the same time, the larger the diameter W3 of the through hole 220a, the better the gas generated from the insulating layer 210 can be discharged to the outside. However, if the diameter of the through hole 220a is too large, the wiring density or area of ​​the circuit layer 220 on the insulating layer 210 may be reduced. In addition, when the wiring density or area of ​​the circuit layer 220 is reduced, the characteristics of the circuit layer 220 may change, or the warping characteristics of the circuit board 100 may deteriorate. Here, the characteristics of the circuit layer 220 may refer to impedance characteristics, but are not limited to this. In addition, the circuit layer 220 can perform a wiring function while also preventing the circuit board 100 from bending. In addition, when the diameter W3 of the through hole 220a provided in the circuit layer 220 is too large, the circuit board 100 cannot be prevented from bending, and therefore, the problem of the circuit board 100 being significantly bent in a specific direction may occur.

[0174] The diameter W3 of the through hole 220a may satisfy the range of 165 μm to 220 μm. Preferably, the diameter W3 of the through hole 220a may satisfy the range of 165 μm to 210 μm. More preferably, the diameter W3 of the through hole 220a may satisfy the range of 165 μm to 205 μm. If the diameter W3 of the through hole 220a is less than 165 μm, as described above, the gas generated in the insulating layer 210 is not properly discharged to the outside of the circuit board 100, and therefore, the problem of gas remaining in the insulating layer 210 may occur. In addition, if the gas remains, the insulating layer 210 and / or the circuit layer 220 may expand, resulting in physical reliability problems. In addition, if the diameter W3 of the through hole 220a exceeds 220 μm, the area or density of the circuit layer 220 is reduced, and therefore, the impedance characteristics between multiple circuit layers may change, or the rigidity of the circuit board 100 may be reduced.

[0175] In addition, the ratio of the diameter of the through hole 220a to the plane area of ​​the insulating layer 210 may satisfy the range of 0.0000825 to 0.000147. In addition, the ratio of the plane area of ​​the through hole 220a to the plane area of ​​the insulating layer 210 may satisfy the range of 0.00025905 to 0.0004605. That is, the plane area of ​​the insulating layer 210 may be 1500 mm 2 Up to 2000mm 2 At least one of the plurality of through holes 220a may have a diameter of 165 μm to 220 μm, and a plane area of ​​at least one of the plurality of through holes 220a may satisfy 518.1 μm 2 To 690.8μm 2 range.

[0176] In this way, the embodiment can solve the problem of the gas generated by the insulating layer 210 being well discharged to the outside of the circuit board 100. In addition, the embodiment can also solve the problem of reducing the area or wiring density of the circuit layer, the change of impedance characteristics between multiple circuit layers, and the problem of reducing the rigidity of the circuit board 100.

[0177] refer to Figure 4, the through electrode 230 may be provided and pass through the insulating layer 210 at the same time. At this time, the circuit layer 220 having the through hole 220a may overlap with the through electrode 230 in the vertical direction. At this time, the through hole 220a provided in the circuit layer 220 may not overlap with the through electrode 230 in the vertical direction. At this time, if the through hole 220a of the circuit layer 220 overlaps with the through electrode 230 in the vertical direction, the electrical connection characteristics between multiple circuit layers through the through electrode 230 may deteriorate. That is, the through electrode 230 may be connected between circuit layers provided in different insulating layers. In addition, if the through hole 220a of the circuit layer 220 overlaps with the through electrode 230 in the vertical direction, the transmission loss of the signal transmitted through the through electrode 230 may increase, so that the signal transmission reliability may be reduced. Therefore, the through hole 220a provided in the circuit layer 220 of the embodiment may not overlap vertically with the through electrode 230 passing through the insulating layer 210.

[0178] In addition, the diameter W3 of the through hole 220a provided in the circuit layer 220 may be larger than the diameter of the through electrode 230. Figure 2 As shown, the through electrode 230 may have a slope whose width gradually changes from the upper surface to the lower surface of the insulating layer 210. In addition, the diameter W3 of the through hole 220a may be greater than the width W4 of the region having the maximum width in the entire region of the through electrode 230 in the vertical direction.

[0179] For example, the width W4 of the through electrode 230 may satisfy the range of 60 μm to 90 μm. For example, the width W4 of the through electrode 230 may satisfy the range of 60 μm to 85 μm. For example, the width W4 of the through electrode 230 may satisfy the range of 60 μm to 80 μm. If the width W4 of the through electrode 230 is less than 60 μm, the allowable current of the signal that can be transmitted through the through electrode 230 is reduced, and thus the electrical characteristics of the circuit board and the semiconductor package may deteriorate. If the width W4 of the through electrode 230 exceeds 90 μm, the process time required to fill the through electrode 230 with a conductive material increases, and thus the product production yield may decrease. In addition, if the width W4 of the through electrode 230 exceeds 90 μm, the spacing between the multiple through electrodes spaced apart in the horizontal direction increases, and thus the circuit integration may decrease.

[0180] In summary, the diameter W3 of the through hole 220a provided in the circuit layer 220 may be 2.5 times or more the width W4 of the through electrode 230. In addition, if the diameter W3 of the through hole 220a provided in the circuit layer 220 is less than 2.5 times the width W4 of the through electrode 230, the gas generated in the insulating layer 210 may not be easily discharged to the outside of the circuit board 100.

[0181] In addition, according to Figure 7 In the embodiment, the circuit layer 220 may be provided with a through hole 220a having a rhombus shape instead of a circular shape. In addition, when the through hole 220a provided in the circuit layer 220 has a rhombus shape, the diameter W3 of the through hole 220a may represent the distance between vertices facing each other on the plane of the through hole 220a.

[0182] In addition, according to Figure 8 In an embodiment of the present invention, the diameter W3 of each of the plurality of through holes 320a provided in the circuit layer 320 may be equal to or greater than the separation distance W4 between two mutually adjacent through holes in the plurality of through holes 320a. That is, the diameter W3 of each of the plurality of through holes 320a provided in the circuit layer 320 may be equal to or greater than the separation distance W4 between two mutually adjacent through holes in the plurality of through holes 320a. At this time, if the diameter W3 of each of the plurality of through holes 320a is smaller than the separation distance W4 between two mutually adjacent through holes in the plurality of through holes 320a, the gas generated in the insulating layer 310 may not be easily discharged to the outside of the circuit board 100. The fact that the diameter W3 of the through hole 320a is smaller than the separation distance W4 may mean that, based on the area in which the through hole 320a is provided in the circuit layer 320, the area in which the gas cannot be discharged through the through hole 320a is larger than the area in which the gas can be discharged through the through hole 320a. Furthermore, when the diameter W3 of the through-hole 320 a is greater than the separation distance W4 between the plurality of through-holes 320 a , gas may not be properly discharged and may remain in the insulating layer 310 , and thus physical characteristics may be deteriorated.

[0183] At this time, the separation distance W4 may vary depending on the arrangement direction and / or arrangement form of the plurality of through holes 320a. Figure 8 In the case where the plurality of through holes 320 a are arranged in a zigzag shape along a diagonal direction as shown, the separation distance W4 may refer to a separation distance between two through holes located diagonally from each other among the plurality of through holes.

[0184] For example, as in Fig. 9 In an embodiment, when a plurality of through holes 320a are arranged at a certain interval in a first horizontal direction parallel to the first side of the circuit board or in a second horizontal direction perpendicular to the first surface, the separation distance W4 may refer to a separation distance between two through holes positioned in the first horizontal direction or the second horizontal direction among the plurality of through holes.

[0185] At this time, the diameter of at least one through hole in the plurality of through holes 320a may be different from the diameter of at least one other through hole. The separation distances between the plurality of through holes adjacent to each other in the plurality of through holes may be different from each other. In this case, the diameter W3 may represent the diameter of the through hole with the smallest diameter in the plurality of through holes 320a. In addition, the separation distance may refer to the maximum separation distance among the separation distances between the plurality of through holes adjacent to each other.

[0186] In other words, the minimum diameter of each of the plurality of through holes 320a of the embodiment can be equal to or greater than the maximum separation distance of the separation distances between the plurality of through holes adjacent to each other. In this way, the embodiment can better discharge the gas generated in the insulating layer 310, thereby further improving the physical reliability of the circuit board and the semiconductor package.

[0187] At this time, since we have already referred to Figure 3 The diameter W3 of the through hole 320 a is described, and thus a detailed description thereof will be omitted.

[0188] The separation distance W4 may be determined based on the diameter W3 of the through hole 320a and the width W5 of the through electrode 330. The separation distance W4 may be less than or equal to the diameter W3 of the through hole 320a and greater than or equal to the width W5 of the through electrode 330. If the separation distance W4 is less than the width W5 of the through electrode 330, the through hole 320a and the through electrode 330 may overlap in the vertical direction, or the area of ​​the region overlapping in the vertical direction may increase. In addition, when the area of ​​the region overlapping in the vertical direction increases, the signal transmission characteristics of the through electrode 330 may deteriorate. In addition, as described above, the separation distance W4 may refer to the separation distance between two through holes disposed adjacent to each other in the plurality of through holes 320a. For example, based on a first through hole, the second through hole disposed most adjacent to the first through hole may be positioned in the diagonal horizontal direction of the first through hole. Therefore, the separation distance W4 may represent the separation distance between two through holes spaced apart from each other in the diagonal horizontal direction. However, the embodiment is not limited thereto. For example, if a second through hole closest to a first through hole is positioned in a horizontal direction (e.g., x-axis direction) or a vertical direction (e.g., y-axis direction), the separation distance may refer to a separation distance between the first through hole and the second through hole positioned in the horizontal direction or the vertical direction.

[0189] In addition, according to Fig.10In an embodiment of the present invention, the through electrode 330 may be arranged to pass through the insulating layer 310, and the circuit layer 320 provided with the through hole 320a may overlap with the through electrode 330 in the vertical direction. At this time, the through hole 320a provided in the circuit layer 320 may not overlap with the through electrode 330 in the vertical direction. At this time, when the through hole 320a of the circuit layer 320 overlaps with the through electrode 330 in the vertical direction, the electrical connection characteristics between the plurality of circuit layers through the through electrode 330 may deteriorate. That is, the through electrode 330 may be connected between circuit layers provided in different insulating layers. In addition, when the through hole 320a of the circuit layer 320 overlaps with the through electrode 330 in the vertical direction, the transmission loss of the signal transmitted through the through electrode 330 may increase, and the signal transmission reliability may be reduced accordingly. Therefore, the through hole 320a provided in the circuit layer 320 of the embodiment is designed not to overlap with the through electrode 330 passing through the insulating layer 310 in the vertical direction, or even if the through hole 320a and the through electrode 330 overlap in the vertical direction, the area of ​​the overlapping region can be minimized.

[0190] In addition, according to Fig.11 and Fig.12 In an embodiment, the circuit board may include a first circuit layer 421 disposed on an insulating layer 411. The first circuit layer 421 may be divided into a plurality of regions. For example, the first circuit layer 421 may be divided into a plurality of regions based on a plurality of circuit patterns disposed in the second circuit layer 422. For example, the first circuit layer 421 may include first to third regions R1, R2, and R3. The first region R1 of the first circuit layer 421 may include a plurality of first through holes 421-1 passing through the upper and lower surfaces of the first region R1. The plurality of first through holes 421-1 may have a first diameter W3. The first diameter W3 of the first through hole 421-1 disposed in the first region R1 may be determined based on the plane area of ​​the circuit board 100. In this case, the first diameter W3 of the first through hole 421-1 may correspond to Figure 3 , Figure 4 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 The diameters of the through holes 220a and 320a described in at least one of the embodiments.

[0191] The first circuit layer 421 may include a second region R2 distinguished from the first region R1 on the insulating layer 411. In one embodiment, the first region R1 and the second region R2 may be distinguished by regions from a single circuit pattern connected to each other in the first circuit layer 421. In another embodiment, the first region R1 and the second region R2 may be distinguished by a plurality of circuit patterns spaced apart from each other in the first circuit layer 421. The second region R2 may include a plurality of second through holes 421-2 passing through the upper and lower surfaces of the second region R2 of the first circuit layer 421. At this time, the plurality of second through holes 421-2 disposed in the second region R2 may have a second diameter W4. At this time, each second diameter W4 of the plurality of second through holes 421-2 disposed in the second region R2 may be different from the first diameter W3 of each of the plurality of first through holes 421-1 disposed in the first region R1. Preferably, each second diameter W4 of the plurality of second through holes 421-2 disposed in the second region R2 may be greater than the first diameter W3 of each of the plurality of first through holes 421-1 disposed in the first region R1. This may be due to the characteristics of the circuit pattern of the second circuit layer 422 vertically overlapping the first region R1 and the second region R2 of the first circuit layer 421. The characteristics of the circuit pattern of the second circuit layer 422 may refer to any one of the wiring density of the circuit pattern, the width / interval of the circuit pattern, and the function of the circuit pattern. In addition, the first circuit layer 421 may include a third region R3 different from the first region R1 and the second region R2. Depending on the arrangement position on the insulating layer 411, the third region R3 of the first circuit layer 421 may be different from the first region R1 and the second region R2. The third region R3 may be connected to the first region R1 and the second region R2, but is not limited thereto. The third region R3 may be physically and / or electrically separated from the first region R1 and the second region R2. The third region R3 may be arranged closer to the periphery of the circuit board 100 than the first region R1 and the second region R2. The third region R3 may be arranged along the edge and / or peripheral direction of the upper surface of the first circuit layer 421. For example, the third region R3 may refer to the edge region of the upper surface of the first circuit layer 421. In other words, the upper surface of the insulating layer 411 may include an edge region adjacent to the edge. In addition, the third region R3 may refer to a region of the first circuit layer 421 that overlaps the edge region of the insulating layer 411 in a vertical direction.

[0192] The first region R1 and the second region R2 may represent the inner region of the edge region corresponding to the third region R3. The third region R3 of the first circuit layer 421 may include a plurality of third through holes 421-3 passing through the upper and lower surfaces of the third region R3. Each of the plurality of third through holes 421-3 disposed in the third region R3 may have a third diameter W5. At this time, the third diameter W5 of each of the plurality of third through holes 421-3 disposed in the third region R3 may be different from the first diameter W3 of each of the plurality of first through holes 421-1 disposed in the first region R1 and the second diameter W4 of each of the plurality of second through holes 421-2 disposed in the second region R2. Preferably, the third diameter W5 of each of the plurality of third through holes 421-3 disposed in the third region R3 may be smaller than the first diameter W3 of each of the plurality of first through holes 421-1 disposed in the first region R1 and the second diameter W4 of each of the plurality of second through holes 421-2 disposed in the second region R2.

[0193] In summary, the first circuit layer 421 is disposed on the insulating layer 411 and can be divided into a first region R1, a second region R2, and a third region R3 along the horizontal direction. In addition, the first region R1 of the first circuit layer 421 may have a plurality of first through holes 421-1. In addition, the second region R2 of the first circuit layer 421 may have a plurality of second through holes 421-2. In addition, the third region R3 of the first circuit layer 421 may have a plurality of third through holes 421-3. At this time, among the first through hole 421-1, the second through hole 421-2, and the third through hole 421-3, the second through hole 421-2 may have the largest diameter, and the third through hole 421-3 may have the smallest diameter. This may be due to the positions of the first region R1, the second region R2, and the third region R3 of the first circuit layer 421, and / or the characteristics of the circuit pattern of the second circuit layer 422 overlapping these regions in the vertical direction.

[0194] The second circuit layer 422 may be disposed on the lower surface of the insulating layer 411. The second circuit layer 422 may include a plurality of circuit patterns. The circuit patterns of the second circuit layer 422 may have different wiring densities. The wiring density may refer to the area occupied by the second circuit layer 422 within a specific unit area of ​​the insulating layer 411. The second circuit layer 422 may include a first circuit pattern 422-1 overlapping with the first region R1 of the first circuit layer 421 in the vertical direction. In addition, the second circuit layer 422 may include a second circuit pattern 422-2 overlapping with the second region R2 of the first circuit layer 421 in the vertical direction and spaced apart from the first circuit pattern 422-1 in the horizontal direction. In addition, the second circuit layer 422 may include a third circuit pattern 422-3 overlapping with the third region R3 of the first circuit layer 421 in the vertical direction. The third circuit pattern 422-3 may refer to a circuit pattern disposed in an edge region corresponding to the third region R3 of the first circuit layer 421 of the lower surface of the insulating layer 411. In addition, the first circuit pattern 422 - 1 and the second circuit pattern 422 - 2 of the second circuit layer 422 may refer to circuit patterns disposed inside the edge region of the lower surface of the insulating layer 411 in the second circuit layer 422 .

[0195] At this time, the first circuit pattern 422-1 and the second circuit pattern 422-2 of the second circuit layer 422 may have different wiring densities. Specifically, the second circuit pattern 422-2 of the second circuit layer 422 may have a greater density than the first circuit pattern 422-1. The width and spacing of the circuit pattern 422-2 in the second region may be smaller than the width and spacing of the circuit pattern 422-1 in the first region. In addition, if a through hole with a relatively small diameter is provided in the second region R2 of the first circuit layer 421 overlapping with the second circuit pattern 422-2 in the vertical direction, the characteristics of the second circuit pattern 422-2 with a relatively high wiring density may change. For example, the second circuit pattern 422-2 may be a circuit pattern for impedance matching. At this time, if a through hole with a relatively small diameter is provided in the second region R2 of the first circuit layer 421 overlapping with the second circuit pattern 422-2 in the vertical direction, the impedance characteristics of the second circuit pattern 422-2 of the second circuit layer 422 may change. In addition, if a through hole having a relatively small diameter is provided in the second region R2 of the first circuit layer 421 overlapping the second circuit pattern 422-2 in the vertical direction, the second circuit pattern 422-2 may be damaged. In addition, if a through hole having a relatively small diameter is provided in the second region R2 of the first circuit layer 421 overlapping the second circuit pattern 422-2 in the vertical direction, the gas in the insulating layer 411 corresponding to the third region R3 may not be easily discharged to the outside, and thus the physical and / or electrical characteristics of the circuit board and the semiconductor package may be deteriorated.

[0196] Therefore, in the embodiment, the second diameter W4 of each of the plurality of second through holes 421-2 disposed in the second region R2 of the first circuit layer 421 is greater than the first diameter W3 of each of the plurality of first through holes 421-1 disposed in the first region R1 of the first circuit layer 421. Therefore, the embodiment enables the gas generated in the insulating layer 411 to be discharged to the upper side of the first circuit layer 421 without affecting the impedance characteristics of the second circuit pattern 422-2.

[0197] However, the embodiment differs in the amount of gas discharged for each region in the first circuit layer 421 , so that the gas generated in the insulating layer 411 can be completely removed without changing the characteristics of the second circuit layer 422 disposed under the first circuit layer 421 .

[0198] Specifically, the gas generated in the insulating layer 411 of the embodiment can be discharged centrally through a plurality of second through holes 421-2 disposed in the second region R2 of the first circuit layer 421 having a relatively large diameter. That is, when the adhesion between the second region R2 and the insulating layer 411 is reduced, the electrical characteristics of the second circuit pattern 422-2 may be reduced. Therefore, the embodiment allows the diameter of the plurality of second through holes 421-2 disposed in the second region R2 to be greater than the diameter of the through holes disposed in other regions. However, when the gas generated in the insulating layer 411 is discharged only through the second through holes 421-2 of the second region R2, the gas in the insulating layer 411 may not be completely discharged. Therefore, even through the first through hole 421-1 of the first region R1 of the first circuit layer 421 having a relatively small diameter, the embodiment may allow a portion of the gas in the insulating layer 411 to be discharged. In this way, the embodiment can completely discharge the gas generated in the insulating layer 411 to the outside of the circuit board 100. Therefore, the embodiment can further improve the physical and / or electrical characteristics of the circuit board and the semiconductor package.

[0199] In addition, the third region R3 of the first circuit layer 421 may be a portion disposed in the edge region of the surface of the insulating layer 411. At this time, the circuit pattern disposed in the edge region of the insulating layer 411 may affect the rigidity of the circuit board and the semiconductor package. That is, if the diameter of the third through hole 421-3 disposed in the third region R3 of the first circuit layer 421 is large, the area of ​​the third region R3 in the edge region of the insulating layer 411 may also be reduced. In addition, if the area of ​​the third region R3 in the edge region is reduced, the rigidity of the circuit board and the semiconductor package may be reduced. For example, if the area of ​​the third region R3 in the edge region is reduced, the problem of the circuit board and the semiconductor package being greatly bent in a specific direction may occur. Therefore, the embodiment allows the diameter of the third through hole 421-3 disposed in the third region R3 to be smaller than each of the diameters of the first through hole 421-1 and the second through hole 421-2. Therefore, the embodiment prevents the circuit board and the semiconductor package from bending in a specific direction, while allowing the gas generated in the insulating layer 411 to be completely discharged to the outside of the circuit board 100. In this way, the embodiment can further improve the physical and / or electrical characteristics of the circuit board and the semiconductor package.

[0200] At this time, although the third region R3 is described as a circuit pattern disposed in the edge region of the insulating layer 411, the embodiment is not limited thereto. For example, unlike the first and second regions R1 and R2, the third region R3 may refer to a circuit pattern disposed in the edge region of the insulating layer.

[0201] In addition, among the plurality of first through holes 421-1 disposed in the first region R1, two adjacent first through holes may be spaced apart from each other by a first separation distance. In addition, among the plurality of second through holes 421-2 disposed in the second region R2, two adjacent second through holes may be spaced apart from each other by a second separation distance. In addition, among the plurality of third through holes 421-3 disposed in the third region R3, two adjacent third through holes may be spaced apart from each other by a third separation distance. At this time, the first separation distance, the second separation distance, and the third separation distance may be different from each other. Preferably, the second separation distance may be the smallest of the first separation distance, the second separation distance, and the third separation distance. In addition, the third separation distance may be the largest of the first separation distance, the second separation distance, and the third separation distance. That is, the embodiment allows the minimum separation distance between the plurality of second through holes 421-2. Therefore, the embodiment allows the second through hole 421-2 having a larger area to be disposed in the second region R2. Therefore, the embodiment enables the gas generated in the insulating layer 411 to be completely discharged while improving the electrical characteristics of the second circuit pattern 422-2. In addition, the embodiment may make the first separation distance of the first through hole 421-1 greater than the second separation distance, so that the gas generated by the first through hole 421-1 in the insulating layer 411 can be completely discharged. In addition, the embodiment may make the third separation distance of the third through hole 421-3 greater than each of the first separation distance and the second separation distance, so that the gas generated in the insulating layer 411 can be completely discharged without affecting the rigidity of the circuit board and the semiconductor package.

[0202] At this time, the diameter W3 of the plurality of first through holes 421-1 disposed in the first region R1 and the first separation distance between the plurality of first through holes will be described. In addition, based on the following description, the diameter W4 and separation distance of the plurality of second through holes 421-2 disposed in the second region R2, and the diameter W5 and separation distance of the plurality of third through holes 421-3 disposed in the third region R3 may have a range that satisfies the conditions.

[0203] The diameter W3 of each of the plurality of first through holes 421-1 disposed in the first region R1 of the first circuit layer 421 may be equal to or greater than the separation distance between two adjacent first through holes in the plurality of first through holes 421-1. That is, the diameter W3 of each of the plurality of first through holes 421-1 disposed in the first region R1 may be equal to or greater than the separation distance between two adjacent first through holes in the plurality of first through holes 421-1. At this time, if the diameter W3 of each of the plurality of first through holes 421-1 is smaller than the separation distance between two adjacent through holes in the plurality of first through holes 421-1, the gas generated in the insulating layer 411 may not be easily discharged to the outside of the circuit board 100. That is, the fact that the diameter W3 of the first through hole 421-1 is smaller than the separation distance between the plurality of first through holes may mean that, relative to the region in which the first through hole 421-1 is disposed in the first region R1, the region in which the gas cannot be discharged is larger than the region in which the gas can be discharged through the first through hole 421-1. In addition, if the separation distance between the plurality of first through holes 421-1 is greater than the diameter W3 of the first through hole 421-1, the gas may not be discharged well and may remain in the insulating layer 411, and thus the physical properties may deteriorate. At this time, the separation distance may vary depending on the arrangement direction of the plurality of first through holes 421-1. For example, if the plurality of first through holes 421-1 are arranged in a zigzag shape in the diagonal direction in the first region R1, the separation distance may refer to the separation distance between two first through holes positioned diagonally from each other in the plurality of first through holes. In addition, if the plurality of first through holes 421-1 are arranged at predetermined intervals in a first horizontal direction parallel to the first side of the circuit board or in a second horizontal direction perpendicular to the first side, the separation distance may refer to the separation distance between two first through holes positioned adjacently in the first horizontal direction or the second horizontal direction in the plurality of first through holes.

[0204] In addition, the embodiment allows the diameter W3 of at least one of the plurality of first through holes 421-1 to be equal to or greater than a certain level while ensuring that the diameter W3 of the first through hole 421-1 is equal to or greater than the separation distance between the through holes. The diameter W3 of the first through hole 421-1 may be determined based on the plane area of ​​the circuit board 100. That is, if the diameter W3 of the first through hole 421-1 is too small compared to the plane area of ​​the circuit board 100, the gas generated from the insulating layer 411 may not be properly discharged to the outside of the circuit board 100, and thus the effect of improving the adhesion between the insulating layer 411 and the circuit layer may be insufficient.

[0205] In addition, as described above based on the aforementioned embodiment, the diameter W3 of the first through hole 421-1 may be at least 165 μm or greater. In addition, as described above, the diameter W3 of the first through hole 421-1 may satisfy the range of 165 μm to 220 μm. Preferably, the diameter W3 of the first through hole 421-1 may satisfy the range of 165 μm to 210 μm. More preferably, the diameter W3 of the first through hole 421-1 may satisfy the range of 165 μm to 205 μm. In addition, as described above, the ratio of the diameter of the first through hole 421-1 to the area of ​​the insulating layer 411 may satisfy the range of 0.0000825 to 0.000147. In addition, as described above, the ratio of the planar area of ​​the first through hole 421-1 to the planar area of ​​the insulating layer 411 may satisfy the range of 0.00025905 to 0.0004605. That is, the planar area of ​​the insulating layer 411 may be 1500 mm 2 Up to 2000mm 2 , at least one of the plurality of first through holes 421-1 may have a diameter of 165 μm to 220 μm, and a plane area of ​​at least one of the plurality of first through holes 421-1 may satisfy 518.1 μm 2 To 690.8μm 2 In addition, the separation distance between the plurality of first through holes 421-1 may be less than or equal to the diameter W3 of the first through hole 421-1 and greater than or equal to the width of the through electrode 430. If the separation distance is less than the width of the through electrode 430, the first through hole 421-1 and the through electrode 430 may overlap in the vertical direction, or the area of ​​the region overlapping in the vertical direction may increase. In addition, if the area of ​​the region overlapping in the vertical direction increases, the signal transmission characteristics of the through electrode 430 may deteriorate.

[0206] For example, refer to Fig.14 In the embodiment of the present invention, the through-electrode 430 may be provided to pass through the insulating layer 411. At this time, the first through-hole 421-1, the second through-hole 421-2, and the third through-hole 421-3 provided in the first circuit layer 421 may not vertically overlap with the through-electrode 430 provided in the first layer of the insulating layer. In this way, the embodiment minimizes the transmission loss of the signal transmitted through the through-electrode 430. In addition, the diameter of the through-hole provided in each of the above-mentioned circuit patterns may be larger than the diameter of the through-electrode 430.

[0207] That is, a diameter W3 of the first through hole 421 - 1 disposed in the first region R1 , a diameter W4 of the second through hole 421 - 2 disposed in the second region R2 , and a diameter W5 of the third through hole 421 - 3 disposed in the third region R3 may each be greater than a diameter of the through electrode 430 .

[0208] At this time, the through electrode 430 may have a slope whose width gradually changes from the upper surface to the lower surface of the insulating layer 411. In addition, the diameter W3 of the first through hole 421-1 disposed in the first region R1, the diameter W4 of the second through hole 421-2 disposed in the second region R2, and the diameter W5 of the third through hole 421-3 disposed in the third region R3 may each be greater than the width of the region having the largest width in the through electrode 430.

[0209] In addition, the first circuit layer 421 may include a pad 421-5 overlapping the through electrode 430 in a vertical direction. The pad 421-5 may be a circuit pattern connected to the through electrode 430. In addition, the first circuit layer 421 may include a fourth through hole 121-4 provided corresponding to the region where the pad 421-5 is provided. At this time, the fourth through hole 421-4 may have a different function from the first to third through holes 421-1, 421-2, and 421-3.

[0210] That is, the first to third through holes 421-1, 421-2, and 421-3 may be used as gas exhaust holes, and therefore, other circuit patterns of the first circuit layer 421 may not be disposed in the inner regions of the first to third through holes 421-1, 421-2, and 421-3. That is, the inner regions of the first to third through holes 421-1, 421-2, and 421-3 may be filled with other insulating layers disposed thereon.

[0211] Alternatively, the fourth through hole 421-4 may be a separation area for separating the pad 421-5 from another circuit pattern. Therefore, other circuit patterns of the first circuit layer 421 may be disposed in the inner area of ​​the fourth through hole 421-4. For example, the pad 421-5 of the first circuit layer 421 may be disposed in the inner area of ​​the fourth through hole 421-4. In addition, the diameter of the fourth through hole 421-4 may be smaller than the diameters of the first to third through holes 421-1, 421-2, and 421-3.

[0212] In summary, the diameter W3 of the first through hole 421-1 disposed in the first region R1, the diameter W4 of the second through hole 421-2 disposed in the second region R2, and the diameter W5 of the third through hole 421-3 disposed in the third region R3 may each be greater than the width of the through electrode 430. In addition, the diameter W4 of the second through hole 421-2 disposed in the second region R2 may be greater than the diameter W3 of the first through hole 421-1 disposed in the first region R1 and the diameter W5 of the third through hole 421-3 disposed in the third region R3. In addition, the diameter W5 of the third through hole 421-3 disposed in the third region R3 may be smaller than each of the diameter W3 of the first through hole 421-1 disposed in the first region R1 and the diameter W4 of the second through hole 421-2 disposed in the second region R2. In addition, the separation distance between two adjacent second through holes in the plurality of second through holes 421-2 may be less than each of the separation distance between two adjacent first through holes in the plurality of first through holes 421-1 and the separation distance W8 between two adjacent third through holes in the plurality of third through holes 421-3. In addition, the separation distance between two adjacent third through holes in the plurality of third through holes 421-3 may be greater than the separation distance between two adjacent first through holes in the plurality of first through holes 421-1 and the separation distance between two adjacent second through holes in the plurality of second through holes 421-2, respectively. In addition, the diameter of each through hole and the separation distance of each through hole may be greater than the width of the through electrode 430.

[0213] On the other hand, when the semiconductor package having the above-mentioned characteristics of the present invention is used for IT devices or household appliances, such as smart phones, server computers, televisions, etc., functions such as signal transmission or power supply can be stably performed. For example, the semiconductor package having the characteristics of the present invention can be used to safely protect the semiconductor device from external moisture or contaminants, or, it can solve the leakage current, electrical short circuit between terminals, and electrical open circuit problems of terminals supplied to the semiconductor device. In addition, when responsible for the signal transmission function, the noise problem can be solved. In this way, the semiconductor package having the above-mentioned characteristics of the present invention can maintain the stable function of the IT device or household appliances, so that the entire product and the semiconductor package applying the present invention can achieve functional unification or technical interlocking.

[0214] When the semiconductor package having the above-mentioned characteristics of the present invention is used in a transportation device such as a vehicle, the problem of signal distortion transmitted to the transportation device can be solved, or the safety of the transportation device can be further improved by safely protecting the semiconductor device controlling the transportation device from the outside and solving the problem of leakage current or electrical short circuit between terminals or electrical open circuit of terminals supplied to the semiconductor device. Therefore, the transportation device and the semiconductor package to which the present invention is applied can achieve functional integrity or technical interlocking with each other.

[0215] The characteristics, structures and effects described in the above embodiments are included in at least one embodiment, but are not limited to one embodiment. In addition, the characteristics, structures and effects shown in each embodiment can even be combined or modified by a person skilled in the art to which the embodiment belongs with respect to other embodiments. Therefore, it should be understood that the contents related to such combination and such modification are included in the scope of the embodiment.

[0216] The above description has focused on the embodiment, but it is merely illustrative and does not limit the embodiment. It will be appreciated by those skilled in the art that various modifications and applications not shown above may be made without departing from the essential features of the embodiment. For example, each component specifically indicated in the embodiment may be modified and implemented. In addition, it should be understood that the differences associated with these changes and applications are included in the scope of the embodiment defined in the appended claims.

Claims

1. A circuit board, comprising: Insulation layer; and a circuit layer, the circuit layer being disposed on the insulating layer and having a lower surface contacting the insulating layer and an upper surface facing the lower surface, wherein the circuit layer includes a plurality of through holes passing through the upper surface and the lower surface, and The diameter of each of the plurality of through holes is equal to or greater than a separation distance between two through holes adjacent to each other in the plurality of through holes.

2. The circuit board according to claim 1, wherein the diameter of each of the plurality of through holes is different from each other, in, The separation distances between two through holes disposed adjacent to each other among the plurality of through holes are different from each other, and The diameter of the smallest through hole among the plurality of through holes is equal to or greater than the maximum separation distance among the separation distances between two through holes arranged adjacent to each other. 3 . The circuit board according to claim 1 , wherein a ratio of a diameter of the through hole to a plane area of ​​the insulating layer satisfies a range of 0.0000825 to 0.000147. 4 . The circuit board according to claim 1 , wherein a ratio of a plane area of ​​the through hole to a plane area of ​​the insulating layer satisfies a range of 0.00025905 to 0.0004605.

5. The circuit board according to claim 3 or 4, wherein the plane area of ​​the insulating layer is 1500 mm 2 Up to 2000mm 2 .

6. The circuit board according to claim 3 or 4, wherein: At least one of the plurality of through holes has a diameter of 165 μm to 220 μm.

7. The circuit board according to claim 3 or 4, wherein: The plane area of ​​at least one of the plurality of through holes satisfies 518.1 μm 2 To 690.8μm 2 range.

8. The circuit board according to claim 3, wherein the circuit layer comprises a plurality of circuit patterns spaced apart in a horizontal direction, in, The plurality of through holes are respectively disposed in the plurality of circuit patterns, and Wherein, the intervals between the plurality of circuit patterns are smaller than the diameter of the through hole.

9. The circuit board according to claim 1, further comprising: a through electrode passing through the insulating layer and connected to the circuit layer, and Wherein, the diameter of the through hole is greater than the width of the through electrode in the horizontal direction. 10 . The circuit board according to claim 9 , wherein each of the plurality of through holes is not connected to an outer surface of the circuit layer and does not overlap with the through electrode in a vertical direction.

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