Array substrate, array mother board, display panel and display device

Abstract

An array substrate (10) has a display region (A) and a first bezel region (B1) arranged in a first direction (X). The first frame area (B1) comprises a chip setting area (C) and a binding area (D), and the binding area (D) is located on at least one side of the chip setting area (C) in the second direction (Y); the second direction (Y) is substantially perpendicular to the first direction (X). The array substrate (10) comprises a plurality of driving bonding pads (110), a plurality of binding pins (120) and a plurality of peripheral connecting lines (130). The plurality of driving bonding pads (110) are arranged in the chip arrangement area (C), and the driving bonding pads (110) are configured to be connected with the driving chip (500). The plurality of binding pins (120) are arranged in the binding area (D). The binding pins (120) are configured to be connected with a circuit board. The plurality of peripheral connecting lines (130) are arranged in the first frame area (B1). One end of each peripheral connecting line (130) is connected with the driving bonding pad (110), and the other end of each peripheral connecting line (130) is connected with the binding pin (120). The plurality of peripheral connecting lines (130) comprise first peripheral connecting lines (131), and the first peripheral connecting lines (131) extend to one side, close to the binding area (D), of the chip setting area (C) in the chip setting area (C). One end of the first peripheral connecting line (131) is connected with the driving bonding pad (110) in the chip setting area (C), and the other end of the first peripheral connecting line (131) is connected with the binding pin (120) of the binding area (D).

Description

Array substrate, array motherboard, display panel and display device Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate, an array motherboard, a display panel, and a display device. Background Art

[0002] With the rapid development of display technology, display technologies such as Liquid Crystal Display (LCD), Organic Light Emitting Display (OLED), Quantum Dot Light Emitting Display (QLED), and Mini / Micro Light Emitting Display (MLED) have become widely integrated into people's daily lives. For example, smartphones, wearable watches, televisions, laptops, and in-car displays have gradually become ubiquitous in people's lives. Currently, how to reduce the bezel of display devices and increase the screen-to-body ratio of display devices has always been the focus of display technology research and development.

[0003] Summary of the Invention

[0004] In one aspect, an array substrate is provided. The array substrate comprises a display area and a first border area arranged along a first direction. The first border area includes a chip placement area and a binding area, wherein the binding area is located on at least one side of the chip placement area along a second direction intersecting the first direction.

[0005] The array substrate includes a plurality of driving pads, a plurality of binding pins and a plurality of peripheral connection lines. The plurality of driving pads are arranged in the chip setting area, and the driving pads are configured to be connected to the driving chip. The plurality of binding pins are arranged in the binding area. The binding pins are configured to be connected to the circuit board. The plurality of peripheral connection lines are arranged in the first border area. One end of each peripheral connection line is connected to the driving pad, and the other end is connected to the binding pin. Wherein, the plurality of peripheral connection lines include a first peripheral connection line, the first peripheral connection line extends in the chip setting area to a side of the chip setting area close to the binding area, and one end of the first peripheral connection line is connected to the driving pad in the chip setting area, and the other end is connected to the binding pin of the binding area.

[0006] In some embodiments, the plurality of drive pads are arranged into a plurality of drive pad groups, and the plurality of drive pad groups include an output pad group and an input pad group. The output pad group includes a plurality of output pads arranged along the second direction. The input pad group includes a plurality of input pads arranged along the second direction. The input pad group is located on a side of the output pad group away from the display area. The first peripheral connection line extends between the input pad group and the output pad group to a side of the chip setting area close to the binding area; and one end of the first peripheral connection line is connected to one end of the input pad close to the output pad group, and the other end is connected to one end of the binding pin close to the display area.

[0007] In some embodiments, the multiple peripheral connection lines also include a second peripheral connection line, which extends from a side of the chip setting area away from the display area to a side of the chip setting area close to the binding area; one end of the second peripheral connection line is connected to an end of the input pad away from the output pad group, and the other end is connected to an end of the binding pin of the binding area close to the display area.

[0008] In some embodiments, the binding pin connected to the first peripheral connection line is a first binding pin. The binding pin connected to the second peripheral connection line is a second binding pin. The first binding pin is farther away from the chip setting area than the second binding pin, and the second peripheral connection line is located on a side of the first peripheral connection line farther away from the display area.

[0009] In some embodiments, the input pad group includes a plurality of input pad subgroups, each of the input pad subgroups including a plurality of input pads arranged adjacent to each other and transmitting the same signal. The plurality of second peripheral connection lines include a first type of second peripheral connection line and a second type of second peripheral connection line. The first type of second peripheral connection line is connected to the binding pin and one of the input pad subgroups. The second type of second peripheral connection line is connected to the binding pin and at least two input pad subgroups, and the second type of second peripheral connection line is located on a side of the first type of second peripheral connection line away from the display area.

[0010] In some embodiments, along the second direction, the binding area is located on opposite sides of the chip setting area. The plurality of second peripheral connection lines include two first-type second peripheral connection lines and one second-type second peripheral connection line. The two first-type second peripheral connection lines are respectively connected to the input solder sub-group and the binding pins on the first side of the chip setting area. The two first-type second peripheral connection lines are sequentially away from the display area. The one second-type second peripheral connection line is connected to the binding pins on the first side of the chip setting area and the two input solder sub-groups. The second-type second peripheral connection line is located on a side of the two first-type second peripheral connection lines away from the display area.

[0011] In some embodiments, the input pad group includes a plurality of input pad subgroups, each of which includes a plurality of input pads that are adjacently arranged and transmit the same signal. The array substrate further includes an input adapter line, the input adapter line being arranged in the chip arrangement area and connected to at least two input pad subgroups. One of the at least two input pad subgroups is further connected to a second peripheral connection line.

[0012] In some embodiments, the bonding area is located on opposite sides of the chip placement area along the second direction. The plurality of second peripheral connection lines include two first-type second peripheral connection lines, the two first-type second peripheral connection lines being connected to the input solder subassembly and the bonding pins on the second side of the chip placement area, respectively. The two first-type second peripheral connection lines are sequentially spaced away from the display area.

[0013] The array substrate further includes an input adapter line connected to three input solder sub-assemblies. Of the three input solder sub-assemblies, two input solder sub-assemblies and one input solder sub-assembly are located on opposite sides of the input solder sub-assembly connected to a first-type second peripheral connection line that is relatively farther from the display area. Furthermore, one input solder sub-assembly is connected to a first-type second peripheral connection line that is relatively closer to the display area.

[0014] In some embodiments, the array substrate further includes a plurality of sub-pixels, a plurality of data lines, a plurality of scan lines, and a test circuit. The plurality of sub-pixels are disposed in the display area. The plurality of data lines are connected to the plurality of sub-pixels. The plurality of scan lines are connected to the plurality of sub-pixels. The test circuit is connected to the plurality of data lines, the plurality of scan lines, and the plurality of sub-pixels. The test circuit is configured to receive a test signal transmitted by an external circuit during a test phase.

[0015] In some embodiments, the sub-pixels include a common electrode. The test circuit includes a first test circuit, a second test circuit, and a first test signal line. The first test circuit is connected to the plurality of data lines. The first test circuit is configured to receive data signals transmitted by an external circuit during a test phase. The second test circuit is connected to the plurality of scan lines. The second test circuit is configured to receive scan signals transmitted by an external circuit during a test phase. The first test signal line is connected to the common electrode of the plurality of sub-pixels. The first test signal line is configured to transmit a common voltage signal.

[0016] In some embodiments, the test circuit further includes a first test pad disposed between the plurality of peripheral connection lines and the display area, and the first test circuit, the second test circuit, and the first test signal line are respectively connected to the first test pad.

[0017] In some embodiments, the test circuit further includes a plurality of residual patch cords. The plurality of residual patch cords are disposed between the binding area and the chip placement area. The residual patch cords extend along the first direction to a boundary of the array substrate. The first test circuit, the second test circuit, and the first test signal line are respectively connected to the residual patch cords.

[0018] In some embodiments, the array substrate includes an output pad group and an input pad group, the output pad group includes a data output pad, and the data output pad is connected to the data line. The first test circuit is disposed between the input pad group and the output pad group and is connected to the data output pad.

[0019] In some embodiments, the array substrate further comprises a second border region, a third border region, and a fourth border region, wherein the second border region is located on a side of the display region away from the first border region; and along the second direction, the third border region and the fourth border region are located on opposite sides of the display region. The first test circuit is disposed in the second border region and is connected to the plurality of data lines.

[0020] In some embodiments, the plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel emitting different colors. The plurality of data lines include a first data line, a second data line, and a third data line, wherein the first data line is connected to the first sub-pixel, the second data line is connected to the second sub-pixel, and the third data line is connected to the third sub-pixel.

[0021] The first test circuit includes a first data test line, a second data test line, a third data test line, a first transistor, a second transistor, a third transistor, and a first switch signal line. The first data test line is configured to transmit a data signal for illuminating a first sub-pixel. The second data test line is configured to transmit a data signal for illuminating a second sub-pixel. The third data test line is configured to transmit a data signal for illuminating a third sub-pixel.

[0022] A first electrode of the first transistor is connected to the first data test line, and a second electrode of the first transistor is connected to the first data line. A first electrode of the second transistor is connected to the second data test line, and a second electrode of the second transistor is connected to the second data line. A first electrode of the third transistor is connected to the third data test line, and a second electrode of the third transistor is connected to the third data line. The first switching signal line is connected to the gates of the first transistor, the second transistor, and the third transistor.

[0023] In some embodiments, the plurality of sub-pixels are arranged in multiple rows and columns, the scan lines include a first scan line and a second scan line, the first scan line is connected to the sub-pixels in odd-numbered rows, and the second scan line is connected to the sub-pixels in even-numbered rows. The plurality of driving pads include a plurality of first scan output pads and a plurality of second scan output pads.

[0024] The array substrate further includes a first scan connection line and a second scan connection line, wherein the first scan connection line is connected to the first scan line and the first scan output pad, and the second scan connection line is connected to the second scan line and the second scan output pad.

[0025] The second test circuit includes a first scan test line, a second scan test line, a fourth transistor, a fifth transistor, and a second switch signal line. The first scan test line is configured to transmit a scan signal for illuminating sub-pixels in odd-numbered rows. The second scan test line is configured to transmit a scan signal for illuminating sub-pixels in even-numbered rows. A first electrode of the fourth transistor is connected to the first scan test line, and a second electrode of the fourth transistor is connected to the first scan output pad. A first electrode of the fifth transistor is connected to the second scan test line, and a second electrode of the fifth transistor is connected to the second scan output pad. The second switch signal line is connected to the gates of the fourth and fifth transistors.

[0026] In some embodiments, the first test circuit includes a first switch signal line, and the second switch signal line and the first switch signal line are the same signal line.

[0027] In some embodiments, the plurality of drive pads include scan output pads, and the array substrate includes a gate drive circuit and a gate control signal line. The gate drive circuit is connected to the plurality of scan lines. The gate control signal line is connected to the gate drive circuit and the scan output pads. The second test circuit includes a plurality of gate control test lines, the plurality of gate control test lines being connected to the scan output pads. The gate control test lines are configured to transmit gate control signals for illuminating sub-pixels.

[0028] In some embodiments, the plurality of driving pads include a common voltage pad connected to a common electrode of the plurality of sub-pixels, and the first test signal line is connected to the common voltage pad.

[0029] In some embodiments, the plurality of drive pads are arranged into a plurality of drive pad groups, the plurality of drive pad groups including an output pad group and an input pad group. The output pad group includes a plurality of output pads arranged along the second direction. The input pad group includes a plurality of input pads arranged along the second direction. Along the second direction, the input pad group is located on at least one side of the output pad group.

[0030] The plurality of drive pad groups are located near a boundary of the display area and substantially overlap with a boundary of the chip setting area near the display area. The first peripheral connection line extends from a side of the plurality of drive pad groups away from the display area to a side of the chip setting area near the binding area. Furthermore, one end of the first peripheral connection line is connected to an end of the input pad group away from the display area, and the other end is connected to an end of the binding pin near the display area.

[0031] Alternatively, the plurality of drive pad groups are located away from a boundary of the display area and substantially coincide with a boundary of the chip setting area away from the display area. The first peripheral connection line extends from a side of the plurality of drive pad groups close to the display area to a side of the chip setting area close to the binding area. Furthermore, one end of the first peripheral connection line is connected to an end of the input pad group close to the display area, and the other end is connected to an end of the binding pin close to the display area.

[0032] In some embodiments, the chip setting area and the binding area are substantially rectangular in shape, the binding area is away from a boundary of the display area, and is substantially flush with the boundary of the chip setting area away from the display area.

[0033] In some embodiments, the plurality of peripheral connection lines include a second peripheral connection line, the distance between the chip placement area and a first boundary is a first distance, and the distance between the binding area and the first boundary is a second distance. The first boundary is a boundary of the first border area of ​​the array substrate away from the display area. The first distance is greater than the second distance.

[0034] In some embodiments, the difference between the first distance and the second distance is 0.3 mm to 0.6 mm.

[0035] In some embodiments, the array substrate has an axis extending along the first direction, and the plurality of driving pads, the plurality of binding pins, and the plurality of peripheral connection lines are symmetrically arranged about the axis.

[0036] In another aspect, an array motherboard is provided. The array motherboard has multiple product areas and multiple to-be-cut areas, with one to-be-cut area located between each two adjacent product areas. The array motherboard includes the array substrate described in any of the above embodiments, the array substrate being located in the product areas.

[0037] In some embodiments, the array substrate includes a first test circuit, a second test circuit, a first test signal line, and a plurality of residual patch cords. The array motherboard also includes a second test pad, which is disposed in the area to be cut. The plurality of test leads are disposed in the area to be cut. The test leads are connected to the residual patch cords and the second test pad.

[0038] In some embodiments, the test leads include a cut patch line and a test connection line. One of the cut patch lines is connected to one of the remaining patch lines. The cut patch line extends along the first direction. The cut patch line and the remaining patch line are made of the same material and are disposed on the same layer. The test connection line is connected to the cut patch line and the second test pad.

[0039] In yet another aspect, a display panel is provided. The display panel includes the array substrate and a color filter substrate as described in any of the above embodiments. The color filter substrate is disposed opposite the array substrate. The boundary of the first border region of the array substrate extends beyond the boundary of the color filter substrate. The boundary of the array substrate away from the first border region and both boundaries in the second direction are substantially flush with the boundary of the color filter substrate. The chip placement area, bonding area, and peripheral connection lines of the array substrate are all located between the boundary of the first border region of the array substrate and the boundary of the color filter substrate.

[0040] In some embodiments, the array substrate includes a first test pad, and the first test pad is disposed between the color filter substrate and the peripheral connection line.

[0041] In another aspect, a display device is provided. The display device includes the display panel described in any of the above embodiments, a driver chip, and a flexible circuit board. The driver chip is connected to a driver pad on an array substrate of the display panel. The flexible circuit board is connected to a binding pin on the array substrate of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the technical solutions of the present disclosure, the following briefly introduces the drawings required for use in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of the present disclosure.

[0043] FIG1 is a structural diagram of a display device according to some embodiments;

[0044] FIG2A is a structural diagram of another display device according to some embodiments;

[0045] FIG2B is a structural diagram of another display device according to some embodiments;

[0046] FIG3 is a cross-sectional view taken along section line AA′ in FIG2A ;

[0047] FIG4 is a structural diagram of the interior of a display device according to some embodiments;

[0048] FIG5 is a structural diagram of the interior of another display device according to some embodiments;

[0049] FIG6A is a top view of an array substrate according to some embodiments;

[0050] FIG6B is a top view of another array substrate according to some embodiments;

[0051] FIG7 is a top view of another array substrate according to some embodiments;

[0052] FIG8 is a diagram illustrating the position relationship between driving pads and binding pins of a display panel according to some embodiments;

[0053] FIG9 is a diagram illustrating the position relationship between driving pads and binding pins of another display panel according to some embodiments;

[0054] FIG10 is a diagram showing the position relationship between driving pads and binding pins of another display panel according to some embodiments;

[0055] FIG11 is a diagram showing the position relationship between driving pads and binding pins of another display panel according to some embodiments;

[0056] FIG12A is a structural diagram of a first binding area of ​​a display panel according to some embodiments;

[0057] FIG12B is a structural diagram of a first binding area of ​​another display panel according to some embodiments;

[0058] FIG13 is a structural diagram of a first binding area of ​​another display panel according to some embodiments;

[0059] FIG14 is a structural diagram of a first binding area of ​​yet another display panel according to some embodiments;

[0060] FIG15A is a partial enlarged view of point E in FIG12A;

[0061] FIG15B is a partial enlarged view of the left side of FIG12B;

[0062] FIG15C is a partial enlarged view of the right side of FIG12B;

[0063] FIG16 is a cross-sectional view along section line BB′ in FIG4 and FIG5;

[0064] FIG17 is another cross-sectional view along section line BB′ in FIG4 and FIG5;

[0065] FIG18 is a structural diagram of a first binding area of ​​another display panel according to some embodiments;

[0066] FIG19 is a partial enlarged view of point H in FIG18;

[0067] FIG20 is a partial enlarged view of L in FIG18;

[0068] FIG21 is a block diagram of a first test circuit according to some embodiments;

[0069] FIG22 is a block diagram of a second test circuit according to some embodiments;

[0070] FIG23 is a top view of an array motherboard according to some embodiments;

[0071] FIG24 is a partial enlarged view of an array motherboard according to some embodiments;

[0072] FIG25 is a partial enlarged view of point J in FIG24 . DETAILED DESCRIPTION

[0073] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the embodiments described are only some embodiments of the present disclosure, not all embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of the present disclosure.

[0074] Unless the context requires otherwise, throughout the specification and claims, the term "comprise" and its other forms, such as the third person singular form "comprises" and the present participle form "comprising", are to be interpreted as open and inclusive, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "example", "specific example" or "some examples" are intended to indicate that the particular features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the particular features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0075] Terms such as "first" and "second" are used herein to describe various elements, but these elements should not be limited by these terms. These terms are only used to distinguish one component from other components. For example, an element referred to as a first element in one embodiment can be referred to as a second element in another embodiment without departing from the scope of the appended claims. Unless otherwise mentioned, terms in the singular may include plural forms.

[0076] When describing some embodiments, the word "connected" and its derivatives may be used. The term "connected" should be understood in a broad sense. For example, "connected" can mean fixed connection, detachable connection, or integration; it can be directly connected or indirectly connected through an intermediate medium.

[0077] “At least one of A, B and C” has the same meaning as “at least one of A, B or C” and both include the following combinations of A, B and C: A only, B only, C only, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B and C.

[0078] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0079] The use of "adapted to" or "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0080] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0081] As used herein, "about," "approximately," or "approximately" are inclusive of the stated value and mean within an acceptable range of deviation for the particular value as determined by one of ordinary skill in the art, taking into account the measurements in question and the errors associated with the measurement of the particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0082] As used herein, "parallel", "perpendicular", and "equal" include the situations described and situations similar to the situations described, and the range of the similar situations is within an acceptable deviation range, wherein the acceptable deviation range is as determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of the specific quantity (i.e., the limitations of the measurement system). For example, "parallel" includes absolute parallelism and approximate parallelism, wherein the acceptable deviation range of approximate parallelism can be, for example, a deviation within 5°; "perpendicular" includes absolute perpendicularity and approximate perpendicularity, wherein the acceptable deviation range of approximate perpendicularity can also be, for example, a deviation within 5°. "Equal" includes absolute equality and approximate equality, wherein the acceptable deviation range of approximate equality can be, for example, that the difference between the two equals is less than or equal to 5% of either one.

[0083] As used herein, "substantially flush" and "substantially overlap" include the conditions described and conditions similar to the conditions described, the range of which is within an acceptable deviation range, wherein the acceptable deviation range is determined by a person of ordinary skill in the art taking into account the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "substantially flush" includes absolute flushness and approximate flushness, wherein the acceptable deviation range for approximate flushness may be, for example, a deviation within 0.05 mm. For example, "substantially overlap" includes absolute overlap and approximate overlap, wherein the acceptable deviation range for approximate overlap may be, for example, a deviation within 0.05 mm.

[0084] It will be understood that when a layer or element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present therebetween.

[0085] In addition, the transistors used in the embodiments of the present disclosure may be thin film transistors (TFT), field effect transistors (MOS) or other switching devices with the same characteristics. The embodiments of the present disclosure are described using thin film transistors as an example.

[0086] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0087] In this specification, unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the present invention belongs. It will be further understood that, unless expressly defined herein, terms (such as those defined in commonly used dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and should not be interpreted as an ideal or overly formal meaning.

[0088] In this disclosure, terms such as "lower," "below," "above," and "upper," and similar terms are used to explain the relationships between components shown in the drawings. These terms may be relative and described based on directions shown in the drawings, or based on the order in which process steps are formed, but are not limited thereto.

[0089] The term "opposite" means that the first element may be directly or indirectly opposite to the second element. In the case where a third element is interposed between the first and second elements, the first and second elements may be understood to be indirectly opposite to each other although they are still opposite to each other.

[0090] As shown in FIG. 1 and FIG. 2A , some embodiments of the present disclosure provide a display device 1000 , which may be any device that displays anything, whether in motion (eg, video) or stationary (eg, still image), and whether textual or graphic.

[0091] For example, referring to Figures 1 and 2A, the display device 1000 can be any product or component with a display function, such as a television, a laptop computer, a tablet computer, a mobile phone, a personal digital assistant (PDA), a navigator, a car display, a flight display, a wearable device, a virtual reality (VR) device, etc.

[0092] For example, as shown in FIG. 1 , the display device 1000 may be a portable display product; for example, the display device 1000 may be the smart phone shown in FIG. 1 .

[0093] For another example, as shown in FIG. 2A and FIG. 2B , the display device 1000 may be a wearable device; for example, the display device 1000 may be a smart watch as shown in FIG. 2A or FIG. 2B .

[0094] Furthermore, the display device 1000 may be a liquid crystal display (LCD), an electroluminescent display, or a photoluminescent display. If the display device 1000 is an electroluminescent display, the electroluminescent display may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device 1000 is a photoluminescent display, the photoluminescent display may be a quantum dot photoluminescent display.

[0095] In the following, some embodiments of the present disclosure are schematically described by taking the display device 1000 as the smart watch shown in FIG. 2A and the display device 1000 as a liquid crystal display device as an example, but the embodiments of the present disclosure are not limited thereto.

[0096] On this basis, as shown in FIG3 , the display device 1000 may include other electronic components such as a display panel 100 , a backlight module 200 , a housing 300 , a flexible circuit board 400 , a driver chip 500 and a mainboard 600 .

[0097] As shown in FIG. 3 , the driving chip 500 is connected to the display panel 100 , and the flexible circuit board 400 is connected to the display panel 100 and the main board 600 to provide various required signals to the display panel 100 .

[0098] As shown in Figure 3, the shell 300 may, for example, include a frame 310 and a cover plate 320. The longitudinal section of the frame 310 is U-shaped. The display panel 100, the backlight module 200, the flexible circuit board 400, the driver chip 500 and the main board 600 are all arranged in the frame 310, and the cover plate 320 is arranged at the opening of the frame 310.

[0099] As shown in FIG3 , the backlight module 200 is disposed on a side of the display panel 100 away from the cover plate 320 and is configured to provide light required for displaying images to the display panel 100. The backlight module 200 includes a backlight source, which includes a plurality of light-emitting devices, such as light-emitting diodes (LEDs).

[0100] It should be noted that the light emitting colors of the multiple light emitting devices may be the same or different. For example, the backlight source includes a red light emitting device emitting red light, a green light emitting device emitting green light, and a blue light emitting device emitting blue light.

[0101] As shown in Figures 3, 4, and 5, the display panel 100 includes an array substrate 10, a color filter substrate 20, and a liquid crystal layer 30. The array substrate 10 and the color filter substrate 20 are disposed opposite and aligned with each other, and the liquid crystal layer 30 is disposed between the array substrate 10 and the color filter substrate 20.

[0102] In some embodiments, as shown in FIG. 4 , FIG. 6A and FIG. 6B , the array substrate 10 has a display area A and a peripheral area B located on at least one side of the display area A.

[0103] The display area A is an area for displaying images, and is configured to be provided with a plurality of sub-pixels P and a plurality of signal lines, etc. The peripheral area B is an area for not displaying images, and is configured to be provided with a driving circuit and connection lines, etc.

[0104] For example, as shown in Figures 4 and 8, the peripheral area B includes a first border area B1, the display area A and the first border area B1 are arranged along a first direction X, and the first border area B1 includes a chip setting area C and a binding area D. The chip setting area C is configured to set the driver chip 500 (see Figure 3), and the binding area D is configured to connect to the flexible circuit board 400 (see Figure 3).

[0105] It should be noted that the first direction X can be, for example, the direction of a line connecting the center of the display area A and the center of the first border area B1. The chip setting area C and the binding area D are substantially polygonal in shape. Exemplarily, the chip setting area C and the binding area D are substantially rectangular, pentagonal, hexagonal, or irregular polygonal in shape.

[0106] In this document, "substantially polygonal" means that the chip placement area C and the bonding area D are generally polygonal in shape, but are not limited to standard polygons. Specifically, "polygonal" here encompasses not only basic polygonal shapes but also, taking into account process conditions, shapes similar to polygons. For example, the two sides of a polygon are curved at each intersection (i.e., at a corner), i.e., the corners are smooth, resulting in the chip placement area C and the bonding area D being rounded polygonal in shape.

[0107] Some embodiments of the present disclosure are schematically described below by taking the chip setting area C and the binding area D as being approximately rectangular as an example, but the embodiments of the present disclosure are not limited thereto.

[0108] It should be understood that the chip placement area C needs to be provided with the driver chip 500, and the bonding area D only needs to be connected to the flexible circuit board 400. Therefore, in the first direction X, the width of the chip placement area C can be greater than the width of the bonding area D.

[0109] 8 , the width of the binding area D is 0.35 mm to 1 mm in the first direction X. For example, the width of the binding area D is any one of 0.35 mm, 0.4 mm, 0.45 mm, 0.5 mm, 0.55 mm, 0.6 mm, 0.65 mm, 0.7 mm, 0.75 mm, 0.8 mm, 0.85 mm, 0.9 mm, 0.95 mm, and 1 mm in the first direction X.

[0110] 8 , the width of the chip placement area C in the first direction X is 0.6 mm to 1.2 mm. For example, the width of the chip placement area C in the first direction X is any one of 0.6 mm, 0.65 mm, 0.7 mm, 0.75 mm, 0.8 mm, 0.85 mm, 0.9 mm, 0.95 mm, 1 mm, 1.05 mm, 1.1 mm, 1.15 mm, and 1.2 mm.

[0111] Furthermore, the aforementioned binding area D is located away from the boundary of the display area A and can be substantially flush with the boundary of the chip placement area C away from the display area A. In this way, the distance between the binding area D and the display area A can be increased without increasing the width of the first border area B1 in the first direction X, thereby facilitating the arrangement of traces (e.g., the peripheral connection lines 130 in FIG. 12A ) or other circuit structures (e.g., the first test pads 1641 in FIG. 18 ) between the binding area D and the display area A.

[0112] In some embodiments, referring to Figures 4 and 5 , the boundary of the first border region B1 of the array substrate 10 extends beyond the boundary of the color filter substrate 20. The boundary of the array substrate 10 away from the first border region B1 and the two boundaries in the second direction Y are substantially flush with the boundary of the color filter substrate 20. It should be noted that the second direction Y intersects with the first direction X; for example, the second direction Y is substantially perpendicular to the first direction X.

[0113] For example, as shown in Figures 4 and 5, the peripheral area B may further include a second border area B2, a third border area B3, and a fourth border area B4. The second border area B2 is located on a side of the display area A away from the first border area B1. Along the second direction Y, the third border area B3 and the fourth border area B4 are located on opposite sides of the display area A.

[0114] The boundaries of the second frame area B2 , the third frame area B3 and the fourth frame area B4 of the array substrate 10 are substantially flush with the boundaries of the color filter substrate 20 .

[0115] In addition, referring to Figures 8 to 11, the chip setting area C and the binding area D of the array substrate 10 can be located between the boundary of the first border area B1 of the array substrate 10 and the boundary of the color filter substrate 20, so as to facilitate the connection of the flexible circuit board 400 (see Figure 3) and the driving chip 500 (see Figure 3) with the array substrate 10.

[0116] Exemplarily, the distance between the boundary of the first border area B1 of the color film substrate 20 and the boundary of the display area A is 0.9 mm to 2.5 mm. For example, the distance between the boundary of the first border area B1 of the color film substrate 20 and the boundary of the display area A is any one of 0.9 mm, 1 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, 1.5 mm, 1.6 mm, 1.7 mm, 1.8 mm, 1.9 mm, 2 mm, 2.1 mm, 2.2 mm, 2.3 mm, 2.4 mm, and 2.5 mm.

[0117] Exemplarily, the distance between the boundary of the first border area B1 of the color filter substrate 20 and the boundary of the chip placement area C is 0.29 mm to 1.5 mm. For example, the distance between the boundary of the first border area B1 of the color filter substrate 20 and the boundary of the chip placement area C is any one of 0.29 mm, 0.3 mm, 0.4 mm, 0.5 mm, 0.55 mm, 0.6 mm, 0.65 mm, 0.7 mm, 0.8 mm, 0.9 mm, 1 mm, 1.1 mm, 1.2 mm, 1.3 mm, 1.4 mm, and 1.5 mm.

[0118] Exemplarily, the distance between the boundary of the first border area B1 and the boundary of the binding area D of the color film substrate 20 is 0.49 mm to 2.35 mm. For example, the distance between the boundary of the first border area B1 and the boundary of the binding area D of the color film substrate 20 is any one of 0.49 mm, 0.5 mm, 0.55 mm, 0.6 mm, 0.7 mm, 0.75 mm, 0.8 mm, 0.9 mm, 1 mm, 1.2 mm, 1.4 mm, 1.5 mm, 1.6 mm, 1.65 mm, 1.7 mm, 1.9 mm, 2 mm, 2.1 mm, 2.2 mm, 2.3 mm, and 2.35 mm.

[0119] Some embodiments of the present disclosure are schematically described below by taking the peripheral area B including the first border area B1, the second border area B2, the third border area B3 and the fourth border area B4 as an example, but the implementation methods of the present disclosure are not limited thereto.

[0120] 6A and 6B , the array substrate 10 includes a first substrate 11 and a plurality of driving pads 110 , a plurality of binding pins 120 , and a plurality of peripheral connection lines 130 disposed on the first substrate 11 .

[0121] 4 , 6A and 8 , all driving pads 110 are disposed in the chip arrangement area C and are configured to connect to the driving chip 500 . That is, the driving chip 500 is provided with pins, and the driving chip 500 is connected to the driving pads 110 via the pins.

[0122] 4 , 6A and 8 , all the binding pins 120 are disposed in the binding area D and are configured to connect to the flexible circuit board 400. That is, the flexible circuit board 400 is provided with gold fingers, and the flexible circuit board 400 is connected to the binding pins 120 via the gold fingers.

[0123] As shown in FIG. 4 , FIG. 6A and FIG. 12A , all peripheral connection lines 130 are disposed in the first border area B1 and are located between the boundary of the first border area B1 of the array substrate 10 and the boundary of the color filter substrate 20 .

[0124] One end of each peripheral connection line 130 is connected to the driving pad 110 , and the other end is connected to the binding pin 120 , so as to connect the flexible circuit board 400 to the driving chip 500 , thereby providing various required signals to the driving chip 500 and the display panel 100 .

[0125] In the related art, the binding pins are located on the side of the driving pads away from the display area, that is, the binding area is located below the chip installation area. This arrangement requires a large width design of the first border area in the first direction, which is not conducive to the narrow border design of the display device.

[0126] Based on this, referring to FIG. 7 to FIG. 11 , some embodiments of the present disclosure provide an array substrate 10 , in which the binding area D is located on at least one side of the chip placement area C along the second direction Y.

[0127] That is to say, in the first border area B1, the binding pins 120 are arranged in the areas on both sides of all the driving pads 110 along the second direction Y. This can avoid increasing the width of the first border area B1 in the first direction X, thereby reducing the lower border of the display device 1000 (see Figure 1) and increasing the screen-to-body ratio.

[0128] Exemplarily, as shown in FIG. 7 to FIG. 11 , along the second direction Y, the binding area D is located on two opposite sides of the chip setting area C, that is, the plurality of binding pins 120 are respectively disposed on two opposite sides of all the driving pads 110 .

[0129] For example, as shown in Figures 7 to 11 , the bonding area D includes a first bonding area D1 and a second bonding area D2. Along the second direction Y, the first bonding area D1 and the second bonding area D2 are located on opposite sides of the chip placement area C. In other words, the plurality of bonding pins 120 can be disposed in the first bonding area D1 and the second bonding area D2, respectively. Furthermore, the plurality of bonding pins 120 can be symmetrically disposed on opposite sides of all driving pads 110.

[0130] On this basis, as shown in Figures 7 to 14, the array substrate 10 has an axis Z extending along the first direction X, and multiple driving pads 110, multiple binding pins 120 and multiple peripheral connection lines 130 can be arranged symmetrically about the axis Z to simplify the circuit structure, improve the regularity of the circuit routing, and reduce the preparation cost. Of course, multiple driving pads 110, multiple binding pins 120 and multiple peripheral connection lines 130 can also be arranged symmetrically about the axis Z. For example, the number of driving pads 110, binding pins 120 and peripheral connection lines 130 located on one side of the axis Z is greater than the number of driving pads 110, binding pins 120 and peripheral connection lines 130 located on the other side of the axis Z.

[0131] Referring to Figures 4, 5, and 8, the display device 1000 includes two flexible circuit boards 400, which are respectively connected to the binding pins 120 of the first binding area D1 and the binding pins 120 of the second binding area D2. This arrangement not only avoids increasing the width of the first border area B1 in the first direction X, thereby reducing the bottom border of the display device 1000, but also facilitates the routing of the peripheral connection lines 130, thereby reducing the routing width occupied by all peripheral connection lines 130 in the first direction X.

[0132] 5 and 8 , the array substrate 10 may further include alignment marks 40 . The alignment marks 40 are disposed on opposite sides of the binding region D along the second direction Y to facilitate alignment and connection between the flexible circuit board 400 and the binding pins 120 of the binding region D.

[0133] It should be noted that the shape of the orthographic projection of the alignment mark 40 on the substrate 11 can be a cross, a T-shape, a quadrilateral, a circle, etc., which is not specifically limited in the embodiment of the present disclosure.

[0134] In some embodiments, referring to FIG. 6B , FIG. 8 , and FIG. 12A , the plurality of peripheral connection lines 130 include a first peripheral connection line 131 . The first peripheral connection line 131 extends within the chip arrangement region C to a side of the chip arrangement region C adjacent to the bonding region D. Furthermore, one end of the first peripheral connection line 131 is connected to the driving pad 110 within the chip arrangement region C, and the other end is connected to the bonding pin 120 of the bonding region D.

[0135] It should be noted that when the first border area B1 includes two binding areas D, one end of the first peripheral connection line 131 is connected to the driving pad 110, and the other end extends to the side of the chip setting area C close to the closer of the two binding areas D, and is connected to the binding pin 120 of the closer binding area D.

[0136] 6B and 15A , the first peripheral connection line 131 includes a first routing segment 1311 , a second routing segment 1312 and a first connecting segment 1313 connected in sequence, the first routing segment 1311 is connected to the driving pad 110 , and the first connecting segment 1313 is connected to the binding pin 120 .

[0137] 6B , 8 , and 15A , the first trace segment 1311 is disposed in the chip placement area C and extends substantially along the first direction X. The second trace segment 1312 is disposed in the chip placement area C and extends substantially along the second direction Y to a side of the chip placement area C near the bonding area D.

[0138] In this case, in the first direction X, the first peripheral connection line 131 can be routed inside the chip setting area C where it overlaps with the chip setting area C, avoiding routing outside the chip setting area C, which would increase the width of the first border area B1 in the first direction X.

[0139] It should be understood that, as shown in FIG. 8 to FIG. 11 , the plurality of driving pads 110 are arranged into a plurality of driving pad groups 1100 , and the plurality of driving pad groups 1100 include an output pad group 1110 and an input pad group 1120 .

[0140] As shown in Figures 8 to 14 , the output pad group 1110 includes a plurality of output pads 1111 arranged along the second direction Y. The input pad group 1120 includes a plurality of input pads 1121 arranged along the second direction Y. One end of the first peripheral connection line 131 is connected to the input pad 1121 , and the other end is connected to the binding pin 120 .

[0141] On this basis, along the second direction Y, the input pad group 1120 is located on at least one side of the output pad group 1110. Alternatively, the input pad group 1120 is located on a side of the output pad group 1110 away from the display area A.

[0142] In some embodiments, as shown in FIG. 10 and FIG. 11 , along the second direction Y, the input pad group 1120 is located on at least one side of the output pad group 1110 .

[0143] 10 and 11 , the bonding region D includes a first bonding region D1 and a second bonding region D2. Along the second direction Y, the first bonding region D1 and the second bonding region D2 are respectively located on opposite sides of the chip setting region C. In this case, the plurality of input pads 1121 may be symmetrically arranged on opposite sides of the output pad group 1110.

[0144] For example, as shown in FIG. 10 , the plurality of driving pad groups 1100 are close to the boundary of the display area A and substantially coincide with the boundary of the chip placement area C close to the display area A.

[0145] On this basis, referring to Figures 10 and 13 , all peripheral connection lines 130 may be first peripheral connection lines 131. The first peripheral connection lines 131 extend from the side of the plurality of driving pad groups 1100 away from the display area A to the side of the chip arrangement area C near the bonding area D. Furthermore, one end of the first peripheral connection line 131 is connected to the end of the input pad group 1120 away from the display area A, and the other end is connected to the end of the bonding pin 120 near the display area A.

[0146] In this way, there is no circuit wiring on the side of the chip setting area C and the binding area D away from the display area A. That is, the distance between the chip setting area C and the binding area D and the boundary of the first frame area B1 away from the display area A can be designed to be extremely small.

[0147] For example, the distance between the chip placement area C and the boundary of the first border area B1 away from the display area A is 0.07 mm to 0.2 mm. For example, the distance between the chip placement area C and the boundary of the first border area B1 away from the display area A is any one of 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.12 mm, 0.15 mm, 0.18 mm, and 0.2 mm.

[0148] For example, the distance between the binding area D and the boundary of the first border area B1 away from the display area A is 0.07 mm to 0.2 mm. For example, the distance between the binding area D and the boundary of the first border area B1 away from the display area A is any one of 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.12 mm, 0.15 mm, 0.18 mm, and 0.2 mm.

[0149] For another example, as shown in FIG. 11 , the plurality of driving pad groups 1100 are close to the boundary of the display area A and substantially coincide with the boundary of the chip arrangement area C away from the display area A.

[0150] On this basis, referring to Figures 11 and 14 , all peripheral connection lines 130 may be first peripheral connection lines 131. The first peripheral connection lines 131 extend from the side of the plurality of driving pad groups 1100 close to the display area A to the side of the chip setting area C close to the bonding area D. Furthermore, one end of the first peripheral connection line 131 is connected to the end of the input pad group 1120 close to the display area A, and the other end is connected to the end of the bonding pin 120 close to the display area A.

[0151] In this way, there is no circuit wiring on the side of the chip setting area C and the binding area D away from the display area A. That is, the distance between the chip setting area C and the binding area D and the boundary of the first frame area B1 away from the display area A can be designed to be extremely small.

[0152] For example, the distance between the chip placement area C and the boundary of the first border area B1 away from the display area A is 0.07 mm to 0.2 mm. For example, the distance between the chip placement area C and the boundary of the first border area B1 away from the display area A is any one of 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.12 mm, 0.15 mm, 0.18 mm, and 0.2 mm.

[0153] For example, the distance between the binding area D and the boundary of the first border area B1 away from the display area A is 0.07 mm to 0.2 mm. For example, the distance between the binding area D and the boundary of the first border area B1 away from the display area A is any one of 0.07 mm, 0.08 mm, 0.09 mm, 0.1 mm, 0.12 mm, 0.15 mm, 0.18 mm, and 0.2 mm.

[0154] In other embodiments, as shown in FIG. 8 and FIG. 9 , the input pad group 1120 is located on a side of the output pad group 1110 away from the display area A.

[0155] On this basis, referring to Figures 8, 9, and 12A, first peripheral connection line 131 extends between input pad group 1120 and output pad group 1110 to a side of chip arrangement area C near bonding area D. Furthermore, one end of first peripheral connection line 131 is connected to one end of input pad 1121 near output pad group 1110, and the other end is connected to one end of bonding pin 120 near display area A.

[0156] Here, the distance between the first peripheral connection line 131 and the output pad group 1110 is greater than or equal to 20 μm to avoid the risk of crushing the first peripheral connection line 131 during the bonding process of the driver chip 500 .

[0157] Some embodiments of the present disclosure are schematically described below by taking the example where the input pad group 1120 is located on a side of the output pad group 1110 away from the display area A, but the embodiments of the present disclosure are not limited thereto.

[0158] It can be understood that, referring to Figures 6B, 8, 12A and 15A, in the chip setting area C, it is not possible to make all the peripheral connection lines 130 within the chip setting area C. In the case where the plurality of peripheral connection lines 130 extend to the side of the chip setting area C close to the binding area D, the plurality of peripheral connection lines 130 also include a second peripheral connection line 132.

[0159] The second peripheral connection line 132 extends from the side of the chip arrangement area C away from the display area A to the side of the chip arrangement area C close to the bonding area D. Furthermore, one end of the second peripheral connection line 132 is connected to the end of the input pad 1121 away from the output pad group 1110, and the other end is connected to the end of the bonding pin 120 in the bonding area D close to the display area A.

[0160] In some embodiments, referring to FIG. 15B and FIG. 15C , input pad group 1120 includes multiple input pad subgroups 1122 . Input pad subgroup 1122 includes multiple input pads 1121 that are adjacently disposed and transmit the same signal.

[0161] At this time, as shown in Figures 12B, 15B, and 15C, the plurality of second peripheral connection lines 132 include first-type second peripheral connection lines 321 and second-type second peripheral connection lines 322. The first-type second peripheral connection lines 321 are connected to the binding pins 120 and one input solder subgroup 1122. The second-type second peripheral connection lines 322 are connected to the binding pins 120 and at least two input solder subgroups 1122, and the second-type second peripheral connection lines 322 are located on a side of the first-type second peripheral connection lines 321 away from the display area A.

[0162] Exemplarily, as shown in FIG. 12B , along the second direction Y, the binding areas D are located on two opposite sides of the chip setting area C, that is, the first border area B1 includes two binding areas D.

[0163] At this time, as shown in Figures 12B and 15B, the plurality of second peripheral connection lines 132 may include, for example, two first-type second peripheral connection lines 321 and one second-type second peripheral connection line 322. The two first-type second peripheral connection lines 321 are respectively connected to the input solder subgroup 1122 and the binding pins 120 on the first side of the chip setting area C (e.g., the left side in Figure 12B). The two first-type second peripheral connection lines 321 are sequentially away from the display area A. The one second-type second peripheral connection line 322 is connected to the binding pins 120 on the first side of the chip setting area C (e.g., the left side in Figure 12B) and the two input solder subgroups 1122. The second-type second peripheral connection line 322 is located on the side of the two first-type second peripheral connection lines 321 away from the display area A.

[0164] In some embodiments, as shown in Figures 12B and 15C, the array substrate 10 further includes an input transfer line 323, which is disposed in the chip placement area C and connected to at least two input solder subgroups 1122. Among the at least two input solder subgroups 1122, one input solder subgroup 1122 is also connected to a second peripheral connection line 132.

[0165] Exemplarily, as shown in FIG. 12B , along the second direction Y, the binding areas D are located on two opposite sides of the chip setting area C, that is, the first border area B1 includes two binding areas D.

[0166] At this time, as shown in FIG12B and FIG15C , the plurality of second peripheral connection lines 132 include two first-type second peripheral connection lines 321. The two first-type second peripheral connection lines 321 are respectively connected to the input pad plate group 1122 and the bonding pins 120 on the second side (e.g., the right side in FIG12B ) of the chip setting area C. The two first-type second peripheral connection lines 321 are sequentially away from the display area A.

[0167] On this basis, as shown in Figures 12B and 15C, the array substrate 10 further includes an input adapter line 323, which is connected to three input solder sub-groups 1122. Of the three input solder sub-groups 1122, two input solder sub-groups 1122 and one input solder sub-group 1122 are located on opposite sides of the input solder sub-group 1122 connected to the first-type second peripheral connection line 321, which is relatively far from the display area A. Furthermore, the one input solder sub-group 1122 is connected to the first-type second peripheral connection line 321, which is relatively close to the display area A.

[0168] The second peripheral connection line 132 can transmit a signal with a high resistance requirement, so that the width of the second peripheral connection line 132 can be increased to reduce the resistance. For example, a second peripheral connection line 132 transmits a common voltage signal.

[0169] It should be noted that when the first border area B1 includes two binding areas D, one end of the second peripheral connection line 132 is connected to the driving pad 110, and the other end extends to the side of the chip setting area C close to the closer of the two binding areas D, and is connected to the binding pin 120 of the closer binding area D.

[0170] For example, as shown in Figures 6B, 8, and 15A, the second peripheral connection line 132 includes a third routing segment 1321, a fourth routing segment 1322, and a second connecting segment 1323, which are connected in sequence. The third routing segment 1321 is connected to the driving pad 110, and the second connecting segment 1323 is connected to the binding pin 120. The first routing segment 1311 is disposed in the chip arrangement area C and extends substantially along the first direction X. The second routing segment 1312 is disposed in the chip arrangement area C and extends substantially along the second direction Y to a side of the chip arrangement area C near the binding area D.

[0171] In this case, among all the peripheral connection lines 130, a portion of the peripheral connection lines 130 (i.e., the first peripheral connection lines 131) are within the chip setting area C and extend to the side of the chip setting area C close to the binding area D, so as to reduce the first border area B1; another portion of the peripheral connection lines 130 (i.e., the second peripheral connection lines 132) are on the side of the chip setting area C away from the display area A and extend to the side of the chip setting area C close to the binding area D, so as to avoid interference with other circuits or driving pads 110 within the chip setting area C.

[0172] 8 and 9 , the distance between the chip placement area C and the first boundary is a first distance L1, and the distance between the binding area D and the first boundary is a second distance L2. The first boundary is the boundary of the first frame area B1 of the array substrate 10 away from the display area A.

[0173] As shown in Figures 8 and 9, the first distance L1 may be greater than the second distance L2. For example, the difference between the first distance L1 and the second distance L2 is 0.3 mm to 0.6 mm. For example, the difference between the first distance L1 and the second distance L2 is any one of 0.3 mm, 0.35 mm, 0.4 mm, 0.45 mm, 0.5 mm, 0.55 mm, and 0.6 mm.

[0174] In some embodiments, as shown in FIG12A and FIG15A , the binding pin 120 connected to the first peripheral connection line 131 is a first binding pin 121 , and the binding pin 120 connected to the second peripheral connection line 132 is a second binding pin 122 .

[0175] The first binding pins 121 are located further away from the chip placement area C than the second binding pins 122, and the second peripheral connection lines 132 are located on the side of the first peripheral connection lines 131 that is further away from the display area A. This arrangement allows the first and second peripheral connection lines 131, 132 to be staggered, simplifying circuit routing. Furthermore, the first and second peripheral connection lines 131, 132 are provided on the same layer and made of the same material, reducing manufacturing costs.

[0176] It should be understood that during the manufacturing process of the display device, after the circuits and signal lines in the array substrate 10 are completed, it is necessary to use a test circuit to detect the circuits and signal lines in the array substrate 10 to determine whether there is a short circuit or open circuit problem in the array substrate 10.

[0177] Based on this, referring to FIG. 6A and FIG. 6B , the array substrate 10 further includes a plurality of sub-pixels P, a plurality of data lines 140 , a plurality of scan lines 150 and a test circuit 160 .

[0178] As shown in FIG. 4 and FIG. 5 , the sub-pixel P is disposed in the display area A. As shown in FIG.

[0179] 5 , 16 , and 17 , the subpixel P includes a pixel circuit 21, a pixel electrode 22, and a common electrode 23. The pixel circuit 21 includes a thin film transistor 210, which includes an active layer 211, a source electrode 212, a drain electrode 213, and a gate electrode 214. The source electrode 212 and the drain electrode 213 are respectively in contact with the active layer 211.

[0180] At this time, the pixel electrode 22 can be electrically connected to the source electrode 212 or the drain electrode 213 of the thin film transistor 210. Figures 16 and 17 illustrate the case where the pixel electrode 22 is electrically connected to the drain electrode 213 of the thin film transistor 210.

[0181] In addition, the pixel electrode 22 and the common electrode 23 are spaced apart from each other, and an electric field is generated between the pixel electrode 22 and the common electrode 23 , so that the liquid crystal molecules in the liquid crystal layer 30 are deflected.

[0182] It should be noted that the pixel electrode 22 and the common electrode 23 can be provided in the same layer and the same material, or can be located in different layers. For details, please refer to the following, and the embodiments of the present disclosure will not be described in detail here.

[0183] In some embodiments, as shown in Figures 6A and 6B, multiple sub-pixels P can be arranged in multiple rows and columns, for example, each row can include multiple sub-pixels P arranged along the second direction Y, and each column can include multiple sub-pixels P arranged along the first direction X.

[0184] It should be noted that, in this article, the definitions of row and column are relative concepts, respectively representing two different extension directions of the array arrangement.

[0185] For the convenience of description, a plurality of sub-pixels P arranged in a row along the second direction Y are referred to as sub-pixels P in the same row, and a plurality of sub-pixels P arranged in a column along the first direction X are referred to as sub-pixels P in the same column.

[0186] As shown in Figures 6A and 6B, a plurality of data lines 140 are connected to a plurality of sub-pixels P. Exemplarily, the plurality of data lines 140 extend along a first direction X, and each data line 140 is connected to the pixel circuits 21 of a column of sub-pixels P. Furthermore, with reference to Figure 8, the output pad group 1110 includes data output pads 1112, and the data lines 140 are further connected to the data output pads 1112 to receive data signals output by the driver chip 500 (see Figure 3) or data signals output by an external circuit.

[0187] As shown in Figures 6A and 6B, multiple scan lines 150 are connected to multiple sub-pixels P. Exemplarily, the multiple scan lines 150 extend along the second direction Y, and each scan line 150 is connected to the pixel circuits 21 of a row of sub-pixels P. Furthermore, in conjunction with Figure 8, the output pad group 1110 includes multiple scan output pads 1124, and the scan lines 150 are further connected to the scan output pads 1124 to receive scan signals output by the driver chip 500 or scan signals output by an external circuit.

[0188] 6A and 6B , the test circuit 160 is connected to the plurality of data lines 140 , the plurality of scan lines 150 , and the plurality of sub-pixels P. The test circuit 160 is configured to receive test signals transmitted from an external circuit during a test phase to test the circuits and signal lines in the array substrate 10 .

[0189] Exemplarily, referring to FIG. 6A , FIG. 18 , FIG. 19 , and FIG. 22 to FIG. 25 , the test circuit 160 includes a first test circuit 161 , a second test circuit 162 , and a first test signal line 163 .

[0190] As shown in Figure 21, the first test circuit 161 is connected to the plurality of data lines 140. The first test circuit 161 is configured to receive data signals transmitted by an external circuit during a test phase.

[0191] When the idle area in the chip setting area C is large and the first test circuit 161 can also be set in the chip setting area C, referring to Figures 19 and 21, the first test circuit 161 is set between the input pad group 1120 and the output pad group 1110, and is connected to the data output pad 1112, thereby connecting to the data line 140.

[0192] It should be noted that the “idle area” refers to an area where no circuit structure (eg, driving pads 110 ) or circuit traces (eg, peripheral connection lines 130 ) are set.

[0193] When the idle area in the chip setting area C is small and the first test circuit 161 cannot be set in the chip setting area C, as shown in FIG. 6B , the first test circuit 161 can be set in the second border area B2 and connected to the plurality of data lines 140 .

[0194] In some embodiments, as shown in Figures 6A and 21, the multiple sub-pixels P include a first sub-pixel, a second sub-pixel, and a third sub-pixel with different luminous colors, and the multiple data lines 140 include a first data line 141, a second data line 142, and a third data line 143. The first data line 141 is connected to the first sub-pixel, the second data line 142 is connected to the second sub-pixel, and the third data line 143 is connected to the third sub-pixel.

[0195] On this basis, as shown in FIG21 , the first test circuit 161 includes a first data test line DR, a second data test line DB, a third data test line DG, a first transistor T1, a second transistor T2, a third transistor T3 and a first switch signal line DSW.

[0196] As shown in FIG21 , the first data test line DR is configured to transmit a data signal for lighting the first sub-pixel, the second data test line DB is configured to transmit a data signal for lighting the second sub-pixel, and the third data test line DG is configured to transmit a data signal for lighting the third sub-pixel.

[0197] Furthermore, as shown in FIG21 , a first electrode of the first transistor T1 is connected to the first data test line DR, and a second electrode of the first transistor T1 is connected to the first data line 141. A first electrode of the second transistor T2 is connected to the second data test line DB, and a second electrode of the second transistor T2 is connected to the second data line 142. A first electrode of the third transistor T3 is connected to the third data test line DG, and a second electrode of the third transistor T3 is connected to the third data line 143. Furthermore, a first switching signal line DSW is connected to the gates of the first transistor T1, the second transistor T2, and the third transistor T3 to control the connection and disconnection between the first data test line DR and the first data line 141, the connection and disconnection between the second data test line DB and the second data line 142, and the connection and disconnection between the third data test line DG and the third data line 143.

[0198] Arranged in this way, as shown in FIG21 , the first test circuit 161 includes a first data test line DR, a second data test line DB, a third data test line DG, and a first switch signal line DSW, which can receive data signals transmitted by an external circuit, thereby lighting up the first sub-pixel, the second sub-pixel, and the third sub-pixel, and detecting the circuits and signal lines in the array substrate 10. The structure is simple and the preparation cost is low.

[0199] That is, as shown in Figures 18, 19, and 20, when the test circuit 160 further includes test pads 164, and is connected to an external circuit via the test pads 164 to receive a test signal inputted by the external circuit, the first test circuit 161 can receive the required data signal by connecting to four test pads 164. This can reduce the number of test pads 164, facilitating the placement of the test pads 164 in an unused area on the array substrate 10, thereby simplifying the process and reducing manufacturing costs.

[0200] As shown in Figures 19, 20 and 22, the second test circuit 162 is connected to the plurality of scan lines 150 (see Figure 6A) and is configured to receive scan signals transmitted from an external circuit during a test phase.

[0201] 6A and 22 , scan line 150 includes a first scan line 151 and a second scan line 152 . Multiple scan output pads 1124 include multiple first scan output pads 1125 and multiple second scan output pads 1126 .

[0202] The first scan lines 151 are connected to the sub-pixels P in odd-numbered rows, and the second scan lines 152 are connected to the sub-pixels P in even-numbered rows. Furthermore, the array substrate 10 further includes first scan connection lines 171 and second scan connection lines 172 . The first scan connection lines 171 are connected to the first scan lines 151 and the first scan output pads 1125 , and the second scan connection lines 172 are connected to the second scan lines 152 and the second scan output pads 1126 .

[0203] On this basis, as shown in FIG22 , the second test circuit 162 includes a first scan test line SG, a second scan test line DS, a fourth transistor T4, a fifth transistor T5, and a second switch signal line SSW. The first scan test line SG is configured to transmit a scan signal for lighting up the sub-pixels P in odd-numbered rows. The second scan test line DS is configured to transmit a scan signal for lighting up the sub-pixels P in even-numbered rows.

[0204] A first electrode of the fourth transistor T4 is connected to the first scan test line SG, and a second electrode of the fourth transistor T4 is connected to the first scan output pad 1125. A first electrode of the fifth transistor T5 is connected to the second scan test line DS, and a second electrode of the fifth transistor T5 is connected to the second scan output pad 1126. A second switch signal line SSW is connected to the gates of the fourth transistor T4 and the fifth transistor T5.

[0205] It should be noted that, as shown in FIG. 21 and FIG. 22 , the second switch signal line SSW and the first switch signal line DSW may be the same signal line, so as to simplify the circuit structure and reduce the manufacturing cost.

[0206] Arranged in this manner, as shown in FIG19 and FIG22 , the second test circuit 162 includes a first scanning test line SG and a second scanning test line DS, which can receive a scanning signal transmitted by an external circuit, thereby lighting up the first sub-pixel, the second sub-pixel, and the third sub-pixel, and detecting the circuits and signal lines in the array substrate 10. The structure is simple and the preparation cost is low.

[0207] That is, as shown in Figures 19 and 22, when the test circuit 160 further includes test pads 164, and is connected to an external circuit via the test pads 164 to receive a test signal inputted by the external circuit, the second test circuit 162 can receive the required scan signal by connecting to two test pads 164. This can reduce the number of test pads 164, facilitating the placement of the test pads 164 in an unused area on the array substrate 10, thereby simplifying the process and reducing manufacturing costs.

[0208] In some other embodiments, referring to FIG. 6B , the array substrate 10 includes a gate driving circuit 180 and a gate control signal line 173 , and the gate driving circuit 180 is disposed in the third border area B3 or the fourth border area B4 .

[0209] 6B and 25 , the gate driving circuit 180 is connected to the plurality of scan lines 150 , and the gate control signal line 173 is connected to the gate driving circuit 180 and the scan output pad 1124 .

[0210] On this basis, the second test circuit 162 includes a plurality of gate control test lines 174, which are connected to the scan output pads 1124. The gate control test lines 174 are configured to transmit gate control signals for lighting up the sub-pixels P.

[0211] When set up in this manner, as shown in Figures 6B and 25, when the test circuit 160 also includes a test pad 164, and an external circuit is connected through the test pad 164 to receive a test signal input by the external circuit, each scan output pad 1124 connected to the gate control test line 174 must be connected to a corresponding test pad 164.

[0212] 6B , 16 and 19 , the first test signal line 163 is connected to the common electrode 23 of the plurality of sub-pixels P. The first test signal line 163 is configured to transmit a common voltage signal.

[0213] The plurality of driving pads 110 include a common voltage pad GND, which is connected to the common electrode 23 of the plurality of sub-pixels P. The first test signal line 163 is connected to the common voltage pad GND. As shown in FIG12A and FIG19 , the common voltage pad GND may be located in the input pad group 1120 and / or the output pad group 1110.

[0214] It is understood that the test circuit 160 further includes a test pad 164 for connecting to an external circuit to receive a test signal input by the external circuit. Here, the test pad 164 can be provided on the array substrate 10 or on the outside of the array substrate 10, and after the test is completed, the outer portion of the array substrate 10 is cut.

[0215] 6A , 19 and 20 , when the array substrate 10 includes first and second scan connection lines 171 and 172 , and the second test circuit 162 includes first and second scan test lines SG and DS, the number of the test pads 164 is greater than or equal to seven.

[0216] For example, as shown in FIG6A and FIG18 to FIG20, there are seven test pads 164. Among them, four test pads 164 are connected to the first test circuit 161, two test pads are connected to the second test circuit 162, and one test pad 164 is connected to the first test signal line 163. In this case, the number of test pads 164 is small, which facilitates setting the test pads 164 in an idle area on the array substrate 10, thereby simplifying the process and reducing the manufacturing cost.

[0217] 6B , 23 , and 24 , when the array substrate 10 includes the gate drive circuit 180 and the gate control signal line 173 , and the second test circuit 162 includes a plurality of gate control test lines 174 , the number of the test pads 164 is 20 to 40. For example, the number of the test pads 164 is 26 to 32.

[0218] For example, as shown in FIG24 , the number of test pads 164 is 28. Four of the test pads 164 are connected to the first test circuit 161, 23 are connected to the second test circuit 162, and one is connected to the first test signal line 163. In this case, the gate drive circuit 180 is disposed in the third border region B3 and / or the fourth border region B4 of the array substrate 10, which can reduce the area of ​​the chip placement region C and thereby reduce the area of ​​the first border region B1, thereby facilitating a narrow-border design for the display device 1000.

[0219] Some embodiments of the present disclosure provide an array substrate 10, as shown in FIG6B and FIG18, in which the test circuit 160 further includes a first test pad 1641, which is disposed between the plurality of peripheral connection lines 130 and the display area A. For example, the first test pad 1641 is disposed between the plurality of peripheral connection lines 130 and the boundary of the color filter substrate 20 to facilitate external circuit connection.

[0220] The first test circuit 161 , the second test circuit 162 , and the first test signal line 163 are respectively connected to the first test pad 1641 .

[0221] Some embodiments of the present disclosure provide an array substrate 10, as shown in Figure 12B, further including a third test pad 1643, which is arranged in the first border area B1, and the third test pad 1643 is connected to a data line 140 or a scan line 150 (see Figure 6B) to test whether the voltage of the scan signal or the data signal is accurate.

[0222] 6B and 12B , the third test pad 1643 connected to the data line 140 may be disposed between the data line 140 and the gate control signal line 173 . The third test pad 1643 connected to the scan line 150 may be disposed between the peripheral connection line 130 and the gate control signal line 173 .

[0223] In some embodiments, referring to FIG. 6B and FIG. 12B , the array substrate 10 further includes an anti-static trace 153 and a shielding trace 154 . The shielding trace 154 is located on a side of the anti-static trace 153 close to the display area A.

[0224] 6B and 12B , the anti-static trace 153 passes through the second frame area B2 , the third frame area B3 , and the fourth frame area B4 , and is connected to the binding pins 120 on both sides of the first frame area B1 to conduct away static electricity on the color filter substrate 20 .

[0225] 6B and 12B , the shielding trace 154 passes through the second border area B2 , the third border area B3 , and the fourth border area B4 , and is connected to the binding pins 120 on both sides of the first border area B1 to shield external electromagnetic interference.

[0226] It should be understood that during the preparation of the array substrate 10, the array substrate 10 is manufactured as a whole on the array motherboard 10' (see Figure 23) and then cut and separated to further complete subsequent processes, thereby improving the production efficiency of the array substrate 10 and reducing production costs.

[0227] Based on this, as shown in FIG23 , some embodiments of the present disclosure provide an array motherboard 10 ′ having a plurality of product areas M and a plurality of to-be-cut areas N, wherein a to-be-cut area N is provided between every two adjacent product areas M.

[0228] FIG23 illustrates an area N to be cut, where the area N to be cut includes a product area M and an area to be cut N arranged along a first direction X. FIG23 illustrates an example of an area N to be cut, where the area N to be cut includes a product area M and an area to be cut N arranged along a first direction X.

[0229] As shown in Figure 23, the product area M is the area where the array substrate 10 (see Figure 6B) is located in the array motherboard 10', and the area to be cut N is the area in the array motherboard 10' that needs to be cut after the circuit test is completed, that is, the area outside the array substrate 10 (see Figure 6B).

[0230] 23 and 24 , the array motherboard 10 ′ includes a second test pad 1642 and a plurality of test leads 165 . The second test pad 1642 is disposed in the to-be-cut area N, and the plurality of test leads 165 is disposed in the to-be-cut area N.

[0231] Here, the plurality of test leads 165 are connected to the second test pad 1642 and the plurality of residual transfer lines 1651 ′, thereby connecting the second test pad 1642 to the first test circuit 161 , the second test circuit 162 , and the first test signal line 163 .

[0232] 25 , the test leads 165 may include a cutout patch line 1651 and a test connection line 1652. A cutout patch line 1651 is connected to a remaining patch line 1651', and a test connection line 1652 is connected to a cutout patch line 1651 and a second test pad 1642.

[0233] At this time, the cut-off transfer line 1651 is located between the binding area D and the chip setting area C and extends along the first direction X. The cut-off transfer line 1651 and the remaining transfer line 1651 ′ can be made of the same material and disposed on the same layer, for example, to reduce manufacturing costs.

[0234] In this case, the portion of the array motherboard 10' located in the to-be-cut area N is cut to form the array substrate 10. The portion of the cut-off transfer line 1651 remaining on the array substrate 10 after the cut-off transfer line 1651 is cut off is the remaining transfer line 1651'.

[0235] That is, in the array substrate 10, the test circuit 160 includes a plurality of residual transfer lines 1651', which are disposed between the bonding area D and the chip placement area C. Furthermore, the residual transfer lines 1651' extend along the first direction X to the boundary of the array substrate 10, and the first test circuit 161, the second test circuit 162, and the first test signal line 163 are respectively connected to the residual transfer lines 1651'.

[0236] FIG16 is a cross-sectional view of a display panel shown in FIG4 or FIG5 along section line BB'; FIG17 is a cross-sectional view of another display panel shown in FIG4 or FIG5 along section line BB'. The display panel 100 of some embodiments of the present disclosure will be exemplified below with reference to FIG16 and FIG17.

[0237] In some embodiments, as shown in Figure 16, the array substrate 10 includes a first substrate 11, a gate metal layer 12, a gate insulation layer 13, a semiconductor layer 14, a source and drain metal layer 15, a first interlayer insulation layer 16, a first planarization layer 191, an electrode layer 18 and a second planarization layer 192, which are stacked in sequence.

[0238] As shown in FIG16 , the gate metal layer 12 includes a gate electrode 214 of a thin-film transistor 210. The semiconductor layer 14 includes an active layer 211 of the thin-film transistor 210. The source-drain metal layer 15 includes a source electrode 212 and a drain electrode 213 of the thin-film transistor 210. The electrode layer 18 includes a pixel electrode 22 and a common electrode 23. Specifically, the pixel electrode 22 and the common electrode 23 are provided in the same layer and made of the same material. In this case, both the pixel electrode 22 and the common electrode 23 have a comb-tooth structure including a plurality of strip-shaped sub-electrodes.

[0239] On this basis, as shown in Figures 16 and 25, the peripheral connection lines 130 and the test connection lines 1652 can be located in the gate metal layer 12. The cut-off transfer lines 1651 and the remaining transfer lines 1651' can be located in the electrode layer 18. The test pads 164, the driving pads 110, and the binding pins 120 can be a multi-layer stacked structure.

[0240] For example, referring to Figures 8, 16, 18 and 25, the test pad 164 includes three stacked sub-test pads, and the three stacked sub-test pads are respectively located on the gate metal layer 12, the source and drain metal layer 15 and the electrode layer 18; the driving pad 110 includes three stacked sub-driving pads, and the three stacked sub-driving pads are respectively located on the gate metal layer 12, the source and drain metal layer 15 and the electrode layer 18; the binding pin 120 includes three stacked sub-binding pins, and the three stacked sub-binding pins are respectively located on the gate metal layer 12, the source and drain metal layer 15 and the electrode layer 18.

[0241] In other embodiments, as shown in Figure 17, the array substrate 10 includes a first substrate 11, a gate metal layer 12, a gate insulation layer 13, a semiconductor layer 14, a source-drain metal layer 15, a first interlayer insulation layer 16, a common electrode layer 181, a second interlayer insulation layer 19, a first planarization layer 191, a pixel electrode layer 182 and a second planarization layer 192, which are stacked in sequence.

[0242] As shown in FIG17 , the gate metal layer 12 includes a gate electrode 214 of the thin film transistor 210. The semiconductor layer 14 includes an active layer 211 of the thin film transistor 210. The source-drain metal layer 15 includes a source electrode 212 and a drain electrode 213 of the thin film transistor 210. The common electrode layer 181 includes a common electrode 23. The pixel electrode layer 182 includes a pixel electrode 22.

[0243] On this basis, as shown in Figures 17 and 25, the peripheral connection lines 130 and test connection lines 1652 can be located in the gate metal layer 12. The cut-off transfer lines 1651 and the remaining transfer lines 1651' can be located in the pixel electrode layer 182. The test pads 164, the driving pads 110, and the binding pins 120 can be a multi-layer stacked structure.

[0244] For example, referring to Figures 8, 17, 18, and 25, the test pad 164 includes four stacked sub-test pads, which are respectively located on the gate metal layer 12, the source / drain metal layer 15, the common electrode layer 181, and the pixel electrode layer 182. The drive pad 110 includes four stacked sub-drive pads, which are respectively located on the gate metal layer 12, the source / drain metal layer 15, the common electrode layer 181, and the pixel electrode layer 182. The binding pin 120 includes four stacked sub-binding pins, which are respectively located on the gate metal layer 12, the source / drain metal layer 15, the common electrode layer 181, and the pixel electrode layer 182.

[0245] 16 and 17 , the color filter substrate 20 may include a second substrate 22 , a color filter layer 23 disposed on the second substrate 22 , and a black matrix 24 .

[0246] As shown in Figures 16 and 17, the color filter layer 23 includes multiple photoresist units 231 of different colors. The black matrix 24 is used to separate the multiple photoresist units of different colors. For example, the color filter layer 23 includes red photoresist units, green photoresist units, and blue photoresist units.

[0247] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in the present disclosure should be included within the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. An array substrate, comprising a display area and a first frame area arranged along a first direction, wherein the first frame area comprises a chip setting area and a binding area, and along a second direction, the binding area is located at least on one side of the chip setting area; the second direction intersects with the first direction; The array substrate comprises: A plurality of driving pads are arranged in the chip arrangement area; the driving pads are configured to be connected to the driving chip; A plurality of binding pins are arranged in the binding area; the binding pins are configured to be connected to a circuit board; A plurality of peripheral connection lines are arranged in the first border area; one end of each peripheral connection line is connected to the driving pad, and the other end is connected to the binding pin; Among them, the multiple peripheral connection lines include a first peripheral connection line, which extends in the chip setting area to a side of the chip setting area close to the binding area, and one end of the first peripheral connection line is connected to the driving pad in the chip setting area, and the other end is connected to the binding pin of the binding area.

2. The array substrate according to claim 1, wherein: The plurality of driving pads are arranged into a plurality of driving pad groups, and the plurality of driving pad groups include: an output pad group, comprising a plurality of output pads arranged along the second direction; An input pad group comprises a plurality of input pads arranged along the second direction; the input pad group is located on a side of the output pad group away from the display area; the first peripheral connection line is between the input pad group and the output pad group, extending to a side of the chip setting area close to the binding area; and one end of the first peripheral connection line is connected to one end of the input pad close to the output pad group, and the other end is connected to one end of the binding pin close to the display area.

3. The array substrate according to claim 2, wherein: The plurality of peripheral connection lines also include: A second peripheral connection line, the second peripheral connection line extends from a side of the chip setting area away from the display area to a side of the chip setting area close to the binding area; one end of the second peripheral connection line is connected to an end of the input pad away from the output pad group, and the other end is connected to an end of the binding pin of the binding area close to the display area.

4. The array substrate according to claim 3, wherein: The binding pin connected to the first peripheral connection line is a first binding pin; the binding pin connected to the second peripheral connection line is a second binding pin; the first binding pin is farther away from the chip setting area than the second binding pin, and the second peripheral connection line is located on a side of the first peripheral connection line farther away from the display area.

5. The array substrate according to claim 3 or 4, wherein: The input pad group includes a plurality of input pad subgroups, and the input pad subgroup includes a plurality of input pads that are adjacently arranged and transmit the same signal; The plurality of second peripheral connection lines include: A first type second peripheral connection line connected to the binding pin and one of the input solder plate groups; The second type of second peripheral connection line is connected to the binding pin and at least two input solder plate groups, and the second The second type peripheral connection line is located at a side of the first type second peripheral connection line away from the display area.

6. The array substrate according to claim 5, wherein: Along the second direction, the binding area is located at two opposite sides of the chip setting area; the plurality of second peripheral connection lines include: Two first-type second peripheral connection lines are respectively connected to the input solder plate group and the binding pins on the first side of the chip setting area; and the two first-type second peripheral connection lines are sequentially away from the display area; A second type second peripheral connection line is connected to the binding pins and two input solder plate groups on the first side of the chip setting area; and the second type second peripheral connection line is located on a side of the two first type second peripheral connection lines away from the display area.

7. The array substrate according to any one of claims 3 to 6, wherein: The input pad group includes a plurality of input pad subgroups, and the input pad subgroup includes a plurality of input pads that are adjacently arranged and transmit the same signal; The array substrate further includes: The input transfer line is arranged in the chip arrangement area and connected to at least two input solder subgroups; among the at least two input solder subgroups, one input solder subgroup is also connected to a second peripheral connection line.

8. The array substrate according to claim 7, wherein: Along the second direction, the binding area is located at two opposite sides of the chip setting area; the plurality of second peripheral connection lines include: Two first-type second peripheral connection lines are respectively connected to the input solder plate group and the binding pins on the second side of the chip setting area; and the two first-type second peripheral connection lines are sequentially away from the display area; The array substrate further includes: An input adapter line is connected to three input solder subgroups; among the three input solder subgroups, two input solder subgroups and one input solder subgroup are respectively located on opposite sides of the input solder subgroup connected to the first type second peripheral connection line that is relatively far away from the display area; and the one input solder subgroup is connected to the first type second peripheral connection line that is relatively close to the display area.

9. The array substrate according to any one of claims 1 to 8, further comprising: A plurality of sub-pixels are arranged in the display area; A plurality of data lines connected to the plurality of sub-pixels; A plurality of scanning lines connected to the plurality of sub-pixels; A test circuit is connected to the plurality of data lines, the plurality of scan lines and the plurality of sub-pixels; the test circuit is configured to receive a test signal transmitted by an external circuit during a test phase.

10. The array substrate according to claim 9, wherein: The sub-pixel includes a common electrode, and the test circuit includes: A first test circuit connected to the plurality of data lines; the first test circuit is configured to receive a data signal transmitted by an external circuit during a test phase; A second test circuit is connected to the plurality of scan lines; the second test circuit is configured to, during a test phase, Receiving a scanning signal transmitted by an external circuit; The first test signal line is connected to the common electrode of the plurality of sub-pixels; the first test signal line is configured to transmit a common voltage signal.

11. The array substrate according to claim 10, wherein: The test circuit further comprises: The first test pad is arranged between the plurality of peripheral connection lines and the display area; the first test circuit, the second test circuit, and the first test signal line are respectively connected to the first test pad.

12. The array substrate according to claim 10, wherein: The test circuit further comprises: A plurality of residual transfer lines are arranged between the binding area and the chip setting area; the residual transfer lines extend along the first direction to the boundary of the array substrate; the first test circuit, the second test circuit, and the first test signal line are respectively connected to the residual transfer lines.

13. The array substrate according to any one of claims 10 to 12, comprising an output pad group and an input pad group, wherein the output pad group comprises a data output pad, and the data output pad is connected to the data line; in, The first test circuit is disposed between the input pad group and the output pad group, and is connected to the data output pad.

14. The array substrate according to any one of claims 10 to 12, further comprising a second frame region, a third frame region and a fourth frame region, wherein the second frame region is located on a side of the display region away from the first frame region; along the second direction, the third frame region and the fourth frame region are located on two opposite sides of the display region; in, The first test circuit is disposed in the second frame area and connected to the plurality of data lines.

15. The array substrate according to any one of claims 10 to 14, wherein: The plurality of sub-pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel emitting different colors, the plurality of data lines include a first data line, a second data line, and a third data line, the first data line is connected to the first sub-pixel, the second data line is connected to the second sub-pixel, and the third data line is connected to the third sub-pixel; The first test circuit comprises: A first data test line is configured to transmit a data signal for lighting a first sub-pixel; A second data test line is configured to transmit a data signal for lighting a second sub-pixel; A third data test line is configured to transmit a data signal for lighting a third sub-pixel; a first transistor, wherein a first electrode of the first transistor is connected to the first data test line, and a second electrode of the first transistor is connected to the first data line; a second transistor, wherein a first electrode of the second transistor is connected to the second data test line, and a second electrode of the second transistor is connected to the second data line; a third transistor, a first electrode of the third transistor being connected to the third data test line, and a second electrode of the third transistor being connected to the third data line; The first switch signal line is connected to the gates of the first transistor, the second transistor and the third transistor.

16. The array substrate according to any one of claims 10 to 15, wherein: The plurality of sub-pixels are arranged in a plurality of rows and columns, the scan lines include a first scan line and a second scan line, the first scan line is connected to the sub-pixels in odd-numbered rows, and the second scan line is connected to the sub-pixels in even-numbered rows; The plurality of driving pads include a plurality of first scanning output pads and a plurality of second scanning output pads, and the array substrate further includes: A first scan connection line connected to the first scan line and the first scan output pad; A second scan connection line connected to the second scan line and the second scan output pad; The second test circuit comprises: A first scanning test line is configured to transmit a scanning signal for lighting up sub-pixels in odd-numbered rows; A second scanning test line is configured to transmit a scanning signal for lighting up sub-pixels of even-numbered rows; a fourth transistor, wherein a first electrode of the fourth transistor is connected to the first scan test line, and a second electrode of the fourth transistor is connected to the first scan output pad; a fifth transistor, wherein a first electrode of the fifth transistor is connected to the second scan test line, and a second electrode of the fifth transistor is connected to the second scan output pad; The second switch signal line is connected to the gates of the fourth transistor and the fifth transistor.

17. The array substrate according to claim 16, wherein: The first test circuit includes a first switch signal line, and the second switch signal line and the first switch signal line are the same signal line.

18. The array substrate according to any one of claims 10 to 15, wherein: The plurality of driving pads include a scan output pad, and the array substrate includes: A gate driving circuit connected to the plurality of scanning lines; A gate control signal line connected to the gate drive circuit and the scan output pad; The second test circuit comprises: A plurality of gate control test lines are connected to the scan output pads; the gate control test lines are configured to transmit gate control signals for lighting up sub-pixels.

19. The array substrate according to any one of claims 10 to 18, wherein: The plurality of driving pads include a common voltage pad connected to a common electrode of the plurality of sub-pixels, and the first test signal line is connected to the common voltage pad.

20. The array substrate according to claim 1, wherein: The plurality of driving pads are arranged into a plurality of driving pad groups, and the plurality of driving pad groups include: an output pad group, comprising a plurality of output pads arranged along the second direction; An input pad group, comprising a plurality of input pads arranged along the second direction; along the second direction, the input pad group is located at least on one side of the output pad group; The plurality of driving pad groups are close to the boundary of the display area and the chip setting area is close to the display area. The first peripheral connection line is connected to the input pad group at one end thereof and the input pad group is connected to the display area; the ... Or, the multiple driving pad groups are away from the boundary of the display area and roughly coincide with the boundary of the chip setting area away from the display area; the first peripheral connection line extends from the side of the multiple driving pad groups close to the display area to the side of the chip setting area close to the binding area; and one end of the first peripheral connection line is connected to one end of the input pad group close to the display area, and the other end is connected to one end of the binding pin close to the display area.

21. The array substrate according to any one of claims 1 to 20, wherein: The chip setting area and the binding area are substantially rectangular in shape. The binding area is away from a boundary of the display area and is substantially flush with a boundary of the chip setting area away from the display area.

22. The array substrate according to claim 21, wherein: The multiple peripheral connection lines include a second peripheral connection line, the distance between the chip setting area and the first boundary is a first distance, and the distance between the binding area and the first boundary is a second distance; the first boundary is the boundary of the first border area of ​​the array substrate away from the display area; the first distance is greater than the second distance.

23. The array substrate according to claim 22, wherein: The difference between the first distance and the second distance is 0.3 mm to 0.6 mm.

24. The array substrate according to any one of claims 1 to 7, wherein: The array substrate has an axis extending along the first direction, and the plurality of driving pads, the plurality of binding pins and the plurality of peripheral connection lines are symmetrically arranged about the axis.

25. An array motherboard, comprising a plurality of product areas and a plurality of to-be-cut areas, wherein a to-be-cut area is provided between each two adjacent product areas; The array motherboard includes the array substrate according to any one of claims 1 to 24, and the array substrate is located in the product area.

26. The array motherboard according to claim 25, wherein: The array substrate includes a first test circuit, a second test circuit, a first test signal line and a plurality of residual patch cords, and the array motherboard also includes: A second test pad is arranged in the area to be cut; A plurality of test leads are arranged in the area to be cut; the test leads are connected to the remaining transfer wires and the second test pads.

27. The array motherboard according to claim 26, wherein: The test leads include: A cut-off patch cord, one cut-off patch cord is connected to one of the residual patch cords; the cut-off patch cord extends along the first direction, and the cut-off patch cord and the residual patch cord are made of the same material and are arranged on the same layer; A test connection line is connected to the cut-off adapter line and the second test pad.

28. A display panel, characterized in that: include: The array substrate according to any one of claims 1 to 24; A color film substrate is arranged opposite to the array substrate; the boundary of the first border area of ​​the array substrate exceeds the boundary of the color film substrate, and the boundary of the array substrate away from the first border area and the two boundaries in the second direction are roughly flush with the boundary of the color film substrate; and the chip setting area, binding area and peripheral connection lines of the array substrate are all located between the boundary of the first border area of ​​the array substrate and the boundary of the color film substrate.

29. The display panel according to claim 28, wherein: The array substrate includes a first test pad, and the first test pad is arranged between the color filter substrate and the peripheral connection line.

30. A display device, characterized in that: include: The display panel as claimed in claim 28 or 29; A driving chip connected to a driving pad on an array substrate of the display panel; A flexible circuit board is connected to the binding pins on the array substrate of the display panel.

Images