Display substrate, preparation method thereof and display device

Abstract

The invention discloses a display substrate, a preparation method thereof and a display device. The display substrate comprises a plurality of repetitive units (100), each repetitive unit (100) comprises at least one first power line (51), at least one compensation signal line (53), at least two data signal line groups and a plurality of sub-pixels, the sub-pixels form at least two pixel rows and at least two pixel columns, each data signal line group comprises at least two data signal lines (52), and each data signal line (52) comprises at least one first power line (51) and at least one compensation signal line (53). The sub-pixel comprises a storage capacitor (60); the first power line (51) and the compensation signal line (53) are arranged between two adjacent pixel columns in the repeating unit (100), and the at least two data signal line groups are respectively arranged on two sides of the repeating unit (100) in the pixel row direction; the storage capacitor (60) is disposed between the data signal line (52) and the first power supply line (51), or the storage capacitor (60) is disposed between the data signal line (52) and the compensation signal line (53).

Description

Display substrate and manufacturing method thereof, and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a preparation method thereof, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, display devices using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0005] On the one hand, the present disclosure provides a display substrate comprising a plurality of repeating units, at least one repeating unit comprising at least one first power line, at least one compensation signal line, at least two data signal line groups and a plurality of sub-pixels, the plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, the data signal line group comprising at least two data signal lines; at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit comprising at least a storage capacitor; the first power line and the compensation signal line being arranged between two adjacent pixel columns in the repeating unit, the at least two data signal line groups being respectively arranged on both sides of the pixel row direction of the repeating unit; the storage capacitor being arranged between the data signal line and the first power line, or the storage capacitor being arranged between the data signal line and the compensation signal line.

[0006] In an exemplary embodiment, the repeating unit includes a compensation signal line and two first power lines, the two first power lines include a first first power line and a second first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; the first first power line is arranged on a side of the compensation signal line close to the first data signal line group, and a storage capacitor in the first pixel column is arranged between the first data signal line group and the first first power line; the second first power line is arranged on a side of the compensation signal line close to the second data signal line group, and a storage capacitor in the second pixel column is arranged between the second data signal line group and the second first power line.

[0007] In an exemplary embodiment, at least one repeating unit further includes two power connection electrodes, wherein the power connection electrodes are in the shape of strips extending along the pixel row direction and are arranged across the first pixel column and the second pixel column, one end of the power connection electrode is connected to the first first power line, and the other end of the power connection electrode is connected to the second first power line, forming a ring structure for transmitting the first power signal within the repeating unit.

[0008] In an exemplary embodiment, at least one repeating unit further includes a power connection electrode, which is shaped like a strip extending along the pixel row direction and spans the first pixel column and the second pixel column. The orthographic projection of the power connection electrode on the display substrate plane does not overlap with the orthographic projection of the data signal line on the display substrate plane, and the orthographic projection of the power connection electrode on the display substrate plane at least partially overlaps with the orthographic projection of the compensation signal line on the display substrate plane.

[0009] In an exemplary embodiment, the repeating unit includes a compensation signal line and a first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; the first power line is arranged on a side of the compensation signal line close to the second data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the compensation signal line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the first power line.

[0010] In an exemplary embodiment, the storage capacitor includes at least two capacitor plates; in the first pixel column, there is a first distance between the edge of at least one capacitor plate close to the compensation signal line and the edge of the compensation signal line close to the capacitor plate, and in the second pixel column, there is a second distance between the edge of at least one capacitor plate close to the first power line and the edge of the first power line close to the capacitor plate, and the first distance is greater than or equal to the second distance.

[0011] In an exemplary embodiment, the repeating unit includes a compensation signal line and a first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; the first power line is arranged on a side of the compensation signal line close to the first data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the first power line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the compensation signal line.

[0012] In an exemplary embodiment, the storage capacitor includes at least two capacitor plates; in the first pixel column, there is a second distance between the edge of at least one capacitor plate close to the first power line and the edge of the first power line close to the capacitor plate, and in the second pixel column, there is a first distance between the edge of at least one capacitor plate close to the compensation signal line and the edge of the compensation signal line close to the capacitor plate, and both the first distance and the second distance are greater than the distance between the edge of the compensation signal line close to the first power line and the edge of the first power line close to the compensation signal line.

[0013] In an exemplary embodiment, the repeating unit includes a first power line and two compensation signal lines, the two compensation signal lines include a first compensation signal line and a second compensation signal line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the first power line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the first power line, and the second data signal line group is arranged on a side of the second pixel column away from the first power line; the first compensation signal line is arranged on a side of the first power line close to the first data signal line group, and the storage capacitor in the first pixel column is arranged between the first data signal line group and the first compensation signal line; the second compensation signal line is arranged on a side of the first power line close to the second data signal line group, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the second compensation signal line.

[0014] In an exemplary embodiment, at least one repeating unit further includes two compensation connection electrodes, which are in the shape of strips extending along the pixel row direction and are arranged across the first pixel column and the second pixel column. One end of the compensation connection electrode is connected to the first compensation signal line, and the other end of the compensation connection electrode is connected to the second compensation signal line, forming a ring structure for transmitting the compensation signal within the repeating unit.

[0015] In an exemplary embodiment, at least one repeating unit further includes two compensation connection electrodes, wherein the compensation connection electrodes are in the shape of strips extending along the pixel row direction and are arranged across the first pixel column and the second pixel column, and the orthographic projection of the compensation connection electrode on the display substrate plane does not overlap with the orthographic projection of the data signal line on the display substrate plane, and the orthographic projection of the compensation connection electrode on the display substrate plane at least partially overlaps with the orthographic projection of the first power line on the display substrate plane.

[0016] In an exemplary embodiment, the repeating unit includes a compensation signal line and a first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the first power line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the first power line, and the second data signal line group is arranged on a side of the second pixel column away from the first power line; the compensation signal line is arranged on a side of the first power line close to the second data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the first power line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the compensation signal line, or the compensation signal line is arranged on a side of the first power line close to the first data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the compensation signal line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the first power line.

[0017] In an exemplary embodiment, the storage capacitor includes at least two capacitor plates; in the first pixel column, there is a third distance between the edge of at least one capacitor plate close to the first power line and the edge of the first power line close to the capacitor plate, and in the second pixel column, there is a fourth distance between the edge of at least one capacitor plate close to the compensation signal line and the edge of the compensation signal line close to the capacitor plate; or, in the first pixel column, there is a fourth distance between the edge of at least one capacitor plate close to the compensation signal line and the edge of the compensation signal line close to the capacitor plate, and in the second pixel column, there is a third distance between the edge of at least one capacitor plate close to the first power line and the edge of the first power line close to the capacitor plate; the third distance and the fourth distance are both greater than the distance between the edge of the compensation signal line close to the first power line and the edge of the first power line close to the compensation signal line.

[0018] In an exemplary embodiment, the storage capacitor includes at least two capacitor plates, and in at least one pixel column, a distance between an edge of at least one capacitor plate close to the compensation signal line and an edge of the compensation signal line close to the capacitor plate is greater than or equal to 3 microns.

[0019] In an exemplary embodiment, the storage capacitor includes a first plate and a second plate, and the pixel driving circuit further includes a first transistor, a second transistor, and a third transistor, the first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is respectively connected to the first plate and the gate electrode of the second transistor, the first electrode of the third transistor is connected to the compensation signal line, and the second electrode of the third transistor is respectively connected to the second plate and the second electrode of the second transistor; in at least one repeating unit, the gate electrodes of multiple first transistors and the gate electrodes of multiple third transistors are connected to the same scanning signal line.

[0020] In an exemplary embodiment, the first transistor includes at least a first active layer, a first region of the first active layer is connected to the data signal line via a connecting electrode, and a second region of the first active layer is connected to the second electrode plate; in at least one sub-pixel, an orthographic projection of the first active layer on the plane of the display substrate does not overlap with an orthographic projection of the data signal line on the plane of the display substrate.

[0021] In an exemplary embodiment, the third transistor includes at least a third active layer, a first region of the third active layer is connected to the compensation signal line via a connecting electrode, and a second region of the third active layer is connected to the first electrode plate; in at least one sub-pixel, an orthographic projection of the third active layer on the plane of the display substrate does not overlap with an orthographic projection of the first power line on the plane of the display substrate.

[0022] On the other hand, the present disclosure further provides a display device comprising the aforementioned display substrate.

[0023] In another aspect, the present disclosure further provides a method for preparing a display substrate, wherein the display substrate includes a plurality of repeating units, and the preparation method includes:

[0024] At least one first power line, at least one compensation signal line, at least two data signal line groups and a plurality of sub-pixels are formed in at least one repeating unit, the plurality of sub-pixels form at least two pixel rows and at least two pixel columns, the data signal line group includes at least one data signal line; at least one sub-pixel includes a pixel driving circuit, the pixel driving circuit includes at least a storage capacitor; the first power line and the compensation signal line are arranged between two adjacent pixel columns in the repeating unit, and the at least two data signal line groups are respectively arranged on both sides of the pixel row direction of the repeating unit; the storage capacitor is arranged between the data signal line and the first power line, or, the storage capacitor is arranged between the data signal line and the compensation signal line.

[0025] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are intended to provide a further understanding of the technical solutions of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solutions of the present disclosure and do not constitute a limitation of the technical solutions of the present disclosure. The shapes and sizes of the components in the drawings do not reflect the actual scale and are intended only to illustrate the contents of the present disclosure.

[0027] FIG1 is a schematic structural diagram of a display device;

[0028] FIG2 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0029] FIG3 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an embodiment of the present disclosure;

[0030] FIG4 is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

[0031] FIG5 is a schematic diagram of a display substrate after forming a first conductive layer pattern according to the present disclosure;

[0032] 6A and 6B are schematic diagrams of a display substrate after forming a second conductive layer pattern according to the present disclosure;

[0033] 7A and 7B are schematic diagrams of a display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0034] FIG8 is a schematic diagram of a display substrate after forming a second insulating layer pattern according to the present disclosure;

[0035] 9A and 9B are schematic diagrams of a display substrate after a third conductive layer pattern is formed according to the present disclosure;

[0036] FIG10 is a schematic diagram of a display substrate after forming a third insulating layer and a planar layer pattern according to the present disclosure;

[0037] 11A and 11B are schematic diagrams of a display substrate after a fourth conductive layer pattern is formed thereon according to the present disclosure;

[0038] FIG12 is a schematic diagram of a display substrate according to the present disclosure after a pixel definition layer pattern is formed;

[0039] FIG13 is an equivalent circuit diagram of a pixel driving circuit in another repeating unit according to an embodiment of the present disclosure;

[0040] FIG14 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0041] FIG15 is an equivalent circuit diagram of a pixel driving circuit in another repeating unit according to an embodiment of the present disclosure;

[0042] FIG16 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0043] 17A and 17B are schematic diagrams of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0044] 18A and 18B are schematic diagrams of another display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0045] FIG19 is a schematic diagram of another display substrate after forming a second insulating layer pattern according to the present disclosure;

[0046] 20A and 20B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure;

[0047] FIG21 is an equivalent circuit diagram of a pixel driving circuit in another repeating unit according to an embodiment of the present disclosure;

[0048] FIG22 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0049] FIG23 is a schematic structural diagram of another display substrate according to an embodiment of the present disclosure;

[0050] FIG24 is a schematic diagram of another display substrate after forming a first conductive layer pattern according to the present disclosure;

[0051] 25A and 25B are schematic diagrams of another display substrate after forming a second conductive layer pattern according to the present disclosure;

[0052] 26A and 26B are schematic diagrams showing another display substrate after a semiconductor layer pattern is formed according to the present disclosure;

[0053] FIG27 is a schematic diagram of another display substrate after forming a second insulating layer pattern according to the present disclosure;

[0054] 28A and 28B are schematic diagrams of another display substrate after forming a third conductive layer pattern according to the present disclosure.

[0055] Explanation of the accompanying drawings: 11—first connecting electrode; 12—second connecting electrode; 13—third connecting electrode; 14—fourth connecting electrode; 15—fifth connecting electrode; 16—sixth connecting electrode; 17—data connecting electrode; 18—power connecting electrode; 19—compensation connecting electrode; 20—tenth connecting electrode; 21—first active layer; 22—second active layer; 23—third active layer; 30—scanning signal line; 31—first gate electrode; 32—second gate electrode; 33—third gate electrode; 41—data jumper electrode; 42—compensation jumper electrode; 51—first power line; 52—data signal line; 53—compensation signal line; 60—storage capacitor; 61—first plate; 62—second plate; 70—first electrode; 100—repeating unit. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. The embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be combined with each other in any way.

[0057] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0058] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0059] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0060] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0061] In this specification, a transistor refers to a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0062] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" can be interchanged, and "source terminal" and "drain terminal" can be interchanged.

[0063] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0064] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0065] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0066] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0067] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0068] Figure 1 is a schematic diagram of the structure of a display device. As shown in Figure 1, the OLED display device may include a timing controller, a data driver, a scan driver, and a pixel array. The timing controller is respectively connected to the data driver and the scan driver. The data driver is respectively connected to a plurality of data signal lines (D1 to Dn). The scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm). The pixel array may include a plurality of sub-pixels Pxij. Each sub-pixel Pxij may be connected to a corresponding data signal line and a corresponding scan signal line. i and j may be natural numbers. At least one sub-pixel Pxij may include at least a circuit unit and a display unit. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to the scan signal line and the data signal line. The display unit may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit. Sub-pixel Pxij may refer to a sub-pixel whose pixel driving circuit is connected to the i-th scan signal line and the j-th data signal line. In an exemplary embodiment, the timing controller may provide grayscale values ​​and control signals suitable for the specifications of the data driver to the data driver, and may provide a clock signal, a scan start signal, etc. suitable for the specifications of the scan driver to the scan driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ..., and Dn using grayscale values ​​and control signals received from a timing controller. For example, the data driver can sample grayscale values ​​using a clock signal and apply data voltages corresponding to the grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ..., and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals having on-level pulses to scan signal lines S1 to Sm. For example, the scan driver can be configured in the form of a shift register and can generate scan signals by sequentially transmitting scan start signals provided in the form of on-level pulses to the next level circuit under the control of a clock signal, where m can be a natural number. In an exemplary embodiment, the pixel array can be provided on a display substrate.

[0069] An exemplary embodiment of the present disclosure provides a display substrate, comprising a plurality of repeating units, wherein at least one repeating unit comprises at least one first power line, at least one compensation signal line, at least two data signal line groups, and a plurality of sub-pixels, wherein the plurality of sub-pixels form at least two pixel rows and at least two pixel columns, and the data signal line group comprises at least one data signal line; at least one sub-pixel comprises a pixel driving circuit, and the pixel driving circuit comprises at least a storage capacitor; the first power line and the compensation signal line are arranged between two adjacent pixel columns in the repeating unit, and the at least two data signal line groups are respectively arranged on both sides of the pixel row direction of the repeating unit; the storage capacitor is arranged between the data signal line and the first power line, or, alternatively, the storage capacitor is arranged between the data signal line and the compensation signal line.

[0070] In an exemplary embodiment, the repeating unit includes a compensation signal line and two first power lines, the two first power lines include a first first power line and a second first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; the first first power line is arranged on a side of the compensation signal line close to the first data signal line group, and a storage capacitor in the first pixel column is arranged between the first data signal line group and the first first power line; the second first power line is arranged on a side of the compensation signal line close to the second data signal line group, and a storage capacitor in the second pixel column is arranged between the second data signal line group and the second first power line.

[0071] In an exemplary embodiment, the repeating unit includes a compensation signal line and a first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; the first power line is arranged on a side of the compensation signal line close to the second data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the compensation signal line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the first power line.

[0072] In an exemplary embodiment, the repeating unit includes a compensation signal line and a first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; the first power line is arranged on a side of the compensation signal line close to the first data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the first power line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the compensation signal line.

[0073] In an exemplary embodiment, the repeating unit includes a first power line and two compensation signal lines, the two compensation signal lines include a first compensation signal line and a second compensation signal line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the first power line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the first power line, and the second data signal line group is arranged on a side of the second pixel column away from the first power line; the first compensation signal line is arranged on a side of the first power line close to the first data signal line group, and the storage capacitor in the first pixel column is arranged between the first data signal line group and the first compensation signal line; the second compensation signal line is arranged on a side of the first power line close to the second data signal line group, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the second compensation signal line.

[0074] In an exemplary embodiment, the repeating unit includes a compensation signal line and a first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the first power line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the first power line, and the second data signal line group is arranged on a side of the second pixel column away from the first power line; the compensation signal line is arranged on a side of the first power line close to the second data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the first power line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the compensation signal line.

[0075] In an exemplary embodiment, the repeating unit includes a compensation signal line and a first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the first power line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the first power line, and the second data signal line group is arranged on a side of the second pixel column away from the first power line; the compensation signal line is arranged on a side of the first power line close to the first data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the compensation signal line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the first power line.

[0076] The display substrate of the present disclosure is described below by way of some exemplary embodiments.

[0077] Figure 2 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 2, in this exemplary embodiment, the display substrate may include multiple repeating units 100 in a direction parallel to the display substrate, and at least one repeating unit 100 may include multiple sub-pixels. In this exemplary embodiment, a repeating unit is the basic unit that makes up the display substrate. The display substrate is constructed by repeatedly and continuously arranging the repeating units along at least one direction. In other words, the display substrate is composed of multiple repeating units.

[0078] In an exemplary embodiment, at least one repeating unit 100 may include four sub-pixels, and the four sub-pixels may include a first sub-pixel P1 that emits a first color light, a second sub-pixel P2 that emits a second color light, a third sub-pixel P3 that emits a third color light, and a fourth sub-pixel P4 that emits a fourth color light. The four sub-pixels may be arranged in a square manner, which can effectively increase the aperture ratio and the area of ​​the light-transmitting region.

[0079] In an exemplary embodiment, in at least one repeating unit 100, the second subpixel P2 may be arranged on one side of the first subpixel P1 in the first direction X, the third subpixel P3 may be arranged on one side of the first subpixel P1 in the second direction Y, and the fourth subpixel P4 may be arranged on one side of the third subpixel P3 in the first direction X. The plurality of subpixels arranged sequentially along the first direction X may be referred to as a pixel row, and the plurality of subpixels arranged sequentially along the second direction Y may be referred to as a pixel column. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array, and the first direction X intersects the second direction Y.

[0080] In an exemplary embodiment, the first subpixel P1 may be a red subpixel (R) that emits red light, the second subpixel P2 may be a blue subpixel (B) that emits blue light, the third subpixel P3 may be a white subpixel (W) that emits white light, and the fourth subpixel P4 may be a green subpixel (G) that emits green light. In some possible embodiments, the arrangement of the RBWGs may be adjusted according to actual needs and is not specifically limited in this disclosure.

[0081] In one exemplary embodiment, the display substrate may include at least a driving circuit layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving circuit layer away from the substrate, in a direction perpendicular to the display substrate. In at least one repeating unit, the driving circuit layer may include multiple circuit units, each of which may include at least a pixel driving circuit. The pixel driving circuits are connected to scan signal lines and data signal lines, respectively. The pixel driving circuits are configured to receive data voltages transmitted by the data signal lines under the control of the scan signal lines and output a corresponding current to the light-emitting device. The light-emitting structure layer may include multiple light-emitting units, each of which may include at least a light-emitting device. The light-emitting device is connected to the pixel driving circuit of the circuit unit for the sub-pixel in which it is located. The light-emitting device is configured to emit light of a corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel in which it is located.

[0082] In another exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a driving circuit layer disposed on a base, a color filter structure layer disposed on a side of the driving circuit layer remote from the base, and a light-emitting structure layer disposed on a side of the color filter structure layer remote from the base. In at least one repeating unit, the color filter structure layer may include multiple color filter units, each of which may include at least a color filter layer configured to cause corresponding sub-pixels to emit light of a desired color.

[0083] In exemplary embodiments, the circuit unit referred to in this disclosure refers to an area divided by pixel driver circuits. The color filter unit referred to in this disclosure refers to an area divided by color filter layers. The display unit referred to in this disclosure refers to an area divided by light-emitting devices. The orthographic projections of the circuit unit, the color filter layer, and the light-emitting unit on the substrate may correspond or may not correspond.

[0084] In the exemplary embodiment of the present disclosure, the positions of the circuit unit's orthographic projection on the substrate, the color filter layer's orthographic projection on the substrate, and the light-emitting unit's orthographic projection on the substrate are one-to-one corresponding, and the circuit unit, the color filter unit, and the light-emitting unit constitute sub-pixels. Therefore, in the following content, sub-pixels are uniformly used to refer to the circuit unit, the color filter unit, and the light-emitting unit.

[0085] Figure 3 is an equivalent circuit diagram of a pixel driving circuit in a repeating unit according to an exemplary embodiment of the present disclosure. As shown in Figure 3, at least one repeating unit may include four pixel driving circuits, which may be arranged in a square and may have a 3T1C structure.

[0086] In an exemplary embodiment, at least one pixel driving circuit may include three transistors (a first transistor T1, a second transistor T2, and a third transistor T3) and a storage capacitor C, and the pixel driving circuit is respectively connected to the scanning signal line 30, the first power line 51, the data signal line 52, and the compensation signal line 53.

[0087] In an exemplary embodiment, each pixel driving circuit may include a first node N1 and a second node N2. The first node N1 is connected to the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the first end of the storage capacitor C, respectively. The second node N2 is connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the second end of the storage capacitor C, respectively.

[0088] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , a second end of the storage capacitor C is connected to the second node N2 , and the storage capacitor C is used to store the potential of the gate electrode of the second transistor T2 .

[0089] In an exemplary embodiment, the first transistor T1 is a switching transistor, the second transistor T2 is a driving transistor, and the third transistor T3 is a compensation transistor.

[0090] In the exemplary embodiment, a gate electrode of the first transistor T1 is connected to the scan signal line 30, a first electrode of the first transistor T1 is connected to the data signal line 52, and a second electrode of the first transistor T1 is connected to the first node N1. When a turn-on signal is applied to the scan signal line 30, the first transistor T1 inputs a data signal of the data signal line 52 to the gate electrode of the second transistor T2.

[0091] In an exemplary embodiment, a gate electrode of the second transistor T2 is connected to the first node N1, a first electrode of the second transistor T2 is connected to the first power line 51, and a second electrode of the second transistor T2 is connected to the second node N2. The second transistor T2 generates a corresponding current at its second electrode under the control of the data signal received at its gate electrode.

[0092] In an exemplary embodiment, a gate electrode of the third transistor T3 is connected to the scan signal line 30, a first electrode of the third transistor T3 is connected to the compensation signal line 53, and a second electrode of the third transistor T3 is connected to the second node N2. When a turn-on signal is applied to the scan signal line 30, the third transistor T3 extracts the threshold voltage Vth and mobility of the second transistor T2 in response to the compensation timing to compensate for the threshold voltage Vth.

[0093] In an exemplary embodiment, in the pixel driving circuit of at least one sub-pixel, the gate electrode of the first transistor T1 and the gate electrode of the third transistor T3 are connected to the same scan signal line 30 .

[0094] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one pixel row, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30 .

[0095] In an exemplary embodiment, in the plurality of pixel driving circuits of at least one repeating unit, the gate electrodes of the plurality of first transistors T1 and the gate electrodes of the plurality of third transistors T3 are connected to the same scan signal line 30 .

[0096] In an exemplary embodiment, the light emitting device EL may be an OLED, including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED, including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode). The first electrode of the light emitting device EL is connected to the second node N2, and the second electrode of the light emitting device EL is connected to the second power line 52. The light emitting device EL emits light of corresponding brightness in response to the current of the second electrode of the second transistor T2.

[0097] In an exemplary embodiment, the signal of the first power line 51 is a continuously provided high-level signal, and the signal of the second power line 52 is a continuously provided low-level signal.

[0098] In an exemplary embodiment, the first to third transistors T1 to T3 may be P-type transistors or N-type transistors. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first to third transistors T1 to T3 may include P-type transistors and N-type transistors.

[0099] In an exemplary embodiment, the first transistor T1 to the third transistor T3 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate, i.e., an LTPS+Oxide (LTPO) display substrate, can leverage the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display quality.

[0100] Figure 4 is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of a pixel driver circuit within a repeating unit (four subpixels) of a bottom-emission display substrate. As shown in Figure 4 , in an exemplary embodiment, at least one repeating unit may include a first subpixel P1, a second subpixel P2, a third subpixel P3, and a fourth subpixel P4 arranged in a square, each of which includes a pixel driver circuit.

[0101] In an exemplary embodiment, at least one repeating unit may include a scan signal line 30, two first power lines 51, four data signal lines 52 and a compensation signal line 53, and the above signal lines are respectively connected to the pixel driving circuits in the corresponding sub-pixels, the scan signal line 30 is configured to provide a scan signal to the pixel driving circuit, the first power line 51 is configured to provide a power signal to the pixel driving circuit, the data signal line 52 is configured to provide a data signal to the pixel driving circuit, and the compensation signal line 53 is configured to provide a compensation signal to the pixel driving circuit.

[0102] In an exemplary embodiment, the shape of the scanning signal line 30 can be a line shape in which the main portion extends along the first direction X (pixel row direction), and the shape of the first power line 51, the data signal line 52 and the compensation signal line 53 can be a line shape in which the main portion extends along the second direction Y (pixel column direction), and the first direction X and the second direction Y intersect.

[0103] In an exemplary embodiment, the scanning signal line 30 can be arranged in the middle of the repeating unit in the second direction Y, and a compensation signal line 53 can be located in the middle of the repeating unit in the first direction X. In this way, a scanning signal line 30 extending along the first direction X can define two pixel rows, and a compensation signal line 53 extending along the second direction Y can define two pixel columns, forming a first sub-pixel P1, a second sub-pixel P2, a third sub-pixel P3, and a fourth sub-pixel P4 arranged in a square manner in a repeating unit.

[0104] In an exemplary embodiment, in at least one repetition unit, the four sub-pixels may be mirror-symmetrical with respect to the scan signal line 30 , and the four sub-pixels may be mirror-symmetrical with respect to the compensation signal line 53 .

[0105] In an exemplary embodiment, in at least one repeating unit, the two pixel columns may include a first pixel column and a second pixel column, the two first power lines 51 may include a first first power line 51-1 and a second first power line 51-2 sequentially arranged along the first direction X, and the four data signal lines 52 may include a first data signal line 52-1, a second data signal line 52-2, a third data signal line 52-3 and a fourth data signal line 52-4 sequentially arranged along the first direction X. The first data signal line 52-1 and the second data signal line 52-2 may constitute a first data signal line group, and the third data signal line 52-3 and the fourth data signal line 52-4 may constitute a second data signal line group.

[0106] In an exemplary embodiment, the compensation signal line 53, the first first power line 51-1, and the second first power line 51-2 can be located in the middle area of ​​the repeating unit in the first direction X, the first data signal line group (including the first data signal line 52-1 and the second data signal line 52-2) can be located on the side opposite to the first direction X of the repeating unit, the second data signal line group (including the third data signal line 52-3 and the fourth data signal line 52-4) can be located on one side of the repeating unit in the first direction X, the first first power line 51-1 can be set on the side of the compensation signal line 53 close to the first data signal line group, and the second first power line 51-2 can be set on the side of the compensation signal line 53 close to the second data signal line group.

[0107] In an exemplary embodiment, a pixel driving circuit for at least one sub-pixel may include at least a storage capacitor 60, a first transistor T1, a second transistor T2, and a third transistor T3. The storage capacitor may include a first plate and a second plate serving as capacitor plates. The storage capacitor 60 of the first pixel column may be disposed between the first first power line 51-1 and the second data signal line 52-2 in the first data signal line group. The storage capacitor 60 of the second pixel column may be disposed between the second first power line 51-2 and the third data signal line 52-3 in the second data signal line group.

[0108] In an exemplary embodiment, a first electrode of the first transistor T1 is connected to the data signal line 52, a second electrode of the first transistor T1 is respectively connected to the gate electrode of the second transistor T2 and the second plate of the storage capacitor 60, a first electrode of the second transistor T2 is connected to the first power line 51, a first electrode of the third transistor T3 is connected to the compensation signal line 53, and a second electrode of the third transistor T3 is respectively connected to the second electrode of the second transistor T2 and the first plate of the storage capacitor 60.

[0109] In an exemplary embodiment, at least one repeating unit further includes two power connection electrodes 18 , each of which may be located on one side of the repeating unit in the second direction Y. Each power connection electrode 18 may be in the shape of a strip extending along the first direction X and spanning the first pixel column and the second pixel column. The first end of each power connection electrode 18 is connected to the first first power line 51 - 1 and the first electrode of the second transistor T2 in the first pixel column, and the second end of each power connection electrode 18 is connected to the second first power line 51 - 2 and the first electrode of the second transistor T2 in the second pixel column. In this way, the two first power lines 51 and the two power connection electrodes 18 within the repeating unit form a ring structure that transmits the first power signal.

[0110] In an exemplary embodiment, the orthographic projection of the power connection electrode 18 on the display substrate plane does not overlap with the orthographic projection of the data signal line 52 on the display substrate plane.

[0111] In an exemplary embodiment, an orthographic projection of the power connection electrode 18 on the display substrate plane at least partially overlaps with an orthographic projection of the compensation signal line 53 on the display substrate plane.

[0112] The following is an illustrative explanation of the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be carried out by any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be carried out by any one or more of spraying, spin coating, and inkjet printing, and etching can be carried out by any one or more of dry etching and wet etching, and the present disclosure does not limit this. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate of a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". As used in this disclosure, "A and B are disposed in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0113] In an exemplary embodiment, taking four sub-pixels (first sub-pixel P1 , second sub-pixel P2 , third sub-pixel P3 and fourth sub-pixel P4 ) of a repeating unit as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0114] (11) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern includes: depositing a first conductive film on a substrate, patterning the first conductive film through a patterning process, and forming the first conductive layer pattern on the substrate, as shown in FIG5 .

[0115] In an exemplary embodiment, the first conductive layer of each sub-pixel in the display substrate may include at least a first connection electrode 11 , a second connection electrode 12 , and a first plate 61 of a storage capacitor.

[0116] In an exemplary embodiment, the shape of the first electrode plate 61 can be rectangular, and the corners of the rectangle can be chamfered. The first electrode plate 61 can serve as a transparent electrode plate of a transparent storage capacitor. The first electrode plate 61 is configured to form a transparent storage capacitor with the subsequently formed second electrode plate.

[0117] In an exemplary embodiment, the first connection electrode 11 and the second connection electrode 12 may be located on both sides of the first electrode plate 61 in the second direction Y, respectively.

[0118] In an exemplary embodiment, in the first subpixel P1 and the second subpixel P2, the first connection electrode 11 may be disposed on one side of the first electrode plate 61 in the opposite direction of the second direction Y, and the second connection electrode 12 may be disposed on one side of the first electrode plate 61 in the second direction Y. In the third subpixel P3 and the fourth subpixel P4, the first connection electrode 11 may be disposed on one side of the first electrode plate 61 in the second direction Y, and the second connection electrode 12 may be disposed on one side of the first electrode plate 61 in the opposite direction of the second direction Y.

[0119] In an exemplary embodiment, the shape of the first connection electrode 11 can be a strip shape with a main portion extending along the second direction Y, the first end of the first connection electrode 11 is connected to the first electrode plate 61, and the second end of the first connection electrode 11 extends in a direction away from the second connection electrode 12, and the first connection electrode 11 is configured to be connected to a third connection electrode formed subsequently.

[0120] In an exemplary embodiment, the shape of the second connection electrode 12 can be a strip shape with a main portion extending along the second direction Y, the first end of the second connection electrode 12 is connected to the first electrode plate 61, and the second end of the second connection electrode 12 extends in a direction away from the first connection electrode 11, and the second connection electrode 12 is configured to be connected to a fourth connection electrode formed subsequently.

[0121] In an exemplary embodiment, in the first pixel column, the first connection electrode 11 may be disposed on a side away from the second pixel column, and an edge of the first connection electrode 11 on the side away from the second pixel column may be substantially flush with an edge of the first electrode plate 61 on the side away from the second pixel column. In the second pixel column, the first connection electrode 11 may be disposed on a side away from the first pixel column, and an edge of the first connection electrode 11 on the side away from the first pixel column may be substantially flush with an edge of the first electrode plate 61 on the side away from the first pixel column.

[0122] In an exemplary embodiment, in the first direction X, the width of the first connection electrode 11 may be greater than the width of the second connection electrode 12 .

[0123] In an exemplary embodiment, in each sub-pixel, the second connection electrode 12 may be disposed near a middle region of the sub-pixel in the first direction X.

[0124] In an exemplary embodiment, the first connection electrode 11 , the second connection electrode 12 , and the first electrode plate 61 of each sub-pixel may be an integrated structure connected to each other.

[0125] In an exemplary embodiment, the areas of the first plates 61 in the respective sub-pixels may be substantially the same, so that the capacities of the storage capacitors in the respective sub-pixels are substantially the same.

[0126] In an exemplary embodiment, the positions of the respective patterns in the first conductive layer in the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, and the positions of the respective patterns in the first conductive layer in the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the horizontal reference line. The positions of the respective patterns in the first conductive layer in the first subpixel P1 and the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the respective patterns in the third subpixel P3 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to the vertical reference line. The horizontal reference line may be a straight line extending along the first direction X and bisecting the repeating unit in the second direction Y, and the vertical reference line may be a straight line extending along the second direction Y and bisecting the repeating unit in the first direction X.

[0127] In an exemplary embodiment, the first conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0128] (12) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a second conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the second conductive film through a patterning process to form a second conductive layer, as shown in FIG6A and FIG6B , where FIG6B is a schematic diagram of the second conductive layer in FIG6A . In an exemplary embodiment, the second conductive layer may be referred to as a shield layer.

[0129] In an exemplary embodiment, the second conductive layer of each sub-pixel in the display substrate may include at least a third connection electrode 13 and a fourth connection electrode 14 .

[0130] In an exemplary embodiment, the third connection electrode 13 may be block-shaped (e.g., rectangular) and may be located on a side of the first electrode plate 61 away from the second connection electrode 12. The orthographic projection of the third connection electrode 13 on the substrate at least partially overlaps the orthographic projection of the first connection electrode 11 on the substrate, and the third connection electrode 13 directly overlaps the first connection electrode 11. In an exemplary embodiment, the third connection electrode 13 is configured to connect to a subsequently formed fifth connection electrode and to shield the second transistor from light, thereby reducing the intensity of light incident on the second transistor and lowering leakage current of the second transistor, thereby alleviating the impact of light on the characteristics of the second transistor.

[0131] In an exemplary embodiment, the fourth connection electrode 14 can be in a block shape (such as a rectangle) and can be located on the side of the first electrode plate 61 away from the first connection electrode 11. The orthographic projection of the fourth connection electrode 14 on the substrate at least partially overlaps with the orthographic projection of the second connection electrode 12 on the substrate, and the fourth connection electrode 14 is directly overlapped with the second connection electrode 12. The fourth connection electrode 14 is configured to be connected to the sixth connection electrode formed subsequently.

[0132] In an exemplary embodiment, in the first direction X, the width of the third connection electrode 13 may be greater than the width of the fourth connection electrode 14 .

[0133] In an exemplary embodiment, the second conductive layer of each repeating unit in the display substrate may include at least two first power lines 51 , four data signal lines 52 , and one compensation signal line 53 .

[0134] In an exemplary embodiment, the shapes of the first power line 51, the data signal line 52 and the compensation signal line 53 can be straight lines or broken lines with the main portion extending along the second direction Y. The compensation signal line 53 can be located in the middle of the repeating unit in the first direction X. The two first power lines 51 can be located on both sides of the compensation signal line 53 in the first direction X. The first data signal line group of the four data signal lines 52 can be located on the side opposite to the first direction X of the repeating unit, and the second data signal line group of the four data signal lines 52 can be located on one side of the repeating unit in the first direction X.

[0135] In an exemplary embodiment, the two first power lines 51 may include a first first power line 51-1 and a second first power line 51-2 arranged in sequence along the first direction X, and the four data signal lines 52 may include a first data signal line group and a second data signal line group, the first data signal line group may include a first data signal line 52-1 and a second data signal line 52-2 arranged in sequence along the first direction X, and the second data signal line group may include a third data signal line 52-3 and a fourth data signal line 52-4 arranged in sequence along the first direction X.

[0136] In an exemplary embodiment, the first data signal line 52-1 and the compensation signal line 53 can define a first pixel column, the second data signal line 52-2 and the first first power line 51-1 are arranged in the first pixel column, the second data signal line 52-2 can be arranged on a side of the first data signal line 52-1 close to the compensation signal line 53, the first first power line 51-1 can be arranged on a side of the compensation signal line 53 close to the first data signal line 52-1, and the first electrode 61, the third connecting electrode 13 and the fourth connecting electrode 14 can be arranged between the second data signal line 52-2 and the first first power line 51-1.

[0137] In an exemplary embodiment, the fourth data signal line 52-4 and the compensation signal line 53 can define a second pixel column, the second first power line 51-2 and the third data signal line 52-3 are arranged in the second pixel column, the second first power line 51-2 can be arranged on the side of the compensation signal line 53 close to the fourth data signal line 52-4, the third data signal line 52-3 can be arranged on the side of the fourth data signal line 52-4 close to the compensation signal line 53, and the first electrode 61, the third connecting electrode 13 and the fourth connecting electrode 14 can be arranged between the second first power line 51-2 and the third data signal line 52-3.

[0138] In an exemplary embodiment, a power connection block 54 may be provided on the first power line 51. The power connection block 54 may be in a block shape (e.g., rectangular), with a first end of the power connection block 54 connected to the first power line 51 and a second end of the power connection block 54 extending in a direction away from the compensation signal line 53. The power connection block 54 is configured to be connected to the first region of the second active layer via a subsequently formed power connection electrode.

[0139] In an exemplary embodiment, the first power line 51 , the data signal line 52 and the compensation signal line 53 may be zigzag lines of unequal widths. Using zigzag lines of varying widths not only facilitates the layout of the pixel structure but also reduces parasitic capacitance.

[0140] In an exemplary embodiment, the orthographic projection of the compensation signal line 53 on the substrate at least partially overlaps with the orthographic projection of the vertical reference line on the substrate, the positions of the two first power lines 51 can be substantially mirror-symmetrical with respect to the vertical reference line, and the positions of the two data signal lines 52 located on the opposite side of the first direction X of the compensation signal line 53 and the positions of the two data signal lines 52 located on the side of the first direction X of the compensation signal line 53 can be substantially mirror-symmetrical with respect to the vertical reference line.

[0141] In an exemplary embodiment, for the third connection electrode 13, the fourth connection electrode 14 and the power connection block 54, the positions of these patterns in the first sub-pixel P1 and the third sub-pixel P3 can be substantially mirror-symmetrical with respect to the horizontal reference line, the positions of these patterns in the second sub-pixel P2 and the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to the horizontal reference line, the positions of these patterns in the first sub-pixel P1 and the second sub-pixel P2 can be substantially mirror-symmetrical with respect to the vertical reference line, and the positions of these patterns in the third sub-pixel P3 and the fourth sub-pixel P4 can be substantially mirror-symmetrical with respect to the vertical reference line.

[0142] (13) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: sequentially depositing a first insulating film and a semiconductor film on the substrate on which the aforementioned pattern is formed, patterning the semiconductor film through a patterning process to form a first insulating layer covering the first conductive layer and the second conductive layer, and a semiconductor layer disposed on the first insulating layer, as shown in FIG7A and FIG7B , where FIG7B is a schematic diagram of the semiconductor layer in FIG7A .

[0143] In an exemplary embodiment, the semiconductor layer of each sub-pixel in the display substrate may include at least a first active layer 21, a second active layer 22, a third active layer 23, and a second electrode 62 of the storage capacitor. The first active layer 21 may serve as the active layer of the first transistor T1, the second active layer 22 may serve as the active layer of the second transistor T2, and the third active layer 23 may serve as the active layer of the third transistor T3. The second electrode 62 may serve as another transparent electrode plate of the transparent storage capacitor. The second electrode plate 62 is configured to form a transparent storage capacitor with the first electrode plate 61.

[0144] In an exemplary embodiment, for the first subpixel P1 and the second subpixel P2, the first active layer 21 and the third active layer 23 can be arranged on one side of the first electrode 61 of the subpixel in the second direction Y, and the second active layer 22 can be arranged on the side of the first electrode 61 of the subpixel in the opposite direction of the second direction Y.

[0145] In an exemplary embodiment, for the first subpixel P1, the first active layer 21 may be disposed on a side of the subpixel away from the second subpixel P2, and the third active layer 23 may be disposed on a side of the subpixel closer to the second subpixel P2. For the second subpixel P2, the first active layer 21 may be disposed on a side of the subpixel away from the first subpixel P1, and the third active layer 23 may be disposed on a side of the subpixel closer to the first subpixel P1.

[0146] In an exemplary embodiment, for the third subpixel P3 and the fourth subpixel P4, the first active layer 21 and the third active layer 23 can be arranged on the side opposite to the second direction Y of the first electrode 61 of the subpixel, and the second active layer 22 can be arranged on the side of the second direction Y of the first electrode 61 of the subpixel.

[0147] In an exemplary embodiment, for the third subpixel P3, the first active layer 21 may be disposed on a side of the subpixel away from the fourth subpixel P4, and the third active layer 23 may be disposed on a side of the subpixel close to the fourth subpixel P4. For the fourth subpixel P4, the first active layer 21 may be disposed on a side of the subpixel away from the third subpixel P3, and the third active layer 23 may be disposed on a side of the subpixel close to the third subpixel P3.

[0148] In example embodiments, the active layer of each transistor may include a first region, a second region, and a channel region between the first region and the second region.

[0149] In an exemplary embodiment, the orthographic projection of the first region of the first active layer 21 of each subpixel on the substrate at least partially overlaps with the orthographic projection of the corresponding data signal line 52 on the substrate, and the second region of the first active layer 21 is connected to the second electrode 62 .

[0150] In an exemplary embodiment, the second electrode plate 62 and the first active layer 21 of each sub-pixel may be an integral structure connected to each other.

[0151] In an exemplary embodiment, the orthographic projection of the first area of ​​the second active layer 22 of each sub-pixel on the substrate at least partially overlaps with the orthographic projection of the power connection block 54 of the first power line 51 on the substrate, and the orthographic projection of the second area and the channel region of the second active layer 22 on the substrate at least partially overlaps with the orthographic projection of the third connection electrode 13 on the substrate, so that the first electrode 61 serving as a shielding layer can shield the channel region of the second transistor T2, prevent light from affecting the channel, and ensure the electrical performance of the second transistor T2.

[0152] In an exemplary embodiment, the orthographic projection of the first area of ​​the third active layer 23 of each sub-pixel on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 53 on the substrate, and the orthographic projection of the second area of ​​the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the fourth connection electrode 14 of the sub-pixel on the substrate.

[0153] In an exemplary embodiment, the first area of ​​the third active layer 23 in the first subpixel P1 and the first area of ​​the third active layer 23 in the second subpixel P2 may be connected to each other, and the first area of ​​the third active layer 23 in the third subpixel P3 and the first area of ​​the third active layer 23 in the fourth subpixel P4 may be connected to each other.

[0154] In an exemplary embodiment, the third active layer 23 in the first subpixel P1 and the third active layer 23 in the second subpixel P2 may be interconnected as an integral structure, and the third active layer 23 in the third subpixel P3 and the third active layer 23 in the fourth subpixel P4 may be interconnected as an integral structure. The present disclosure, by providing the third active layers of two adjacent subpixels in a pixel row as an interconnected integral structure, not only saves space but also reduces the number of via connection structures, simplifying the manufacturing process.

[0155] In an exemplary embodiment, an orthographic projection of the third active layer 23 on the substrate at least partially overlaps an orthographic projection of the first power line 51 on the substrate.

[0156] In an exemplary embodiment, the shape of the second electrode plate 62 can be rectangular, the corners of the rectangle can be chamfered, and it can be arranged between the second active layer 22 and the third active layer 23 of the sub-pixel. The orthographic projection of the second electrode plate 62 on the substrate at least partially overlaps with the orthographic projection of the first electrode plate 61 on the substrate. The second electrode plate 62 can serve as a transparent intermediate electrode plate of a transparent storage capacitor, and the first electrode plate 61 and the second electrode plate 62 form a transparent first capacitor.

[0157] In an exemplary embodiment, the area of ​​the second electrode 62 in each sub-pixel may be substantially the same, so that the capacity of the storage capacitor in each sub-pixel is substantially the same.

[0158] In exemplary embodiments, the semiconductor layer may be formed of a metal oxide, such as an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, an oxide containing indium, gallium, and zinc, etc. The semiconductor layer may be a single layer, a double layer, or a multilayer.

[0159] In an exemplary embodiment, the positions of the respective patterns in the semiconductor layer in the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the positions of the respective patterns in the semiconductor layer in the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a horizontal reference line, the positions of the respective patterns in the semiconductor layer in the first subpixel P1 and the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the respective patterns in the semiconductor layer in the third subpixel P3 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line.

[0160] (14) Forming a second insulating layer pattern. In an exemplary embodiment, forming the second insulating layer pattern may include: depositing a second insulating film on the substrate on which the aforementioned pattern is formed, patterning the second insulating film through a patterning process to form a second insulating layer pattern covering the semiconductor layer, wherein a plurality of vias are provided on the second insulating layer, as shown in FIG8 .

[0161] In an exemplary embodiment, the plurality of via holes of each sub-pixel in the display substrate includes at least a first via hole V1 , a second via hole V2 , a third via hole V3 , a fourth via hole V4 , a fifth via hole V5 , and a sixth via hole V6 .

[0162] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate at least partially overlaps with the orthographic projection of the first region of the first active layer 21 on the substrate, and the orthographic projection of the first via hole V1 on the substrate at least partially overlaps with the orthographic projection of the data signal line 52 on the substrate. The first via hole V1 is a via hole in a transfer structure and includes two half holes. The second insulating layer in the shallow half hole is etched away, exposing the surface of the first region of the first active layer 21, and the first and second insulating layers in the deep half hole are etched away, exposing the surface of the data signal line 52. Thus, the first via hole V1 in the transfer structure, consisting of the two half holes, simultaneously exposes the first region of the first active layer 21 and the data signal line 52. The first via hole V1 is configured to allow a subsequently formed data connection electrode to simultaneously connect to the first region of the first active layer 21 and the data signal line 52 through the via hole.

[0163] In an exemplary embodiment, the orthographic projection of the second via V2 on the substrate at least partially overlaps with the orthographic projection of the first region of the second active layer 22 on the substrate. The orthographic projection of the second via V2 on the substrate at least partially overlaps with the orthographic projection of the power connection block 54 of the first power line 51 on the substrate. The second via V2 is a via hole in a transition structure, comprising two half holes. The second insulating layer in the shallow half hole is etched away, exposing the surface of the first region of the second active layer 22. The first and second insulating layers in the deep half hole are etched away, exposing the surface of the power connection block 54. Thus, the second via V2 in the transition structure, consisting of the two half holes, simultaneously exposes the first region of the second active layer 22 and the power connection block 54. The second via V2 is configured to allow a subsequently formed power connection electrode to simultaneously connect to the first region of the second active layer 22 and the power connection block 54 through the via hole.

[0164] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate at least partially overlaps with the orthographic projection of the second region of the second active layer 22 on the substrate, and the orthographic projection of the third via hole V3 on the substrate at least partially overlaps with the orthographic projection of the third connecting electrode 13 on the substrate. The third via hole V3 is a via hole in a transition structure, comprising two half holes. The second insulating layer in the shallow half hole is etched away, exposing the surface of the second region of the second active layer 22, while the first and second insulating layers in the deep half hole are etched away, exposing the surface of the third connecting electrode 13. Thus, the third via hole V3 in the transition structure, consisting of the two half holes, simultaneously exposes the second region of the second active layer 22 and the third connecting electrode 13. The third via hole V3 is configured to allow a subsequently formed fifth connecting electrode to be simultaneously connected to the second region of the second active layer 22 and the third connecting electrode 13 through the via hole.

[0165] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the first region of the third active layer 23 on the substrate, and the orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 53 on the substrate. The fourth via hole V4 is a via hole in a transition structure, comprising two half holes. The second insulating layer in the shallow half hole is etched away, exposing the surface of the first region of the third active layer 23, while the first and second insulating layers in the deep half hole are etched away, exposing the surface of the compensation signal line 53. Thus, the fourth via hole V4 in the transition structure, consisting of the two half holes, simultaneously exposes the first region of the third active layer 23 and the compensation signal line 53. The fourth via hole V4 is configured to allow a subsequently formed compensation connection electrode to be connected to both the first region of the third active layer 23 and the compensation signal line 53 through the via hole.

[0166] In an exemplary embodiment, since the first regions of the third active layer in the first subpixel P1 and the second subpixel P2 are connected to each other, and the first regions of the third active layer in the third subpixel P3 and the fourth subpixel P4 are connected to each other, the first subpixel P1 and the second subpixel P2 share one fourth via hole V4, and the third subpixel P3 and the fourth subpixel P4 share one fourth via hole V4.

[0167] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate at least partially overlaps with the orthographic projection of the second region of the third active layer 23 on the substrate, and the orthographic projection of the fifth via hole V5 on the substrate at least partially overlaps with the orthographic projection of the fourth connecting electrode 14 on the substrate. The fifth via hole V5 is a via hole in a transition structure, comprising two half holes. The second insulating layer in the shallow half hole is etched away, exposing the surface of the second region of the third active layer 23, and the first and second insulating layers in the deep half hole are etched away, exposing the surface of the fourth connecting electrode 14. The fifth via hole V5 in the transition structure, formed by the two half holes, simultaneously exposes the second region of the third active layer 23 and the fourth connecting electrode 14. The fifth via hole V5 is configured to allow a subsequently formed sixth connecting electrode to be connected to both the second region of the third active layer 23 and the fourth connecting electrode 14 through the via hole.

[0168] In an exemplary embodiment, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second electrode plate 62 on the substrate, the second insulating layer in the sixth via V6 is etched away to expose the surface of the second electrode plate 62, and the sixth via V6 is configured to connect the subsequently formed second gate electrode to the second electrode plate 62 through the via.

[0169] In an exemplary embodiment, during the process of forming the second insulating layer pattern, a dry etching process is used to form a plurality of via holes. Simultaneously, a primary conductive process is performed on the semiconductor layer exposed within the via holes, thereby forming a primary conductive region within the semiconductor layer exposed within the via holes. During the primary conductive process, the edge portion of the semiconductor layer covered by the second insulating layer near the via hole is also conductively conductive, meaning that the primary conductive semiconductor layer extends away from the via hole.

[0170] (15) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer pattern may include: depositing a third conductive film on the substrate having the aforementioned pattern formed thereon, patterning the third conductive film through a patterning process, and forming a third conductive layer pattern on the second insulating layer, as shown in FIG. 9A and FIG. 9B , where FIG. 9B is a schematic diagram of the third conductive layer in FIG. 9A . In an exemplary embodiment, the third conductive layer may be referred to as a gate metal (GT) layer.

[0171] In an exemplary embodiment, the third conductive layer of each sub-pixel in the display substrate may include at least a fifth connection electrode 15, a sixth connection electrode 16, a data connection electrode 17, a power connection electrode 18, a compensation connection electrode 19, a scanning signal line 30, a first gate electrode 31, a second gate electrode 32 and a third gate electrode 33.

[0172] In an exemplary embodiment, the shape of the scan signal line 30 can be a line shape in which the main portion extends along the first direction X. One scan signal line 30 can define two pixel rows. The scan signal line 30 is located between the first pixel row (including the first sub-pixel P1 and the second sub-pixel P2) and the second pixel row (including the third sub-pixel P3 and the fourth sub-pixel P4). The scan signal line 30 is configured to simultaneously control the conduction or disconnection of all the first transistors T1 and all the third transistors T3 in the four sub-pixels of the repeating unit.

[0173] In an exemplary embodiment, the first gate electrode 31 may be in the shape of a strip extending along the second direction Y and may be disposed on a side of the scan signal line 30 close to the first active layer 21. A first end of the first gate electrode 31 is connected to the scan signal line 30, and a second end of the first gate electrode 31 extends toward the first active layer 21. The orthographic projection of the first gate electrode 31 on the substrate at least partially overlaps with the orthographic projection of the first active layer 21 on the substrate. In an exemplary embodiment, the first gate electrode 31 may serve as the gate electrode of the first transistor T1, so that the scan signal line 30 can control whether the first transistor T1 is turned on or off.

[0174] In an exemplary embodiment, the second gate electrode 32 may be in the shape of a strip extending along the second direction Y. A first end of the second gate electrode 32 is connected to the second electrode plate 62 via a sixth via V6, and a second end of the second gate electrode 32 extends toward the second active layer 22. The orthographic projection of the second gate electrode 32 on the substrate at least partially overlaps with the orthographic projection of the second active layer 22 on the substrate. In an exemplary embodiment, the second gate electrode 32 may serve as the gate electrode of the second transistor T2 and may control whether the second transistor T2 is turned on or off.

[0175] In an exemplary embodiment, since the second gate electrode 32 is connected to the second electrode plate 62, and the second electrode plate 62 is connected to the second region of the first active layer 21, the second electrode of the first transistor T1, the gate electrode of the second transistor T2, and the second electrode plate 62 (the first end of the storage capacitor) have the same potential, forming a first node in the pixel driving circuit, and the second electrode plate 62 has the potential of the first node in the pixel driving circuit.

[0176] In an exemplary embodiment, the third gate electrode 33 may be in the shape of a strip extending along the second direction Y and may be disposed on a side of the scan signal line 30 close to the third active layer 23. A first end of the third gate electrode 33 is connected to the scan signal line 30, and a second end of the third gate electrode 33 extends toward the third active layer 23. The orthographic projection of the third gate electrode 33 on the substrate at least partially overlaps with the orthographic projection of the third active layer 23 on the substrate. In an exemplary embodiment, the third gate electrode 33 may serve as the gate electrode of the third transistor T3, so that the scan signal line 30 can control the conduction or disconnection of the third transistor T3.

[0177] In an exemplary embodiment, in one sub-pixel, one scan signal line 30 is connected to both the first gate electrode 31 and the third gate electrode 33 , so that the scan signal line 30 can control the on / off switching of the first transistor T1 and the third transistor T3 in one sub-pixel.

[0178] In an exemplary embodiment, in one pixel row, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 in a plurality of sub-pixels, so that the scan signal line 30 can control the conduction or disconnection of all first transistors T1 and all third transistors T3 in one pixel row.

[0179] In an exemplary embodiment, in one repeating unit, one scan signal line 30 is simultaneously connected to all first gate electrodes 31 and all third transistors 33 in a plurality of sub-pixels, so that the scan signal line 30 can simultaneously control the on or off of all first transistors T1 and all third transistors T3 in the repeating unit.

[0180] In an exemplary embodiment, within at least one repeating unit, the scan signal line 30 , the first gate electrode 31 , and the third gate electrode 33 may be an integral structure connected to each other.

[0181] In an exemplary embodiment, the fifth connection electrode 15 can be in a block shape (such as a rectangle) and can be arranged on a side of the second electrode plate 62 away from the scan signal line 30. The fifth connection electrode 15 is connected to the second region of the second active layer 22 and the third connection electrode 13 at the same time through the third via hole V3.

[0182] In the exemplary embodiment, since the third connection electrode 13 is connected to the first connection electrode 11, and the first connection electrode 11 is connected to the first electrode plate 61, the fifth connection electrode 15 allows the second electrode of the second transistor and the first electrode plate 61 to have the same potential. In the exemplary embodiment, the fifth connection electrode 15 is configured to be connected to a tenth connection electrode formed subsequently.

[0183] In an exemplary embodiment, the sixth connection electrode 16 can be in a block shape (such as a rectangle) and can be arranged on the side of the second electrode plate 62 close to the scan signal line 30. The sixth connection electrode 16 is simultaneously connected to the second region of the third active layer 23 and the fourth connection electrode 14 through the fifth via hole V5.

[0184] In the exemplary embodiment, since the fourth connection electrode 14 is connected to the second connection electrode 12 , and the second connection electrode 12 is connected to the first electrode plate 61 , the sixth connection electrode 16 allows the second electrode of the third transistor and the first electrode plate 61 to have the same potential.

[0185] In an exemplary embodiment, the fifth connecting electrode 15 and the sixth connecting electrode 16 realize the connection between the second electrode of the second transistor, the second electrode of the third transistor and the first electrode plate 61 (the second end of the storage capacitor), forming a second node in the pixel driving circuit, so that the first electrode plate 61 has the potential of the second node in the pixel driving circuit.

[0186] In an exemplary embodiment, since the first plate 61 has the potential of the second node in the pixel driving circuit and the second plate 62 has the potential of the first node in the pixel driving circuit, the first plate 61 having the potential of the second node and the second plate 62 having the potential of the first node form a storage capacitor.

[0187] In an exemplary embodiment, since the first electrode 61 is made of a transparent conductive material and the second electrode 62 is made of a transparent metal oxide, the storage capacitor is a transparent capacitor.

[0188] In an exemplary embodiment, the data connection electrode 17 may be in a block shape (e.g., a rectangle). The data connection electrode 17 is connected to both the first region of the first active layer 21 and the data signal line 52 through the first via hole V1, thereby enabling the data signal line 52 to write the data signal into the first electrode of the first transistor T1. In an exemplary embodiment, each data signal line 52 may be connected to the first region of the first active layer in a sub-pixel through the first via hole V1, thereby enabling the four data signal lines 52 to write the data signals into the first electrodes of the four first transistors T1 in a repeating unit.

[0189] In an exemplary embodiment, the four data signal lines 52 may include a first data signal line 52-1, a second data signal line 52-2, a third data signal line 52-3, and a fourth data signal line 52-4, which are sequentially arranged along the first direction X. The first data signal line 52-1 may be located on a side of the first pixel column opposite to the first direction X and may be connected to the first region of the first active layer in the first subpixel P1 via the data connection electrode 17. The second data signal line 52-2 may be located on a side of the first data signal line in the first direction X and may be connected to the first region of the first active layer in the third subpixel P3 via the data connection electrode 17. The fourth data signal line 52-4 may be located on a side of the second pixel column in the first direction X and may be connected to the first region of the first active layer in the fourth subpixel P4 via the data connection electrode 17. The third data signal line 52-3 may be located on a side of the fourth data signal line 52-4 opposite to the first direction X and may be connected to the first region of the first active layer in the second subpixel P2 via the data connection electrode 17.

[0190] In an exemplary embodiment, the power connection electrode 18 may be in the shape of a strip extending along the first direction X and may be disposed on a side of the second electrode plate 62 away from the scan signal line 30. The power connection electrode 18 may be connected to both the first region of the second active layer 22 and the power connection block 54 through the second via hole V2. Since the power connection block 54 is connected to the first power line 51, the first power line 51 writes the first power signal into the first electrode of the second transistor T2.

[0191] In an exemplary embodiment, the two first power lines 51 may include a first first power line 51-1 and a second first power line 51-2 sequentially arranged along the first direction X. The first first power line 51-1 may be located in a first pixel column on a side opposite to the first direction X of the compensation signal line 54, and may be connected to the first regions of the second active layer 22 in the first subpixel P1 and the third subpixel P3, respectively, through the two power connection electrodes 18 in the first pixel column. The second first power line 51-2 may be located in a second pixel column on a side opposite to the first direction X of the compensation signal line 54, and may be connected to the first regions of the second active layer 22 in the second subpixel P2 and the fourth subpixel P4, respectively, through the two power connection electrodes 18 in the second pixel column.

[0192] In an exemplary embodiment, the first power line 51 in the first pixel column can simultaneously provide a first power signal to the pixel driving circuits in the first subpixel P1 and the third subpixel P3. The first power line 51 in the second pixel column can simultaneously provide a first power signal to the pixel driving circuits in the second subpixel P2 and the fourth subpixel P4. Thus, the first power lines 51 in a repeating unit form a one-to-two structure. By designing the first power lines as a one-to-two structure, the display substrate of the present disclosure reduces the number of signal lines and the space occupied. The resulting structure is simple, the layout is rational, and the layout space is fully utilized, improving space utilization and facilitating higher resolution.

[0193] In an exemplary embodiment, the two first power lines 51 in a repeating unit are symmetrically arranged relative to the compensation signal line 53, and the second transistor T2 of the first pixel column and the second transistor T2 of the second pixel column are symmetrically arranged relative to the compensation signal line 53. This symmetrical structure of the present disclosure can ensure that the voltage drop written by the first power line to the second transistor T2 is substantially the same, thereby ensuring display uniformity.

[0194] In an exemplary embodiment, the power connection electrodes 18 in the first and second subpixels P1 and P2 may be connected to each other, and the power connection electrodes 18 in the third and fourth subpixels P3 and P4 may be connected to each other.

[0195] In an exemplary embodiment, the power connection electrodes 18 in the first subpixel P1 and the second subpixel P2 may be connected to each other in an integrated structure, that is, the first subpixel P1 and the second subpixel P2 share one power connection electrode 18. The power connection electrodes 18 in the third subpixel P3 and the fourth subpixel P4 may be connected to each other in an integrated structure, that is, the third subpixel P3 and the fourth subpixel P4 share one power connection electrode 18.

[0196] In an exemplary embodiment, the power connection electrode 18 can serve as a horizontal power connection line. The power connection electrode of the integrated structure is in the shape of a strip extending along the first direction X, and is arranged across the first pixel column and the second pixel column, so that the first sub-pixel P1 and the second sub-pixel P2 share one power connection electrode 18, and the third sub-pixel P3 and the fourth sub-pixel P4 share one power connection electrode 18. The two first voltage lines 51 can simultaneously provide the first voltage signal to the pixel driving circuits in the four sub-pixels, so that the four pixel driving circuits in a repeating unit can share two first voltage lines 51.

[0197] In an exemplary embodiment, the orthographic projection of the power connection electrode on the substrate does not overlap with the orthographic projection of the data signal line 52 on the substrate, and the orthographic projection of the power connection electrode 18 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 53 on the substrate.

[0198] In an exemplary embodiment, the shape of the compensation connection electrode 19 can be a block shape (such as a rectangle), and can be arranged between the third gate electrodes 33 of two adjacent sub-pixels in the first direction X. The compensation connection electrode 19 can be simultaneously connected to the first area of ​​the third active layer 23 and the compensation signal line 53 through the fourth via hole V4, thereby enabling the compensation signal line 53 to write the compensation signal into the first electrode of the third transistor T3.

[0199] In an exemplary embodiment, since the first regions of the third active layers in the first subpixel P1 and the second subpixel P2 are connected to each other, the first subpixel P1 and the second subpixel P2 share a fourth via hole V4, and thus the first subpixel P1 and the second subpixel P2 share a compensation connection electrode 19. Since the first regions of the third active layers in the third subpixel P3 and the fourth subpixel P4 are connected to each other, the third subpixel P3 and the fourth subpixel P4 share a fourth via hole V4, and thus the third subpixel P3 and the fourth subpixel P4 share a compensation connection electrode 19.

[0200] In an exemplary embodiment, compensation signal line 53 can simultaneously provide compensation signals to the pixel driver circuits in four sub-pixels. Therefore, the four pixel driver circuits in a repeating unit can share a single compensation signal line 53, i.e., the compensation signal lines 53 in a repeating unit form a one-to-four structure. By designing the display substrate as a one-to-four structure, the disclosed display substrate reduces the number of signal lines and space requirements. This results in a simple structure, a rational layout, and full utilization of layout space, improving space efficiency and facilitating higher resolution.

[0201] In an exemplary embodiment, the compensation signal line 53 is arranged between the first pixel column and the second pixel column, and the third transistor T3 of the first pixel column and the third transistor T3 of the second pixel column are symmetrically arranged with respect to the compensation signal line 53. This symmetrical structure of the present disclosure can ensure that the RC delay of the compensation signal written into the third transistor T3 is substantially the same, thereby ensuring display uniformity.

[0202] In an exemplary embodiment, the positions of the respective patterns in the third conductive layer in the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the positions of the respective patterns in the third conductive layer in the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a horizontal reference line, the positions of the respective patterns in the third conductive layer in the first subpixel P1 and the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the respective patterns in the third conductive layer in the third subpixel P3 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line.

[0203] In an exemplary embodiment, during the process of forming the third conductive layer pattern, a wet etching process is first used to form the third conductive layer pattern, thereby enabling at least one connecting electrode to simultaneously connect to the second conductive layer and the semiconductor layer through the via hole of the transition structure. The via hole of the transition structure can include at least two half-holes: a shallow half-hole and a deep half-hole. The second insulating layer in the shallow half-hole is removed, exposing the surface of the semiconductor layer. The second insulating layer and the first insulating layer in the deep half-hole are removed, exposing the surface of the second conductive layer. This allows the connecting electrode to simultaneously connect to the semiconductor layer and the second conductive layer through both the shallow and deep half-holes. In this exemplary embodiment, a distance is provided between the end of the connecting electrode located in the shallow half-hole region and the edge of the shallow half-hole, meaning that the connecting electrode does not fully cover the shallow half-hole.

[0204] In an exemplary embodiment, after the third conductive layer pattern is formed by a wet etching process, a self-alignment process using the third conductive layer as a mask is used to etch the second insulating layer in an area outside the third conductive layer by a dry etching process. While etching away the second insulating layer, the exposed semiconductor layer is subjected to a second conductorization to form a second conductorization area.

[0205] In an exemplary embodiment, during the second conductorization process, the edge portion of the semiconductor layer covered by the third conductive layer is also conductorized, that is, the semiconductor layer that is conductorized for the second time extends toward the area that was conductorized for the first time, forming a double conductorization area in the overlapping area of ​​the first conductorization area and the second conductorization area, thereby ensuring a reliable connection between the third conductive layer and the semiconductor layer.

[0206] (16) Forming a third insulating layer and a planar layer pattern. In an exemplary embodiment, forming the third insulating layer and the planar layer pattern may include: depositing a third insulating film on the substrate on which the aforementioned pattern is formed, then coating a planar film, patterning the planar film and the third insulating film through a patterning process to form a third insulating layer covering the third conductive layer and a planar layer pattern disposed on the third insulating layer, wherein a plurality of vias are disposed on the planar layer, as shown in FIG. 10 .

[0207] In an exemplary embodiment, the via holes of each sub-pixel in the display substrate include at least an eleventh via hole V11 .

[0208] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the fifth connecting electrode 15 on the substrate, the third insulating layer and the planar layer in the eleventh via hole V11 are etched away to expose the surface of the fifth connecting electrode 15, and the eleventh via hole V11 is configured to connect the subsequently formed tenth connecting electrode to the fifth connecting electrode 15 through the via hole.

[0209] In an exemplary embodiment, this process can use a single patterning process to simultaneously form vias on the third insulating layer and the flat layer. The third insulating layer and the flat layer share a halftone or gray tone mask (MASK) process, effectively reducing the number of patterning processes.

[0210] (17) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film through a patterning process, and forming a fourth conductive layer pattern on the flat layer, as shown in FIG. 11A and FIG. 11B , where FIG. 11B is a schematic diagram of the fourth conductive layer in FIG. 11A .

[0211] In an exemplary embodiment, the fourth conductive layer of each sub-pixel in the display substrate may include at least the tenth connection electrode 20 and the first electrode 70 , and the first electrode 70 may be an anode.

[0212] In an exemplary embodiment, the first electrode 70 may be rectangular in shape, and the corners of the rectangle may be provided with chamfers, grooves or protrusions, and the orthographic projection of the first electrode 70 on the substrate at least partially overlaps with the orthographic projection of the second electrode plate 62 on the substrate.

[0213] In an exemplary embodiment, the tenth connecting electrode 20 may be in a block shape (such as a rectangle) and may be located on a side of the first electrode 70 away from the scanning signal line 30. The first end of the tenth connecting electrode 20 is connected to the first electrode 70, and the second end of the tenth connecting electrode 20 extends in a direction away from the scanning signal line 30 and is connected to the fifth connecting electrode 15 through the eleventh via hole V11.

[0214] In an exemplary embodiment, in at least one sub-pixel, the tenth connection electrode 20 and the first electrode 70 may be an integral structure connected to each other.

[0215] In an exemplary embodiment, the four first electrodes 70 in a repeating unit are arranged in a square, with the upper left anode connected to the pixel driving circuit in the first sub-pixel P1, the upper right anode connected to the pixel driving circuit in the second sub-pixel P2, the lower left anode connected to the pixel driving circuit in the third sub-pixel P3, and the lower right anode connected to the pixel driving circuit in the fourth sub-pixel P4. In some possible implementations, the arrangement of the anodes can be adjusted according to actual needs and is not specifically limited in this disclosure.

[0216] In an exemplary embodiment, the first conductive layer may be made of a transparent conductive material, such as indium tin oxide (ITO) or indium zinc oxide (IZO).

[0217] In an exemplary embodiment, the positions of the respective patterns in the fourth conductive layer in the first subpixel P1 and the third subpixel P3 may be substantially mirror-symmetrical with respect to a horizontal reference line, the positions of the respective patterns in the fourth conductive layer in the second subpixel P2 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a horizontal reference line, the positions of the respective patterns in the fourth conductive layer in the first subpixel P1 and the second subpixel P2 may be substantially mirror-symmetrical with respect to a vertical reference line, and the positions of the respective patterns in the fourth conductive layer in the third subpixel P3 and the fourth subpixel P4 may be substantially mirror-symmetrical with respect to a vertical reference line.

[0218] In an exemplary embodiment, the first electrode 70 can also serve as an auxiliary capacitor of the storage capacitor. Since the first electrode 70 is connected to the tenth connection electrode 20, and the tenth connection electrode 20 is connected to the first plate 61 through the fifth connection electrode 15, the third connection electrode 13 and the first connection electrode 11, the first electrode 70 has the potential of the second node in the pixel driving circuit, so that the first electrode 70 having the second node potential and the second plate 62 having the first node potential form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. The present disclosure uses the anode to form an auxiliary capacitor, and the auxiliary capacitor and the storage capacitor are connected in parallel. On the one hand, it can effectively increase the capacitance value of the storage capacitor, and on the other hand, it can reduce the plate area while ensuring the capacitance value of the storage capacitor, effectively reducing the occupied area.

[0219] (18) Forming a pixel definition layer. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on the substrate having the aforementioned pattern formed thereon, and patterning the pixel definition film through a patterning process to form a pixel definition layer covering the fourth conductive layer, as shown in FIG. 12 .

[0220] In an exemplary embodiment, a pixel opening K is opened on the pixel definition layer of each sub-pixel in the display substrate, and the pixel definition film in the pixel opening K is removed to expose a portion of the surface of the first electrode 70. The orthographic projection of the pixel opening K on the substrate is located within the range of the orthographic projection of the first electrode 70 on the substrate.

[0221] In an exemplary embodiment, the shape of the pixel opening K in a plane parallel to the substrate may be similar to that of the first electrode 70 , and the cross-sectional shape of the pixel opening K in a plane perpendicular to the substrate may be rectangular or trapezoidal.

[0222] In exemplary embodiments, the shape of the pixel opening may include any one or more of a triangle, a rectangle, a trapezoid, a parallelogram, a five-frame shape, a six-frame shape, a circle, and an ellipse.

[0223] In an exemplary embodiment, the shapes of the pixel openings of the four sub-pixels may be the same or different, and the areas of the pixel openings of the four sub-pixels may be the same or different.

[0224] In an exemplary embodiment, the shapes and areas of the pixel openings of the four sub-pixels may be different to accommodate the transmittance of different sub-pixel filters, so that the light-emitting devices of the four sub-pixels can emit the same brightness at different currents, thereby maximizing the lifespan of the four sub-pixel light-emitting devices and ensuring the product lifespan.

[0225] In an exemplary embodiment, at least one partition groove may be further provided on the pixel definition layer of each repeating unit in the display substrate. The partition groove M may be in the shape of a strip with a main portion extending along the first direction X or the second direction Y. The partition groove M may be provided between adjacent sub-pixels in the first direction X or the second direction Y. The partition groove M is configured to cut off a subsequently formed organic light-emitting layer, block the lateral propagation path of hole-type carriers, eliminate lateral leakage, and eliminate lateral crosstalk between sub-pixels.

[0226] In an exemplary embodiment, the pixel definition layer may be made of polyimide, acryl, polyethylene terephthalate, or the like.

[0227] (19) Forming an organic light-emitting layer and a cathode pattern. In an exemplary embodiment, forming the organic light-emitting layer and the cathode pattern may include: first forming an organic light-emitting layer pattern, wherein the organic light-emitting layer is connected to the first electrode 70 through the pixel opening K. Then forming a cathode, wherein the cathode is connected to the organic light-emitting layer.

[0228] In an exemplary embodiment, the organic light-emitting layer may include an emission layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the organic light-emitting layer may be formed using a fine metal mask (FMM) or open mask evaporation, or using an inkjet process.

[0229] (20) Forming a packaging structure layer pattern. In an exemplary embodiment, forming a packaging structure layer pattern may include: first using an open mask to deposit a first inorganic thin film to form a first packaging layer. Subsequently, using an inkjet printing process to inkjet print an organic material on the first packaging layer, and after curing into a film, forming a second packaging layer. Subsequently, using an open mask to deposit a second inorganic thin film to form a third packaging layer, the first packaging layer, the second packaging layer and the third packaging layer constitute a packaging structure layer. The first packaging layer and the third packaging layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon carbide (SiC), silicon carbonitride (SiCN) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer. The second packaging layer can be made of a resin material to form a laminated structure of inorganic material / organic material / inorganic material. The organic material layer is arranged between the two inorganic material layers to ensure that external water vapor cannot enter the light-emitting structure layer.

[0230] At this point, the preparation of the display substrate of the exemplary embodiment of the present disclosure is completed. The display substrate may include a driving circuit layer arranged on a substrate, a light-emitting structure layer arranged on the side of the driving circuit layer away from the substrate, and an encapsulation structure layer arranged on the side of the light-emitting structure layer away from the substrate. In a direction perpendicular to the substrate, the driving circuit layer may include a first conductive layer, a second conductive layer, a first insulating layer, a semiconductor layer, a second insulating layer, a third conductive layer, a third insulating layer, and a flat layer arranged in sequence on the substrate, the light-emitting structure layer may include an anode, a pixel definition layer, an organic light-emitting layer, and a cathode, and the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer.

[0231] In an exemplary embodiment, for a display substrate including a color filter structure layer, after forming the third conductive layer, a third insulating layer can be formed first, and then a red color filter layer, a green color filter layer and a blue color filter layer are formed in sequence, and then a flat layer is formed, which will not be repeated here.

[0232] In an exemplary embodiment, the substrate may be a flexible substrate or a rigid substrate. The rigid substrate may be, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The material of the semiconductor layer may be amorphous silicon (a-Si).

[0233] In an exemplary embodiment, the second conductive layer and the third conductive layer can be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or alloys of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single layer structure or a multilayer composite structure, such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, and the third insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be a single layer, a multilayer, or a composite layer. The planar layer can be made of an organic material, such as a resin.

[0234] At present, existing display devices have problems such as low aperture ratio and pixel light leakage. The inventors of this application have found that the above problems are caused by unreasonable signal line arrangement. In a repeating unit of an existing display device, one compensation signal line, two first power lines and four data signal lines are arranged as follows: the compensation signal line is arranged between the first pixel column and the second pixel column, two data signal lines are arranged on the side of the first pixel column away from the compensation signal line, one first power line is arranged on the side of the two data signal lines away from the compensation signal line, the other two data signal lines are arranged on the side of the second pixel column away from the compensation signal line, and another first power line is arranged on the side of the two data signal lines away from the compensation signal line, and the pixel driving circuit is arranged between the data signal line and the compensation signal line. Since only one compensation signal line is arranged between the first pixel column and the second pixel column, the distance between the first sub-pixel and the third sub-pixel in the first pixel column and the second sub-pixel and the fourth sub-pixel in the second pixel column is close, which not only easily loses the pixel opening, resulting in a reduced aperture ratio, but also increases the risk of pixel light leakage, resulting in pixel light leakage problems. In addition, for the first repeating unit and the second repeating unit adjacent to each other in the first direction, since five signal lines (two data signal lines for each pixel column and a first power line shared by the two pixel columns) are arranged between the second pixel column in the first repeating unit and the first pixel column in the second repeating unit, the distance between the second sub-pixel and the fourth sub-pixel in the second pixel column in the first repeating unit and the first sub-pixel and the third sub-pixel in the first pixel column in the second repeating unit is relatively far, which relatively wastes space.

[0235] The embodiment of the present disclosure provides a display substrate with a bottom emission structure, which can effectively increase the aperture ratio and reduce the risk of pixel light leakage by adjusting the arrangement of signal lines. The arrangement of one compensation signal line, two first power lines and four data signal lines in a repeating unit of the present disclosure is as follows: the compensation signal line is arranged in the middle of the first direction of the repeating unit (between the first pixel column and the second pixel column), the first first power line is arranged on the side of the first pixel column close to the compensation signal line, the second first power line is arranged on the side of the second pixel column close to the compensation signal line, two data signal lines are arranged on the side of the first pixel column away from the compensation signal line, and the other two data signal lines are arranged on the side of the second pixel column away from the compensation signal line, and the signal line arrangement order is changed to: the first data signal line, the second data signal line, the first first power line, the compensation signal line, the second first power line, the third data signal line and the fourth data signal line, and the pixel driving circuit of the first pixel column is arranged between the second data signal line and the first first power line, and the pixel driving circuit of the second pixel column is arranged between the second first power line and the third data signal line. The present disclosure effectively balances the distance distribution of the opaque metal signal lines between sub-pixels by arranging the first power line and the compensation signal line in the middle of the repeating unit and the data signal line on both sides of the repeating unit. Since a compensation signal line and two first power lines are arranged between the first pixel column and the second pixel column, the distance between the sub-pixels in the first pixel column and the sub-pixels in the second pixel column is increased, which not only avoids pixel opening loss and effectively increases the aperture ratio, but also reduces the risk of pixel light leakage and can effectively eliminate pixel light leakage. In addition, since four signal lines (two data signal lines for each pixel column) are arranged between the second pixel column in the first repeating unit and the first pixel column in the second repeating unit, the distance between the sub-pixels in the first repeating unit and the sub-pixels in the second repeating unit is reduced, which relatively saves space and is conducive to improving resolution.

[0236] In existing display devices, because the first power line in each pixel column is located on the side of the two data signal lines away from the compensation signal line, each pixel column requires a power connection line extending along the first direction X (transverse direction) to connect the first power line to the second transistor. The orthographic projection of the power connection line on the substrate overlaps with the orthographic projections of the two data signal lines on the substrate. In other words, in the existing structure, the power connection line overlaps all four data signal lines.

[0237] In the disclosed embodiment, by positioning the first power line on the side of the pixel column closest to the compensation signal line and the data signal line on the side of the pixel column farther from the compensation signal line, the orthographic projection of the power connection electrode, which serves as the lateral power connection line, on the substrate does not overlap with the orthographic projection of the data signal line on the substrate. In other words, the power connection electrode in the disclosed embodiment does not cross-line overlap with any four data signal lines, but only cross-line overlaps with one compensation signal line. By reducing cross-line structures, the disclosed embodiment effectively improves process accuracy and increases product yield.

[0238] The disclosed embodiment provides two power connection electrodes in a repeating unit, and the two power connection electrodes are respectively connected to two first power lines, thereby forming a ring structure within the repeating unit for transmitting the first power signal, which is beneficial for improving product yield. For example, when a short circuit occurs at the position where the power connection electrode crosses the compensation signal line, the short circuit can be repaired by cutting off one power connection electrode, thereby improving product yield. For another example, when a short circuit occurs at the position where the third active layer crosses the first power line, the short circuit can be repaired by cutting off one first power line, thereby improving product yield.

[0239] In the embodiment of the present disclosure, by arranging two first power lines on both sides of the compensation signal line, the first power lines with a constant potential can effectively shield the influence of the jump signal in the pixel driving circuit on the compensation signal line, thereby improving the accuracy of external compensation and improving the display effect and display quality.

[0240] The embodiment of the present disclosure arranges structures such as the first power line, the data signal line and the compensation signal line in the SHIELD layer, which is located on the side of the semiconductor layer close to the substrate, and arranges structures such as the scanning signal line and the gate electrodes of multiple transistors in the GT layer, which is located on the side of the semiconductor layer away from the substrate. This not only reduces one conductive layer, but also reduces the patterning process of the transfer via and the patterning process of the transfer conductive layer, so that the preparation process of the driving structure layer only requires six patterning processes, reducing the number of patterning processes, effectively improving production efficiency, effectively reducing production costs, and maximizing product yield.

[0241] The disclosed embodiment uses a 3T1C pixel driver circuit with one scan signal line, where the scan signal line is connected to the first transistor and the third transistor in the pixel driver circuit. By reducing the number of scan signal lines, the structure of the pixel driver circuit can be simplified, reducing the occupied area of ​​the pixel driver circuit, which is conducive to achieving high-resolution display. In addition, since a repeating unit only requires one scan signal line to drive, the number of corresponding gate driver circuits (GOA) and clock signal lines (CLK) can be reduced exponentially, effectively reducing the occupied area of ​​the gate driver circuit and clock signal lines, which is conducive to achieving a narrow frame and improving product advantages.

[0242] The present disclosure exemplifies a transparent storage capacitor composed of a transparent conductive layer and a transparent semiconductor layer, so that light can be emitted through the transparent storage capacitor. Therefore, the storage capacitor can be set in the pixel opening, which can not only effectively increase the capacitance of the storage capacitor, but also effectively increase the pixel aperture ratio.

[0243] The pixels of the embodiment of the present disclosure are arranged in a square manner. By adopting a first power line structure with a non-mesh structure, the pixel aperture ratio can be effectively increased, the display effect is improved, and it is more suitable for display type display.

[0244] The preparation process disclosed in the present invention is well compatible with existing preparation processes, is simple to implement, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0245] Figure 13 shows an equivalent circuit diagram of a pixel driver circuit in another repeating unit according to an exemplary embodiment of the present disclosure, and Figure 14 shows a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figures 13 and 14, the main structures of the pixel driver circuit and display substrate in this embodiment are substantially the same as those in Figures 3 and 4, with the difference being that one first power line 51 is provided per repeating unit in this embodiment.

[0246] In an exemplary embodiment, at least one repeating unit may include a scan signal line 30, a first power line 51, four data signal lines 52, and a compensation signal line 53. The shapes, positions, and connections between the scan signal line 30, the data signal line 52, and the compensation signal line 53 and the pixel driving circuit may be substantially the same as those in the aforementioned embodiment. The pixel driving circuit of at least one sub-pixel may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor 60. The storage capacitor 60 may include at least a first plate 61 and a second plate 62 as capacitor plates. The related connection structure is substantially the same as in the aforementioned embodiment and will not be further described here.

[0247] In one exemplary embodiment, the first power line 51 may be disposed on one side of the compensation signal line 53 in the first direction X, that is, the first power line 51 is disposed on a side of the second pixel column close to the compensation signal line 53. In another exemplary embodiment, the first power line 51 may be disposed on a side opposite to the first direction X of the compensation signal line 53, that is, the first power line 51 is disposed on a side of the first pixel column close to the compensation signal line 53.

[0248] In an exemplary embodiment, the power connection electrode 18 may be in the shape of a strip extending along the first direction X, the power connection electrodes 18 in the first sub-pixel P1 and the second sub-pixel P2 may be an integrated structure connected to each other, and the power connection electrodes 18 in the third sub-pixel P3 and the fourth sub-pixel P4 may be an integrated structure connected to each other.

[0249] In the exemplary embodiment, the first power line 51 is provided in the second pixel column as an example. The first end of the power connection electrode 18 is connected to the first region of the second active layer 22 in the first pixel column through the second via hole V2 in the first pixel column. The second end of the power connection electrode 18 extends along the first direction X to the second pixel column and is then connected to both the first region of the second active layer 22 in the second pixel column and the first power line 51 through the second via hole V2 in the second pixel column. This enables the first power line 51 to write the first power signal to the first electrodes of the four second transistors T2 in the two pixel columns.

[0250] In an exemplary embodiment, a single first power line 51 can simultaneously provide a first power signal to the pixel driving circuits of four sub-pixels, thus forming a one-to-four structure within a repeating unit. By designing the first power line as a one-to-four structure, the display substrate of the present disclosure reduces the number of signal lines and space requirements, resulting in a simple structure and a rational layout, fully utilizing the layout space, improving space utilization, and facilitating higher resolution.

[0251] In an exemplary embodiment, the power connection electrode 18 can serve as a horizontal power connection line, and the orthographic projection of the power connection electrode 18 on the substrate does not overlap with the orthographic projection of the data signal line 52 on the substrate, and the orthographic projection of the power connection electrode 18 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 53 on the substrate.

[0252] In an exemplary embodiment, for two adjacent sub-pixels in a repeating unit along a first direction X, the sub-pixel without the first power line 51 is referred to as a "no-power-line sub-pixel," and the sub-pixel with the first power line 51 is referred to as a "power-line sub-pixel." The first distance between the storage capacitor and the compensation signal line in the "no-power-line" sub-pixel may be greater than or equal to the second distance between the storage capacitor and the first power line in the "power-line" sub-pixel. In an exemplary embodiment, the distance between the storage capacitor and the compensation signal line may be the maximum distance between at least one capacitor plate in the storage capacitor and the compensation signal line, and the distance between the storage capacitor and the first power line may be the maximum distance between at least one capacitor plate in the storage capacitor and the first power line.

[0253] For example, let's take the example of a first power line 51 being arranged in the second pixel column. In the first pixel column, a first distance L1 exists between the right edge of the first electrode 61 on the side closest to the compensation signal line 53 and the left edge of the compensation signal line 53 on the side closest to the first electrode 61. In the second pixel column, a second distance L2 exists between the left edge of the first electrode 61 on the side closest to the first power line 51 and the right edge of the first power line 51 on the side closest to the first electrode 61. For another example, let's take the example of a first power line 51 being arranged in the first pixel column. In the first pixel column, a second distance L2 exists between the right edge of the second electrode 62 on the side closest to the first power line 51 and the left edge of the first power line 51 on the side closest to the second electrode 62. In the second pixel column, a first distance L1 exists between the left edge of the second electrode 62 on the side closest to the compensation signal line 53 and the right edge of the compensation signal line 53 on the side closest to the second electrode 62. The first distance L1 can be greater than or equal to the second distance L2. The first distance L1 and the second distance L2 can be dimensions in the first direction X.

[0254] In an exemplary embodiment, the first distance L1 and the second distance L2 may both be greater than a minimum distance between an edge of the compensation signal line 53 close to the first power line 51 and an edge of the first power line 51 close to the compensation signal line 53 .

[0255] In an exemplary embodiment, the first distance L1 may be greater than or equal to 3 micrometers.

[0256] By setting a distance between the storage capacitor and the compensation signal line, the present disclosure can effectively reduce the impact of a jump signal in the pixel drive circuit on the compensation signal line, thereby ensuring the accuracy of external compensation. Because a first power line is provided between the pixel drive circuit and the compensation signal line in a sub-pixel with a power line, the first power line, with a constant potential, can effectively shield the impact of the jump signal in the pixel drive circuit on the compensation signal line. Therefore, while ensuring the accuracy of external compensation, the distance between the storage capacitor and the compensation signal line can be maintained or appropriately reduced.

[0257] The display substrate provided by the embodiment of the present disclosure also has the technical effects of the aforementioned embodiment, namely, it can effectively increase the aperture ratio, reduce the risk of pixel light leakage, effectively improve process accuracy, effectively improve product yield, etc. In addition, by reducing one first power line, the embodiment of the present disclosure can effectively improve space utilization, which is conducive to improving resolution. By setting the distance between the storage capacitor and the compensation signal line in different sub-pixels, the embodiment of the present disclosure can effectively reduce the impact of the jump signal in the pixel drive circuit on the compensation signal line, thereby ensuring the accuracy of external compensation and ensuring the display effect and display quality.

[0258] Figure 15 shows an equivalent circuit diagram of a pixel driver circuit in another repeating unit according to an exemplary embodiment of the present disclosure, and Figure 16 shows a schematic diagram of the structure of a display substrate according to another exemplary embodiment of the present disclosure. As shown in Figures 15 and 16, the main structures of the pixel driver circuit and display substrate in this embodiment are substantially the same as those in Figures 3 and 4, with the difference being that one first power line 51 and two compensation signal lines 53 are provided per repeating unit in this embodiment.

[0259] In an exemplary embodiment, at least one repeating unit may include a scan signal line 30, a first power line 51, four data signal lines 52, and two compensation signal lines 53. The shapes, positions, and connections between the scan signal line 30 and the data signal line 52 and the pixel driving circuit may be substantially the same as those in the embodiments shown in Figures 3 and 4. The pixel driving circuit of at least one sub-pixel may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor 60. The storage capacitor 60 may include at least a first plate and a second plate serving as capacitor plates. The related connection structure is substantially the same as in the previous embodiment and will not be further described here.

[0260] In an exemplary embodiment, a first power line 51 may be located in the middle of the repeating unit in the first direction X. The first power line 51 may define two pixel columns: a first pixel column and a second pixel column. The two compensation signal lines 53 may include a first compensation signal line 53-1 and a second compensation signal line 53-2 sequentially arranged along the first direction X.

[0261] In an exemplary embodiment, the first compensation signal line 53-1 may be disposed on a side of the first power line 51 close to the first data signal line group, and the storage capacitor of the first pixel column may be disposed between the second data signal line 52-2 and the first compensation signal line 53-1. The second compensation signal line 53-2 may be disposed on a side of the first power line 51 close to the second data signal line group, and the storage capacitor of the second pixel column may be disposed between the second compensation signal line 53-2 and the third data signal line 52-3.

[0262] In an exemplary embodiment, at least one repeating unit further includes two compensation connection electrodes 19. The two compensation connection electrodes 19 may be located in the middle region of the repeating unit in the second direction Y. Each compensation connection electrode 19 may be in the shape of a strip extending along the first direction X and spanning the first pixel column and the second pixel column. The first end of each compensation connection electrode 19 is connected to the first compensation signal line 53-1 and the first electrode of the third transistor T3 in the first pixel column, and the second end of each compensation connection electrode 19 is connected to the second compensation signal line 53-2 and the first electrode of the third transistor T3 in the second pixel column. In this way, the two compensation signal lines 53 and the two compensation connection electrodes 19 within the repeating unit form a ring structure for transmitting compensation signals.

[0263] In an exemplary embodiment, the orthographic projection of the compensation connection electrode 19 on the display substrate plane does not overlap with the orthographic projection of the data signal line 52 on the display substrate plane.

[0264] In an exemplary embodiment, an orthographic projection of the compensation connection electrode 19 on the display substrate plane at least partially overlaps with an orthographic projection of the first power line 51 on the display substrate plane.

[0265] In an exemplary embodiment, taking four sub-pixels of a repeating unit as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0266] (21) Forming a First Conductive Layer Pattern In the exemplary embodiment, the process of forming the first conductive layer and the structure of the first conductive layer are substantially the same as those in the aforementioned embodiment.

[0267] (22) Forming a second conductive layer pattern. In the exemplary embodiment, the process of forming the second conductive layer and the structure of the second conductive layer are substantially the same as those in the aforementioned embodiment, except that each repeating unit in this embodiment includes a first power supply line 51 and two compensation signal lines 53, as shown in FIG17A and FIG17B . FIG17B is a schematic diagram of the second conductive layer in FIG17A .

[0268] In an exemplary embodiment, the shapes and positions of the third connection electrode 13 , the fourth connection electrode 14 and the four data signal lines 52 in the second conductive layer of this embodiment are substantially the same as those of the previous embodiment.

[0269] In an exemplary embodiment, the shapes of the first power line 51, the data signal line 52 and the compensation signal line 53 can be straight lines or broken lines with the main portion extending along the second direction Y. The first power line 51 can be located in the middle of the repeating unit in the first direction X, the two compensation signal lines 53 can be located on both sides of the first power line 51 in the first direction X, two of the four data signal lines 52 can be located on one side of the repeating unit in the opposite direction of the first direction X, and the other two of the four data signal lines 52 can be located on one side of the repeating unit in the first direction X.

[0270] In an exemplary embodiment, the two compensation signal lines 53 may include a first compensation signal line 53 - 1 and a second compensation signal line 53 - 2 sequentially disposed along the first direction X.

[0271] In an exemplary embodiment, the first data signal line 52-1 and the first power line 51 can define a first pixel column, the second data signal line 52-2 and the first compensation signal line 53-1 are arranged in the first pixel column, the second data signal line 52-2 can be arranged on a side of the first data signal line 52-1 close to the first power line 51, the first compensation signal line 53-1 can be arranged on a side of the first power line 51 close to the first data signal line 52-1, and the first electrode 61, the third connecting electrode 13 and the fourth connecting electrode 14 of the first pixel column can be arranged between the second data signal line 52-2 and the first compensation signal line 53-1.

[0272] In an exemplary embodiment, the fourth data signal line 52-4 and the first power line 51 can define a second pixel column, the second compensation signal line 53-2 and the third data signal line 52-3 are arranged in the second pixel column, the second compensation signal line 53-2 can be arranged on the side of the first power line 51 close to the fourth data signal line 52-4, the third data signal line 52-3 can be arranged on the side of the fourth data signal line 52-4 close to the first power line 51, and the first electrode 61, the third connection electrode 13 and the fourth connection electrode 14 of the second pixel column can be arranged between the second compensation signal line 53-2 and the third data signal line 52-3.

[0273] In an exemplary embodiment, a power connection block 54 may be connected to the first power line 51 . The power connection block 54 may be in a block shape and configured to be connected to the first region of the second active layer through a subsequently formed power connection electrode.

[0274] In an exemplary embodiment, the orthographic projection of the first power line 51 on the substrate at least partially overlaps with the orthographic projection of the vertical reference line on the substrate, the positions of the two compensation signal lines 53 can be substantially mirror-symmetrical with respect to the vertical reference line, and the positions of the two data signal lines 52 located on the opposite side of the first direction X of the first power line 51 and the positions of the two data signal lines 52 located on the side of the first direction X of the first power line 51 can be substantially mirror-symmetrical with respect to the vertical reference line.

[0275] (23) Forming a semiconductor layer pattern. In the exemplary embodiment, the process of forming the semiconductor layer and the structure of the semiconductor layer are substantially the same as those in the aforementioned embodiment, except that the third active layer 23 of each sub-pixel in this embodiment is separately provided, as shown in FIG18A and FIG18B . FIG18B is a schematic diagram of the semiconductor layer in FIG18A .

[0276] In the exemplary embodiment, the shapes and positions of the first active layer 21 , the second active layer 22 and the second plate 62 of the storage capacitor in the semiconductor layer of this embodiment are substantially the same as those of the previous embodiment.

[0277] In an exemplary embodiment, the shape of the third active layer 23 of each sub-pixel can be a strip shape extending along the first direction X, and the orthographic projection of one end of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the fourth connection electrode 14 of the sub-pixel on the substrate, and the orthographic projection of the other end of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 53 on the substrate.

[0278] In an exemplary embodiment, the third active layers 23 in the first subpixel P1 and the second subpixel P2 are not connected, the third active layers 23 in the third subpixel P3 and the fourth subpixel P4 are not connected, and the orthographic projection of the third active layer 23 on the substrate does not overlap with the orthographic projection of the first power line 51 on the substrate.

[0279] (24) Forming a second insulating layer pattern. In the exemplary embodiment, the process of forming the second insulating layer pattern and the structure of the plurality of via holes are substantially the same as those in the previous embodiment, except that the present embodiment further includes a seventh via hole V7, as shown in FIG. 19 .

[0280] In an exemplary embodiment, the positions and functions of the first via hole V1 , the third via hole V3 , the fourth via hole V4 , the fifth via hole V5 , and the sixth via hole V6 are substantially the same as those in the previous embodiment.

[0281] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the first area of ​​the second active layer 22 on the substrate, the second insulating layer in the second via hole V2 is etched away to expose the surface of the first area of ​​the second active layer 22, and the second via hole V2 is configured to connect a subsequently formed power connection electrode to the first area of ​​the second active layer 22 through the via hole.

[0282] In an exemplary embodiment, each sub-pixel further includes a seventh via hole V7. The orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the power connection block 54 of the first power line 51 on the substrate. The first insulating layer and the second insulating layer within the seventh via hole V7 are etched away, exposing the surface of the power connection block 54. The seventh via hole V7 is configured to connect a subsequently formed power connection electrode to the power connection block 54 through the via hole.

[0283] In an exemplary embodiment, different from the aforementioned embodiment, each subpixel is provided with a fourth via hole V4, that is, the first subpixel P1 and the second subpixel P2 do not share the fourth via hole V4, and the third subpixel P3 and the fourth subpixel P4 do not share the fourth via hole V4.

[0284] (25) Forming a third conductive layer pattern. In the exemplary embodiment, the process of forming the third conductive layer and the structure of the third conductive layer are substantially the same as those in the aforementioned embodiment, except that the connection structure of the power connection electrode 18 and the compensation connection electrode 19 in this embodiment is different, as shown in Figures 20A and 20B. Figure 20B is a schematic diagram of the third conductive layer in Figure 20A.

[0285] In an exemplary embodiment, the shapes and positions of the fifth connecting electrode 15, the sixth connecting electrode 16, the data connecting electrode 17, the scan signal line 30, the first gate electrode 31, the second gate electrode 32 and the third gate electrode 33 in the third conductive layer of this embodiment are substantially the same as those of the previous embodiment.

[0286] In an exemplary embodiment, the power connection electrode 18 may be in the shape of a strip extending along the first direction X. It may be disposed on a side of the second electrode plate 62 away from the scan signal line 30 and span the first pixel column and the second pixel column. The first end of the power connection electrode 18 is connected to the first region of the second active layer 22 in the first pixel column via a second via hole V2 in the first pixel column. The second end of the power connection electrode 18 is connected to the first region of the second active layer 22 in the second pixel column via a second via hole V2 in the second pixel column. The middle region between the first and second ends of the power connection electrode 18 is connected to the power connection block 54 via a seventh via hole V7. Since the power connection block 54 is connected to the first power line 51, the first power line 51 writes the first power signal to the first electrode of the second transistor T2.

[0287] In an exemplary embodiment, the first power line 51 can simultaneously provide a first power signal to four pixel driving circuits in the first and second pixel columns, thus forming a one-to-four structure within a repeating unit. By designing the first power line as a one-to-four structure, the display substrate of the present disclosure reduces the number of signal lines and space requirements, resulting in a simple structure and a rational layout, fully utilizing the layout space, improving space utilization, and facilitating higher resolution.

[0288] In an exemplary embodiment, the power connection electrode 18 can serve as a horizontal power connection line, and the orthographic projection of the power connection electrode 18 on the substrate does not overlap with the orthographic projection of the data signal line 52 on the substrate, and the orthographic projection of the power connection electrode 18 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 53 on the substrate.

[0289] In an exemplary embodiment, the shape of the compensation connection electrode 19 can be a strip shape extending along the first direction X, and can be arranged across the first pixel column and the second pixel column. The first end of the compensation connection electrode 19 is simultaneously connected to the first area of ​​the third active layer 23 and the compensation signal line 53 in the first pixel column through the fourth via hole V4 in the first pixel column, and the second end of the compensation connection electrode 19 is simultaneously connected to the first area of ​​the third active layer 23 and the compensation signal line 53 in the second pixel column through the fourth via hole V4 in the second pixel column, thereby realizing that the compensation signal line 53 writes the compensation signal into the first electrode of the third transistor T3.

[0290] In an exemplary embodiment, the two compensation signal lines 53 may include a first compensation signal line 53-1 and a second compensation signal line 53-2 sequentially arranged along the first direction X. The first compensation signal line 53-1 may be located in a first pixel column on a side opposite to the first direction X of the first power line 51, and may be connected to the first region of the third active layer 23 in the first subpixel P1 and the third subpixel P3, respectively, via the compensation connection electrode 19. The second compensation signal line 53-2 may be located in a second pixel column on a side of the first direction X of the first power line 51, and may be connected to the first region of the third active layer 23 in the second subpixel P2 and the fourth subpixel P4, respectively, via the compensation connection electrode 19.

[0291] In an exemplary embodiment, although the third active layers in the first and second subpixels P1 and P2 are unconnected, and the third active layers in the third and fourth subpixels P3 and P4 are unconnected, the present disclosure provides a compensation connection electrode 19 spanning the first and second pixel columns. The compensation connection electrode 19 can function as a transverse compensation connection line, enabling the first and second subpixels P1 and P2 to share a single compensation connection electrode 19, and the third and fourth subpixels P3 and P4 to share a single compensation connection electrode 19. Two compensation signal lines 53 can simultaneously provide compensation signals to the pixel drive circuits in the four subpixels. Consequently, the four pixel drive circuits in a repeating unit can share two compensation signal lines 53, forming a one-to-two compensation signal line structure within the repeating unit. By designing the compensation signal lines as a one-to-two structure, the display substrate of the present disclosure reduces the number of signal lines and the space occupied. This results in a simple structure, a rational layout, and full utilization of the layout space, improving space utilization and facilitating improved resolution.

[0292] In an exemplary embodiment, the present disclosure provides a compensation connection electrode 19 spanning the first and second pixel columns, forming a ring-shaped structure in the region where the compensation signal line 53 connects to the third transistor T3 in a repeating unit, thereby facilitating improved product yield. For example, if a short circuit occurs where the power connection electrode 18, acting as a lateral power connection line, crosses the compensation signal line 53, the short circuit can be repaired by severing one compensation signal line 53, thereby improving product yield. For another example, if a short circuit occurs where the compensation connection electrode 19 crosses the first power line 51, the short circuit can be repaired by severing one compensation connection electrode 19, thereby improving product yield.

[0293] In an exemplary embodiment, the orthographic projection of the compensation connection electrode 19 on the substrate does not overlap with the orthographic projection of the data signal line 52 on the substrate, and the orthographic projection of the compensation connection electrode 19 on the substrate at least partially overlaps with the orthographic projection of the first power line 51 on the substrate.

[0294] In an exemplary embodiment, since the positions of the two compensation signal lines 53 are substantially mirror-symmetrical with respect to the vertical reference line, the third transistors T3 of the first pixel column and the third transistors T3 of the second pixel column are substantially mirror-symmetrical with respect to the vertical reference line. This symmetrical structure of the present disclosure can ensure that the RC delay of the compensation signal written into the third transistors T3 is substantially the same, thereby ensuring display uniformity.

[0295] (26) The subsequent process of forming the third insulating layer, the planar layer, the fourth conductive layer, the pixel definition layer, the organic light-emitting layer, the cathode and the encapsulation structure layer is basically the same as that of the aforementioned embodiment and will not be repeated here.

[0296] In the display substrate provided by the disclosed embodiment, the first power line and compensation signal line are arranged in the middle of the repeating unit, and the data signal lines are arranged on both sides of the repeating unit, effectively balancing the distance distribution of the opaque metal signal lines between sub-pixels. Thus, the display substrate also has the technical effects of the aforementioned embodiments, namely, effectively increasing the aperture ratio, reducing the risk of pixel light leakage, effectively improving process accuracy, and effectively increasing product yield. Furthermore, by providing a separate third active layer for each sub-pixel, the orthographic projection of the third active layer on the substrate does not overlap with the orthographic projection of the first power line on the substrate. This effectively reduces the extended length of the semiconductor traces, effectively avoids the impact of conductor process differences on external compensation, ensures the accuracy of external compensation, and guarantees the display effect and quality. Furthermore, by providing a compensation connection electrode spanning the first pixel column and the second pixel column, the disclosed embodiment forms a ring structure in the area where the compensation signal line connects to the third transistor, facilitating short circuit repair and improving product yield.

[0297] Figure 21 shows an equivalent circuit diagram of a pixel driver circuit in another repeating unit of an exemplary embodiment of the present disclosure, and Figure 22 shows a schematic diagram of the structure of a display substrate in another exemplary embodiment of the present disclosure. As shown in Figures 21 and 22, the main structure of the pixel driver circuit and display substrate of this embodiment is substantially the same as that of the embodiment shown in Figures 15 and 16, with the difference being that one compensation signal line 53 is provided per repeating unit in this embodiment.

[0298] In an exemplary embodiment, at least one repeating unit may include a scan signal line 30, a first power line 51, four data signal lines 52, and a compensation signal line 53. The shapes, positions, and connections between the scan signal line 30, the data signal line 52, and the first power line 51 and the pixel driving circuit may be substantially the same as those in the embodiments shown in Figures 15 and 16. The pixel driving circuit of at least one sub-pixel may include a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor 60. The storage capacitor 60 may include at least a first plate 61 and a second plate 62 as capacitor plates. The related connection structure is substantially the same as in the previous embodiment and will not be further described here.

[0299] In one exemplary embodiment, the compensation signal line 53 may be disposed on one side of the first power line 51 in the first direction X, that is, the compensation signal line 53 is disposed on a side of the second pixel column close to the first power line 51. In another exemplary embodiment, the compensation signal line 53 may be disposed on a side of the first power line 51 in the opposite direction of the first direction X, that is, the compensation signal line 53 is disposed on a side of the first pixel column close to the first power line 51.

[0300] In the exemplary embodiment, the shape and position of the compensation connection electrode 19 are substantially the same as those of the embodiment shown in FIG15 and FIG16 , except that the first end of the compensation connection electrode 19 is connected to the first area of ​​the third active layer 23 in one pixel column and the compensation signal line 53 at the same time through the fourth via hole V4 in the pixel column, and the second end of the compensation connection electrode 19 is connected to the first area of ​​the third active layer 23 in another pixel column through the fourth via hole V4 in the pixel column, thereby realizing that one compensation signal line 53 writes the compensation signal into the first electrodes of the four third transistors T3 in the two pixel columns, forming a one-to-four compensation signal line structure, saving the number of signal lines, reducing the occupied space, having a simple structure and a reasonable layout, making full use of the layout space, improving space utilization, and facilitating improved resolution.

[0301] In an exemplary embodiment, the compensation connection electrode 19 can serve as a horizontal compensation connection line, and the orthographic projection of the compensation connection electrode 19 on the substrate does not overlap with the orthographic projection of the data signal line 52 on the substrate, and the orthographic projection of the compensation connection electrode 19 on the substrate at least partially overlaps with the orthographic projection of the first power line 51 on the substrate.

[0302] In one exemplary embodiment, the compensation signal line 53 is provided in the second pixel column as an example. In the first pixel column, a third distance L3 is defined between the right edge of the first electrode 61 on the side closest to the first power line 51 and the left edge of the first power line 51 on the side closest to the first electrode 61. In the second pixel column, a fourth distance L4 is defined between the left edge of the first electrode 61 on the side closest to the compensation signal line 53 and the right edge of the compensation signal line 53 on the side closest to the first electrode 61. In another exemplary embodiment, the compensation signal line 53 is provided in the first pixel column as an example. In the first pixel column, a fourth distance L4 is defined between the right edge of the second electrode 62 on the side closest to the compensation signal line 53 and the left edge of the compensation signal line 53 on the side closest to the second electrode 62. In the second pixel column, a third distance L3 is defined between the left edge of the second electrode 62 on the side closest to the first power line 51 and the right edge of the first power line 51 on the side closest to the second electrode 62. The third distance L3 and the fourth distance L4 can both be greater than the minimum distance between the edge of the first power line 51 close to the compensation signal line 53 and the edge of the compensation signal line 53 close to the first power line 51, and the third distance L3 and the fourth distance L4 can be the dimensions in the first direction X.

[0303] In an exemplary embodiment, the fourth distance L4 may be greater than or equal to 3 micrometers.

[0304] The present disclosure can effectively improve space utilization while ensuring external compensation accuracy by setting the distance between the storage capacitor and the first power line in the sub-pixel without compensation line, which is conducive to improving resolution.

[0305] The display substrate provided by the disclosed embodiment also has the technical effects of the aforementioned embodiments, namely, it can effectively increase the aperture ratio, reduce the risk of pixel light leakage, effectively improve process accuracy, and effectively improve product yield. In addition, by reducing one compensation signal line, the disclosed embodiment can effectively improve space utilization, which is conducive to improving resolution. By setting the distance between the storage capacitor and the first power line in different sub-pixels, the disclosed embodiment further improves space utilization and further improves resolution while ensuring the accuracy of external compensation.

[0306] Figure 23 is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure. As shown in Figure 23, the main structure of the pixel driving circuit and display substrate of this embodiment is substantially the same as that of the embodiment shown in Figure 22, except that the first active layer in the first and fourth sub-pixels of this embodiment does not overlap with the data signal line.

[0307] In an exemplary embodiment, at least one repeating unit may include one scan signal line 30 , one first power line 51 , four data signal lines 52 and one compensation signal line 53 , and the compensation signal line 53 may be disposed on one side of the first power line 51 in the first direction X.

[0308] In an exemplary embodiment, the shape and connection structure of the data connection electrode 17 in the second subpixel P2 and the third subpixel P3 are substantially the same as those in the aforementioned embodiment. The data connection electrode 17 in the first subpixel P1 and the fourth subpixel P4 may be in an "L" shape, with a first end of the data connection electrode 17 connected to both the first region of the first active layer and the data jumper electrode through a via hole, and a second end of the data connection electrode 17 connected to the data signal line through a via hole, with the orthographic projection of the data connection electrode 17 on the substrate at least partially overlapping with the orthographic projection of the data signal line 52 on the substrate.

[0309] In an exemplary embodiment, an orthographic projection of the first active layer in the first subpixel P1 and the fourth subpixel P4 on the substrate does not overlap with an orthographic projection of the data signal line 52 on the substrate.

[0310] In an exemplary embodiment, taking four sub-pixels of a repeating unit as an example, the preparation process of the display substrate of this embodiment may include the following operations.

[0311] (31) Forming a First Conductive Layer Pattern In the exemplary embodiment, the process of forming the first conductive layer and the structure of the first conductive layer are substantially the same as those in the previous embodiment, as shown in FIG.

[0312] (32) Forming a second conductive layer pattern. In the exemplary embodiment, the process of forming the second conductive layer and the structure of the second conductive layer are substantially the same as those in the aforementioned embodiment, except that the second conductive layer of this embodiment further includes a data jumper electrode 41 and a compensation jumper electrode 42, as shown in Figures 25A and 25B. Figure 25B is a schematic diagram of the second conductive layer in Figure 25A.

[0313] In an exemplary embodiment, the shapes and positions of the third connection electrode 13 , the fourth connection electrode 14 and the four data signal lines 52 in the second conductive layer of this embodiment are substantially the same as those of the previous embodiment.

[0314] In an exemplary embodiment, the shapes of the first power line 51, the data signal line 52 and the compensation signal line 53 can be straight lines or broken lines with the main part extending along the second direction Y. The first power line 51 can be located in the middle of the repeating unit in the first direction X, and the compensation signal line 53 can be located on one side of the first power line 51 in the first direction X.

[0315] In an exemplary embodiment, the data jumper electrode 41 can be block-shaped (rectangular) and can be arranged between the fourth connection electrode 14 and the data signal line 52 in the first sub-pixel P1 and the fourth sub-pixel P4. The data jumper electrode 41 is configured to be connected to the data signal line through a subsequently formed data connection electrode.

[0316] In an exemplary embodiment, the compensation jumper electrode 42 can be block-shaped (rectangular) and can be arranged between the fourth connection electrode 14 and the first power line 51 in the first pixel column. The compensation jumper electrode 42 is configured to be connected to the compensation signal line through a subsequently formed compensation connection electrode.

[0317] In an exemplary embodiment, the first electrode 61, the third connection electrode 13, the fourth connection electrode 14, the data jumper electrode 41 and the compensation jumper electrode 42 of the first pixel column can be arranged between the second data signal line 52-2 and the first power line 51, and the first electrode 61, the third connection electrode 13, the fourth connection electrode 14 and the data jumper electrode 41 of the second pixel column can be arranged between the compensation signal line 53 and the third data signal line 52-3.

[0318] (33) Forming a semiconductor layer pattern. In the exemplary embodiment, the process of forming a semiconductor layer and the structure of the semiconductor layer are substantially the same as those in the aforementioned embodiment, except that the first active layer 21 of the first sub-pixel P1 and the fourth sub-pixel P4 does not overlap with the data signal line 51, as shown in FIG26A and FIG26B . FIG26B is a schematic diagram of the semiconductor layer in FIG26A .

[0319] In the exemplary embodiment, the shapes and positions of the second active layer 22 and the second plate 62 of the storage capacitor in the semiconductor layer of this embodiment are substantially the same as those of the previous embodiment.

[0320] In an exemplary embodiment, the first active layer 21 of each subpixel may be shaped like a strip extending along the first direction X. In the first subpixel P1 and the fourth subpixel P4, the orthographic projection of the first region of the first active layer 21 on the substrate at least partially overlaps with the orthographic projection of the data jumper electrode 41 on the substrate, the second region of the first active layer 21 is connected to the second electrode plate 62, and the orthographic projection of the first active layer 21 on the substrate does not overlap with the orthographic projection of the data signal line 52 on the substrate. In the second subpixel P2 and the third subpixel P3, the orthographic projection of the first region of the first active layer 21 on the substrate at least partially overlaps with the orthographic projection of the corresponding data signal line 52 on the substrate, and the second region of the first active layer 21 is connected to the second electrode plate 62.

[0321] In an exemplary embodiment, the third active layer 23 of each subpixel may be shaped like a strip extending along the first direction X. In the first subpixel P1 and the third subpixel P3, the orthographic projection of one end of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the fourth connection electrode 14 of the subpixel, and the orthographic projection of the other end of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the compensation jumper electrode 42 on the substrate. In the second subpixel P2 and the fourth subpixel P4, the orthographic projection of one end of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the fourth connection electrode 14 of the subpixel, and the orthographic projection of the other end of the third active layer 23 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 53 on the substrate.

[0322] In an exemplary embodiment, an orthographic projection of the third active layer 23 of each sub-pixel on the substrate does not overlap with an orthographic projection of the first power line 51 on the substrate.

[0323] (34) Forming a second insulating layer pattern. In the exemplary embodiment, the process of forming the second insulating layer pattern and the structure of the plurality of via holes are substantially the same as those in the aforementioned embodiment, except that this embodiment further includes an eighth via hole V8, as shown in FIG. 27 .

[0324] In the exemplary embodiment, the positions and functions of the third via hole V3 , the fifth via hole V5 , and the sixth via hole V6 are substantially the same as those in the previous embodiment.

[0325] In an exemplary embodiment, in the first subpixel P1 and the fourth subpixel P4, the orthographic projection of the first via hole V1 on the substrate at least partially overlaps with the orthographic projection of the first region of the first active layer 21 on the substrate. The orthographic projection of the first via hole V1 on the substrate at least partially overlaps with the orthographic projection of the data crossover electrode 41 on the substrate. The first via hole V1 is a via hole with a transition structure, comprising two half holes. The second insulating layer in the shallow half hole is etched away, exposing the surface of the first region of the first active layer 21, while the first and second insulating layers in the deep half hole are etched away, exposing the surface of the data crossover electrode 41. As a result, the first via hole V1 of the transition structure, consisting of the two half holes, simultaneously exposes the first region of the first active layer 21 and the data crossover electrode 41. In the second subpixel P2 and the third subpixel P3, the orthographic projection of the first via hole V1 on the substrate is located within the range of the first region of the first active layer 21 and the orthographic projection of the data signal line 52 on the substrate. The first via hole V1 is a via hole with a transition structure, and the connection structure is substantially the same as in the previous embodiment.

[0326] In an exemplary embodiment, the orthographic projection of the second via hole V2 of each sub-pixel on the substrate is located within the range of the orthographic projection of the first region of the second active layer 22 on the substrate, and the second insulating layer in the second via hole V2 is etched away to expose the surface of the first region of the second active layer 22.

[0327] In an exemplary embodiment, in the first and third subpixels P1 and P3, the orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the first region of the third active layer 23 on the substrate. The orthographic projection of the fourth via hole V4 on the substrate at least partially overlaps with the orthographic projection of the compensation bridge electrode 42 on the substrate. The fourth via hole V4 is a via hole with a transition structure, comprising two half holes. The second insulating layer in the shallow half hole is etched away, exposing the surface of the first region of the third active layer 23. The first and second insulating layers in the deep half hole are etched away, exposing the surface of the compensation bridge electrode 42. This transition structure of the fourth via hole V4, formed by the two half holes, simultaneously exposes the first region of the third active layer 23 and the compensation bridge electrode 42. In the second and fourth subpixels P2 and P4, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the first region of the third active layer 23 and the orthographic projection of the compensation signal line 53 on the substrate. The fourth via hole V4 is a via hole with a transition structure, and its connection structure is substantially the same as that of the previous embodiment.

[0328] In an exemplary embodiment, each sub-pixel further includes a seventh via hole V7. The orthographic projection of the seventh via hole V7 on the substrate is located within the orthographic projection of the first power line 51 on the substrate. The first and second insulating layers within the seventh via hole V7 are etched away, exposing the surface of the first power line 51.

[0329] In an exemplary embodiment, the first subpixel P1 and the fourth subpixel P4 further include an eighth via hole V8. The orthographic projection of the eighth via hole V8 on the substrate is located within the range of the orthographic projection of the data signal line 52 on the substrate. The first insulating layer and the second insulating layer within the eighth via hole V8 are etched away, exposing the surface of the data signal line 52.

[0330] (35) Forming a third conductive layer pattern. In the exemplary embodiment, the process of forming the third conductive layer and the structure of the third conductive layer are substantially the same as those in the aforementioned embodiment, except that the connection structure of the power connection electrode 18 and the compensation connection electrode 19 in this embodiment is different, as shown in Figures 28A and 28B. Figure 28B is a schematic diagram of the third conductive layer in Figure 28A.

[0331] In an exemplary embodiment, the shapes and positions of the fifth connection electrode 15 , the sixth connection electrode 16 , the scan signal line 30 , the first gate electrode 31 , the second gate electrode 32 and the third gate electrode 33 in the third conductive layer of this embodiment are substantially the same as those of the previous embodiment.

[0332] In an exemplary embodiment, the data connection electrode 17 in the first subpixel P1 and the fourth subpixel P4 may be in an "L" shape, with a first end of the data connection electrode 17 connected to both the first region of the first active layer 21 and the data jumper electrode 41 via a first via hole V1, and a second end of the data connection electrode 17 connected to the data signal line 52 via an eighth via hole V8. The data connection electrode 17 in the second subpixel P2 and the third subpixel P3 may be in a block shape, with the data connection electrode 17 connected to both the first region of the first active layer 21 and the data signal line 52 via a first via hole V1, and the connection structure is substantially the same as in the previous embodiment.

[0333] In an exemplary embodiment, the data link electrode 17 in the first subpixel P1 is connected to the first data signal line 52-1, and the orthographic projection of the data link electrode 17 on the substrate at least partially overlaps with the orthographic projection of the second data signal line 52-2 on the substrate. The data link electrode 17 in the fourth subpixel P4 is connected to the fourth data signal line 52-4, and the orthographic projection of the data link electrode 17 on the substrate at least partially overlaps with the orthographic projection of the third data signal line 52-3 on the substrate.

[0334] In an exemplary embodiment, the power connection electrode 18 may be shaped like a strip extending along the first direction X, and may be disposed on a side of the second electrode plate 62 away from the scanning signal line 30, and spanning the first pixel column and the second pixel column. The first end of the power connection electrode 18 is connected to the first region of the second active layer 22 in the first pixel column through the second via hole V2 in the first pixel column, and the second end of the power connection electrode 18 is connected to the first region of the second active layer 22 in the second pixel column through the second via hole V2 in the second pixel column. The middle area between the first end and the second end of the power connection electrode 18 is connected to the first power line 51 through the seventh via hole V7, thereby enabling the first power line 51 to write the first power signal into the first electrode of the second transistor T2.

[0335] In an exemplary embodiment, the power connection electrode 18 can serve as a horizontal power connection line, and the orthographic projection of the power connection electrode 18 on the substrate does not overlap with the orthographic projection of the data signal line 52 on the substrate, and the orthographic projection of the power connection electrode 18 on the substrate at least partially overlaps with the orthographic projection of the compensation signal line 53 on the substrate.

[0336] In an exemplary embodiment, the compensation connection electrode 19 may be in the shape of a strip extending along the first direction X and may be arranged across the first pixel column and the second pixel column. The first end of the compensation connection electrode 19 is connected to both the first region of the third active layer 23 in the first pixel column and the compensation jumper electrode 42 via a fourth via hole V4 in the first pixel column. The second end of the compensation connection electrode 19 is connected to both the first region of the third active layer 23 in the second pixel column and the compensation signal line 53 via a fourth via hole V4 in the second pixel column. This enables the compensation signal line 53 to write the compensation signal to the first electrode of the third transistor T3.

[0337] In an exemplary embodiment, the orthographic projection of the compensation connection electrode 19 on the substrate does not overlap with the orthographic projection of the data signal line 52 on the substrate, and the orthographic projection of the compensation connection electrode 19 on the substrate at least partially overlaps with the orthographic projection of the first power line 51 on the substrate.

[0338] (36) The subsequent process of forming the third insulating layer, the planar layer, the fourth conductive layer, the pixel definition layer, the organic light-emitting layer, the cathode and the encapsulation structure layer is basically the same as that of the aforementioned embodiment and will not be repeated here.

[0339] In the display substrate provided by the embodiment of the present disclosure, the first power line and the compensation signal line are arranged in the middle of the repeating unit, and the data signal lines are arranged on both sides of the repeating unit, which effectively balances the distance distribution of the opaque metal signal lines between the sub-pixels. Therefore, it also has the technical effects of the aforementioned embodiments, that is, it can effectively increase the aperture ratio, reduce the risk of pixel light leakage, effectively improve the process accuracy, and effectively improve the product yield. By setting a first power line and a compensation signal line, the embodiment of the present disclosure can effectively improve space utilization, which is conducive to improving resolution. By setting a separate third active layer in each sub-pixel, the orthographic projection of the third active layer on the substrate does not overlap with the orthographic projection of the first power line on the substrate, effectively reducing the extension length of the semiconductor trace, effectively avoiding the influence of the conductor process difference on the external compensation, ensuring the accuracy of the external compensation, and ensuring the display effect and display quality. Furthermore, the embodiment of the present disclosure sets data jumper electrodes in the first sub-pixel and the fourth sub-pixel, and the outer data signal line can be connected to the first transistor through the data connection electrode of the metal material, thereby avoiding the use of the conductive semiconductor layer as the cross-line overlapping routing, effectively avoiding the display unevenness caused by the difference in conductive resistance, and improving the display effect and display quality.

[0340] Although this embodiment is described with reference to the structure shown in FIG. 22 , the structures of the data connection electrodes and the data jumper electrodes in this embodiment can also be applied to the embodiments shown in FIG. 4 , FIG. 14 and FIG. 16 .

[0341] The structure and preparation process shown in the present disclosure are merely exemplary. In exemplary embodiments, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit them.

[0342] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED) or quantum dot light-emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0343] The exemplary embodiments of the present disclosure further provide a method for preparing a display substrate, wherein the display substrate includes a plurality of repeating units, and the method includes:

[0344] At least one first power line, at least one compensation signal line, at least two data signal line groups and a plurality of sub-pixels are formed in at least one repeating unit, the plurality of sub-pixels form at least two pixel rows and at least two pixel columns, the data signal line group includes at least one data signal line; at least one sub-pixel includes a pixel driving circuit, the pixel driving circuit includes at least a storage capacitor; the first power line and the compensation signal line are arranged between two adjacent pixel columns in the repeating unit, and the at least two data signal line groups are respectively arranged on both sides of the pixel row direction of the repeating unit; the storage capacitor is arranged between the data signal line and the first power line, or, the storage capacitor is arranged between the data signal line and the compensation signal line.

[0345] The present disclosure also provides a display device comprising the display substrate of the aforementioned embodiment. The display device can be any product or component with a display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigation system.

[0346] While the embodiments disclosed herein are as described above, it should be noted that the above embodiments are merely illustrative and not restrictive. Therefore, the present disclosure is not limited to what is specifically shown and described herein. Various modifications, substitutions, or omissions may be made to the forms and details of the embodiments without departing from the scope of the present disclosure.

Claims

1. A display substrate, comprising a plurality of repeating units, at least one repeating unit comprising at least one first power line, at least one compensation signal line, at least two data signal line groups and a plurality of sub-pixels, the plurality of sub-pixels forming at least two pixel rows and at least two pixel columns, the data signal line group comprising at least two data signal lines; at least one sub-pixel comprising a pixel driving circuit, the pixel driving circuit comprising at least a storage capacitor; the first power line and the compensation signal line are arranged between two adjacent pixel columns in the repeating unit, the at least two data signal line groups are respectively arranged on both sides of the pixel row direction of the repeating unit; the storage capacitor is arranged between the data signal line and the first power line, or, the storage capacitor is arranged between the data signal line and the compensation signal line.

2. The display substrate according to claim 1, wherein: The repeating unit includes a compensation signal line and two first power lines, the two first power lines include a first first power line and a second first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; the first first power line is arranged on a side of the compensation signal line close to the first data signal line group, and a storage capacitor in the first pixel column is arranged between the first data signal line group and the first first power line; the second first power line is arranged on a side of the compensation signal line close to the second data signal line group, and a storage capacitor in the second pixel column is arranged between the second data signal line group and the second first power line.

3. The display substrate according to claim 2, wherein: At least one repeating unit also includes two power connection electrodes, which are in the shape of strips extending along the pixel row direction and are arranged across the first pixel column and the second pixel column. One end of the power connection electrode is connected to the first first power line, and the other end of the power connection electrode is connected to the second first power line, forming a ring structure for transmitting the first power signal within the repeating unit.

4. The display substrate according to claim 1, wherein: At least one repeating unit also includes a power connection electrode, which is in the shape of a strip extending along the pixel row direction and is arranged across the first pixel column and the second pixel column. The orthographic projection of the power connection electrode on the display substrate plane does not overlap with the orthographic projection of the data signal line on the display substrate plane, and the orthographic projection of the power connection electrode on the display substrate plane at least partially overlaps with the orthographic projection of the compensation signal line on the display substrate plane.

5. The display substrate according to claim 1, wherein: The repeating unit includes a compensation signal line and a first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; the first power line is arranged on a side of the compensation signal line close to the second data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the compensation signal line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the first power line.

6. The display substrate according to claim 5, wherein: The storage capacitor includes at least two capacitor plates; in the first pixel column, there is a first distance between the edge of at least one capacitor plate close to the compensation signal line and the edge of the compensation signal line close to the capacitor plate, and in the second pixel column, there is a second distance between the edge of at least one capacitor plate close to the first power line and the edge of the first power line close to the capacitor plate, and the first distance is greater than or equal to the second distance.

7. The display substrate according to claim 1, wherein: The repeating unit includes a compensation signal line and a first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the compensation signal line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the compensation signal line, and the second data signal line group is arranged on a side of the second pixel column away from the compensation signal line; the first power line is arranged on a side of the compensation signal line close to the first data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the first power line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the compensation signal line.

8. The display substrate according to claim 7, wherein: The storage capacitor includes at least two capacitor plates; in the first pixel column, there is a second distance between the edge of at least one capacitor plate close to the first power line and the edge of the first power line close to the capacitor plate, and in the second pixel column, there is a first distance between the edge of at least one capacitor plate close to the compensation signal line and the edge of the compensation signal line close to the capacitor plate, and the first distance and the second distance are both greater than the distance between the edge of the compensation signal line close to the first power line and the edge of the first power line close to the compensation signal line.

9. The display substrate according to claim 1, wherein: The repeating unit includes a first power line and two compensation signal lines, the two compensation signal lines include a first compensation signal line and a second compensation signal line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the first power line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the first power line, and the second data signal line group is arranged on a side of the second pixel column away from the first power line; the first compensation signal line is arranged on a side of the first power line close to the first data signal line group, and a storage capacitor in the first pixel column is arranged between the first data signal line group and the first compensation signal line; the second compensation signal line is arranged on a side of the first power line close to the second data signal line group, and a storage capacitor in the second pixel column is arranged between the second data signal line group and the second compensation signal line.

10. The display substrate according to claim 9, wherein: At least one repeating unit also includes two compensation connection electrodes, which are in the shape of strips extending along the pixel row direction and are arranged across the first pixel column and the second pixel column. One end of the compensation connection electrode is connected to the first compensation signal line, and the other end of the compensation connection electrode is connected to the second compensation signal line, forming a ring structure for transmitting the compensation signal within the repeating unit.

11. The display substrate according to claim 1, wherein: At least one repeating unit also includes two compensation connection electrodes, which are in the shape of strips extending along the pixel row direction and are arranged across the first pixel column and the second pixel column. The orthographic projection of the compensation connection electrode on the display substrate plane does not overlap with the orthographic projection of the data signal line on the display substrate plane, and the orthographic projection of the compensation connection electrode on the display substrate plane at least partially overlaps with the orthographic projection of the first power line on the display substrate plane.

12. The display substrate according to claim 1, wherein: The repeating unit includes a compensation signal line and a first power line, the at least two data signal line groups include a first data signal line group and a second data signal line group, and the at least two pixel columns include a first pixel column and a second pixel column; the first power line is arranged between the first pixel column and the second pixel column in the repeating unit, the first data signal line group is arranged on a side of the first pixel column away from the first power line, and the second data signal line group is arranged on a side of the second pixel column away from the first power line; the compensation signal line is arranged on a side of the first power line close to the second data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the first power line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the compensation signal line, or the compensation signal line is arranged on a side of the first power line close to the first data signal line group, the storage capacitor in the first pixel column is arranged between the first data signal line group and the compensation signal line, and the storage capacitor in the second pixel column is arranged between the second data signal line group and the first power line.

13. The display substrate according to claim 12, wherein: The storage capacitor includes at least two capacitor plates; in the first pixel column, there is a third distance between the edge of at least one capacitor plate close to the first power line and the edge of the first power line close to the capacitor plate, and in the second pixel column, there is a fourth distance between the edge of at least one capacitor plate close to the compensation signal line and the edge of the compensation signal line close to the capacitor plate; or, in the first pixel column, there is a fourth distance between the edge of at least one capacitor plate close to the compensation signal line and the edge of the compensation signal line close to the capacitor plate, and in the second pixel column, there is a third distance between the edge of at least one capacitor plate close to the first power line and the edge of the first power line close to the capacitor plate; the third distance and the fourth distance are both greater than the distance between the edge of the compensation signal line close to the first power line and the edge of the first power line close to the compensation signal line.

14. The display substrate according to any one of claims 1 to 13, wherein: The storage capacitor includes at least two capacitor plates. In at least one pixel column, the distance between an edge of at least one capacitor plate close to the compensation signal line and an edge of the compensation signal line close to the capacitor plate is greater than or equal to 3 microns.

15. The display substrate according to any one of claims 1 to 13, wherein: The storage capacitor includes a first electrode plate and a second electrode plate, the pixel driving circuit also includes a first transistor, a second transistor and a third transistor, the first electrode of the first transistor is connected to the data signal line, the second electrode of the first transistor is respectively connected to the first electrode plate and the gate electrode of the second transistor, the first electrode of the third transistor is connected to the compensation signal line, and the second electrode of the third transistor is respectively connected to the second electrode plate and the second electrode of the second transistor; In at least one repetitive unit, gate electrodes of a plurality of the first transistors and gate electrodes of a plurality of the third transistors are connected to the same scanning signal line.

16. The display substrate according to claim 14, wherein: The first transistor at least comprises a first active layer, a first region of the first active layer is connected to the data signal line via a connecting electrode, and a second region of the first active layer is connected to the second electrode plate; In at least one sub-pixel, an orthographic projection of the first active layer on the plane of the display substrate does not overlap with an orthographic projection of the data signal line on the plane of the display substrate.

17. The display substrate according to claim 14, wherein: The third transistor at least comprises a third active layer, a first region of the third active layer is connected to the compensation signal line via a connecting electrode, and a second region of the third active layer is connected to the first electrode plate; In at least one sub-pixel, an orthographic projection of the third active layer on the plane of the display substrate does not overlap with an orthographic projection of the first power line on the plane of the display substrate.

18. A display device comprising the display substrate according to any one of claims 1 to 17.

19. A method for preparing a display substrate, the display substrate comprising a plurality of repeating units, the method comprising: At least one first power line, at least one compensation signal line, at least two data signal line groups and a plurality of sub-pixels are formed in at least one repeating unit, the plurality of sub-pixels form at least two pixel rows and at least two pixel columns, the data signal line group includes at least one data signal line; at least one sub-pixel includes a pixel driving circuit, the pixel driving circuit includes at least a storage capacitor; the first power line and the compensation signal line are arranged between two adjacent pixel columns in the repeating unit, and the at least two data signal line groups are respectively arranged on both sides of the pixel row direction of the repeating unit; the storage capacitor is arranged between the data signal line and the first power line, or, the storage capacitor is arranged between the data signal line and the compensation signal line.

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