MRAM structure with chiral spin-orbit torque metal electrode

Abstract

A magnetoresistive random access memory (MRAM) structure is provided. The MRAM structure includes a chiral spin-orbit torque (SOT) metal bottom electrode (18) underneath a magnetic free layer (26), wherein the chiral SOT metal bottom electrode (18) is surrounded by a via dielectric material structure (24). The chiral SOT metal bottom electrode (18) is such that the charging current direction, the spin current direction, and the spin polarization direction are in the same direction perpendicular to the horizontal surface of the chiral SOT metal bottom electrode (18).

Description

Background Art

[0001] The present application relates to memory structures, and more particularly to a magnetoresistive random access memory (MRAM) structure including a chiral spin-orbit torque (SOT) metal bottom electrode (ie, a chiral SOT via structure).

[0002] MRAM is a non-volatile random access memory technology in which data is stored by magnetic storage elements. These elements are typically formed of two ferromagnetic plates, each of which can maintain magnetization, separated by a thin dielectric layer (i.e., a tunnel barrier layer). One of the two plates (i.e., the magnetic reference or pinned layer) is a magnet whose magnetic moment direction is set to a specific direction; the magnetization of the other plate (i.e., the magnetic free layer) can change in at least two different directions, thereby representing different digital states for memory applications, such as 0 and 1. In MRAM, these elements may be referred to as magnetic tunnel junction (MTJ) structures. In a typical MTJ structure, the magnetization of the magnetic reference layer is fixed in one direction (e.g., pointing upward), while the direction of the magnetic free layer can be "switched" by some external force, such as a magnetic field or a spin transfer torque that produces a charging current. A small current (of either polarity) can be used to read the resistance of the device, which depends on the relative orientation of the magnetization of the magnetic free layer and the magnetic reference layer. When the magnetizations are antiparallel, the resistance is generally high, and when they are parallel, the resistance is generally low (although this can be reversed, depending on the material).

[0003] One type of MRAM that can use an MTJ structure is a spin transfer torque (STT) MRAM. STT MRAM has the advantages of lower power consumption and better scalability than conventional MRAM that uses a magnetic field to flip the active element. In STT MRAM, spin transfer torque is used to flip (switch) the orientation of the magnetic free layer. For STT MRAM devices, a current passing through the MTJ structure is used to switch or "write" the bit state of the MTJ memory element. The current passing downward through the MTJ structure makes the magnetic free layer parallel to the magnetic reference layer, while the current passing upward through the MTJ structure makes the magnetic free layer antiparallel to the magnetic reference layer. Summary of the invention

[0004] An MRAM structure is provided that includes a chiral SOT metal bottom electrode (i.e., a chiral SOT via structure) below a bottom magnetic free layer, wherein the chiral SOT metal bottom electrode is surrounded by a via dielectric. The chiral SOT metal bottom electrode causes the charge current, spin current, and spin polarization directions to be in the same direction perpendicular to the surface of the chiral SOT via structure. This makes the SOT assist more efficient than the prior art MRAM containing SOT metal, in which the spin current is polarized perpendicular to its transmission direction.

[0005] In one aspect of the present application, a memory structure is provided. In one embodiment, the memory structure includes a chiral SOT metal bottom electrode, a via dielectric material structure located laterally adjacent to the chiral SOT metal bottom electrode, and an MTJ structure located on top of the chiral SOT metal bottom electrode, wherein the magnetic free layer of the MTJ structure is located below the magnetic reference layer of the MTJ. The memory structure also includes a top electrode located on top of the magnetic channel junction structure.

[0006] In an embodiment of the present application, the chiral SOT metal bottom electrode makes each of the charge current direction, the spin current direction, and the spin polarization direction perpendicular to the horizontal surface of the chiral SOT metal bottom electrode. This chiral SOT lower layer structure can produce a spin current with non-zero vertical spin polarization (due to the increase of the tilted interface orientation after the spiral growth). This produces a net spin accumulation of the surface polarized perpendicular to the chiral SOT metal bottom electrode, which is then coupled to the nanomagnet with perpendicular magnetization of the free layer for initiating or assisting spin current induced switching. This makes SOT assistance more effective than the prior art, in which the spin current is polarized perpendicular to its transmission direction.

[0007] In an embodiment of the present application, the chiral SOT metal bottom electrode is a via structure. The via structure allows the formation of the desired gradient tilt interface of the chiral SOT metal structure so as to effectively convert the charge current into a spin current with a considerable vertical polarization. In addition, the via structure under the MTJ can help eliminate any possible partial shunting of the MTJ tunneling barrier during the patterning process.

[0008] In an embodiment of the present application, each of the chiral SOT metal bottom electrode, the MTJ structure, and the top electrode may be cylindrical.

[0009] In some embodiments of the present application, the magnetic free layer of the MTJ structure has a width different from that of the chiral SOT metal bottom electrode, while in other embodiments, the magnetic free layer of the MTJ structure has a width substantially equal to that of the chiral SOT metal bottom electrode.

[0010] In an embodiment of the present application, the memory structure further comprises an interconnect layer, the interconnect layer comprising an interconnect dielectric material layer and a conductive structure located below the chiral SOT metal bottom electrode, wherein the chiral SOT metal bottom electrode is located on the surface of the conductive structure. In such an embodiment, the interconnect dielectric material layer has a recessed surface located near the conductive structure, and wherein the via dielectric material structure is located on the recessed surface of the interconnect dielectric material layer.

[0011] In an embodiment of the present application, the chiral SOT metal bottom electrode is composed of a double-layer or multi-layer thin film structure deposited into a pre-opened via recess to achieve a tilted interface. The material of the layer with strong SOT charge to spin conversion at its interface is selected, and at least one layer has a very high spin current conductivity to propagate the spin current generated at the interface to the free layer of the switching nanomagnet. In an embodiment of the present application, such an example of a double-layer or multi-layer structure of a chiral SOT metal bottom electrode can be constructed using the form of A / B or A / I / B, where A = β-Ta, β-W, Cu x Pt 1-x , Cu 1-x Ta x , Pd x Pt 1-x 、Au x Pt 1-x , Pt, Bi2Se3, WTe2, PtTe2 or TaS2, Pt x R 1-x or any material known to produce a large SOT charge spin conversion efficiency, x is from 0 to 1; and B = Cu, Ag, Au... are known good spin conductors, and "I" is a poor charge conductor, but a good spin conductor, such as NiO, FeOx, and other magnon-mediated spin-conducting, but charge-insulating, ferro- or antiferromagnetic materials. In this case, the I layer acts as an interface layer between A and B to promote spin conduction but prevent charge current shunting.

[0012] In an embodiment of the present invention, the structure further comprises a passivation layer on the sidewalls of each of the top electrode, the MTJ structure, and the chiral SOT metal bottom electrode. In such embodiments, the structure further comprises a dielectric fill material on the passivation layer, wherein the dielectric fill material has a topmost surface coplanar with a topmost surface of the top electrode.

[0013] In an embodiment of the present application, the structure further comprises an interconnect dielectric material layer located above the top electrode, wherein the conductive structure is embedded in the interconnect dielectric material layer, and the conductive structure contacts the surface of the top electrode. In such embodiments, the conductive structure has a width different from that of the top electrode, or the conductive structure has a width equal to that of the top electrode.

[0014] In another embodiment of the present application, a memory structure includes an interconnect level including at least one first conductive structure embedded in a first interconnect dielectric material layer, wherein the first interconnect dielectric material has a recessed surface adjacent to the at least one first conductive structure. The memory structure also includes a chiral SOT metal bottom electrode located on the surface of the at least one first conductive structure, a via dielectric material structure located laterally adjacent to the chiral SOT metal bottom electrode and contacting the recessed surface of the first interconnect dielectric material layer, and an MTJ structure located on top of the chiral SOT metal bottom electrode, wherein the magnetic free layer of the MTJ structure is located below the magnetic reference layer of the MTJ. The memory structure further includes a top electrode located on top of the MTJ structure, and at least one second conductive structure embedded in a second interconnect dielectric material layer located on top of the top electrode, wherein at least one second conductive structure contacts the top electrode.

[0015] In this other embodiment, the chiral SOT metal bottom electrode is such that each of the charge current direction, the spin current direction, and the spin polarization direction are perpendicular to the horizontal surface of the chiral SOT metal bottom electrode.

[0016] In this alternative embodiment, the chiral SOT metal bottom electrode is a via structure.

[0017] In this other embodiment, each of the chiral SOT metal bottom electrode, the MTJ structure, and the top electrode are cylindrical.

[0018] In this alternative embodiment, the magnetic free layer of the MTJ structure has a width different from that of the chiral SOT metal bottom electrode, or the magnetic free layer of the MTJ structure has a width substantially equal to that of the chiral SOT metal bottom electrode.

[0019] In another aspect of the present application, a method for forming a memory structure is provided. In one embodiment of the present application, the method includes forming an interconnect layer including at least one conductive structure embedded in an interconnect dielectric material layer, forming at least one sacrificial dielectric material layer via structure on the interconnect dielectric material layer while physically exposing the at least one conductive structure, and forming a chiral SOT metal layer on the physically exposed at least one conductive structure, wherein the formation of the chiral SOT metal layer includes depositing the chiral SOT metal by physical vapor deposition, wherein the deposition is performed while rotating (in the same rotation direction) the interconnect layer and the at least one sacrificial dielectric material layer via structure.

[0020] The method of the present application may further include planarizing the chiral SOT metal layer to provide a precursor chiral SOT metal bottom electrode, and patterning the precursor chiral SOT metal bottom electrode layer to provide a chiral SOT metal bottom electrode, wherein during patterning, a surface with a recess is formed in the interconnect dielectric material layer. This step removes at least one sacrificial dielectric material layer via structure from the structure.

[0021] The method of the present application may further include forming a via dielectric material structure on the recessed surface of the interconnect dielectric material layer and laterally adjacent to the chiral SOT bottom electrode.

[0022] The method of the present application may further include forming an MTJ structure and a top electrode on top of the chiral SOT metal bottom electrode, wherein the MTJ structure is located between the chiral SOT metal bottom electrode and the top electrode, and wherein the magnetic free layer of the MTJ structure is located below the magnetic reference layer of the MTJ structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a cross-sectional view of an exemplary structure that can be used according to embodiments of the present application, the exemplary structure comprising an interconnect level including at least one first conductive structure embedded in a first interconnect dielectric material layer.

[0024] Figure 2 After forming a sacrificial dielectric material layer on the interconnect layer Figure 1 A cross-sectional view of an exemplary structure is shown.

[0025] Figure 3A-3B After patterning the sacrificial dielectric material layer into at least one sacrificial dielectric material via structure Figure 2 Different views of the exemplary structure shown, Figure 3A is a top-down view. Figure 3B is along Figure 3A A cross-sectional view of XX is shown.

[0026] Figure 4A After forming a chiral SOT metal layer on the physically exposed surface of at least one first conductive structure using at least one sacrificial dielectric material layer via structure as a deposition shadow mask Figure 3B A cross-sectional view of an exemplary structure is shown.

[0027] Figure 4B Is a description Figure 4A Figure 2 shows the formation process of the chiral SOT metal layer.

[0028] Figure 5 yes Figure 4A The illustrated cross-sectional view of the exemplary structure after performing a planarization process that converts the chiral SOT metal layer into a precursor chiral SOT metal bottom electrode.

[0029] Figure 6 After forming a patterned mask stack with a via pattern on the precursor chiral SOT metal bottom electrode Figure 5 A cross-sectional view of an exemplary structure is shown.

[0030] Figure 7 yes Figure 6 A cross-sectional view of an exemplary structure shown, which utilizes a patterned mask stack as an etch mask to pattern a precursor chiral SOT metal bottom electrode to provide a chiral SOT metal bottom electrode, wherein the patterning removes at least one sacrificial dielectric material and a portion of the precursor chiral SOT metal bottom electrode through the structure, and wherein the patterning forms a recessed surface in the first interconnect dielectric material layer.

[0031] Figure 8 After forming a via dielectric material structure laterally adjacent to the chiral SOT metal bottom electrode on the recessed surface of the first interconnect dielectric material layer Figure 7 A cross-sectional view of an exemplary structure is shown.

[0032] Fig. 9 After forming a stack containing magnetic materials Figure 8 The cross-sectional view of the exemplary structure shown in , includes a stack of magnetic material including a blanket layer of nonmagnetic material, a blanket layer of tunnel barrier material, a blanket layer of magnetic reference material, and a blanket layer of top electrode material.

[0033] Fig.10 After patterning the stack comprising magnetic material to provide a patterned stack Fig. 9 A cross-sectional view of an exemplary structure shown in the figure, wherein the patterned stack consists of the remaining unetched portion of a covering layer of non-magnetic material (hereinafter referred to as the non-magnetic layer), the remaining unetched portion of a covering layer of tunnel barrier material (hereinafter referred to as the tunnel barrier layer), the remaining unetched portion of a covering layer of magnetic reference material (hereinafter referred to as the magnetic reference layer), and the remaining unetched portion of a covering layer of top electrode material (hereinafter referred to as the top electrode); in this embodiment, the width of the magnetic free layer is less than the width of the chiral SOT metal bottom electrode.

[0034] Fig.11 is based on Figure 1-10 Cross-sectional view of another exemplary structure processed by the steps shown, where the width of the magnetic free layer is greater than the width of the chiral SOT metal bottom electrode.

[0035] Fig.12 is based on Figure 1-10 A cross-sectional view of another exemplary structure processed by the illustrated steps, wherein the width of the magnetic free layer is substantially equal to the width of the chiral SOT metal bottom electrode.

[0036] Fig.13 yes Fig.10 0 is a cross-sectional view of the exemplary structure shown in FIG. 1 after further MRAM device processing. DETAILED DESCRIPTION

[0037] The present application will now be described in more detail by reference to the following discussion and the accompanying drawings of the present application. Note that the drawings of the present application are for illustrative purposes only and therefore the drawings are not drawn to scale. It should also be noted that identical and corresponding elements are represented by identical reference numerals.

[0038] In the following description, many specific details, such as specific structures, components, materials, dimensions, processing steps and techniques are set forth to provide an understanding of the various embodiments of the present application. However, it will be appreciated by those of ordinary skill in the art that the various embodiments of the present application can be practiced without these specific details. In other cases, in order to avoid obscuring the present application, well-known structures or processing steps are not described in detail.

[0039] It will be understood that when an element as a layer, region, or substrate is referred to as being "on" or "above" another element, it can be directly on the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly on" or "directly above" another element, there are no intervening elements. It will also be understood that when an element is referred to as being "below" or "under" another element, it can be directly below or under the other element, or there can be intervening elements. Conversely, when an element is referred to as being "directly below" or "directly under" another element, there are no intervening elements.

[0040] Complementary metal oxide semiconductor (CMOS) integration is expected to have a simple, two-terminal memory bit that can be driven by a field effect transistor (FET) with a limited current (<<100 μA). One approach proposed to improve MTJ-based memory bits is to use SOTs to generate more spin current to assist the switching of MTJs under limited charge current supply. The key challenge of the spin current generated by SOTs is to provide such spin polarization in the direction of the perpendicularly magnetized magnetic free layer. However, normal SOTs generate spin currents polarized in a direction perpendicular to their transport direction, making the SOT assist efficiency low.

[0041] The present application solves the above-mentioned problems regarding SOTs containing MTJs by providing a chiral via SOT structure as a bottom metal electrode. The chiral via SOT structure of the present application generates a spin current whose spin polarization direction is significantly along the current propagation direction and has a large conversion efficiency for charge to spin current conversion. Therefore, it is effective in generating a spin current with axially polarized spins along the via axis. This is achieved by forming a multilayer transport structure with a spiral pattern for charge and spin current conduction. The chiral via structure consists of a double-layer or multilayer structure in the form of A / B or A / I / B, where A = β-Ta, β-W, Cu x Pt 1-x , Cu 1-x Ta x , Pd x Pt 1-x 、Au x Pt 1-x , Pt, Bi2Se3, WTe2, PtTe2 or TaS2, Pt x R 1-x or any material known to produce a large SOT charge-to-spin conversion efficiency, x is 0 to 1; and B = Cu, Ag, Au... are known good spin conductors, and "I" as a poor charge conductor, but a good spin conductor such as NiO, FeOx and other magnon-mediated spin-conducting, but charge-insulating, ferro- or antiferromagnetic materials. In this case, the I layer acts as an interface layer between A and B to promote spin conduction but prevent charge current shunting. The gradually increasing tilt of the A / B or A / I / B interface normal produces a gradient of spin current to accumulate a significant component with axial (relative to helical) spin polarization, thereby achieving efficient conversion of charge current to axially polarized spin current, which is important for efficient switching of perpendicularly magnetized nanomagnets built on top of chiral via structures.

[0042] First reference Figure 1 , showing an exemplary structure that can be used according to an embodiment of the present application; note that including Figure 1 All cross-sectional views, including those shown, are taken along Figure 3A XX shown. The exemplary structure comprises an interconnect layer including at least one first conductive structure 12 (three are shown by way of example in the drawings of the present application) embedded in a first interconnect dielectric material layer 10 .

[0043] Figure 1The interconnect layer shown in the figure may be located above at least one underlying metal layer (not shown) and a front-end layer (FEOL) also not shown. In some embodiments, the metal layer may be a middle-of-the-line (MOL) layer. In other embodiments, the metal layer may be at least one lower interconnect layer of a multi-layer interconnect structure. In still other embodiments, the metal layer may be a combination of the MOL layer and at least one lower interconnect layer of a multi-level interconnect structure. The metal layer may include a bottom conductive structure embedded in a dielectric material layer. The FEOL may include a semiconductor substrate having one or more semiconductor devices (e.g., transistors) formed thereon. The metal layer and the FEOL may be formed using materials and techniques known to those skilled in the art. In order not to obscure the memory structure of the present application, the materials and techniques used to provide the metal layer and the FEOL are not described in the present application.

[0044] The first interconnect dielectric material layer 10 can be composed of any interconnect dielectric material, including, for example, silicon oxide (SiOx), silsesquioxane, C-doped oxides including Si, C, O and H atoms (i.e., organosilicates), thermosetting polyarylene ethers or multilayers thereof. The term "polyarylene" is used in this application to represent aromatic moieties or inert substituted aromatic moieties linked together by bonds, fused rings or inert linking groups such as oxygen, sulfur, sulfone, sulfoxide, carbonyl, etc.

[0045] The first interconnect dielectric material layer 10 may have a dielectric constant of about 4.0 or less (unless otherwise stated, all dielectric constants mentioned herein are measured relative to a vacuum). In one embodiment, the first interconnect dielectric material layer 10 has a dielectric constant of 2.8 or less. These dielectrics typically have lower parasitic crosstalk than dielectric materials having a dielectric constant greater than 4.0. The first interconnect dielectric material layer 10 may be formed by a deposition process, such as chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or spin coating. The first interconnect dielectric material layer 10 may have a thickness from 50 nm to 250 nm. Other thicknesses less than 50 nm and greater than 250 nm may also be used in the present application as the thickness of the first interconnect dielectric material layer 10.

[0046] The at least one first conductive structure 12 may be made of a conductive metal or a conductive metal alloy. Illustrative examples of conductive materials that may be used in the present application to provide the at least one first conductive structure 12 include, but are not limited to, Cu, Al, Cu-Al alloy, W, Ru, or Rh. Figure 3A As apparent from the top-down view shown in FIG. 1 , the at least one first conductive structure 12 is generally cylindrical. Although the at least one first conductive structure 12 is illustrated as being cylindrical in shape, the shape of the at least one first conductive structure 12 is not limited to being cylindrical.

[0047] In some embodiments, a diffusion barrier liner (not shown) may be present at least along the sidewalls (in some embodiments, along the bottom wall) of at least one conductive structure 12. When present, the diffusion barrier liner may be composed of any known diffusion barrier material, such as Ta, TaN, Ti, TiN, W, or WN. In some embodiments, the diffusion barrier liner may include a material stack of two or more diffusion barrier materials. In one example, the diffusion barrier liner may be composed of a Ta / TaN stack or a Ti / TiN stack.

[0048] Figure 1 The exemplary structure shown in can be formed by first depositing a first interconnect dielectric material layer 10. Next, at least one opening is formed in the first interconnect dielectric material layer 10 by photolithography and etching. Photolithography includes forming a photoresist material on the surface of the material layer or structure to be patterned, exposing the deposited photoresist material to a radiation pattern, and then developing the exposed photoresist material. The etching used in providing at least one opening into the first interconnect dielectric material layer 10 may include a dry etching process (i.e., reactive ion etching, plasma etching, or ion beam etching) or a chemical wet etching. Next, if a diffusion barrier material layer is present, a diffusion barrier material layer may be formed in at least the opening and on top of the first interconnect dielectric material layer 10, and the formation of the diffusion barrier material layer includes a deposition process, such as CVD, PECVD, physical vapor deposition (PVD) or atomic layer deposition (ALD). The diffusion barrier material layer does not fill the entirety of at least one opening. Next, one of the above-mentioned conductive materials (e.g., Cu) is then deposited on the diffusion barrier material layer. The deposition of the conductive material may include CVD, PECVD, PVD, ALD, sputtering, or electroplating. A planarization process, such as chemical mechanical polishing (CMP), is then performed to remove the diffusion barrier material layer (if present) and the conductive material formed outside the at least one opening and on top of the first interconnect dielectric material layer 10. After the planarization process, the conductive material and the diffusion barrier material layer (if present) remain in the opening. The conductive material remaining in the opening provides the first conductive structure 12, and the diffusion barrier material layer remaining in the opening provides the diffusion barrier liner ( Figure 1 In the embodiment of the present application, at least one first conductive structure 12 has a top surface coplanar with at least a top surface of the first interconnect dielectric material layer 10; if a diffusion barrier liner is present, the topmost surface of the at least one first conductive structure 12 may also be coplanar with the topmost surface of the diffusion barrier layer and with the topmost surface of the first interconnect dielectric material layer 10.

[0049] Reference now Figure 2 , showing the formation of a sacrificial dielectric material layer 14L on the interconnect layer Figure 11. An exemplary structure shown. As shown, a sacrificial dielectric material layer 14L is formed on the first interconnect dielectric material layer 10 and the at least one first conductive structure 12, the sacrificial dielectric material layer 14L includes a dielectric material that is different in composition from the dielectric material that provides the first interconnect dielectric material layer 10, and in one example, the sacrificial dielectric material layer 14L is composed of silicon nitride (SiN) or silicon oxynitride (SiON). The sacrificial dielectric material layer 14L can be formed by a deposition process, such as CVD, PECVD, PVD, or ALD. The sacrificial dielectric material layer 14L can have a thickness from 20nm to 200nm, although other thicknesses are contemplated and can be used as the thickness of the sacrificial dielectric material layer 14L.

[0050] Reference now Figure 3A-3B , showing the sacrificial dielectric material layer 14L after patterning into at least one sacrificial dielectric material via structure 14 Figure 2 In the exemplary structure shown in , the at least one sacrificial dielectric material via structure 14 is present on a portion of the first interconnect dielectric material layer 10, but not on any portion of the at least one first conductive structure 12, thereby leaving the at least one first conductive structure 12 physically exposed. Patterning includes lithography and etching as described above. In cross-section, the at least one sacrificial dielectric material via structure 14 has a width from 5nm to 100nm. The at least one sacrificial dielectric material via structure 14 has a vertical height from 20nm to 500nm. The at least one sacrificial dielectric material via structure 14 is configured to allow effective shadow deposition of a chiral SOT metal layer, which will be described in detail below.

[0051] Reference now Figure 4A , showing the chiral SOT metal layer 18L after forming the chiral SOT metal layer 18L on the physically exposed surface of at least one first conductive structure 12 Figure 3B The exemplary structure shown in ; the chiral SOT metal layer 18L may also extend onto portions of the first interconnect dielectric material layer 10 that are not protected by at least one sacrificial dielectric material via structure 14, in which element 16 represents an undesirable region of the structure where the chiral SOT metal is not desired to be formed. The undesired region includes a composition similar to that of the chiral SOT metal layer 18L, but lacks the orientation (i.e., chirality) of the chiral SOT metal layer 18L. Note that the region that is not protected by at least one sacrificial dielectric material via structure 14 defines a via, and the chiral SOT metal layer 18L is formed in the via. In this deposition step, at least one sacrificial dielectric material layer via structure 14 is used as a deposition shadow mask that blocks some areas of the structure from having undesired SOT metal deposition.

[0052] The chiral SOT metal layer 18L is composed of a conductor that is capable of generating a spin current to assist the switching of the subsequently formed MTJ under a limited supply of charging current. The chiral via SOT structure of the present application generates a spin current whose spin polarization direction is significantly along the current propagation direction and has a large conversion efficiency for charge to spin current conversion. Therefore, it is effective in generating a spin current with axially polarized spins along the via axis. This is achieved by forming a multilayer transmission structure with a spiral pattern for charge and spin current conduction. The chiral via structure consists of a double-layer or multilayer structure in the form of A / B or A / I / B, where A = β-Ta, β-W, Cu x Pt 1-x , Cu 1-x Ta x , Pd x Pt 1-x 、Au x Pt 1-x , Pt, Bi2Se3, WTe2, PtTe2 or TaS2, Pt x R 1-x or any material known to produce a large SOT charge-to-spin conversion efficiency, x is 0 to 1; and B = Cu, Ag, Au... are known good spin conductors, and "I" acts as a poor charge conductor, but a good spin conductor such as NiO, FeOx and other magnon-mediated spin-conducting, but charge-insulating, ferro- or antiferromagnetic materials. In this case, the I layer acts as an interface layer between A and B to promote spin conduction but prevent charge current shunting. The gradually increasing tilt of the A / B or A / I / B interface normal produces a gradient of spin current to accumulate a significant component with axial (relative to helical) spin polarization, thereby achieving high efficiency of charge current to axially polarized spin current, which is important for efficient switching of perpendicularly magnetized nanomagnets constructed above the chiral via structure. The chiral SOT metal layer 18L can be formed by PVD using at least two targets while rotating a substrate having an exemplary structure; this aspect of the present application is, for example, in Figure 4B The rotation can be in the clockwise or counterclockwise direction. Figure 3A-3BThe chirality of the chiral SOT metal layer 18L is determined by the rotation direction of the structure during the deposition process. In the present application, the chiral SOT metal layer 18L can be optimized to give the maximum vertical polarization spin accumulation at the topmost surface. This can be achieved, for example, by controlling the incident angle and deposition rate of various sources to adjust the tilt change rate of the multilayer interface during spiral growth. The relative thickness of the A / B or A / I / B film can also be optimized by adjusting the deposition rate of the relevant source. These are all intended to optimize the current conversion efficiency of the charge to the spin, and maximize the spin current with polarization in the axial direction of the spiral.

[0053] The chiral SOT metal layer 18L has a vertical height greater than about 20 nm, and the chiral SOT metal layer 18L has a topmost surface, which at this point in the present application is generally located above the topmost surface of at least one sacrificial dielectric material via structure 14. In an embodiment, after deposition, groove etching can be used to reduce the vertical height of the chiral SOT metal layer 18L to adjust the vertical height of the chiral SOT metal layer 18L.

[0054] Reference now Figure 5 , showing the Figure 4A The exemplary structure shown in FIG. 1 is a CMP process, for example, which converts the chiral SOT metal layer 18L into a precursor chiral SOT metal bottom electrode 18P. The planarization process removes a portion of the chiral SOT metal layer 18L and an upper portion of the unneeded region 16 and an upper portion of at least one sacrificial dielectric material via structure 14. The final result of the planarization is that each precursor chiral SOT metal bottom electrode 18P is formed to have a top surface coplanar with the remaining portion of the at least one sacrificial dielectric material via structure 14.

[0055] Reference now Figure 6 , showing after forming a patterned mask stack 20 / 22 having a via pattern on a precursor chiral SOT metal bottom electrode Figure 5 The exemplary structure shown. 18p. The patterned mask stack 20 / 22 protects some, but not all, of the precursor chiral SOT metal bottom electrode 18P. Therefore, a portion of the precursor chiral SOT metal bottom electrode 18P is unprotected, such as Figure 6 As shown, however, the patterned mask stack 20 / 22 does not cover the undesired area 16 .

[0056] The patterned mask stack 20 / 22 includes a bottom hard mask material layer 20 and a top soft mask material layer 22. In some embodiments, the bottom hard mask material layer 20 is composed of a dielectric hard mask material such as silicon nitride or silicon oxynitride. In other embodiments, the bottom hard mask material layer 20 is composed of a metallic hard mask material, such as AlO x . The hard mask material providing the bottom hard mask material layer 20 may be the same or different in composition from the dielectric material providing the at least one sacrificial dielectric material via structure 14, and the top soft mask material layer 22 is composed of an organic planarization layer (OPL) or any other similar organic mask material. The patterned mask stack 20 / 22 may be formed by uniformly depositing the hard mask material, then uniformly depositing the soft mask material, and then photolithographically patterning it as the deposited hard mask material / soft mask material. The deposition may include, but is not limited to, CVD, PECVD, or spin coating or coating. These capping layers of hard mask material and soft mask material may be deposited using the same or different deposition processes. The bottom hard mask material layer 20 may have a thickness from 20nm to 150nm, and the top soft mask material layer 22 may have a thickness from 50nm to 500nm. However, other thicknesses for the bottom hard mask material layer 20 and the top soft mask material layer 22 are contemplated and may be used in the present application.

[0057] Reference now Figure 7 , showing the precursor chiral SOT metal bottom electrode 18P after patterning the precursor chiral SOT metal bottom electrode 18 using the patterned mask stack 20 / 22 as an etch mask to provide the chiral SOT metal bottom electrode 18 Figure 6 , wherein the patterning removes at least one sacrificial dielectric material via structure 14 and a portion of the precursor chiral SOT metal bottom electrode 18P, and wherein the patterning forms a recessed surface S1 in the first interconnect dielectric material layer 10. Note that the recessed surface S1 is formed in a region of the first interconnect dielectric material layer 10 that is laterally adjacent to the first conductive structure 12 that now includes the chiral SOT metal bottom electrode 18 on the top surface of the first conductive structure 12. Figure 7 As shown, the patterning step may also form a notched surface S2 at an upper corner of at least one first conductive structure. Such notching occurs due to the difference in etching rates between the metal and the dielectric.

[0058] Patterning includes reactive ion etching or ion beam etching. During the patterning, the upper portion of the soft mask material layer 22 and the hard mask material layer 20 may be removed. The resulting chiral SOT metal bottom electrode 18 has a sidewall surface that is generally perpendicular to the topmost surface of the at least one first conductive structure 12, however, some taper of the sidewall of the chiral SOT metal bottom electrode 18 may occur. The chiral SOT metal bottom electrode 18 is a generally cylindrical via structure.

[0059] Reference now Figure 8 , showing the via dielectric material structure 24 formed on the recessed surface S1 of the first interconnect dielectric material layer 10 and laterally adjacent to the chiral SOT metal bottom electrode 18 Figure 7 ; note that the via dielectric material structure 24 is also formed on the non-recessed surface of the first interconnect dielectric material layer 10. The via dielectric material structure 24 can be composed of one of the dielectric materials described above for the first interconnect dielectric material layer 10, or another dielectric material such as silicon nitride can be used when providing the via dielectric material structure 24. The dielectric material providing the via dielectric material structure 24 can be composed of a dielectric material that is the same as or different in composition from the dielectric material providing the first interconnect dielectric material layer. The via dielectric material structure 24 can be formed by depositing a dielectric material followed by a planarization process. The deposition of the dielectric material providing the via dielectric 24 can include CVD, PECVD, PVD, or spin coating. After planarization, as Figure 8 As shown, the topmost surface of the via dielectric material structure 24 is coplanar with the topmost surface of the chiral SOT metal bottom electrode 18 .

[0060] Reference now Fig. 9 , showing the structure of the magnetic material-containing stack after forming a capping layer 26L of non-magnetic material, a capping layer 28L of tunnel barrier material, a capping layer 30L of magnetic reference material, and a capping layer 32L of upper electrode material. Figure 8 ; Subsequently, the blanket layer of top electrode material 32L will be patterned and used as an etch mask for the remaining blanket layers in the stack containing magnetic materials. It should be noted that other magnetic and non-magnetic materials typically present in MTJ structures may be formed in Fig. 9 In a stack containing magnetic materials as shown. Fig. 9 As shown, the magnetic material stack is located on the via dielectric material structure 24 and the chiral SOT metal bottom electrode 18 . In the embodiment of the present invention, the non-magnetic material cover layer 26L forms a direct interface with the chiral SOT metal bottom electrode 18 .

[0061] The stacked magnetic free material covering layer 26L containing magnetic material is composed of at least one magnetic material, at least one magnetic material having a magnetization that can be changed in orientation relative to the magnetization orientation of a magnetic reference material; note that the term "magnetic free material" means that the magnetic layer does not have a fixed magnetization; however, the term does not mean that the layer does not contain magnetic material. Exemplary materials for the covering layer of non-magnetic material 26L include, but are not limited to, alloys and / or multilayers of cobalt, iron, alloys of cobalt-iron, nickel, alloys of nickel-iron, and alloys of cobalt-iron-boron. The non-magnetic material covering layer 26L may have a thickness from 0.3 nm to 3 nm; although other thicknesses are possible and may be used as the thickness of the non-magnetic material covering layer 26L.

[0062] The blanket layer of the stacked tunnel barrier material 28L containing magnetic material is composed of an insulator material and is formed with a thickness that provides an appropriate tunneling resistance. Exemplary materials for the covering layer of the tunnel barrier material 28L include magnesium oxide, aluminum oxide, and titanium oxide, or a material with a higher electrical tunneling conductance, such as a semiconductor or a low bandgap insulator. The thickness of the blanket layer of the tunnel barrier material 28L will depend on the material selected. In one example, the blanket layer of the tunnel barrier material 28L may have a thickness from 0.5 nm to 1.5 nm; although other thicknesses are possible as long as the thickness of the covering layer of the tunnel barrier material 28L provides an appropriate tunneling resistance.

[0063] The magnetic reference material cover layer 30L has a fixed magnetization. The blanket layer 30L of magnetic reference material is composed of a metal or metal alloy, the metal or metal alloy including one or more metals that exhibit high spin polarization. In alternative embodiments, exemplary metals for forming the magnetic reference layer include iron, nickel, cobalt, chromium, boron, and manganese. Exemplary metal alloys may include the metals exemplified above. In another embodiment, the magnetic reference layer may be a multilayer arrangement having (1) a high spin polarization region formed by metals and / or metal alloys using the above metals, and (2) a region constructed of one or more materials exhibiting strong perpendicular magnetic anisotropy (strong PMA). Exemplary materials with strong PMA that can be used include metals such as cobalt, nickel, platinum, palladium, iridium, or ruthenium, and can be arranged as alternating layers. Strong PMA regions may also include alloys that exhibit strong PMA, exemplary alloys including cobalt-iron-terbium, cobalt-iron-gadolinium, cobalt-chromium-platinum, cobalt-palladium, iron-platinum, and / or iron-palladium. The alloys may be arranged as alternating layers. In one embodiment, combinations of these materials and regions may also be employed.The magnetic reference material cover layer 30L may have a thickness of 0.3 nm to 3 nm; although other thicknesses are possible and may be used as the thickness of the magnetic reference material blanket layer 30L.

[0064] The top electrode material capping layer 32L is composed of a conductive material, such as Ta, TaN, Ti, TiN, Ru, RuN, RuTa, RuTaN, Co, CoWP, CoN, W, WN, or any combination thereof. The top electrode material capping layer 32L may have a thickness of 5 nm to 100 nm; other thicknesses are possible and may be used as the thickness of the blanket layer of the top electrode material 32L in the present application.

[0065] like Fig. 9 As shown, the stack 26L / 28L / 30L / 32L containing magnetic materials may be formed using one or more deposition processes, including but not limited to CVD, PECVD, PVD, ALD (including plasma enhanced ALD) or sputtering.

[0066] Reference now Fig.10 , showing after patterning a stack comprising a magnetic material to provide a patterned stack Fig. 9 , the patterned stack is composed of a remaining unetched portion 26L of a blanket layer of non-magnetic material (hereinafter referred to as non-magnetic layer 26), a remaining unetched portion 28L of a blanket layer of tunnel barrier material (hereinafter referred to as tunnel barrier layer 28), a remaining unetched portion 30L of a blanket layer of magnetic reference material (hereinafter referred to as magnetic reference layer 30), and a remaining unetched portion 32L of a blanket layer of top electrode material (hereinafter referred to as top electrode 32). In this embodiment, the width of the magnetic free layer 26L is less than the width of the chiral SOT metal bottom electrode 18; note that the width of the chiral SOT metal bottom electrode 18 is the average width of the electrode. The combination of the magnetic free layer 26, the tunnel barrier layer 28, and the magnetic reference layer 30 provides an MTJ structure located between the top electrode 32 and the chiral SOT metal bottom electrode 18.

[0067] The patterning includes a photolithography process in which a patterned resist (not shown) is formed on the surface of the capping layer of the top electrode material 32L. The patterned resist can be formed by depositing a photoresist material, exposing the photoresist material to a desired irradiation pattern, and developing the exposed photoresist material. The patterned resist protects a portion of the capping layer 32L of the top electrode material while leaving other portions of the capping layer 32L of the top electrode material physically exposed. The physically exposed portion of the blanket layer of the top electrode material 32L is removed in the initial transfer etch. After the initial transfer etch, the patterned resist is removed using a conventional resist removal process, such as ashing. Patterning is continued using another etch, in which the top electrode 32 is used as an etching mask for the remaining patterning process. This other etch stops on the secondary surface of the via dielectric material structure 24, the term "secondary surface" representing the material surface between the topmost surface and the bottom surface of the material. The other etching removes the remaining portion of the stack containing magnetic material that is not covered by the top electrode 32, and the upper portion of the via dielectric material structure 24. In some embodiments, the etching can also remove the portion of the chiral SOT metal bottom electrode 18 that is not protected by the top electrode 32. The transfer etching and subsequent etching can include ion beam etching, reactive ion beam etching, or any combination thereof. The transfer etching can be the same or different from the other etching used in the patterning step. For example, the transfer etching can include reactive ion etching, and the other etching can include ion beam etching.

[0068] In some embodiments of the present application, Fig.10 The exemplary structure shown in may be subjected to an oxygen treatment process or any other gas treatment process in order to remove any unwanted metal particles that may have been redeposited on the sidewalls of the MTJ structure during this patterning.

[0069] The top electrode 32 and the underlying MTJ structure 26 / 28 / 30 are generally cylindrical in shape. In some embodiments of the present application, the top electrode 32 and the underlying MTJ structure 26 / 28 / 30 generally have the same width. Therefore, the outermost wall of the top electrode 32 and the underlying MTJ structure 26 / 28 / 30 are generally vertically aligned with each other. In other embodiments of the present application, the top electrode 32 and the underlying MTJ structure 26 / 28 / 30 may have different widths to provide a certain taper in the outermost wall of the stack containing the top electrode 32 and the underlying MTJ structure 26 / 28 / 30.

[0070] Reference now Fig.11 , showing that according to Figure 1-10Another exemplary structure processed by the steps shown, wherein the width of the magnetic free layer 26 is greater than the width of the chiral SOT metal bottom electrode 18; the width of the chiral SOT metal bottom electrode 18 is also the average width. In this embodiment, the magnetic free layer 26 is suspended on the outermost wall of the chiral SOT metal bottom electrode 18, and the intermediate layer window dielectric material structure 24 is located under the suspended portion of the magnetic free layer 26. This structure can be formed by ion beam etching, reactive ion etching, or a combination of the two.

[0071] Reference now Fig.12 , showing that according to Figure 1-10 The steps shown process another exemplary structure in which the width of the magnetic free layer is substantially equal to (ie, ±5%) the width (ie, average width) of the chiral SOT metal bottom electrode 18 .

[0072] Reference now Fig.13 , showing the MRAM device after further processing Fig.10 The exemplary structure is shown in FIG. Further processing of the MRAM element can also be performed in Fig.11 and 12 The structure shown in FIG. 1 is performed on the structure shown in FIG. 1 , and further processing of the MRAM element includes forming an encapsulation layer 34, which laterally surrounds the top electrode 32, the MTJ structure 26 / 28 / 30, and any exposed upper portion of the chiral SOT metal bottom electrode 18, and is present on the top of the via dielectric material structure 24, and the encapsulation layer 34 is formed by depositing (e.g., CVD, PECVD, PVD, ALD or spin coating) an encapsulation material (typically a dielectric material), followed by a planarization process to remove the encapsulation material deposited on the top of the top electrode 32. In another embodiment, the encapsulation material is a dielectric material containing silicon, carbon, and hydrogen atoms. In some embodiments, in addition to carbon atoms and hydrogen atoms, the encapsulation material may include at least one of nitrogen atoms and oxygen atoms. In other embodiments, in addition to silicon, nitrogen, carbon, and hydrogen atoms, the encapsulation material may include boron atoms. In one example, the encapsulation layer 34 may be composed of an nBLOK dielectric material containing silicon, carbon, hydrogen, nitrogen, and oxygen atoms. In an alternative example, encapsulation layer 34 may be composed of a SiBCN dielectric material containing atoms of silicon, boron, carbon, hydrogen, and nitrogen. Encapsulation layer 34 may have a thickness from 10 nm to 200 nm. Other thicknesses are also possible and may be used as the thickness of encapsulation layer 34.

[0073] After forming the packaging layer 34, the MTJ dielectric filling material 36 is formed on the packaging layer 34 and laterally adjacent to the top electrode 32 and the MTJ structure 26 / 28 / 30. The dielectric MTJ dielectric filling material 36 may include one of the dielectric materials described above for the via dielectric material structure 24. The dielectric material providing the MTJ dielectric filling material 36 may be the same or different in composition from the dielectric material providing the via dielectric material structure 24. Note that in an embodiment of the present application, the planarization process is used to remove the packaging material and the dielectric material from the top of the top electrode. The MTJ dielectric filling material 36 has a topmost surface coplanar with the topmost surface of the top electrode 32.

[0074] The further MRAM device processing also includes forming a second interconnect dielectric material layer 38 having at least one second conductive structure 40 embedded therein and contacting the surface of the top electrode 32, and then forming a third interconnect dielectric material 42 on top of the second interconnect dielectric material 38 and the at least one second conductive structure 40; in some embodiments of the present application, the formation of the third interconnect dielectric material 42 may be omitted. The second interconnect dielectric material layer 38 may include one of the dielectric materials mentioned above for the first interconnect dielectric material layer 10, the dielectric material providing the second interconnect dielectric material layer 38 may be the same or different in composition from the dielectric material providing the first interconnect dielectric material layer 10, and the second interconnect dielectric material layer 38 may be formed using one of the deposition processes mentioned above for forming the first interconnect dielectric material layer 10.

[0075] The at least one second conductive structure 40 is formed of one of the conductive materials described above for the at least one first conductive structure 12. In some embodiments, a diffusion barrier liner (not shown) may be formed along the sidewalls and bottom wall of the second conductive structure 40. In some embodiments, the diffusion barrier liner is not present. The diffusion barrier liner is formed of a diffusion barrier material as defined above. The at least one second conductive structure 40 and the diffusion barrier liner (if present) may be formed as described above, providing Figure 1 In the exemplary structure shown, at least one second conductive structure 40 may have a width greater than, less than, or equal to the width of the top electrode 32. In some embodiments and as shown in FIG. Fig.13 As shown, separate (three in the illustrated embodiment) second conductive structures 40 are formed, each of which contacts a single top electrode 32 . In other embodiments, second conductive structures 40 contacting two or more top electrodes 32 may be formed.

[0076] When present, the third interconnect dielectric material layer 42 may include one of the dielectric materials mentioned above for the first interconnect dielectric material layer 10, and the dielectric material providing the third interconnect dielectric material layer 42 may be the same or different in composition from the dielectric material providing the first interconnect dielectric material layer 10 and / or the dielectric material providing the second interconnect dielectric material layer. The third interconnect dielectric material layer 42 may be formed using one of the deposition processes described above for forming the first interconnect dielectric material layer 10, and a third conductive structure (not shown) may be formed into the third interconnect dielectric material and in contact with at least one second conductive structure.

[0077] Although the present application has been specifically shown and described with reference to the preferred embodiments of the present application, it should be understood by those skilled in the art that the foregoing and other changes may be made in form and detail without departing from the scope of the present application. Therefore, the present application should not be limited to the exact form and details described and shown, but fall within the scope of the appended claims.

Claims

1. A memory structure comprising: Chiral spin-orbit torque (SOT) metal bottom electrode; a via dielectric material structure, the via dielectric material structure being located laterally adjacent to the chiral SOT metal bottom electrode; a magnetic tunnel junction (MTJ) structure located on top of the chiral SOT metal bottom electrode, wherein a magnetic free layer of the MTJ structure is located below a magnetic reference layer of the MTJ; as well as A top electrode is located on a top of the MTJ structure.

2. The memory structure of claim 1, wherein the chiral SOT metal bottom electrode enables each of a charge current direction, a spin current direction, and a spin polarization direction to be perpendicular to a horizontal surface of the chiral SOT metal bottom electrode.

3. The memory structure of claim 1, wherein the chiral SOT metal bottom electrode is a via structure. 4 . The memory structure of claim 1 , wherein each of the chiral SOT metal bottom electrode, the MTJ structure, and the top electrode is cylindrical. 5 . The memory structure of claim 1 , wherein the magnetic free layer of the MTJ structure has a different width than the chiral SOT metal bottom electrode.

6. The memory structure of claim 1, wherein a width of the magnetic free layer of the MTJ structure is substantially equal to a width of the chiral SOT metal bottom electrode.

7. The memory structure of claim 1 , further comprising an interconnect level comprising an interconnect dielectric material layer and a conductive structure underlying the chiral SOT metal bottom electrode, wherein the chiral SOT metal bottom electrode is located on a surface of the conductive structure.

8. The memory structure of claim 7, wherein the interconnect dielectric material layer has a recessed surface located adjacent to the conductive structure, and wherein the via dielectric material structure is located on the recessed surface of the interconnect dielectric material layer.

9. The memory structure of claim 1, wherein the chiral SOT metal bottom electrode is composed of a conductor that generates a spin current to assist switching of the MTJ.

10. The memory structure according to claim 9, wherein the chiral SOT metal bottom electrode is composed of a double-layer or multi-layer structure in the form of A / B or A / I / B, wherein A = β-Ta, β-W, Cu x Pt 1-x , Cu 1-x Ta x , Pd x Pt 1-x 、Au x Pt 1-x , Pt, Bi2Se3, WTe2, PtTe2 or TaS2, Pt x R 1-x , x is 0 to 1, and B=Cu, Ag or Au, and I includes NiO, FeOx or other spin-conducting but charge-insulating ferromagnetic, ferrimagnetic or antiferromagnetic materials.

11. The memory structure of claim 1 , further comprising a passivation layer on sidewalls of each of the top electrode, the MTJ structure, and the chiral SOT metal bottom electrode.

12. The memory structure of claim 11, further comprising a dielectric fill material on the passivation layer, wherein the dielectric fill material has a topmost surface that is coplanar with a topmost surface of the top electrode.

13. The memory structure of claim 1, further comprising an interconnect dielectric material layer over the top electrode, wherein a conductive structure is embedded in the interconnect dielectric material layer, and the conductive structure contacts a surface of the top electrode.

14. The memory structure of claim 13 wherein a width of the conductive structure is different than a width of the top electrode.

15. The memory structure of claim 13 wherein a width of the conductive structure is equal to a width of the top electrode.

16. A memory structure comprising: an interconnect level comprising at least one first conductive structure embedded in a layer of a first interconnect dielectric material, wherein the first interconnect dielectric material has a recessed surface adjacent to the at least one first conductive structure; a chiral spin-orbit torque (SOT) metal bottom electrode disposed on a surface of the at least one first conductive structure; a via dielectric material structure, the via dielectric material structure being located laterally adjacent to the chiral SOT metal bottom electrode and contacting the recessed surface of the first interconnect dielectric material layer; a magnetic tunnel junction (MTJ) structure located on top of the chiral SOT metal bottom electrode, wherein a magnetic free layer of the MTJ structure is located below a magnetic reference layer of the MTJ; a top electrode located on top of the MTJ structure; as well as At least one second conductive structure is embedded in a second interconnect dielectric material layer on top of the top electrode, wherein the at least one second conductive structure contacts the top electrode.

17. The memory structure of claim 16, wherein the chiral SOT metal bottom electrode enables each of a charge current direction, a spin current direction, and a spin polarization direction to be perpendicular to a horizontal surface of the chiral SOT metal bottom electrode.

18. The memory structure of claim 16, wherein the chiral SOT metal bottom electrode is a via structure.

19. The memory structure of claim 16, wherein each of the chiral SOT metal bottom electrode, the MTJ structure, and the top electrode is cylindrical.

20. The memory structure of claim 16, wherein a width of the magnetic free layer of the MTJ structure is different than a width of the chiral SOT metal bottom electrode.

21. The memory structure of claim 16, wherein a width of the magnetic free layer of the MTJ structure is substantially equal to a width of the chiral SOT metal bottom electrode.

22. A method of forming a memory structure, the method comprising: forming an interconnect level including at least one conductive structure embedded in a layer of interconnect dielectric material; forming at least one sacrificial dielectric material layer via structure on the interconnect dielectric material layer while physically exposing the at least one conductive structure; as well as A chiral spin-orbit torque (SOT) metal layer is formed on the physically exposed at least one conductive structure, wherein the formation of the chiral SOT metal layer includes depositing the chiral SOT metal by physical vapor deposition, wherein the deposition is performed while rotating the interconnect level and the at least one sacrificial dielectric material layer via structure in the same rotation direction.

23. The method according to claim 22, further comprising: The chiral SOT metal layer is planarized to provide a precursor chiral SOT metal bottom electrode, and the precursor chiral SOT metal bottom electrode layer is patterned to provide a chiral SOT metal bottom electrode, wherein during the patterning, a recessed surface is formed in the interconnect dielectric material layer.

24. The method of claim 23, further comprising forming a via dielectric material structure on the recessed surface of the interconnect dielectric material layer and laterally adjacent to the chiral SOT bottom electrode.

25. The method of claim 24, further comprising forming a magnetic tunnel junction (MTJ) structure and a top electrode on top of the chiral SOT metal bottom electrode, wherein the MTJ structure is located between the chiral SOT metal bottom electrode and the top electrode, and wherein the magnetic free layer of the MTJ structure is located below the magnetic reference layer of the MTJ structure.

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