Display panel and display device

Abstract

The invention belongs to the technical field of display, and particularly relates to a display panel and a display device.The display panel comprises a substrate and pixel units, each pixel unit comprises a first pixel subunit and a second pixel subunit, the first pixel subunit and the second pixel subunit comprise first sub-pixels and second sub-pixels, each first sub-pixel and each second sub-pixel comprise first transistors and second transistors, and the first transistors and the second transistors are arranged on the substrate. The first / second transistor comprises a first / second grid electrode, a first / second source electrode, a first / second drain electrode and a first / second semiconductor layer. A first scanning line and a second scanning line are arranged between every two adjacent rows of pixel units and extend in the row direction, the first scanning line and the second scanning line are connected with the first grid electrode and the second grid electrode, and scanning is conducted in the scanning direction from the first scanning line to the second scanning line. The direction of the first source electrode pointing to the first drain electrode is the same as the direction of the second source electrode pointing to the second drain electrode. According to the scheme, the head shaking line phenomenon can be reduced, and the product taste of the display panel is improved.

Description

Technical Field

[0001] The present application belongs to the field of display technology, and specifically relates to a display panel and a display device. Background Art

[0002] In the field of display technology, display panels and display devices are usually driven by thin film transistors. With the development of display technology, in order to reduce costs, a half-source (also called dual gate) driving method is usually used to drive the pixel array. The dual gate driving method can halve the number of data lines compared to the number of data lines in the traditional driving method, thereby reducing the number of source driving circuits, and then reducing the number of driving chips and reducing costs.

[0003] However, existing dual-gate drive display panels are prone to vertical stripe defects such as head shakes. Summary of the invention

[0004] The purpose of the present application is to solve the problem of head shaking wrinkles occurring in a dual-gate drive display panel in the prior art.

[0005] In a first aspect, the present application provides a display panel, comprising a substrate and pixel units formed on the substrate, wherein a plurality of the pixel units are arranged in an array in row and column directions, and each of the pixel units comprises: a first pixel sub-unit, comprising a plurality of first sub-pixels sequentially arranged in sequence in the row direction, wherein the first sub-pixels each comprise a first transistor, wherein the first transistor comprises a first gate, a first source, a first drain and a first semiconductor layer, wherein the first source and the first drain are respectively overlapped at opposite ends of the first semiconductor layer, and an orthographic projection of the first semiconductor layer on the substrate and an orthographic projection of the first gate on the substrate have at least a partial overlapping area; and a second pixel sub-unit, wherein the second pixel unit is sequentially arranged in sequence in the row direction and is spaced apart from the first pixel sub-unit, and wherein the second pixel unit comprises a plurality of second sub-pixels sequentially arranged in sequence and spaced apart from each other in the row direction. The pixel, the second sub-pixel includes a second transistor, the second transistor includes a second gate, a second source, a second drain and a second semiconductor layer, the second source and the second drain are respectively overlapped at opposite ends of the second semiconductor layer, and the orthographic projection of the second semiconductor layer on the substrate and the orthographic projection of the second gate on the substrate have at least a partial overlapping area; wherein, between two adjacent rows of the pixel units, a first scanning line and a second scanning line are arranged in sequence in the column direction, the first scanning line and the second scanning line are extended in the row direction, the first scanning line is connected to the first gate, the second scanning line is connected to the second gate, and the scanning direction is scanned in the direction from the first scanning line to the second scanning line; the direction in which the first source points to the first drain is the same as the direction in which the second source points to the second drain.

[0006] In an exemplary embodiment of the present application, the first source includes a first part and a second part connected to each other, the first part points to the first drain, the orthographic projection of the first part on the substrate overlaps with the orthographic projection of the first semiconductor layer on the substrate, and the second part is arranged on a side of the first part away from the first drain; the second source includes a third part and a fourth part connected to each other, the third part points to the second drain, the orthographic projection of the third part on the substrate overlaps with the orthographic projection of the second semiconductor layer on the substrate, and the fourth part is arranged on a side of the third part away from the second drain.

[0007] In an exemplary embodiment of the present application, the first sub-pixel further includes a first common electrode, the first common electrode includes a first main frame, a first extended electrode block, and a first extension line connecting the first main frame and the first extended electrode block, the first common electrodes of adjacent first sub-pixels are connected through the first main frame, and the orthographic projection of the first extended electrode block on the substrate substrate and the orthographic projection of the second portion on the substrate substrate have at least an overlapping area; the second sub-pixel further includes a second common electrode, the second common electrode includes a second main frame, a second extended electrode block, and a second extension line connecting the second main frame and the second extended electrode block, the second common electrodes of adjacent second sub-pixels are connected through the second The first main frame is connected to the first main frame, the second main frame is arranged in sequence with the first main frame in the row direction and is connected to each other, and the orthographic projection of the second extended electrode block on the substrate substrate and the orthographic projection of the fourth part on the substrate substrate have at least an overlapping area; wherein the first main frame and the second main frame between adjacent first sub-pixels and second sub-pixels are connected and extended in the same row direction; the first extended electrode block is arranged on one side of the first main frame, and the first extension line is extended in the direction from the first scanning line to the second scanning line; the second extended electrode block is arranged on one side of the second main frame, and the second extension line is extended in the direction from the second scanning line to the first scanning line.

[0008] In an exemplary embodiment of the present application, the orthographic projection of the first extension line on the base substrate has no overlapping area with the orthographic projections of the first scanning line and the second scanning line on the base substrate; the orthographic projection of the second extension line on the base substrate has no overlapping area with the orthographic projections of the first scanning line and the second scanning line on the base substrate.

[0009] In an exemplary embodiment of the present application, the first sub-pixel further includes a first pixel electrode, the first pixel electrode includes a first electrode block, a second electrode block and a first electrode line for connecting the first electrode block and the second electrode block, the orthographic projection of the first electrode block on the substrate overlaps with the orthographic projection of the second part on the substrate, and the first electrode block is electrically connected to the second part through a first via hole; the second electrode block includes a first column trunk extending in the column direction and a first row trunk extending in the row direction, the first column trunk and the first row trunk intersect and divide the second electrode block into four first slit electrode parts, the first slit electrode part has a plurality of electrode branches arranged at intervals, and two adjacent electrode branches in the first slit electrode part A slit is formed between the two portions; the second sub-pixel also includes a second pixel electrode, the second pixel electrode includes a third electrode block, a fourth electrode block and a second electrode line for connecting the third electrode block and the fourth electrode block, the orthographic projection of the third electrode block on the substrate overlaps with the orthographic projection of the fourth portion on the substrate, and the third electrode block is electrically connected to the fourth portion through a second via hole; the fourth electrode block includes a second column trunk extending in the column direction and a second row trunk extending in the row direction, the second column trunk and the second row trunk intersect and divide the fourth electrode block into four second slit electrode portions, the second slit electrode portion has a plurality of electrode branches arranged at intervals, and the slit is formed between two adjacent electrode branches in the second slit electrode portion.

[0010] In an exemplary embodiment of the present application, the display panel further includes a data line extending in the column direction, the data line being connected to the first drain or the second drain; the first scan line includes a first connection line, a second connection line and a third connection line, the first connection line and the third connection line being extended in the row direction, and the first connection line and the third connection line being parallel to each other, one end of the second connection line being connected to the first connection line, and the other end of the second connection line being connected to the third connection line, the second connection line being extended in the column direction, the orthographic projection of the second connection line on the substrate being located between the orthographic projection of the data line on the substrate and the orthographic projection of the first electrode block on the substrate, and the third connection line being away from the second connection line one end of the fifth connection line is connected to the first gate; the second scan line includes a fourth connection line, a fifth connection line and a sixth connection line, the fourth connection line and the sixth connection line are extended in the row direction, and the fourth connection line is parallel to the first connection line, the sixth connection line is parallel to the third connection line, one end of the fifth connection line is connected to the fourth connection line, and the other end of the fifth connection line is connected to the sixth connection line, the fifth connection line is extended in the column direction and is parallel to the second connection line, the orthographic projection of the fifth connection line on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the third electrode block on the substrate, and the end of the sixth connection line away from the fifth connection line is connected to the second gate.

[0011] In an exemplary embodiment of the present application, the length of the second electrode line in the column direction is greater than the length of the first electrode line in the column direction; the first pixel electrode also includes a first electrode strip, the first electrode strip is arranged on a side of the second electrode block away from the first electrode line, and extends in a direction away from the second electrode block, and the first electrode strip and the first electrode line are located on the same column; the second pixel electrode also includes a second electrode strip, the second electrode strip is arranged on a side of the fourth electrode block away from the second electrode line, and extends in a direction away from the fourth electrode block, and the second electrode strip and the second electrode line are located on the same column; wherein the sum of the lengths of the first electrode strip and the first electrode line in the column direction is equal to the sum of the lengths of the second electrode strip and the second electrode line in the column direction.

[0012] In an exemplary embodiment of the present application, the first source electrode also includes a first overlapping portion, the first overlapping portion is connected to the second portion, and the orthographic projection of the first overlapping portion on the substrate substrate and the orthographic projection of the first extension line on the substrate substrate have an overlapping area; the second source electrode also includes a second overlapping portion, the second overlapping portion is connected to the fourth portion, and the orthographic projection of the second overlapping portion on the substrate substrate and the orthographic projection of the second extension line on the substrate substrate have an overlapping area.

[0013] In an exemplary embodiment of the present application, the display panel also includes a data line, and the data line includes a data main line, a first data branch line and a second data branch line, the first data branch line and the second data branch line are both connected to the data main line, the first data branch line is used to connect to the first drain of the Nth (N≥1) first sub-pixel in the first pixel sub-unit, and the second data branch line is used to connect to the second drain of the Nth (N≥1) second sub-pixel in the second pixel sub-unit; and / or the colors of the first sub-pixels in the same column are the same; the colors of the second sub-pixels in the same column are the same.

[0014] A second aspect of the present application provides a display device, comprising: a flexible circuit board; a chip-on-chip film connected to the flexible circuit board; and a display panel as described in any one of the above items, wherein the display panel is electrically connected to the flexible circuit board via the chip-on-chip film.

[0015] The display panel and display device of the present application have at least the following beneficial effects:

[0016] The display panel of the present application includes a substrate and a pixel unit, wherein the plurality of pixel units are arranged in an array in the row direction and the column direction, each pixel unit includes a first pixel sub-unit and a second pixel sub-unit arranged adjacently, the first pixel sub-unit includes a plurality of first sub-pixels, each of the first sub-pixels includes a first transistor, the first transistor includes a first gate, a first source, a first drain and a first semiconductor layer. The second pixel sub-unit includes a plurality of second sub-pixels, each of the second sub-pixels includes a second transistor, the second transistor includes a second gate, a second source, a second drain and a second semiconductor layer. Among them, a first scanning line and a second scanning line are arranged in sequence in the column direction between two adjacent rows of pixel units, the first scanning line and the second scanning line are extended in the row direction, the first scanning line is connected to the first gate, and the second scanning line is connected to the second gate. The scanning direction is scanned from the first scanning line to the second scanning line, so that the second sub-pixel is first coupled by the first gate in the first sub-pixel, and then charged with its own preset signal, so that the charging effect of the second pixel electrode is not affected by the parasitic capacitance of the adjacent first sub-pixel, and the influence of the feedthrough voltage (Feedthrough△V) is reduced, the brightness difference between adjacent sub-pixels is small, and the shaking head wrinkles can be significantly improved.

[0017] In addition, the direction in which the first source points to the first drain is the same as the direction in which the second source points to the second drain, that is, the channel bending direction of the first transistor is the same as the channel bending direction of the second transistor. The parasitic capacitance in the first sub-pixel and the parasitic capacitance in the second sub-pixel will not be different due to process reasons, thereby reducing the difference in pixel brightness under the same gray scale, further reducing the shaking head pattern phenomenon, and improving the product taste of the display panel.

[0018] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0019] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0021] Figure 1 A schematic diagram of the planar structure of the display panel provided in Embodiments 1 to 4 of the present application is shown.

[0022] Figure 2 A schematic structural diagram of the first sub-pixel and the second sub-pixel provided in Embodiment 1 or Embodiment 4 of the present application is shown.

[0023] Figure 3 A schematic structural diagram of the data line, the first / second source electrode, the first / second drain electrode and the first / second semiconductor layer provided in the first, second or fourth embodiment of the present application, which are arranged on a substrate, is shown.

[0024] Figure 4 A schematic structural diagram of the first / second scanning lines and the first / second common electrode lines provided in the first, second or fourth embodiment of the present application are arranged on a base substrate is shown.

[0025] Figure 5 A schematic diagram of the structure of the first pixel electrode and the second pixel electrode provided in Embodiment 1 or Embodiment 4 of the present application is shown.

[0026] Figure 6 A schematic cross-sectional structure diagram of a storage capacitor formed by a common electrode and a first / second pixel electrode provided in Embodiments 1 to 4 of the present application is shown.

[0027] Figure 7 A schematic cross-sectional structure diagram of a storage capacitor formed by the first / second source and the pixel electrode provided in Embodiments 1 to 4 of the present application is shown.

[0028] Figure 8 A schematic diagram of the structure in which the first pixel electrode provided in the second embodiment or the fourth embodiment of the present application is provided with a first electrode strip and the second pixel electrode is provided with a second electrode strip is shown.

[0029] Fig. 9 A schematic diagram of the structure of the pixel electrode provided in the second or fourth embodiment of the present application is shown.

[0030] Fig.10 A schematic structural diagram showing that the first / second source provided in the third or fourth embodiment of the present application also includes a first / second overlapping portion.

[0031] Fig.11 A schematic diagram of the structure of the first / second source and the first / second drain provided in the third or fourth embodiment of the present application is shown.

[0032] Fig.12 It shows a structural schematic diagram in which the first pixel electrode provided in the third or fourth embodiment of the present application further includes a fifth / sixth electrode block.

[0033] Description of reference numerals:

[0034] 10. Display device; 100. Display panel; 110. Base substrate; 120. Pixel unit;

[0035] 121, first pixel subunit; 1210, first subpixel;

[0036] 1211, a first transistor; 12110, a first gate; 12111, a first semiconductor layer; 12112, a first source; 12112a, a first portion; 12112b, a second portion; 12112c, a first overlapping portion; 12113, a first drain;

[0037] 1212, first common electrode; 12120, first main frame; 121200, annular frame; 121201, second electrode trunk; 12121, first extended electrode block; 12122, first extension line;

[0038] 1213, first pixel electrode; 12130, first electrode block; 12131, second electrode block; 121310, first column trunk; 121311, first row trunk; 12132, first electrode line; 12133, first electrode strip; 12134, fifth electrode block;

[0039] 122, second pixel subunit; 1220, second subpixel;

[0040] 1221, a second transistor; 12210, a second gate; 12211, a second semiconductor layer; 12212, a second source; 12212a, a third portion; 12212b, a fourth portion; 12212c, a second overlapping portion; 12213, a second drain;

[0041] 1222, second common electrode; 12220, second main frame; 12221, second extended electrode block; 12222, second extended line;

[0042] 1223, second pixel electrode; 12230, third electrode block; 12231, fourth electrode block; 122310, second column trunk; 122311, second row trunk; 12232, second electrode line; 12233, second electrode strip; 12234, sixth electrode block;

[0043] 130, first scanning line; 131, first connecting line; 1310, first extending portion; 132, second connecting line; 133, third connecting line;

[0044] 140, second scanning line; 141, fourth connecting line; 1410, second extending portion; 142, fifth connecting line; 143, sixth connecting line;

[0045] 150, first via hole; 160, second via hole; 170, data line; 171, data main line; 172, first data branch line; 173, second data branch line; 200, flexible circuit board; 300, flip chip film. DETAILED DESCRIPTION

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0047] In this application, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0048] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0049] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0050] Embodiment 1

[0051] Figure 1 A schematic diagram of the planar structure of the display panel provided in the present application is shown.

[0052] See also Figure 1 As shown, the first embodiment of the present application provides a display panel 100 , and the display panel 100 may include a base substrate 110 and a plurality of pixel units 120 .

[0053] The base substrate 110 can be a glass substrate, but can also be a substrate made of other materials, such as PI material and the like.

[0054] See also Figure 1 As shown, a plurality of pixel units 120 may be arranged in an array along a row direction X and a column direction Y on a substrate 110. Each pixel unit 120 includes a first pixel subunit 121 and a second pixel subunit 122. The first pixel subunit 121 and the second pixel subunit 122 have the same structure, and the first pixel subunit 121 and the second pixel subunit 122 are sequentially arranged in the row direction X.

[0055] In some embodiments of the present application, the first pixel sub-unit 121 and the second pixel sub-unit 122 both include a plurality of sub-pixels, that is, both include the same number of sub-pixels.

[0056] For example, the first pixel sub-unit 121 includes six first sub-pixels 1210, and the six first sub-pixels 1210 are arranged in sequence along the row direction X. The six first sub-pixels 1210 may include two red first sub-pixels, two green first sub-pixels, and two blue first sub-pixels. Correspondingly, the second pixel sub-unit 122 may also include six second sub-pixels 1220, and the six second sub-pixels 1220 are arranged in sequence along the row direction X. The six second sub-pixels 1220 may include two red second sub-pixels, two green second sub-pixels, and two blue second sub-pixels.

[0057] For example, the arrangement of the six first sub-pixels 1210 in the first pixel sub-unit 121 may be a red first sub-pixel, a green first sub-pixel, a blue first sub-pixel, a red first sub-pixel, a green first sub-pixel, and a blue first sub-pixel. The arrangement of the six second sub-pixels 1220 in the second pixel sub-unit 122 may be the same as the arrangement of the six first sub-pixels 1210 in the first pixel sub-unit 121, so as to ensure that there is no color difference and to ensure the display effect of the display panel 100. For example, the arrangement of the six second sub-pixels 1220 in the second pixel sub-unit 122 may be a red second sub-pixel, a green second sub-pixel, a blue second sub-pixel, a red second sub-pixel, a green second sub-pixel, and a blue second sub-pixel.

[0058] It can be understood that the red first / second sub-pixel, the green first / second sub-pixel and the blue first / second sub-pixel correspond to sub-pixels emitting corresponding color light. For example, the red first / second sub-pixel emits red light, the green first / second sub-pixel emits green light, and the blue first / second sub-pixel emits blue light.

[0059] Figure 2 A schematic structural diagram of a first sub-pixel and a second sub-pixel provided in an embodiment of the present application is shown. Figure 3 A schematic structural diagram of a data line, a first / second source electrode, a first / second drain electrode, and a first / second semiconductor layer provided in an embodiment of the present application, which are arranged on a substrate, is shown. Figure 4 A schematic structural diagram showing the first / second scanning lines and the first / second common electrode lines are arranged on a base substrate. Figure 5 A schematic structural diagram of a first pixel electrode and a second pixel electrode provided in an embodiment of the present application is shown. Figure 6 A schematic cross-sectional structure diagram of a storage capacitor formed by a common electrode and a first / second pixel electrode provided in an embodiment of the present application is shown. Figure 7 A schematic cross-sectional structure diagram of a storage capacitor formed by a first / second source electrode and a pixel electrode provided in an embodiment of the present application is shown.

[0060] in, Figure 2 The related structure of the first sub-pixel 1210 and the second sub-pixel 1220 provided by the present application is shown. Figures 2 to 4 As shown, each first sub-pixel 1210 includes a first transistor 1211. The first transistor 1211 includes a first gate electrode 12110, a first semiconductor layer 12111, and a first source electrode 12112 and a first drain electrode 12113 disposed in the same layer. A gate insulating layer (not shown in the figure) is disposed between the first gate electrode 12110 and the first semiconductor layer 12111 to insulate the first gate electrode 12110 from the first semiconductor layer 12111.

[0061] It should be noted that the orthographic projection of the first semiconductor layer 12111 on the base substrate 110 may be located within the orthographic projection of the first gate 12110 on the base substrate 110. The first source 12112 and the first drain 12113 are respectively overlapped on the source and drain doped regions of the first semiconductor layer 12111; that is, the first source 12112 and the first drain 12113 are respectively overlapped on the opposite ends of the first semiconductor layer 12111.

[0062] Accordingly, see Figures 2 to 4 As shown, each second sub-pixel 1220 includes a second transistor 1221. The second transistor 1221 includes a second gate electrode 12210, a second semiconductor layer 12211, and a second source electrode 12212 and a second drain electrode 12213 disposed in the same layer. A gate insulating layer is disposed between the second gate electrode 12210 and the second semiconductor layer 12211 to insulate the second gate electrode 12210 from the second semiconductor layer 12211.

[0063] It should be noted that the orthographic projection of the second semiconductor layer 12211 on the base substrate 110 may be located within the orthographic projection of the second gate 12210 on the base substrate 110. The second source 12212 and the second drain 12213 are respectively overlapped on the source and drain doping regions of the second semiconductor layer 12211; that is, the second source 12212 and the second drain 12213 are respectively overlapped on the opposite ends of the second semiconductor layer 12211.

[0064] In addition, the first gate 12110, the second gate 12210, and the first scan line 130 and the second scan line 140 described below are arranged on the same layer, the first source 12112, the first drain 12113, the second source 12212, the second drain 12213, and the data line 170 described below are arranged on the same layer, and the first semiconductor layer 12111 and the second semiconductor layer 12211 are arranged on the same layer.

[0065] In addition, in the present application, "same-layer arrangement" refers to the use of the same film-forming process to form a film layer for forming a specific pattern, and then using the same mask to form a layer structure through a single patterning process. That is, one patterning process corresponds to a mask (also called a photomask). Depending on the specific pattern, a single patterning process may include multiple exposure, development or etching processes, and the specific pattern in the formed layer structure may be continuous or discontinuous, and these specific patterns may also be at different heights or have different thicknesses. This simplifies the manufacturing process, saves manufacturing costs, and improves production efficiency.

[0066] It is worth mentioning that see Figure 2 As shown, the channel bending direction of the first transistor 1211 in the first sub-pixel 1210 is the same as the channel bending direction of the second transistor 1221 in the second sub-pixel 1220, that is, the direction of the first source 12112 pointing to the first drain 12113 is the same as the direction of the second source 12212 pointing to the second drain 12213. In this way, the parasitic capacitance Cgs generated between the first source 12112 and the first gate 12110 and the parasitic capacitance Cgs generated between the second source 12212 and the second gate 12210 will not differ due to process reasons, ensuring that the brightness between adjacent sub-pixels at the same gray scale remains consistent, reducing the appearance of head shake lines, and improving the product taste of the display panel 100.

[0067] For example, the direction in which the first source 12112 points to the first drain 12113 and the direction in which the second source 12212 points to the second drain 12213 are designed to be the same direction. When the first / second semiconductor layer is offset to the left or right due to process reasons, the area covered by the first semiconductor layer 12111 in the first sub-pixel 1210 and the area covered by the first semiconductor layer 12111 in the second sub-pixel 1220 are the same. In other words, the parasitic capacitance Cgs generated by the first source 12112 and the first gate 12110 is the same as the parasitic capacitance Cgs generated by the second source 12212 and the second gate 12210, ensuring that the brightness of pixels under the same gray scale remains consistent, reducing the appearance of head shake lines, and improving the product taste of the display panel 100.

[0068] In some embodiments of the present application, see Figure 1 and Figure 2 As shown, a first scan line 130 and a second scan line 140 are arranged in sequence and spaced apart in the column direction Y between two adjacent rows of pixel units 120, that is, the first scan line 130 is located above the second scan line 140. And the first scan line 130 and the second scan line 140 are both extended in the row direction X.

[0069] Among them, the first scan line 130 is connected to the first gate 12110 of the first sub-pixel 1210 in the first pixel sub-unit 121 to provide a scan signal to the first gate 12110; the second scan line 140 is connected to the second gate 12210 of the second sub-pixel 1220 in the second pixel sub-unit 122 to provide a scan signal to the second gate 12210.

[0070] That is to say, the scanning signal on the first scanning line 130 controls the first transistor 1211 of the first sub-pixel 1210 in the first pixel sub-unit 121 to turn on or off, and the scanning signal on the second scanning line 140 controls the second transistor 1221 of the second sub-pixel 1220 in the second pixel sub-unit 122 to turn on or off, and both control the sub-pixels in different pixel sub-units respectively.

[0071] The first scanning line 130 and the second scanning line 140 can be made of metal or alloy materials, such as molybdenum, aluminum and titanium, to ensure good electrical conductivity, but are not limited thereto and can also be made of other materials with good electrical conductivity.

[0072] In some embodiments of the present application, the scanning direction in the present application is scanned from the first scanning line 130 to the second scanning line 140, that is, the first transistor 1211 of the first sub-pixel 1210 in the first pixel sub-unit 121 is first turned on, and then the second transistor 1221 of the second sub-pixel 1220 in the second pixel sub-unit 122 is turned on.

[0073] In this way, when the first scan line 130 controls the first transistor 1211 in the first sub-pixel 1210 to turn on, the second sub-pixel 1220 is affected by the parasitic capacitance Cgs of the first source 12112 and the first gate 12110 in the first sub-pixel 1210 to generate a feed-through voltage (Feedthrough△V). However, after scanning the first scan line 130, the second scan line 140 is scanned again, so that the second sub-pixel 1220 is charged with its own preset signal. The final charging effect of the second sub-pixel 1220 will not be affected by the feed-through voltage (Feedthrough△V) generated by the parasitic capacitance Cgs of the first source 12112 and the first gate 12110 in the first sub-pixel 1210, thereby reducing the difference in brightness between the first sub-pixel 1210 and the second sub-pixel 1220, further reducing the shaking head problem of the display panel 100, and improving the display quality of the display panel 100.

[0074] For example, a first scan line 130, a second scan line 140, a third scan line, and a fourth scan line are sequentially arranged from top to bottom. The first scan line 130 and the second scan line 140 are located between two adjacent rows of pixel units 120, and the third scan line and the fourth scan line are located between another two adjacent rows of pixel units 120, and are respectively connected to transistors in different sub-pixels. For example, the first scan line 130 is connected to the first sub-pixel 1210, the second scan line 140 is connected to the second sub-pixel 1220, the third scan line is connected to the third sub-pixel, and the fourth scan line is connected to the fourth sub-pixel. The first sub-pixel 1210 is arranged in the same row and adjacent to the second sub-pixel 1220, the first sub-pixel 1210 is arranged in the same column and adjacent to the third sub-pixel, the third sub-pixel is arranged in the same row and adjacent to the fourth sub-pixel, and the second sub-pixel 1220 is arranged in the same column and adjacent to the fourth sub-pixel.

[0075] The scanning direction is the direction of the first scanning line 130, the second scanning line 140, the third scanning line and the fourth scanning line. When the second scanning line 140 is turned on, the third sub-pixel is affected by the feed-through voltage (Feedthrough△V) generated by the parasitic capacitance Cgs between the gate and the source in the second sub-pixel 1220, but then the third scanning line is turned on, so that the third sub-pixel will be charged with its own preset signal, and the final charging effect of the third sub-pixel is not affected by the feed-through voltage (Feedthrough△V) generated by the parasitic capacitance Cgs between the gate and the source in the second sub-pixel 1220. When the second scan line 140 or the third scan line is turned on, the fourth sub-pixel is affected by the feed-through voltage (Feedthrough△V) generated by the parasitic capacitance Cgs between the source and the gate in the second sub-pixel 1220 and the third sub-pixel, respectively, that is, the fourth sub-pixel is affected by the first feed-through voltage △V1 in the second sub-pixel 1220 and the second feed-through voltage △V2 in the third sub-pixel, but when the fourth scan line is subsequently turned on, the fourth sub-pixel will charge its own preset signal, and the final charging effect of the fourth sub-pixel is not affected by the feed-through voltage (Feedthrough△V) generated by the parasitic capacitance Cgs of the second scan line 140 and the parasitic capacitance Cgs of the third scan line.

[0076] In this way, the novel pixel architecture in the present application is not affected by the feedthrough voltage (Feedthrough△V) generated by the parasitic capacitance Cgs of the adjacent scan lines, thereby reducing the brightness difference between adjacent sub-pixels and thus better reducing the shaking head wrinkle problem.

[0077] In some embodiments of the present application, see Figure 3 As shown, the first source 12112 includes a first portion 12112a and a second portion 12112b connected to each other, the first portion 12112a points to the first drain 12113, and the orthographic projection of the first portion 12112a on the base substrate 110 overlaps with the orthographic projection of the first semiconductor layer 12111 on the base substrate 110, that is, the first portion 12112a overlaps one end of the first semiconductor layer 12111. The second portion 12112b is disposed on a side of the first portion 12112a away from the first drain 12113.

[0078] Accordingly, see Figure 3As shown, the second source 12212 includes a third portion 12212a and a fourth portion 12212b connected to each other, the third portion 12212a points to the second drain 12213, and the orthographic projection of the third portion 12212a on the base substrate 110 overlaps with the orthographic projection of the second semiconductor layer 12211 on the base substrate 110, that is, the third portion 12212a overlaps one end of the second semiconductor layer 12211. The fourth portion 12212b is disposed on a side of the third portion 12212a away from the second drain 12213.

[0079] In some embodiments of the present application, see Figure 4 As shown, the first sub-pixel 1210 further includes a first common electrode 1212 , and the first common electrode 1212 can be disposed in the same layer as the first scan line 130 , the second scan line 140 , the first gate 12110 , and the second gate 12210 .

[0080] Among them, see Figure 4 As shown, the first common electrode 1212 includes a first main frame 12120, a first extension electrode block 12121, and a first extension line 12122 connecting the first main frame 12120 and the first extension electrode block 12121. The first main frames 12120 of adjacent first sub-pixels 1210 are connected, that is, the first main frames 12120 in adjacent first sub-pixels 1210 are extended in the row direction X. The orthographic projection of the first extension electrode block 12121 on the base substrate 110 and the orthographic projection of the second portion 12112b on the base substrate 110 have at least an overlapping area, which increases the storage capacitance Cst of the first sub-pixel 1210, thereby ensuring that the first sub-pixel 1210 has sufficient storage capacitance Cst to maintain the voltage holding capability of the first sub-pixel 1210 and reduce the influence of the parasitic capacitance Cgs generated by the scanning line itself and the parasitic capacitance Cpd between the data line 170 and the pixel electrode described below on the first sub-pixel 1210.

[0081] For example, see Figure 2 As shown, the orthographic projection of the first extended electrode block 12121 on the base substrate 110 completely overlaps with the orthographic projection of the second portion 12112b on the base substrate 110, and the first extended electrode block 12121 and the second portion 12112b of the first source electrode 12112 form a storage capacitor Cst to ensure that the first sub-pixel 1210 has sufficient storage capacitor Cst to maintain the voltage maintenance capability of the first sub-pixel 1210 and reduce the influence of the parasitic capacitance Cgs generated by its own scanning line and the parasitic capacitance Cpd between the data line 170 and the pixel electrode described below on the first sub-pixel 1210.

[0082] Accordingly, see Figure 4As shown, the second sub-pixel 1220 further includes a second common electrode 1222 , and the second common electrode 1222 can be disposed in the same layer as the first scan line 130 , the second scan line 140 , the first gate 12110 , and the second gate 12210 .

[0083] Among them, see Figure 4 As shown, the second common electrode 1222 includes a second main frame 12220, a second extended electrode block 12221, and a second extended line 12222 connecting the second main frame 12220 and the second extended electrode block 12221, and the second main frames 12220 of adjacent second sub-pixels 1220 are connected, that is, the second main frames 12220 in adjacent second sub-pixels 1220 are extended in the row direction X. In addition, the second main frame 12220 in the second sub-pixel 1220 is connected to the first main frame 12120 in the first sub-pixel 1210, and the second main frame 12220 and the first main frame 12120 are sequentially arranged in the row direction X.

[0084] The orthographic projection of the first extended electrode block 12121 on the base substrate 110 and the orthographic projection of the fourth part 12212b on the base substrate 110 have at least an overlapping area, thereby increasing the storage capacitance Cst of the second sub-pixel 1220, thereby ensuring that the second sub-pixel 1220 has sufficient storage capacitance Cst to maintain the voltage maintenance capability of the second sub-pixel 1220 and reduce the influence of the parasitic capacitance Cgs generated by its own scanning line and the parasitic capacitance Cpd between the data line 170 and the pixel electrode described below on the second sub-pixel 1220.

[0085] For example, see Figure 2 As shown, the orthographic projection of the second extended electrode block 12221 on the base substrate 110 completely overlaps with the orthographic projection of the fourth portion 12212b on the base substrate 110, and the second extended electrode block 12221 and the fourth portion 12212b of the second source electrode 12212 form a storage capacitor Cst to ensure that the second sub-pixel 1220 has sufficient storage capacitor Cst to maintain the sustaining voltage capability of the second sub-pixel 1220 and reduce the influence of the parasitic capacitor Cgs generated by the scanning line itself and the parasitic capacitor Cpd between the data line 170 and the pixel electrode described below on the second sub-pixel 1220. In addition, the storage capacitor Cst is formed by the second extended electrode block 12221 and the fourth portion 12212b, so that the storage capacitor Cst of the second sub-pixel 1220 is the same as the storage capacitor Cst of the first sub-pixel 1210, reducing the difference in parasitic capacitance between adjacent sub-pixels, thereby reducing the difference in brightness between adjacent sub-pixels.

[0086] In some embodiments of the present application, see Figure 2 and Figure 4As shown, the first extended electrode block 12121 and the first extended line 12122 and the second extended electrode block 12221 and the second extended line 12222 are respectively located on different sides of the main frame to avoid overlap between the extended electrode blocks and the extended lines and the first scan line 130 and the second scan line 140, and to reasonably arrange the first common electrode 1212, the second common electrode 1222, the first scan line 130 and the second scan line 140.

[0087] For example, see Figure 2 As shown, the first extension electrode block 12121 and the first extension line 12122 are located below the first main frame 12120, and the second extension electrode block 12221 and the second extension line 12222 are located above the second main frame 12220. In this way, the first source electrode 12112 in the first sub-pixel 1210 corresponds to the first extension electrode block 12121 of the first common electrode 1212 corresponding to itself, and the second source electrode 12212 in the second sub-pixel 1220 corresponds to the second extension electrode block 12221 of the second common electrode 1222 adjacent to it in the column direction Y, so that the second extension electrode block 12221 and the second extension line 12222 will not overlap with the first scan line 130 and the second scan line 140.

[0088] In some embodiments of the present application, the first extension line 12122 scans in the direction from the first scan line 130 to the second scan line 140, that is, it is extended from top to bottom, and the orthographic projection of the first extension line 12122 on the base substrate 110 has no overlapping area with the first scan line 130 and the second scan line 140, so as to avoid the first scan line 130 and the second scan line 140. The second extension line 12222 scans in the direction from the second scan line 140 to the first scan line 130, that is, it is extended from bottom to top, and the orthographic projection of the second extension line 12222 on the base substrate 110 has no overlapping area with the first scan line 130 and the second scan line 140, so as to avoid the first scan line 130 and the second scan line 140.

[0089] In some embodiments of the present application, see Figure 2 and Figure 5 As shown, the first sub-pixel 1210 further includes a first pixel electrode 1213 . The first pixel electrode 1213 may be connected to the first source electrode 12112 through a first via hole 150 , so that a data signal on a data line 170 described below is written into the first pixel electrode 1213 .

[0090] See also Figure 2 and Figure 5As shown, the second sub-pixel 1220 further includes a second pixel electrode 1223 . The second pixel electrode 1223 may be connected to the second source electrode 12212 through a second via hole 160 , so that a data signal on the data line 170 described below is written into the second pixel electrode 1223 .

[0091] The first pixel electrode 1213 and the second pixel electrode 1223 of the embodiment of the present application may be transparent electrodes. For example, they may be made of ITO (indium tin oxide) material to improve light transmittance, but are not limited thereto and may also be made of other transparent conductive materials.

[0092] For example, see Figure 7 As shown, the first pixel electrode 1213 may be formed after the first source 12112 and the first drain 12113 of the first transistor 1211 are formed, and the second pixel electrode 1223 may be formed after the second source 12212 and the second drain 12213 of the second transistor 1221 are formed. An insulating layer may be provided between the first pixel electrode 1213 and the second pixel electrode 1223 and the metal layer where the source and drain of the transistor are located, and the first pixel electrode 1213 may be connected to the first source 12112 of the first transistor 1211 through a first via hole 150 penetrating the insulating layer, and the second pixel electrode 1223 may be connected to the second source 12212 of the second transistor 1221 through a second via hole 160 penetrating the insulating layer.

[0093] Among them, see Figure 5 As shown, the first pixel electrode 1213 includes a first electrode block 12130, a second electrode block 12131, and a first electrode line 12132 for connecting the first electrode block 12130 and the second electrode block 12131. The first electrode block 12130 is electrically connected to the second portion 12112b of the first source electrode 12112 through the first via hole 150, so that the data signal on the second portion 12112b is transmitted to the second electrode block 12131 through the first via hole 150, the first electrode block 12130, and the first electrode line 12132, so as to control the deflection angle of the liquid crystal molecules in the display panel 100.

[0094] See also Figure 2 As shown, the orthographic projection of the first electrode block 12130 on the base substrate 110 overlaps with the orthographic projection of the second part 12112b on the base substrate 110 to ensure that the second part 12112b can be electrically connected to the first electrode block 12130 through the first via 150, thereby ensuring signal transmission stability and convenience in opening the first via 150.

[0095] For example, the orthographic projection of the first electrode block 12130 on the base substrate 110 completely overlaps with the orthographic projection of the second portion 12112 b on the base substrate 110 .

[0096] See also Figure 5 As shown, the second electrode block 12131 is a slit electrode, which includes a first column trunk 121310 extending in the column direction Y and a first row trunk 121311 extending in the row direction X. The first column trunk 121310 and the first row trunk 121311 intersect and divide the second electrode block 12131 into four first slit electrode parts (not shown in the figure). The first slit electrode part has a plurality of electrode branches arranged at intervals, and a slit is formed between two adjacent electrode branches in the first slit electrode part.

[0097] Accordingly, see Figure 2 and Figure 5 As shown, the second pixel electrode 1223 includes a third electrode block 12230, a fourth electrode block 12231 and a second electrode line 12232 for connecting the third electrode block 12230 and the fourth electrode block 12231. The third electrode block 12230 is electrically connected to the fourth part 12212b of the second source electrode 12212 through the second via 160, so that the data signal on the fourth part 12212b is transmitted to the fourth electrode block 12231 through the second via 160, the third electrode block 12230 and the second electrode line 12232 to control the deflection angle of the liquid crystal molecules in the display panel 100.

[0098] The orthographic projection of the third electrode block 12230 on the base substrate 110 overlaps with the orthographic projection of the fourth portion 12212b on the base substrate 110 to ensure that the fourth portion 12212b can be electrically connected to the third electrode block 12230 through the second via 160, thereby ensuring signal transmission stability and convenience in opening the second via 160.

[0099] For example, the orthographic projection of the third electrode block 12230 on the base substrate 110 completely overlaps with the orthographic projection of the fourth portion 12212 b on the base substrate 110 .

[0100] See also Figure 5 As shown, the fourth electrode block 12231 is a slit electrode, which includes a second column trunk 122310 extending in the column direction Y and a second row trunk 122311 extending in the row direction X. The second column trunk 122310 and the second row trunk 122311 intersect and divide the fourth electrode block 12231 into four second slit electrode portions (not shown in the figure). The second slit electrode portion has a plurality of electrode branches arranged at intervals, and a slit is formed between two adjacent electrode branches in the second slit electrode portion.

[0101] It is worth mentioning that the storage capacitor Cst in the first sub-pixel 1210 also includes the storage capacitor formed by the second electrode block 12131 and the first main frame 12120. The storage capacitor in the second sub-pixel 1220 also includes the storage capacitor formed by the fourth electrode block 12231 and the second main frame 12220.

[0102] The existing common electrode includes a ring-shaped ring frame 121200 and a first electrode trunk and a second electrode trunk 121201 arranged in the ring frame 121200. The first electrode trunk and the second electrode trunk 121201 are perpendicular to each other, and the first electrode trunk is extended along the column direction Y, and the second electrode trunk 121201 is extended along the row direction X. The storage capacitor formed by the existing common electrode and the pixel electrode includes the storage capacitor formed by the first electrode trunk and the second electrode block 12131, the second electrode trunk 121201 and the second electrode block 12131, and the outer edge of the ring frame 121200 and the second electrode block 12131.

[0103] See also Figure 2 As shown, since there is an overlap between the second part 12112b of the first source electrode 12112 and the first extended electrode block 12121, and there is an overlap between the fourth part 12212b of the second source electrode 12212 and the second extended electrode block 12221, the storage capacitance of the first sub-pixel 1210 is increased, and the storage capacitance of the second sub-pixel 1220 is increased. Therefore, the storage capacitance formed by the original first electrode trunk and the second electrode block 12131 and the first electrode trunk and the fourth electrode block 12231 can be removed, that is, the first electrode trunk is removed.

[0104] At this time, the storage capacitor of the first sub-pixel 1210 includes the storage capacitor formed by the second electrode trunk 121201 and the second electrode block 12131, the annular frame 121200 and the second electrode block 12131, and the second portion 12112b and the first extended electrode block 12121. The storage capacitor of the second sub-pixel 1220 includes the storage capacitor formed by the second electrode trunk 121201 and the fourth electrode block 12231, the annular frame 121200 and the fourth electrode block 12231, and the fourth portion 12212b and the second extended electrode block 12221, thereby reducing the arrangement of the first electrode trunk.

[0105] Since there is no obstruction by the main trunk of the first electrode in the common electrode, the pixel aperture ratio of the first sub-pixel 1210 and the second sub-pixel 1220 is increased, the pixel penetration rate is improved, and the product competitiveness is enhanced.

[0106] In addition, since the first electrode trunk is reduced, the width of the first column trunk 121310 in the second electrode block 12131 and the second column trunk 122310 in the fourth electrode block 12231 can be reduced; for example, the width of the first column trunk 121310 and the second column trunk 122310 can be reduced from 8μm to 4μm, thereby improving pixel penetration and enhancing the competitiveness of the display panel 100.

[0107] It is worth mentioning that see Figure 6 and Figure 7 As shown, the second part 12112b and the fourth part 12212b are closer to the base substrate 110 than the second electrode block 12131 and the fourth electrode block 12231. Therefore, for the same overlapping area, the storage capacitor Cst formed by the second part 12112b and the first extended electrode block 12121 is greater than the storage capacitor formed by the pixel electrode and the common electrode, and the storage capacitor Cst formed by the fourth part 12212b and the second extended electrode block 12221 is greater than the storage capacitor formed by the pixel electrode and the common electrode.

[0108] Therefore, the storage capacitance generated by the second portion 12112b and the first extended electrode block 12121 can satisfy the storage capacitance required by the first sub-pixel 1210 , and the storage capacitance generated by the fourth portion 12212b and the second extended electrode block 12221 can satisfy the storage capacitance required by the second sub-pixel 1220 .

[0109] In some embodiments of the present application, see Figure 1 and Figure 3 As shown, the display panel 100 further includes a data line 170 extending in the column direction Y. The data line 170 may be connected to the first drain 12113 of the first transistor 1211, and the data line 170 may be connected to the second drain 12213 of the second transistor 1221, so as to write a data signal to the first source 12112 of the first transistor 1211 and write a data line 170 signal to the second source 12212 of the second transistor 1221.

[0110] Optionally, the data line 170 may be disposed in the same layer as the first source 12112 and the first drain 12113 of the first transistor 1211 and the second source 12212 and the second drain 12213 of the second transistor 1221 .

[0111] The data line 170 may be made of metal or alloy materials, such as molybdenum, aluminum, and titanium, to ensure good conductivity, but is not limited thereto, and may also be made of other materials with good conductivity.

[0112] In some embodiments of the present application, see Figure 4As shown, the first scan line 130 includes a first connection line 131 , a second connection line 132 and a third connection line 133 .

[0113] The first connection line 131 and the third connection line 133 are extended in the row direction X, and the first connection line 131 and the third connection line 133 are parallel to each other; one end of the second connection line 132 is connected to the first connection line 131, and the other end of the second connection line 132 is connected to the third connection line 133, and the second connection line 132 is extended in the column direction Y. The orthographic projection of the second connection line 132 on the base substrate 110 is located between the orthographic projection of the data line 170 on the base substrate 110 and the orthographic projection of the first electrode block 12130 on the base substrate 110, so as to shield the lateral parasitic capacitance Cpd formed between the data line 170 and the first electrode block 12130 and the lateral parasitic capacitance Cpd formed between the first electrode line 12132 and the data line 170, thereby improving the panel crosstalk problem. One end of the third connection line 133 away from the second connection line 132 is connected to the first gate 12110 to transmit a scan signal to the first gate 12110.

[0114] It can be understood that the data signal on the data line 170 is different from the data signal on the first electrode block 12130 and the first electrode line 12132, so that the second connecting line 132 can shield the lateral parasitic capacitance Cpd between the data line 170 and the first electrode block 12130 and the first electrode line 12132 and the data line 170, thereby improving the crosstalk problem.

[0115] Accordingly, see Figure 4 As shown, the second scan line 140 includes a fourth connection line 141 , a fifth connection line 142 and a sixth connection line 143 .

[0116] The fourth connection line 141 and the sixth connection line 143 are extended in the row direction X, and the fourth connection line 141 is parallel to the first connection line 131, the sixth connection line 143 is parallel to the third connection line 133, one end of the fifth connection line 142 is connected to the fourth connection line 141, and the other end of the fifth connection line 142 is connected to the sixth connection line 143. The fifth connection line 142 is extended in the column direction Y and is parallel to the second connection line 132. The orthographic projection of the fifth connection line 142 on the base substrate 110 is located between the orthographic projection of the data line 170 on the base substrate 110 and the orthographic projection of the third electrode block 12230 on the base substrate 110, so as to shield the lateral parasitic capacitance Cpd formed between the data line 170 and the third electrode block 12230 and the lateral parasitic capacitance Cpd formed between the second electrode line 12232 and the data line 170, thereby improving the panel crosstalk problem. One end of the sixth connection line 143 away from the fifth connection line 142 is connected to the second gate 12210 to transmit the parasitic capacitance Cpd of the scan signal to the second gate 12210 to improve the crosstalk problem.

[0117] It can be understood that the data line 170 signal on the data line 170 is different from the data signal on the third electrode block 12230 and the second electrode line 12232, so that the fifth connecting line 142 can shield the lateral parasitic capacitance Cpd between the data line 170 and the third electrode block 12230 and the second electrode line 12232 and the data line 170, thereby improving the crosstalk problem.

[0118] In some embodiments of the present application, see Figure 4 As shown, the first connection line 131 includes a first extension portion 1310, the first extension portion 1310 is extended toward the first extension line 12122, the orthographic projection of the first extension portion 1310 on the substrate 110 is located between the orthographic projection of the first main frame 12120 on the substrate 110 and the orthographic projection of the first extension electrode block 12121 on the substrate 110, and the orthographic projection of the first extension portion 1310 on the substrate 110 and the orthographic projection of the first electrode line 12132 on the substrate 110 have an overlapping area, so as to further improve the storage capacitance Cst of the first sub-pixel 1210. In addition, the first extension portion 1310 can also be used to shield the vertical parasitic capacitance formed by the second portion 12112b and the first main frame 12120, and improve vertical crosstalk.

[0119] Accordingly, see Figure 4As shown, the fourth connecting line 141 includes a second extension portion 1410, and the second extension portion 1410 is extended toward the second extension line 12222. The orthographic projection of the second extension portion 1410 on the base substrate 110 is located between the orthographic projection of the second main frame 12220 on the base substrate 110 and the orthographic projection of the second extension electrode block 12221 on the base substrate 110. The second extension portion 1410 is used to shield the vertical parasitic capacitance formed by the fourth portion 12212b and the second main frame 12220, thereby improving the vertical crosstalk.

[0120] In addition, the orthographic projections of the first connection line 131 and the sixth connection line 143 on the base substrate 110 and the orthographic projections of the second electrode line 12232 on the base substrate 110 have an overlapping area, so as to increase the storage capacitance of the second sub-pixel 1220 .

[0121] It is worth mentioning that the parasitic capacitance Cgs generated by the first gate 12110 and the first source 12112 in the first sub-pixel 1210 will be shielded by the fourth connecting line 141 and the sixth connecting line 143 in the second scanning line 140, thereby weakening the influence of the feed-through voltage (Feedthrough△V) and reducing the brightness difference between sub-pixels, thereby better reducing the shaking head wrinkle problem.

[0122] In addition, the sub-pixels in the same column direction Y have the same color, that is, the first sub-pixels 1210 in the same column have the same color, and the second sub-pixels 1220 in the same column have the same color.

[0123] In some embodiments of the present application, see Figure 1 As shown, the data line 170 includes a data main line 171, a first data branch line 172 and a second data branch line 173. The first data branch line 172 and the second data branch line 173 are both connected to the data main line 171. The first data branch line 172 and the second data branch line 173 are respectively connected to the first drain 12113 in the first sub-pixel 1210 and the second drain 12213 in the second sub-pixel 1220.

[0124] For example, the first data branch line 172 is used to connect to the first drain 12113 of the Nth (N≥1) first sub-pixel 1210 in the first pixel sub-unit 121, and the second data branch line 173 is used to connect to the second drain 12213 of the Nth (N≥1) second sub-pixel 1220 in the second pixel sub-unit 122.

[0125] For example, the first data branch line 172 is used to connect to the first drain 12113 of the first first sub-pixel 1210 in the first pixel sub-unit 121, and the second data branch line 173 is connected to the second drain 12213 of the first second sub-pixel 1220 in the second pixel sub-unit 122. The first data branch line 172 is used to connect to the first drain 12113 of the second first sub-pixel 1210 in the first pixel sub-unit 121, and the second data branch line 173 is connected to the second drain 12213 of the second second sub-pixel 1220 in the second pixel sub-unit 122, and so on.

[0126] In this way, the number of data lines 170 can be reduced, the driving cost can be reduced, and the production cost can be reduced.

[0127] Embodiment 2

[0128] The difference between the second embodiment of the present application and the first embodiment is that the first pixel electrode 1213 further includes a first electrode bar 12133 , and the second pixel electrode 1223 further includes a second electrode bar 12233 .

[0129] Figure 8 A schematic structural diagram is shown in which the first pixel electrode 1213 provided in an embodiment of the present application is provided with a first electrode strip 12133 and the second pixel electrode 1223 is provided with a second electrode strip 12233 . Fig. 9 A schematic structural diagram of a pixel electrode provided in an embodiment of the present application is shown.

[0130] In some embodiments of the present application, see Figure 8 and Fig. 9 As shown, the length of the first electrode line 12132 in the column direction Y is smaller than the length of the second electrode line 12232 in the column direction Y.

[0131] See also Figure 8 and Fig. 9 As shown, the first electrode strip 12133 is arranged on a side of the second electrode block 12131 away from the first electrode line 12132, and is extended in the direction from the second scanning line 140 to the first scanning line 130, that is, the first electrode strip 12133 is extended upward, and the first electrode strip 12133 and the first electrode line 12132 are located in the same column.

[0132] Accordingly, see Figure 8 and Fig. 9 As shown, the second electrode strip 12233 is arranged on a side of the fourth electrode block 12231 away from the second electrode line 12232, and is extended in the direction from the second scanning line 140 to the first scanning line 130, that is, the second electrode strip 12233 is extended upward, and the second electrode strip 12233 and the second electrode line 12232 are located in the same column.

[0133] Among them, see Figure 8 and Fig. 9 As shown, the length of the first electrode strip 12133 is greater than that of the second electrode strip 12233 , and the sum of the lengths of the first electrode strip 12133 and the first electrode line 12132 in the column direction Y is equal to the sum of the lengths of the second electrode strip 12233 and the second electrode line 12232 in the column direction Y.

[0134] It is worth mentioning that the first electrode strips 12133 , the first electrode lines 12132 , the second electrode strips 12233 , and the second electrode lines 12232 have the same width.

[0135] By making the sum of the lengths of the first electrode strips 12133 and the first electrode lines 12132 in the column direction Y equal to the sum of the lengths of the second electrode strips 12233 and the second electrode lines 12232 in the column direction Y, it is possible to ensure that each data line 170 is equally affected by the parasitic capacitance generated by the adjacent pixel electrodes, thereby improving the vertical stripes and crosstalk problems in the vertical direction of the panel and improving the quality of the display panel 100.

[0136] Embodiment 3

[0137] The difference between the third embodiment of the present application and the first or second embodiment is that the storage capacitor of the first sub-pixel 1210 and the storage capacitor of the second sub-pixel 1220 are further increased.

[0138] Fig.10 A schematic structural diagram showing that the first / second source provided by an embodiment of the present application also includes a first / second overlapping portion. Fig.11 A schematic diagram of the structure of the first / second source and the first / second drain provided in an embodiment of the present application is shown. Fig.12 A schematic structural diagram showing that the first / second pixel electrode provided in an embodiment of the present application also includes a fifth / sixth electrode block.

[0139] In some embodiments of the present application, see Figures 10 to 12 As shown, the first source electrode 12112 also includes a first overlapping portion 12112c, and the first overlapping portion 12112c is connected to the second portion 12112b. The first pixel electrode 1213 also includes a fifth electrode block 12134, and the fifth electrode block 12134 is connected to the first electrode block 12130, and the orthographic projection of the fifth electrode block 12134 on the base substrate 110 has an overlapping area with the orthographic projection of the first overlapping portion 12112c on the base substrate 110. The fifth electrode block 12134 is connected to the first overlapping portion 12112c through the first via 150 to receive the data signal on the first source electrode 12112.

[0140] The orthographic projection of the first overlapping portion 12112c on the base substrate 110 overlaps with the orthographic projection of the first extension line 12122 on the base substrate 110 , so that the first overlapping portion 12112c and the first extension line 12122 form a storage capacitor to further enhance the storage capacitance of the first sub-pixel 1210 .

[0141] See also Fig.10 As shown, since the first overlapping portion 12112c and the first extension line 12122 form a storage capacitor to further increase the storage capacitance in the first sub-pixel 1210, the second electrode trunk 121201 in the first main frame 12120 can be cancelled and the width of the first row trunk 121311 can be reduced to further increase the pixel aperture ratio and the pixel penetration rate, thereby improving the market competitiveness of the display panel 100.

[0142] Accordingly, see Figures 10 to 12 As shown, the second source electrode 12212 also includes a second overlapping portion 12212c, and the second overlapping portion 12212c is connected to the fourth portion 12212b. The second pixel electrode 1223 also includes a sixth electrode block 12234, and the sixth electrode block 12234 is connected to the third electrode block 12230, and the orthographic projection of the sixth electrode block 12234 on the base substrate 110 has an overlapping area with the orthographic projection of the second overlapping portion 12212c on the base substrate 110. The sixth electrode block 12234 is connected to the second overlapping portion 12212c through the second via 160 to receive the data signal on the second source electrode 12212.

[0143] The orthographic projection of the second overlapping portion 12212c on the base substrate 110 overlaps with the orthographic projection of the second extension line 12222 on the base substrate 110 , so that the second overlapping portion 12212c and the second extension line 12222 form a storage capacitor to further increase the storage capacitance of the second sub-pixel 1220 .

[0144] Since the second overlapping portion 12212c and the second extension line 12222 form a storage capacitor to further increase the storage capacitance in the second sub-pixel 1220, the second electrode trunk 121201 in the second main frame 12220 can be cancelled and the width of the second row trunk 122311 can be reduced to further increase the pixel aperture ratio and pixel penetration rate, thereby improving the market competitiveness of the display panel 100.

[0145] Optionally, the width of the first row of stems 121311 and the second row of stems 122311 is reduced from 8 μm to 4 μm.

[0146] It is worth mentioning that arranging the first via 150 and the second via 160 at the fifth electrode block 12134 and the sixth electrode block 12234 can make the vias farther away from the pixel electrodes, thereby reducing the influence of the vias on the pixel electrodes in the display area and ensuring the display effect.

[0147] Embodiment 4

[0148] See also Figure 1 As shown, the fourth embodiment of the present application provides a display device 10, which includes a flexible circuit board 200, a chip-on-chip film 300 and a display panel 100 provided by the first, second or third embodiment. The display panel 100 can be electrically connected to the flexible circuit board 200 through the chip-on-chip film 300.

[0149] According to the embodiments of the present application, the specific type of the display device 10 is not particularly limited, and any type of display device 10 commonly used in the art can be used, such as liquid crystal display screens, mobile phones, laptop computers and other mobile devices, watches and other wearable devices, VR devices, etc. Those skilled in the art can make corresponding selections based on the specific purpose of the display device, which will not be repeated here.

[0150] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0151] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A display panel, comprising a base substrate and pixel units formed on the base substrate, wherein a plurality of the pixel units are arranged in an array in a row direction and a column direction, wherein: Each of the pixel units comprises: A first pixel sub-unit includes a plurality of first sub-pixels sequentially arranged in sequence in the row direction, each of the first sub-pixels includes a first transistor, the first transistor includes a first gate, a first source, a first drain and a first semiconductor layer, the first source and the first drain are respectively overlapped at opposite ends of the first semiconductor layer, and an orthographic projection of the first semiconductor layer on the substrate and an orthographic projection of the first gate on the substrate have at least a partial overlapping area; A second pixel subunit is arranged in sequence with the first pixel subunit in the row direction, the second pixel subunit includes a plurality of second subpixels arranged in sequence in the row direction, each of the second subpixels includes a second transistor, the second transistor includes a second gate, a second source, a second drain, and a second semiconductor layer, the second source and the second drain are respectively overlapped at opposite ends of the second semiconductor layer, and an orthographic projection of the second semiconductor layer on the substrate and an orthographic projection of the second gate on the substrate have at least a partial overlapping area; Wherein, a first scan line and a second scan line are arranged in sequence and spaced apart in the column direction between two adjacent rows of pixel units, the first scan line and the second scan line are extended in the row direction, the first scan line is connected to the first gate, the second scan line is connected to the second gate, and the scanning direction is from the first scan line to the second scan line. The direction in which the first source points to the first drain is the same as the direction in which the second source points to the second drain.

2. The display panel according to claim 1, characterized in that: The first source electrode comprises a first part and a second part connected to each other, the first part points to the first drain electrode, an orthographic projection of the first part on the substrate overlaps with an orthographic projection of the first semiconductor layer on the substrate, and the second part is arranged on a side of the first part away from the first drain electrode; The second source includes a third part and a fourth part which are connected to each other, the third part points to the second drain, the orthographic projection of the third part on the substrate overlaps with the orthographic projection of the second semiconductor layer on the substrate, and the fourth part is arranged on a side of the third part away from the second drain.

3. The display panel according to claim 2, characterized in that: The first sub-pixel further includes a first common electrode, the first common electrode includes a first main frame, a first extended electrode block, and a first extended line connecting the first main frame and the first extended electrode block, the first common electrodes of adjacent first sub-pixels are connected through the first main frame, and the orthographic projection of the first extended electrode block on the base substrate and the orthographic projection of the second portion on the base substrate have at least an overlapping area; The second sub-pixel further includes a second common electrode, the second common electrode includes a second main frame, a second extended electrode block, and a second extended line connecting the second main frame and the second extended electrode block, the second common electrodes of adjacent second sub-pixels are connected via the second main frame, the second main frame and the first main frame are sequentially arranged in the row direction and connected to each other, and the orthographic projection of the second extended electrode block on the base substrate and the orthographic projection of the fourth portion on the base substrate have at least an overlapping area; Among them, the first main frame and the second main frame between the adjacent first sub-pixels and the second sub-pixels are connected and extended in the same row direction; the first extended electrode block is arranged on one side of the first main frame, and the first extension line is extended in the direction from the first scanning line to the second scanning line; the second extended electrode block is arranged on one side of the second main frame, and the second extension line is extended in the direction from the second scanning line to the first scanning line.

4. The display panel according to claim 3, characterized in that: The orthographic projection of the first extension line on the substrate has no overlapping area with the orthographic projections of the first scanning line and the second scanning line on the substrate; The orthographic projection of the second extension line on the base substrate has no overlapping area with the orthographic projections of the first scanning line and the second scanning line on the base substrate.

5. The display panel according to claim 3, characterized in that: The first sub-pixel further includes a first pixel electrode, the first pixel electrode includes a first electrode block, a second electrode block and a first electrode line for connecting the first electrode block and the second electrode block, the orthographic projection of the first electrode block on the substrate overlaps with the orthographic projection of the second portion on the substrate, and the first electrode block is electrically connected to the second portion through a first via hole; the second electrode block includes a first column trunk extending in the column direction and a first row trunk extending in the row direction, the first column trunk and the first row trunk intersect and divide the second electrode block into four first slit electrode portions, the first slit electrode portion has a plurality of electrode branches arranged at intervals, and a slit is formed between two adjacent electrode branches in the first slit electrode portion; The second sub-pixel also includes a second pixel electrode, which includes a third electrode block, a fourth electrode block and a second electrode line for connecting the third electrode block and the fourth electrode block, the orthographic projection of the third electrode block on the substrate overlaps with the orthographic projection of the fourth part on the substrate, and the third electrode block is electrically connected to the fourth part through a second via hole; the fourth electrode block includes a second column trunk extending in the column direction and a second row trunk extending in the row direction, the second column trunk and the second row trunk intersect and divide the fourth electrode block into four second slit electrode parts, the second slit electrode part has a plurality of electrode branches arranged at intervals, and the slit is formed between two adjacent electrode branches in the second slit electrode part.

6. The display panel according to claim 5, characterized in that: The display panel further includes a data line extending in the column direction, wherein the data line is connected to the first drain electrode or the second drain electrode; The first scan line includes a first connection line, a second connection line and a third connection line, the first connection line and the third connection line are extended in the row direction, and the first connection line and the third connection line are parallel to each other, one end of the second connection line is connected to the first connection line, and the other end of the second connection line is connected to the third connection line, the second connection line is extended in the column direction, the orthographic projection of the second connection line on the base substrate is located between the orthographic projection of the data line on the base substrate and the orthographic projection of the first electrode block on the base substrate, and one end of the third connection line away from the second connection line is connected to the first gate; The second scan line includes a fourth connection line, a fifth connection line and a sixth connection line, the fourth connection line and the sixth connection line are extended in the row direction, and the fourth connection line is parallel to the first connection line, the sixth connection line is parallel to the third connection line, one end of the fifth connection line is connected to the fourth connection line, and the other end of the fifth connection line is connected to the sixth connection line, the fifth connection line is extended in the column direction and is parallel to the second connection line, the orthographic projection of the fifth connection line on the substrate is located between the orthographic projection of the data line on the substrate and the orthographic projection of the third electrode block on the substrate, and the end of the sixth connection line away from the fifth connection line is connected to the second gate.

7. The display panel according to claim 5, characterized in that: The length of the second electrode line in the column direction is greater than the length of the first electrode line in the column direction; The first pixel electrode further comprises a first electrode strip, which is arranged on a side of the second electrode block away from the first electrode line and extends in a direction away from the second electrode block, and the first electrode strip and the first electrode line are located in the same column; The second pixel electrode further comprises a second electrode strip, which is arranged on a side of the fourth electrode block away from the second electrode line and extends in a direction away from the fourth electrode block, and the second electrode strip and the second electrode line are located in the same column; The sum of the lengths of the first electrode strips and the first electrode lines in the column direction is equal to the sum of the lengths of the second electrode strips and the second electrode lines in the column direction.

8. The display panel according to claim 3, characterized in that: The first source electrode further includes a first overlapping portion, the first overlapping portion is connected to the second portion, and an orthographic projection of the first overlapping portion on the substrate and an orthographic projection of the first extension line on the substrate have an overlapping area; The second source electrode further includes a second overlapping portion, the second overlapping portion is connected to the fourth portion, and an orthographic projection of the second overlapping portion on the base substrate and an orthographic projection of the second extension line on the base substrate have an overlapping area.

9. The display panel according to claim 1, characterized in that: The display panel further includes data lines, the data lines including a data main line, a first data branch line and a second data branch line, the first data branch line and the second data branch line are both connected to the data main line, the first data branch line is used to connect to the first drain of the Nth (N≥1)th first sub-pixel in the first pixel sub-unit, and the second data branch line is used to connect to the second drain of the Nth (N≥1)th second sub-pixel in the second pixel sub-unit; and / or The colors of the first sub-pixels in the same column are the same; the colors of the second sub-pixels in the same column are the same.

10. A display device, characterized in that: include: Flexible circuit boards; A chip-on-chip film connected to the flexible circuit board; The display panel according to any one of claims 1 to 9, wherein the display panel is electrically connected to the flexible printed circuit board via a chip-on-film.

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