Memory system, operating method thereof, memory device, and storage medium

Abstract

The embodiment of the invention provides a memory system and an operation method thereof, a memory device and a storage medium, and the memory system comprises the memory device which comprises a first storage area, a second storage area and a page buffer; the storage units in the first storage area store N-bit data in a first mode, and the storage units in the second storage area store M-bit data in a second mode; one page buffer comprises M latches, and the M latches are respectively used for storing data of M pages corresponding to M storage bits of the storage unit; m and N are positive integers, and N is less than M; the memory controller is coupled with the memory device and is configured to send a first reading instruction, and the first reading instruction comprises page indication information corresponding to current to-be-transferred data when the data in the first storage area is transferred to the second storage area; the memory device is configured to transfer the data to be transferred to a corresponding latch in the page buffer according to the page indication information.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of semiconductor technology, and in particular to a memory system and an operating method thereof, a memory device, and a storage medium. Background Art

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, Not-And (NAND) memory has gradually become a mainstream product in the storage market due to its high storage density, controllable production cost, suitable editing and erasing speed and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and systems thereof. Summary of the invention

[0004] According to a first aspect of an embodiment of the present application, a memory system is provided, comprising: a memory device, comprising a first storage area, a second storage area and a page buffer; a storage unit in the first storage area stores N-bit data in a first mode, and a storage unit in the second storage area stores M-bit data in a second mode; a page buffer comprises M latches, and the M latches are respectively used to store M pages of data corresponding to the M storage bits of the storage unit; M and N are both positive integers, and N<M; a memory controller is coupled to the memory device and configured to: send a first read instruction, the first read instruction includes page indication information corresponding to the current data to be transferred when transferring the data in the first storage area to the second storage area; the memory device is configured to: transfer the data to be transferred to the corresponding latch in the page buffer according to the page indication information.

[0005] In the above solution, the first read instruction includes read start flag information, page indication information, address information of the data row to be read, and read end flag information.

[0006] In the above scheme, the page indication information includes Q bits of binary data, and the Q bits of binary data include 2 Q data states, each data state corresponds to one latch among the M latches; Q is a positive integer.

[0007] In the above scheme, the memory controller is configured to: before sending the first read instruction, generate page indication information indicating the corresponding latches in sequence according to the reading order of the data to be transferred in the first storage area; or, before sending the first read instruction, randomly generate page indication information indicating the corresponding latches for the data to be transferred in the first storage area.

[0008] In the above scheme, the memory controller is further configured to: send a write instruction; the memory device is further configured to: write the data in the corresponding latch in the page buffer to the storage bit corresponding to the storage unit in the second storage area in response to the write instruction.

[0009] In the above scheme, the memory device includes at least one memory chip, the memory chip includes at least one memory plane, the memory plane includes multiple memory blocks, the multiple memory blocks are divided into a first memory area and a second memory area, and the first memory area and the second memory area in one memory plane are coupled to a page buffer.

[0010] In the above scheme, the storage cell includes four data bits, the storage cell in the first storage area stores one bit of data in a first mode, and the storage cell in the second storage area stores four bits of data in a second mode; when the data of 4P storage cells in the first storage area are transferred to P storage cells in the second storage area, the page indication information includes the information of any latch of the four latches of the page buffer corresponding to each P data in the 4P storage cells; P is a positive integer; the page indication information of the page buffer includes two bits of binary data.

[0011] The memory system of any one of the above solutions comprises a universal flash memory device UFS, and the memory device comprises a NAND type memory.

[0012] According to a second aspect of an embodiment of the present application, a memory device is provided, comprising: a memory cell array, comprising a first storage area and a second storage area; the memory cells in the first storage area store N-bit data in a first mode, and the memory cells in the second storage area store M-bit data in a second mode; M and N are both positive integers, and N<M; a peripheral circuit, comprising a page buffer; a page buffer comprises M latches; the M latches are respectively used to store M pages of data corresponding to M storage bits of the memory cell; the peripheral circuit is coupled to the memory cell array and is configured to: receive a first read instruction, the first read instruction includes page indication information corresponding to the current data to be transferred when transferring data in the first storage area to the second storage area; according to the page indication information, transfer the data bits to be transferred to the corresponding latches of the page buffer.

[0013] In the above solution, the first read instruction includes read start flag information, page indication information, address information of the data row to be read, and read end flag information.

[0014] In the above scheme, the memory device includes at least one memory chip, the memory chip includes at least one memory plane, the memory plane includes multiple memory blocks, the multiple memory blocks are divided into a first memory area and a second memory area, and the first memory area and the second memory area in one memory plane are coupled to a page buffer.

[0015] In the above scheme, the storage cell includes four data bits, the storage cell in the first storage area stores one bit of data in a first mode, and the storage cell in the second storage area stores four bits of data in a second mode; when the data of 4P storage cells in the first storage area are transferred to P storage cells in the second storage area, the page indication information includes the information of any latch of the four latches of the page buffer corresponding to each P data in the 4P storage cells; P is a positive integer; the page indication information of the page buffer includes two bits of binary data.

[0016] In the above scheme, the page cache includes a first cache latch corresponding to the first storage area, and a first latch, a second latch, a third latch and a fourth latch corresponding to the second storage area; the peripheral circuit is specifically configured to: in response to a first read instruction, directly send the data in the first cache latch to the first latch, the second latch, the third latch and the fourth latch of the second storage area in sequence according to the page indication information.

[0017] In the above scheme, the page buffer also includes a second cache latch corresponding to the second storage area, and the peripheral circuit is also configured to: receive a second read instruction; the second read instruction includes read start flag information, column address information of data to be read, row address information of data to be read, and read end flag information; in response to the second read instruction, send the data in the first cache latch to the second buffer latch; and send the data in the second buffer latch to the first latch, the second latch, the third latch and the fourth latch of the second storage area in sequence.

[0018] In the above solution, the peripheral circuit is further configured to: receive a write instruction; and in response to the write instruction, write the data in the corresponding latch of the page buffer into the storage bit corresponding to the storage unit in the second storage area.

[0019] According to a third aspect of an embodiment of the present application, a method for operating a memory system is provided, the memory system comprising: a memory device and a memory controller coupled to the memory device; the memory device comprising a first storage area, a second storage area and a page buffer; the storage unit in the first storage area stores N-bit data in a first mode, and the storage unit in the second storage area stores M-bit data in a second mode; a page buffer comprises M latches, the M latches being respectively used to store M pages of data corresponding to the M storage bits of the storage unit; M and N are both positive integers, and N<M; the operating method comprises: the memory controller sends a first read instruction, the first read instruction includes page indication information corresponding to the current data to be transferred when transferring data in the first storage area to the second storage area; the memory device transfers the data to be transferred to the corresponding latch in the page buffer according to the page indication information.

[0020] In the above solution, the first read instruction includes read start flag information, page indication information, address information of the data row to be read, and read end flag information.

[0021] In the above scheme, the page indication information includes Q bits of binary data, and the Q bits of binary data include 2 Q data states, each data state corresponds to one latch among the M latches; Q is a positive integer.

[0022] In the above scheme, the operating method also includes: before sending the first read instruction, the memory controller generates page indication information indicating the corresponding latches in sequence according to the reading order of the data to be transferred in the first storage area; or, before sending the first read instruction, the memory controller randomly generates page indication information indicating the corresponding latches for the data to be transferred in the first storage area.

[0023] In the above scheme, the operation method further includes: the memory controller sends a write instruction; the memory device responds to the write instruction and writes the data in the corresponding latch in the page buffer to the storage bit corresponding to the storage unit in the second storage area.

[0024] In the above scheme, the storage cell includes four data bits, the storage cell in the first storage area stores one bit of data in a first mode, and the storage cell in the second storage area stores four bits of data in a second mode; when the data of 4P storage cells in the first storage area are transferred to P storage cells in the second storage area, the page indication information includes the information of any latch of the four latches of the page buffer corresponding to each P data in the 4P storage cells; P is a positive integer; the page indication information of the page buffer includes two bits of binary data.

[0025] According to a fourth aspect of an embodiment of the present application, a storage medium is provided, on which executable instructions are stored. When the executable instructions are executed, the steps of any one of the operating methods in the above-mentioned schemes can be implemented.

[0026] In each embodiment of the present application, when transferring data in the first storage area to the second storage area, the page indication information in the first read instruction is used to directly move the data in the first storage area to the corresponding latch corresponding to the page in the page buffer, thereby avoiding the data in the first storage area first going to the cache latch in the page buffer and then from the cache latch to the latch corresponding to the page. In other words, each embodiment of the present application saves the step of moving the data from the first storage area to the cache latch in the page buffer, so that the solution of the present application can improve the efficiency of the copy-back program operation of the memory system. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1A schematic diagram of an exemplary system having a memory system according to an embodiment of the present application;

[0028] Figure 2A A schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present application;

[0029] Figure 2B A schematic diagram of an exemplary solid-state drive having a memory system according to an embodiment of the present application;

[0030] Figure 3 A schematic diagram of an exemplary memory device including a peripheral circuit according to an embodiment of the present application;

[0031] Figure 4 A cross-sectional schematic diagram of a memory array including a NAND memory string according to an embodiment of the present application;

[0032] Figure 5 A schematic diagram of an exemplary memory device including a memory cell array and a peripheral circuit according to an embodiment of the present application;

[0033] Fig. 6A A timing diagram of a copy-back read operation of a lower page of a NAND memory according to an embodiment of the present application;

[0034] Figure 6B A timing diagram of a copy-back programming operation of a lower page of a NAND memory according to an embodiment of the present application;

[0035] Figure 6C A timing diagram of a copy-back read operation of a middle page of a NAND memory according to an embodiment of the present application;

[0036] Fig.6D A timing diagram of a copy-back programming operation of a middle page of a NAND memory according to an embodiment of the present application;

[0037] Fig. 7A A timing diagram of a copy-back read operation of page data of a memory system according to an embodiment of the present application;

[0038] Figure 7B A timing diagram of a copy-back programming operation of page data of a memory system according to an embodiment of the present application;

[0039] Figure 7C A timing diagram of a copy-back read operation of page data of a memory system according to another embodiment of the present application;

[0040] Figure 8 A schematic diagram of the correspondence between page indication information of a NAND memory and a page of the NAND memory according to an embodiment of the present application;

[0041] Fig. 9A schematic diagram of a NAND memory according to an embodiment of the present application directly moving page data to a latch of a page buffer through a copy-back procedure operation;

[0042] Fig.10 A schematic diagram of a NAND memory according to another embodiment of the present application directly moving page data to a latch of a page buffer through a copy-back procedure operation;

[0043] Fig.11 A schematic diagram of a NAND memory according to another embodiment of the present application directly moving page data to a latch of a page buffer through a copy-back procedure operation;

[0044] Fig.12 A block diagram of a readable storage medium provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] The technical solution of the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. Although the exemplary implementation method of the present application is shown in the accompanying drawings, it should be understood that the present application can be implemented in various forms and should not be limited by the implementation methods described here. On the contrary, these implementation methods are provided in order to enable a more thorough understanding of the present application and to fully convey the scope of the present application to those skilled in the art.

[0046] The present application is described in more detail in the following paragraphs by way of example with reference to the accompanying drawings. The advantages and features of the present application will become more apparent from the following description and claims. It should be noted that the accompanying drawings are in very simplified form and in non-precise proportions, and are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present application.

[0047] The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present application. When used herein, the singular forms "one", "an" and "said / the" are also intended to include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "consisting of" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0048] It should be noted that the technical solutions described in the embodiments of the present application can be combined arbitrarily without conflict.

[0049] Figure 11 shows a block diagram of an exemplary system with memory according to some aspects of the present application. System 100 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 1 As shown in , system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system on chip (SoC) (e.g., an application processor (AP)) of an electronic device. The host 108 may be configured to send data to the memory device 104 or receive data from the memory device 104.

[0050] The memory device 104 may be any memory as claimed in the present application. As described in detail below, the memory device 104 (e.g., a NAND flash memory (e.g., a three-dimensional (3D) NAND flash memory)) may have reduced leakage current from a drive transistor (e.g., a string driver) coupled to an unselected word line during an erase operation, which allows for further size reduction of the drive transistor.

[0051] According to some embodiments, the memory controller 106 is coupled to the memory device 104 and the host 108, and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in a low duty cycle environment, such as a secure digital (SD) card, a compact flash (CF) card, a universal serial bus (USB) flash drive, or other media for use in electronic devices such as personal computers, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in a high duty cycle environment SSD or embedded multimedia card (eMMC), which is used as a data storage for mobile devices such as smart phones, tablet computers, laptop computers, etc. and enterprise storage arrays.

[0052] The memory controller 106 may be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions regarding data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) regarding data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with an external device (e.g., a host 108) according to a specific communication protocol. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, peripheral component interconnect (PCI) protocol, PCI Express (PCI-E) protocol, advanced technology attachment (ATA) protocol, serial ATA protocol, parallel ATA protocol, small computer mini interface (SCSI) protocol, enhanced small disk interface (ESDI) protocol, integrated drive electronics (IDE) protocol, Firewire protocol, etc.

[0053] The memory controller 106 and one or more memory devices 104 may be integrated into various types of storage devices, for example, included in the same package (eg, a universal flash storage (UFS) package or an eMMC package). That is, the memory system 102 may be implemented and packaged into different types of terminal electronic products.

[0054] In such Figure 2A In one example shown in , the memory controller 106 and the single memory device 104 can be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a processor that connects the memory card 202 to a host (e.g., Figure 1 A memory card connector 204 is coupled to the host 108 in the memory card connector.

[0055] In such Figure 2B In another example shown in , the memory controller 106 and the plurality of memory devices 104 may be integrated into an SSD 206. The SSD 206 may also include a processor that interfaces the SSD 206 with a host (e.g., Figure 1In some implementations, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0056] Figure 3 1 shows a schematic circuit diagram of an exemplary device including a memory array and peripheral circuits according to some aspects of the present application. Here, the memory device 300 may be Figure 1 300. The memory device 300 may include a memory array 301 and a peripheral circuit 302 coupled to the memory array 301. The memory array 301 is taken as a three-dimensional NAND type memory array for illustration, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as a voltage or charge, which depends on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating gate type memory cell including a floating gate transistor, or a charge trapping type memory cell including a charge trapping transistor.

[0057] In some embodiments, each memory cell 306 is a single-level cell (SLC) having two possible storage states and thus can store one bit of data. For example, the first storage state "0" can correspond to a first voltage range, and the second storage state "1" can correspond to a second voltage range. In some embodiments, each memory cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC can store two bits per cell (also referred to as a two-bit storage cell, Double-Level Cell), three bits per cell (also referred to as a three-bit storage cell (Trinary-Level Cell, TLC)), four bits per cell (also referred to as a four-bit storage cell (Quad-Level Cell, QLC)), five bits per cell (also referred to as a five-bit storage cell (Penta-level cell, PLC)), or more than five bits per cell. Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLCs can be programmed to assume one of three possible programming levels from an erased state by writing one of three possible nominal storage values ​​to the cell, a fourth nominal storage value can be used for the erased state.

[0058] like Figure 3 As shown in , each NAND memory string 308 may include a lower select gate (BSG) 310 at its source terminal and an upper select gate (TSG) 312 at its drain terminal. The BSG 310 and the TSG 312 may be configured to activate the selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled by the same source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some embodiments, each NAND memory string 308 is configured to be selected or deselected by applying a select voltage (e.g., higher than the threshold voltage of a transistor having TSG 312) or a deselect voltage (e.g., 0 V) ​​to a corresponding TSG 312 via one or more TSG lines 313 and / or by applying a select voltage (e.g., higher than the threshold voltage of a transistor having BSG 310) or a deselect voltage (e.g., 0 V) ​​to a corresponding BSG 310 via one or more BSG lines 315.

[0059] like Figure 3 As shown in , the NAND memory string 308 can be organized into a plurality of memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, that is, all memory cells 306 on the same memory block 304 are erased at the same time. In order to erase the memory cells 306 in a selected memory block 304, the source lines 314 coupled to the selected memory block 304 and the unselected memory blocks in the same plane as the selected memory block 304 can be biased with an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)). It should be understood that in some examples, the erase operation can be performed at a half-memory block level, at a quarter-memory block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. The memory cells 306 of adjacent NAND memory strings 308 can be coupled by word lines 318, which can be biased with read and program voltages V WL(e.g., a read voltage (e.g., 0.3V), a program voltage (e.g., 3V)) bias coupled to a selected word line selects which row of memory cells 306 is affected by the read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic unit of data for programming operations. The size of a page 320 in bits can be related to the number of NAND memory strings 308 coupled by word lines 318 in one memory block 304. Each word line 318 can include a plurality of control gates (gate electrodes) at each memory cell 306 in a corresponding page 320 and a gate line coupling the control gates.

[0060] Figure 4 A cross-sectional schematic diagram of an exemplary memory array including NAND memory strings according to some aspects of the present application is shown. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes a plurality of gate layers 411 and a plurality of insulating layers 412 that are alternately stacked in sequence, and a memory string 308 that vertically penetrates the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 may be alternately stacked, and two adjacent gate layers 411 are separated by a layer of insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 may determine the number of memory cells included in the memory array 301.

[0061] The constituent material of the gate layer 411 may include a conductive material. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, for example, a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stacked structure 410 may extend laterally as an upper selection gate line, the gate layer 411 at the bottom of the stacked structure 410 may extend laterally as a lower selection gate line, and the gate layer 411 extending laterally between the upper selection gate line and the lower selection gate line may serve as a word line layer.

[0062] In some embodiments, the stacked structure 410 may be disposed on a substrate 401. The substrate 401 may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material.

[0063] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes a channel hole filled with (one or more) semiconductor materials (e.g., as a semiconductor channel) and (one or more) dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trapping / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a column shape). According to some embodiments, the semiconductor channel, the tunneling layer, the storage layer, and the barrier layer are arranged radially from the center of the column toward the outer surface of the column in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0064] Return to reference Figure 3 , the peripheral circuit 302 may be coupled to the memory array 301 through the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuit 302 may include any suitable analog, digital, and mixed signal circuits for facilitating the operation of the memory array 301 by applying and sensing voltage signals and / or current signals to and from each target memory cell 306 via the bit lines 316, the word lines 318, the source lines 314, the BSG lines 315, and the TSG lines 313. The peripheral circuit 302 may include various types of peripheral circuits formed using metal-oxide-semiconductor (MOS) technology.

[0065] Figure 5 A schematic circuit diagram of an exemplary memory device including peripheral circuits and a memory array according to some aspects of the present application is shown. Figure 5 Some exemplary peripheral circuits and memory arrays are shown below. Figure 3 and Figure 5 It is understood that the peripheral circuit 302 includes a page buffer / sense amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include Figure 5 Additional peripheral circuits not shown.

[0066] The page buffer / sense amplifier 504 may be configured to read data from the memory array 301 and program (write) data to the memory array 301 according to a control signal from the control logic unit 512. In one example, the page buffer / sense amplifier 504 may store a page of programming data (write data) to be programmed into one page 320 of the memory array 301. In another example, the page buffer / sense amplifier 504 may perform a program verification operation to ensure that the data has been correctly programmed into the memory cell 306 coupled to the selected word line 318. In yet another example, the page buffer / sense amplifier 504 may also sense a low-power signal from the bit line 316 representing a data bit stored in the memory cell 306, and amplify a small voltage swing to a recognizable logic level in a read operation. The column decoder / bit line driver 506 may be configured to be controlled by the control logic unit 512, and select one or more NAND memory strings 308 by applying a bit line voltage generated from the voltage generator 510.

[0067] The row decoder / word line driver 508 may be configured to be controlled by the control logic unit 512 and select / deselect the memory block 304 of the memory array 301 and select / deselect the word line 318 of the memory block 304. The row decoder / word line driver 508 may also be configured to drive the word line 318 using the word line voltage generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 may also select / deselect and drive the BSG line 315 and the TSG line 313. As described in detail below, the row decoder / word line driver 508 is configured to perform a programming operation on the memory cell 306 coupled to the selected word line(s) 318. The voltage generator 510 may be configured to be controlled by the control logic unit 512 and generate a word line voltage (e.g., a read voltage, a program voltage, a pass voltage, a local voltage, a verification voltage, etc.), a bit line voltage, and a source line voltage to be supplied to the memory array 301.

[0068] In some specific embodiments, the programming operation may include multiple steps. For example, the programming operation may include a bit line setting step, a programming execution step, and a programming recovery step. After performing the programming operation, a programming verification operation needs to be performed; after performing the programming verification operation, a programming verification recovery operation needs to be performed. During the bit line setting step of the programming operation, the voltage for the unselected word lines can be maintained at the ground voltage GND. During the programming execution step of the programming operation, a pass voltage Vpass can be applied to the unselected word lines, and a programming voltage Vpgm can be applied to the selected word lines. Therefore, the storage cells connected to the selected word lines can be programmed. During the programming recovery step of the programming operation, the voltage applied to all word lines can be reduced to the ground voltage GND.

[0069] In the process of performing the program verification operation, a verification voltage Vvrf may be applied to a selected word line, and a pass voltage Vpass may be applied to unselected word lines.

[0070] During the program verification recovery operation, a recovery operation of dropping a voltage to the ground voltage GND may be performed on both the unselected word lines and the selected word line.

[0071] The control logic unit 512 may be coupled to each peripheral circuit described above, and is configured to control the operation of each peripheral circuit. The register 514 may be coupled to the control logic unit 512, and includes a status register, a command register, and an address register for storing status information, a command operation code (OP code), and a command address for controlling the operation of each peripheral circuit. The interface 516 may be coupled to the control logic unit 512, and act as a control buffer to buffer control commands received from a host (not shown) and relay them to the control logic unit 512, and to buffer status information received from the control logic unit 512 and relay them to the host. The interface 516 may also be coupled to the column decoder / bit line driver 506 via a data bus 518, and act as a data I / O interface and a data buffer to buffer data and relay them to the memory array 301 or relay or buffer data from the memory array 301.

[0072] refer to Figure 5 In some embodiments, the memory array 301 of the memory device 300 has one or more storage plane structures ( Figure 5 (not shown). For example, the number of storage surfaces may be two, four or more.

[0073] In NAND memory, a single-bit storage cell (SLC) has fast read and write speed, high reliability, and long service life, but small storage capacity, while a multi-bit storage cell (MLC, TLC, QLC, PLC) has large storage capacity and low cost, but slow read and write speed; in other words, when a single-bit storage cell (SLC) and a multi-bit storage cell (MLC, TLC, QLC, PLC) perform read operations respectively, there is a large gap in read performance between the two, that is, there is a large gap in read access performance of the memory system to the two; among them, when the memory system reads data in a single-bit storage cell, the reading speed is fast, the reading time is short, and the data access performance is high; comparatively, when the memory system reads data in a multi-bit storage cell, the reading speed is slow, the reading time is long, and the data access performance is low.

[0074] Considering that the storage blocks of the memory device in SLC mode are faster to read and write and more durable, some storage blocks in the memory device with multi-bit storage units such as MLC, TLC, QLC or PLC are configured to be accessed in SLC mode as a cache (which may be called SLC cache, or SLC cache) for caching data. When the memory device starts to write data, it can be written to the SLC cache first. Later, when the space configured as the SLC cache is full or about to be full, the data in the SLC cache needs to be moved to the MLC, TLC, QLC or PLC to release the SLC cache space.

[0075] The memory device may include: a plurality of memory blocks, and the plurality of memory blocks may be divided into a first memory area and a second memory area. The first memory area includes a plurality of memory cells that store data in a single-bit mode, and the second memory area includes a plurality of memory cells that store data in a multi-bit mode. Exemplarily, the memory cells in the first memory area are all configured as single-bit memory cells (SLC) from multi-bit memory cells, and the memory cells in the second memory area remain as ordinary multi-bit memory cells (e.g., MLC, TLC, QLC, PLC, etc.).

[0076] Taking the storage unit as TLC as an example, the 3 data bits stored in a TLC are called upper, middle and lower bits respectively; the page composed of the upper bits of all storage cells coupled to a word line is called an upper page, the page composed of the middle bits is called a middle page, and the page composed of the lower bits is called a lower page.

[0077] First, the data is read or written through the SLC mode, and then when the SLC cache space is full or about to be full, the copyback program operation (including the copyback read operation and the copyback program operation) is called to transfer the 3 SLC page data to the upper page, middle page and lower page of 1 TLC.

[0078] For example, Fig. 6A A timing diagram of a copy-back read operation of a lower page of a NAND memory according to an embodiment of the present application; Figure 6B A timing diagram of a copy-back programming operation of a lower page of a NAND memory according to an embodiment of the present application; Figure 6C A timing diagram of a copy-back read operation of a middle page of a NAND memory according to an embodiment of the present application; Fig.6D This is a timing diagram of a copy-back programming operation of a middle page of a NAND memory according to an embodiment of the present application. It should be noted that the timing diagram of the copy-back reading operation and the timing diagram of the programming operation of the upper page of the NAND memory are not further shown.

[0079] refer to Fig. 6A , the NAND memory reads the lower page data of the first cache latch corresponding to the first storage area by calling back the copy read operation and sends it to the second cache latch corresponding to the second storage area. Figure 6B The NAND memory programs the lower page data of the second cache latch corresponding to the second storage area into the lower page latch of the page buffer corresponding to the second storage area by calling back the copy programming operation.

[0080] refer to Figure 6C , the NAND memory reads the middle page data of the first cache latch corresponding to the first storage area by calling back the copy read operation and sends it to the second cache latch corresponding to the second storage area. Fig.6D The NAND memory programs the middle page data read from the second cache latch corresponding to the second storage area into the middle page latch of the page cache corresponding to the second storage area by calling back the copy programming operation.

[0081] It can be understood that the NAND memory reads the upper page data of the first cache latch corresponding to the first storage area by calling back the copy read operation and sends it to the second cache latch corresponding to the second storage area. The NAND memory programs the upper page data of the second cache latch corresponding to the second storage area into the upper page latch of the page buffer corresponding to the second storage area by calling back the copy program operation.

[0082] In some embodiments, the NAND type memory is configured to first move the page data measured (or read out) on the bit line from the sense latch SA of the page buffer to the cache latch corresponding to the SLC high-speed storage in the page buffer by calling back the copy program operation, and then transfer the data in the cache latch corresponding to the SLC in the page buffer to the cache latch corresponding to the TLC in the page buffer by calling back the copy program operation, and then move from the cache latch corresponding to the TLC in the page buffer to the latch corresponding to the page of the page buffer, and move the data moved to the latch corresponding to the page of the page buffer to the storage bits corresponding to the TLC respectively.

[0083] However, when NAND memory calls back the copy program operation to complete this task, the data is twisted through more latches, which is inefficient.

[0084] In view of this, embodiments of the present application provide a memory system and an operating method thereof, a memory device, and a storage medium.

[0085] According to a first aspect of an embodiment of the present application, a memory system is provided, comprising: a memory device, comprising a first storage area, a second storage area and a page buffer; a storage unit in the first storage area stores N-bit data in a first mode, and a storage unit in the second storage area stores M-bit data in a second mode; a page buffer comprises M latches, and the M latches are respectively used to store M pages of data corresponding to the M storage bits of the storage unit; M and N are both positive integers, and N<M; a memory controller is coupled to the memory device and configured to: send a first read instruction, the first read instruction includes page indication information corresponding to the current data to be transferred when transferring the data in the first storage area to the second storage area; the memory device is configured to: transfer the data to be transferred to the corresponding latch in the page buffer according to the page indication information.

[0086] refer to Figure 1 , the memory system 102 includes one or more memory devices 104 and a memory controller 106. The memory device 104 may be a NAND flash memory, for example, a three-dimensional (3D) NAND flash memory. The memory controller 106 is coupled to the memory device 104, and the memory controller 106 may manage data stored in the memory device 104. The memory controller 106 may be configured to control operations of the memory device 104, such as read, erase, and program operations.

[0087] In some embodiments, a memory device includes at least one memory chip, the memory chip includes at least one memory plane, the memory plane includes multiple memory blocks, the multiple memory blocks are divided into a first memory area and a second memory area, and the first memory area and the second memory area in one memory plane are coupled to a page buffer.

[0088] refer to Figure 5 , the memory device 104 includes at least one memory chip, and the memory chip includes at least one memory plane ( Figure 5 (not shown), a storage plane can be divided into multiple storage blocks. Exemplarily, the memory chip includes two storage planes. In some specific embodiments, the first storage area and the second storage area are different storage blocks in a storage plane, and the first storage area and the second storage area in a storage plane are coupled to a page buffer.

[0089] Here, the storage cells in the first storage area store N-bit data in a first mode, and the storage cells in the second storage area store M-bit data in a second mode. Here, the first mode can be understood as an SLC mode, and the second mode can be understood as an MLC mode, a TLC mode, or a QLC mode, etc. Exemplarily, the storage cells in the first storage area store 1-bit data in an SLC mode, and the storage cells in the second storage area store 4-bit data in a QLC mode.

[0090] In some specific embodiments, the memory device is specifically configured as follows: n pages of data stored in the first storage area are respectively sent to corresponding n latches of the page buffer, where n is a natural number.

[0091] In some embodiments, taking the memory unit of the memory device as QLC as an example, the latch of the page buffer may include a first latch D1, a second latch D2, a third latch D3, and a fourth latch DX.

[0092] The first latch D1, the second latch D2, the third latch D3, and the fourth latch DX can be respectively used to store data of the lower page, the middle page, the upper page, and the extra page of the memory device 104. The page buffer also includes a first cache latch SA corresponding to the first storage area, and the first cache latch SA can store data measured (or read out) on the bit line from the first storage area of ​​the memory device 104.

[0093] In some embodiments, the page indication information is used to indicate that the data to be transferred is transferred to the corresponding latch in the page buffer. The memory system can be configured to directly move the page data in the first storage area to the corresponding latch in the page buffer according to the page indication information.

[0094] Fig. 7A FIG. 1 is a timing diagram of a copy-back read operation of page data of a memory system according to an embodiment of the present application. Figure 7B FIG. 1 is a timing diagram of a copy-back programming operation of page data of a memory system according to an embodiment of the present application.

[0095] refer to Fig. 7AIn some embodiments, the memory system is configured to call back the copy read operation to read the data in the first storage area measured (or read out) on the bit line by the first cache latch SA of the page buffer, and, according to the page indication information, transfer the data measured (or read out) on the bit line by the first cache latch SA of the page buffer to the corresponding latch in the page buffer. In some specific embodiments, the memory system is configured to call back the copy read operation to read the 4 SLC page data in the first storage area measured (or read out) on the bit line by the first cache latch SA of the page buffer, and, according to the page indication information, transfer the data read from the 4 SLC pages to the corresponding 4 latches in the page buffer respectively.

[0096] In the implementation of the present application, the memory system can be configured to call the copy back program operation to move the SLC page data directly to the latch of the page buffer, rather than the cache latch of the page buffer, thereby saving the time of the memory system to transfer data and improving the efficiency of the copy back program operation of the memory system.

[0097] Figure 7C FIG. 1 is a timing diagram of a copy-back read operation of page data of a memory system according to another embodiment of the present application.

[0098] refer to Figure 7C In some embodiments, the copy-back read instruction includes read start flag information, to-be-read data column address information, to-be-read data row address information, and read end flag information.

[0099] In some embodiments, the copy back read instruction <cmd:00h><ADDR:Column&Row> <cmd:35h>, including: reading the start mark information <cmd:00h>, data column address information to be read <addr:column>, address information of the data row to be read <addr:row>And read the end mark information <cmd:35h>. Exemplarily, the copyback reads 4 SLC pages of data, and the copyback read instruction <cmd:00h><ADDR:C1&C2><ADDR:R1&R2&R3&R4> <cmd:35h>, including: reading the start mark information <cmd:00h>, data column address information to be read<ADDR:C1&C2> , address information of the data row to be read<ADDR:R1&R2&R3&R4> And read the end mark information <cmd:35h>.

[0100] refer to Fig. 7A In some embodiments, the first read instruction includes read start flag information, page indication information, address information of a data row to be read, and read end flag information.

[0101] Compared to the copy-back read instruction (ref. Figure 7C ),refer to Fig. 7A , the column address of the first read instruction (the column address information of the data to be read <addr:column>) is actually useless, so the column address becomes the page indication information for the next programming<ADDR:RSV&PAGE> It should be noted that, considering efficiency and power, the amount of data copied back is generally not the amount of data corresponding to one or a few storage cells, but the amount of data corresponding to more storage cells, for example, the amount of data corresponding to storage cells coupled to a word line or multiple word lines, so the information used to specify the read column address is not used.

[0102] In some embodiments, the first read instruction <cmd:00h><ADDR:RSV&PAGE> <addr:row> <cmd:35h>, including: reading the start mark information <cmd:00h>,<ADDR:RSV&PAGE> , address information of the data row to be read <addr:row>And read the end mark information <cmd:35h>. Exemplarily, the copyback reads 4 SLC pages of data, and the first read instruction <cmd:00h><ADDR:RSV&PAGE><ADDR:R1&R2&R3&R4> <cmd:35h>, including: reading the start mark information <cmd:00h>, page instructions<ADDR:RSV&PAGE> , address information of the data row to be read<ADDR:R1&R2&R3&R4> And read the end mark information <cmd:35h>.

[0103] Figure 8 Schematic diagram of the correspondence between page indication information of a NAND memory and a page of the NAND memory according to an embodiment of the present application. Fig. 9 It is a schematic diagram of a NAND memory according to an embodiment of the present application that directly moves page data to a latch of a page buffer through a copy-back process operation.

[0104] in, Figure 8 The codes include a first code 00, a second code 01, a third code 02, and a fourth code 03. The page includes a lower page Low page, a middle page Mid page, an upper page Up page, and an extra page Xp page of the QCL page data. The first code 00, the second code 01, the third code 02, and the fourth code 03 correspond to the lower page Low page, the middle page Mid page, the upper page Up page, and the extra page Xp page of the QCL page data, respectively.

[0105] in, Fig. 9 The latches include a first cache latch SA, a first latch D1, a second latch D2, a third latch D3 and a fourth latch DX. The first cache latch SA, the first latch D1, the second latch D2, the third latch D3 and the fourth latch DX are respectively used to cache the data of the SLC page SLC-CB measured (or read out) on the bit line by the copy back program operation, the data of the lower page QLC-LP storing the QCL page data, the data of the middle page QLC-MP storing the QCL page data, the data of the upper page QLC-UP storing the QCL page data, and the data of the extra page QLC-XP storing the QCL page data.

[0106] In some embodiments, the page indication information includes Q bits of binary data, and the Q bits of binary data include 2 Q data states, each data state corresponds to one latch in the M latches; Q is a positive integer. In some specific embodiments, each latch is used to store data of multiple memory cells in the same memory page.

[0107] refer to Figure 8 and Fig. 9 In some specific embodiments, the page indication information includes 2 bits of binary data, and the 2 bits of binary data include 4 data states, each data state ( Figure 8 The first code 00, the second code 01, the third code 02 or the fourth code 03) corresponds to a latch ( Figure 8 The first latch D1, the second latch D2, the third latch D3 or the fourth latch DX of the page indication information). The four latches can store four SLC page data accordingly. Exemplarily, the first code 00 of the page indication information indicates that the data of one SLC page is stored in the latch corresponding to the lower page Low page, namely the first latch D1, the second code 01 indicates that the data of one SLC page is stored in the latch corresponding to the middle page Mid page, namely the second latch D2, the third code 02 indicates that the data of one SLC page is stored in the latch corresponding to the upper page Up page, namely the third latch D3, and the fourth code 03 indicates that the data of one SLC page is stored in the latch corresponding to the extra page Xp page, namely the fourth latch D4. In other words, the first code 00, the second code 01, the third code 02, and the fourth code 03 of the page indication information can correspond to the first latch D1, the second latch D2, the third latch D3, and the fourth latch DX, respectively.

[0108] It should be noted that Figure 8 and Fig. 9 The description is only made by taking the storage unit as QLC as an example, and the type of storage unit of the present application is not limited. It is understandable that for MLC, only any two of the four numbers can be used to indicate the corresponding latch; for TLC, only any three of the four numbers can be used to indicate the corresponding latch.

[0109] In some embodiments, the memory controller is configured to: before sending a first read instruction, sequentially generate page indication information indicating corresponding latches according to the reading order of the data to be transferred in the first storage area; or, before sending the first read instruction, randomly generate page indication information indicating corresponding latches for the data to be transferred in the first storage area.

[0110] refer to Figure 8 and Fig. 9 In some specific embodiments, the page buffer may include a first latch D1, a second latch D2, a third latch D3, and a fourth latch DX, which may be used to store data of a lower page, a middle page, an upper page, and an additional page of the memory device 104, respectively. In some specific embodiments, the page buffer may include a first cache latch SA, which may store data of a lower page, a middle page, an upper page, and an additional page measured (or read out) on a bit line by the first cache latch SA from the page buffer, and is also referred to as a read latch.

[0111] In some specific embodiments, before sending the first read instruction, the memory controller is configured to generate a first code 00, a second code 01, a third code 02, and a fourth code 03 of the page indication information in sequence according to the reading order of the data to be transferred in the first storage area, and transfer the data to be transferred in the first storage area to the corresponding first latch D1, second latch D2, third latch D3 and fourth latch DX according to the indication information.

[0112] In other specific embodiments, before sending the first read instruction, the memory controller is configured to randomly generate page indication information encoding for multiple data to be transferred in the first storage area (in other words, four encodings appear randomly), and transfer the data to be transferred in the first storage area to the corresponding second latch D2, first latch D1, fourth latch DX and third latch D3 according to the indication information.

[0113] refer to Figure 7B In some embodiments, the memory controller is further configured to send a write instruction; the memory device is further configured to write the data in the corresponding latch in the page buffer to the storage bit corresponding to the storage unit in the second storage area in response to the write instruction.

[0114] refer to Figure 7B The write (copy-back programming) instruction includes programming start mark information, column address information of data to be programmed, row address information of data to be programmed, and programming end mark information.

[0115] In some embodiments, the programming instructions are copied back <cmd:85h><ADDR:Column&Row> <cmd:10h>, including: programming start mark information <cmd:85h>, address information of the data column to be programmed <addr:column>, address information of the data row to be programmed <addr:row>And programming end mark information <cmd:10h>For example, the copy-back programming command copies and combines four SLC pages of data into one QLC page of data storing four bits of data. <cmd:85h><ADDR:C1&C2><ADDR:R1&R2&R3&R4> <cmd:10h>, including: programming start mark information <cmd:85h>, address information of the data column to be programmed<ADDR:C1&C2> , address information of the data row to be programmed<ADDR:R1&R2&R3&R4> And programming end mark information <cmd:10h>.

[0116] In some other embodiments, the address information of the data column to be programmed <addr:column>, address information of the data row to be programmed <addr:row>For example, the copy back programming 4 SLC page data are copied and combined into 1 QLC page data storing 4 bits of data, and the copy back programming instruction <cmd:85h><ADDR:C1&C2><ADDR:R1&R2&R3&R4> <cmd:10h>, including: programming start mark information <cmd:85h>, address information of the data column to be programmed<ADDR:C1&C2> , address information of the data row to be programmed<ADDR:R1&R2&R3&R4> And programming end mark information <cmd:10h>; Among them, the address information of the data column to be programmed<ADDR:C1&C2> , address information of the data row to be programmed<ADDR:R1&R2&R3&R4> is useless.

[0117] In some embodiments, the memory system may be configured to call back the copy program operation to write the page data transferred to the corresponding latch in the page buffer into the page in the second storage area.

[0118] In this way, the memory system can be configured to first call back the copy read operation to move multiple SLC page data in the first storage area directly to the latch of the page buffer, and then call back the copy programming operation to write the multiple SLC page data transferred to the corresponding latch in the page buffer into a page in the second storage area, thereby completing the copying of multiple SLC page data and combining them into 1 MLC, TLC or QLC page data.

[0119] In some embodiments, a storage cell includes four data bits, a storage cell in a first storage area stores one bit of data in a first mode, and a storage cell in a second storage area stores four bits of data in a second mode; when data of 4P storage cells in the first storage area are transferred to P storage cells in the second storage area, page indication information includes information of any one of four latches of a page buffer corresponding to each P data in the 4P storage cells; P is a positive integer; the page indication information of the page buffer includes two bits of binary data.

[0120] In some specific embodiments, data of four storage pages in the first storage area are transferred to one storage page in the second storage area, where one storage page includes P storage cells.

[0121] In some embodiments, the memory system includes a universal flash memory device UFS, and the memory device includes a NAND type memory.

[0122] The memory system can include PC card (PCMCIA, Personal Computer Memory Card International Association), CF card, Smart Media (SM) card, memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), UFS, etc.

[0123] In this way, the memory system can be configured to first call back the copy read operation to move the SLC page data in the first storage area directly to the latch of the page buffer, and then call back the copy programming operation to write the page data transferred to the corresponding latch in the page buffer to the page in the second storage area, thereby completing the copying of multiple SLC page data and combining them into 1 MLC, TLC or QLC page data.

[0124] According to a second aspect of an embodiment of the present application, a memory device is provided, including:

[0125] A memory cell array comprises a first memory area and a second memory area; the memory cells in the first memory area store N-bit data in a first mode, and the memory cells in the second memory area store M-bit data in a second mode; M and N are both positive integers, and N<M;

[0126] The peripheral circuit includes a page buffer; one page buffer includes M latches; the M latches are respectively used to store M pages of data corresponding to M storage bits of the storage unit; the peripheral circuit is coupled to the storage unit array and is configured as follows:

[0127] receiving a first read instruction, the first read instruction including page indication information corresponding to the current data to be transferred when transferring the data in the first storage area to the second storage area;

[0128] According to the page indication information, the data bits to be transferred are transferred and sent to the corresponding latches of the page buffer.

[0129] Here, the memory device can be understood as Figure 5 Here, the memory cell array can be understood as Figure 5 Here, the peripheral circuit can be understood as Figure 5 The peripheral circuit 302 is coupled to the memory array 301. The page buffer can be understood as Figure 5 The page buffer / sense amplifier 504 is shown in FIG.

[0130] In some embodiments, the first read instruction includes read start flag information, page indication information, address information of a data row to be read, and read end flag information.

[0131] In some embodiments, the first read instruction <cmd:00h><ADDR:RSV&PAGE> <addr:row> <cmd:35h>, including: reading the start mark information <cmd:00h>,<ADDR:RSV&PAGE> , address information of the data row to be read <addr:row>And read the end mark information <cmd:35h>.

[0132] In some embodiments, a memory device includes at least one memory chip, the memory chip includes at least one memory plane, the memory plane includes multiple memory blocks, the multiple memory blocks are divided into a first memory area and a second memory area, and the first memory area and the second memory area in one memory plane are coupled to a page buffer.

[0133] Here, the memory chip can be understood as Figure 5 The memory device 300 includes a memory chip including a memory array. The memory array may be divided into a plurality of memory planes. One memory plane may be divided into a plurality of memory blocks.

[0134] In some specific embodiments, the first storage area and the second storage area are different storage blocks in a storage plane. Exemplarily, a portion of storage blocks (one storage block or multiple storage blocks) in a storage plane are used as the first storage area, and the remaining storage blocks in a storage plane are used as the second storage area.

[0135] In some embodiments, a storage cell includes four data bits, a storage cell in a first storage area stores one bit of data in a first mode, and a storage cell in a second storage area stores four bits of data in a second mode; when data of 4P storage cells in the first storage area are transferred to P storage cells in the second storage area, page indication information includes information of any one of four latches of a page buffer corresponding to each P data in the 4P storage cells; P is a positive integer; the page indication information of the page buffer includes two bits of binary data.

[0136] In some specific embodiments, data of four storage pages in the first storage area are transferred to one storage page in the second storage area, wherein data of P storage cells of one storage page. Each latch may include P data latches, and the P data latches are used to store data of P storage cells of one storage page.

[0137] In some embodiments, the page cache includes a first cache latch SA corresponding to a first storage area, and a first latch D1, a second latch D2, a third latch D4 and a fourth latch DX corresponding to a second storage area; the peripheral circuit is specifically configured to: in response to a first read instruction, directly send the data in the first cache latch SA to the first latch D1, the second latch D2, the third latch D3 and the fourth latch DX of the second storage area in sequence according to the page indication information.

[0138] In some specific embodiments, the peripheral circuit is specifically configured to: in response to the first read instruction, directly send the data in the first cache latch SA (corresponding to the data of the lower page Low page, the middle page Midpage, the upper page Up page and the extra page Xp page) to the corresponding first latch D1, the second latch D2, the third latch D3 and the fourth latch DX in sequence according to the sequentially generated page indication information.

[0139] In some other specific embodiments, the peripheral circuit is specifically configured to: in response to the first read instruction, directly send the data in the first cache latch SA (corresponding to the data of the middle page Mid page, the lower page Lowpage, the extra page Xp page and the upper page Up page) to the corresponding second latch D2, the first latch D1, the fourth latch DX and the third latch D3 in sequence according to the randomly generated page indication information.

[0140] Fig.10 It is a schematic diagram of a NAND memory according to another embodiment of the present application that directly moves page data to a latch of a page buffer through a copy-back procedure operation.

[0141] refer to Fig.10 In some embodiments, the page cache also includes a second cache latch CA (Cache Latch) corresponding to the second storage area, and the peripheral circuit is also configured to: receive a second read instruction; the second read instruction includes read start flag information, column address information of data to be read, row address information of data to be read, and read end flag information; in response to the second read instruction, send the data in the first cache latch SA to the second buffer latch CA; and send the data in the second buffer latch CA to the first latch D1, the second latch D2, the third latch D3 and the fourth latch DX of the second storage area in sequence.

[0142] refer to Fig.10 The latch may include a first cache latch SA, a second cache latch CA, a first latch D1, a second latch D2, a third latch D3, and a fourth latch DX. The first cache latch SA, the second cache latch CA, the first latch D1, the second latch D2, the third latch D3, and the fourth latch DX are respectively used to cache data of SLC pages SCL-CB, cache data of QLC pages CA-CB, store data of a lower page QLC-LP of QCL page data, store data of a middle page QLC-MP of QCL page data, store data of an upper page QLC-UP of QCL page data, and store data of an extra page QLC-XP of QCL page data.

[0143] In some specific embodiments, the second cache latch CA stores prohibition information to control whether to prohibit the memory cell from being programmed. In some specific embodiments, the second cache latch CA stores data information that can be used for host read verification or for host data correction, and can correct or modify the possibility of, for example, upper page, middle page, lower page or extra page data.

[0144] Fig.11 It is a schematic diagram of a NAND memory directly moving page data to a latch of a page buffer through a copy-back procedure operation according to yet another embodiment of the present application.

[0145] In some other embodiments, the second cache latch can be functionally merged with the latch corresponding to any page. For example, the second cache latch and the fourth latch DX are functionally merged into the fourth latch DX. Fig.11 , the peripheral circuits are also configured as:

[0146] Receive a second read instruction; the second read instruction includes read start flag information, to-be-read data column address information, to-be-read data row address information, and read end flag information;

[0147] In response to the second read instruction, the data in the first cache latch SA is sent to the corresponding fourth latch DX latch of the second storage area; and

[0148] The data of the fourth latch DX corresponding to the second storage area is sequentially sent to the first latch D1, the second latch D2, and the third latch D3 of the second storage area.

[0149] refer to Fig.11 , the latch may include a first cache latch SA, a first latch D1, a second latch D2, a third latch D3 and a fourth latch DX. The first cache latch SA, the first latch D1, the second latch D2, the third latch D3 and the fourth latch DX are respectively used to cache the data of the SLC page SLC-CB, the data of the lower page QLC-LP storing the QCL page data, the data of the middle page QLC-MP storing the QCL page data, the data of the upper page QLC-UP storing the QCL page data, the data of the cache QLC page CA-CB or the data of the extra page QLC-XP storing the QCL page data. It should be noted that when the first latch D1, the second latch D2 and the third latch D3 have respectively stored the data of the lower page QLC-LP storing the QCL page data, the data of the middle page QLC-MP storing the QCL page data and the data of the upper page QLC-UP storing the QCL page data, the fourth latch DX can be used to store the data of the extra page QLC-XP of the QCL page data.

[0150] refer to Figure 7C The second read instruction (copy-back read instruction) includes read start flag information, to-be-read data column address information, to-be-read data row address information, and read end flag information.

[0151] In some embodiments, the copy back read instruction <cmd:00h><ADDR:Column&Row> <cmd:35h>, including: reading the start mark information <cmd:00h>, data column address information to be read <addr:column>, address information of the data row to be read <addr:row>And read the end mark information <cmd:35h>For example, the copyback reads 4 SLC pages of data, and the copyback read instruction <cmd:00h><ADDR:C1&C2><ADDR:R1&R2&R3&R4> <cmd:35h>, including: reading the start mark information <cmd:00h>, data column address information to be read<ADDR:C1&C2> , address information of the data row to be read<ADDR:R1&R2&R3&R4> And read the end mark information <cmd:35h>.

[0152] In some embodiments, the peripheral circuit is further configured to: receive a write instruction; and in response to the write instruction, write the data in the corresponding latch of the page buffer into the storage bit corresponding to the storage unit in the second storage area.

[0153] refer to Figure 7B The write instruction (copy-back programming instruction) includes programming start mark information, column address information of data to be programmed, row address information of data to be programmed, and programming end mark information.

[0154] In some embodiments, the programming instructions are copied back <cmd:85h><ADDR:Column&Row> <cmd:10h>, including: programming start mark information <cmd:85h>, address information of the data column to be programmed <addr:column>, address information of the data row to be programmed <addr:row>And programming end mark information <cmd:10h>For example, the copy-back programming command copies and combines four SLC pages of data into one QLC page of data storing four bits of data. <cmd:85h><ADDR:C1&C2><ADDR:R1&R2&R3&R4> <cmd:10h>, including: programming start mark information <cmd:85h>, address information of the data column to be programmed<ADDR:C1&C2> , address information of the data row to be programmed<ADDR:R1&R2&R3&R4> And programming end mark information <cmd:10h>.

[0155] In this way, the memory device can be configured to first call back the copy read operation to move multiple SLC page data in the first storage area directly to the latch of the page buffer, and then call back the copy programming operation to write the multiple SCL page data transferred to the corresponding latch in the page buffer to the page in the second storage area, thereby completing the copying of multiple SLC page data and combining them into 1 MLC, TLC or QLC page data.

[0156] In each embodiment of the present application, when transferring data in the first storage area to the second storage area, the page indication information in the first read instruction is used to directly move the data in the first storage area to the corresponding latch corresponding to the page in the page buffer, thereby avoiding the data in the first storage area first going to the cache latch in the page buffer and then from the cache latch to the latch corresponding to the page. In other words, each embodiment of the present application saves the step of transferring data from the first storage area to the cache latch in the page buffer, so that the solution of the present application can improve the efficiency of the copy-back program operation of the memory system.

[0157] According to a third aspect of an embodiment of the present application, a method for operating a memory system is provided, the memory system comprising: a memory device and a memory controller coupled to the memory device; the memory device comprising a first storage area, a second storage area and a page buffer; a storage unit in the first storage area stores N-bit data in a first mode, and a storage unit in the second storage area stores M-bit data in a second mode; a page buffer comprises M latches, the M latches are respectively used to store M pages of data corresponding to M storage bits of the storage unit; M and N are both positive integers, and N<M; the operating method comprises:

[0158] The memory controller sends a first read instruction, where the first read instruction includes page indication information corresponding to the current data to be transferred when transferring the data in the first storage area to the second storage area;

[0159] The memory device transfers the data to be transferred to the corresponding latch in the page buffer according to the page indication information.

[0160] In some embodiments, the first read instruction includes read start flag information, page indication information, address information of a data row to be read, and read end flag information.

[0161] In some embodiments, the page indication information includes Q bits of binary data, and the Q bits of binary data include 2 Q data states, each data state corresponds to one latch among the M latches; Q is a positive integer.

[0162] In some embodiments, the operating method also includes: before sending the first read instruction, the memory controller generates page indication information indicating the corresponding latches in sequence according to the reading order of the data to be transferred in the first storage area; or, before sending the first read instruction, the memory controller randomly generates page indication information indicating the corresponding latches for the data to be transferred in the first storage area.

[0163] In some embodiments, the operation method further includes: the memory controller sends a write instruction; and the memory device writes the data in the corresponding latch in the page buffer to the storage bit corresponding to the storage unit in the second storage area in response to the write instruction.

[0164] In some embodiments, a storage cell includes four data bits, a storage cell in a first storage area stores one bit of data in a first mode, and a storage cell in a second storage area stores four bits of data in a second mode; when data of 4P storage cells in the first storage area are transferred to P storage cells in the second storage area, page indication information includes information of any one of four latches of a page buffer corresponding to each P data in the 4P storage cells; P is a positive integer; the page indication information of the page buffer includes two bits of binary data.

[0165] The memory system that the memory system operation method provided in the embodiment of the present application should have is similar to the memory system in the above-mentioned embodiment. For the technical features not fully disclosed in the embodiment of the present application, please refer to the above-mentioned embodiment for understanding, and no further details will be given here.

[0166] Fig.12 A block diagram of a readable storage medium provided in an embodiment of the present application. Fig.12 According to the fourth aspect of the embodiments of the present application, a storage medium 120 is provided, on which executable instructions 122 are stored. When the executable instructions 122 are executed, the steps of the operating method in any of the above embodiments can be implemented.

[0167] The operation method comprises: a memory device and a memory controller coupled to the memory device; the memory device comprises a first storage area, a second storage area and a page buffer; the storage unit in the first storage area stores N-bit data in a first mode, and the storage unit in the second storage area stores M-bit data in a second mode; a page buffer comprises M latches, and the M latches are respectively used to store M pages of data corresponding to the M storage bits of the storage unit; M and N are both positive integers, and N<M; the operation method comprises: the memory controller sends a first read instruction, the first read instruction contains page indication information corresponding to the current data to be transferred when transferring the data in the first storage area to the second storage area; the memory device transfers the data to be transferred to the corresponding latch in the page buffer according to the page indication information.

[0168] It should be understood that "one embodiment" or "an embodiment" mentioned throughout the specification means that specific features, structures or characteristics related to the embodiment are included in at least one embodiment of the present application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. In addition, these specific features, structures or characteristics can be combined in one or more embodiments in any suitable manner. It should be understood that in various embodiments of the present application, the size of the serial number of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application. The above-mentioned serial numbers of the embodiments of the present application are for description only and do not represent the advantages and disadvantages of the embodiments.

[0169] The above description is only a preferred embodiment of the present application, and does not limit the patent scope of the present application. All equivalent structural changes made by using the contents of the present application specification and drawings under the inventive concept of the present application, or directly / indirectly applied in other related technical fields are included in the patent protection scope of the present application. < / addr:row> < / addr:column> < / addr:row> < / addr:column> < / addr:row> < / addr:row> < / addr:row> < / addr:column> < / addr:row> < / addr:column> < / addr:row> < / addr:row> < / addr:column> < / addr:row> < / addr:column>

Claims

1. A memory system, characterized in that: include: A memory device comprising a first storage area, a second storage area and a page buffer; The storage cells in the first storage area store N-bit data in a first mode, and the storage cells in the second storage area store M-bit data in a second mode; One of the page buffers includes M latches, and the M latches are respectively used to store M pages of data corresponding to the M storage bits of the storage unit; M and N are both positive integers, and N<M; A memory controller coupled to the memory device and configured to: send a first read instruction, wherein the first read instruction includes page indication information corresponding to the current data to be transferred when transferring the data in the first storage area to the second storage area; The memory device is configured to transfer the to-be-transferred data to a corresponding latch in the page buffer according to the page indication information.

2. The memory system according to claim 1, wherein: The first read instruction includes read start flag information, the page indication information, address information of a data row to be read, and read end flag information.

3. The memory system according to claim 1, wherein: The page indication information includes Q-bit binary data, and the Q-bit binary data includes 2 Q data states, each data state corresponds to one latch among the M latches; and Q is a positive integer.

4. The memory system according to claim 1, wherein: The memory controller is configured to: Before sending the first read instruction, sequentially generating the page indication information indicating the corresponding latches according to the reading order of the data to be transferred in the first storage area; or, Before sending the first read instruction, the page indication information of the corresponding latch is randomly generated from the data to be transferred in the first storage area.

5. The memory system according to claim 1, wherein: The memory controller is further configured to: send a write instruction; The memory device is further configured to: in response to the write instruction, write the data in the corresponding latch in the page buffer to the storage bit corresponding to the storage unit in the second storage area.

6. The memory system according to claim 1, wherein: The memory device includes at least one memory chip, the memory chip includes at least one memory plane, the memory plane includes a plurality of memory blocks, the plurality of memory blocks are divided into the first memory area and the second memory area, and the first memory area and the second memory area in one memory plane are coupled to one page buffer.

7. The memory system according to claim 1, wherein: The storage unit includes four data bits, the storage unit in the first storage area stores one bit of data in a first mode, and the storage unit in the second storage area stores four bits of data in a second mode; when transferring the data of 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes information of any latch of four latches of the page buffer corresponding to each P data in the 4P storage units; P is a positive integer; The page indication information of the page buffer includes two bits of binary data.

8. The memory system according to any one of claims 1 to 7, characterized in that: The memory system comprises a universal flash memory device UFS, the memory device comprising a NAND type memory.

9. A memory device, characterized in that: include: A memory cell array includes a first memory area and a second memory area; The storage units in the first storage area store N-bit data in a first mode, and the storage units in the second storage area store M-bit data in a second mode; both M and N are positive integers, and N<M; A peripheral circuit, comprising a page buffer; one of the page buffers comprises M latches; the M latches are respectively used to store M pages of data corresponding to the M storage bits of the storage unit; the peripheral circuit is coupled to the storage unit array and is configured as follows: receiving a first read instruction, wherein the first read instruction includes page indication information corresponding to the current data to be transferred when transferring the data in the first storage area to the second storage area; According to the page indication information, the data bits to be transferred are transferred and sent to the corresponding latches of the page buffer.

10. The memory device according to claim 9, wherein: The first read instruction includes read start flag information, the page indication information, address information of a data row to be read, and read end flag information.

11. The memory device according to claim 9, wherein: The memory device includes at least one memory chip, the memory chip includes at least one memory plane, the memory plane includes a plurality of memory blocks, the plurality of memory blocks are divided into the first memory area and the second memory area, and the first memory area and the second memory area in one memory plane are coupled to one page buffer.

12. The memory device according to claim 9, wherein: The storage cells include four data bits, the storage cells in the first storage area store one bit of data in a first mode, and the storage cells in the second storage area store four bits of data in a second mode; When transferring data of 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes information of any latch of four latches of the page buffer corresponding to each P data in the 4P storage units; P is a positive integer; The page indication information of the page buffer includes two bits of binary data.

13. The memory device according to claim 12, wherein: The page buffer includes a first cache latch corresponding to the first storage area, and a first latch, a second latch, a third latch and a fourth latch corresponding to the second storage area; The peripheral circuit is specifically configured as follows: In response to the first read instruction, the data in the first cache latch is directly sent to the first latch, the second latch, the third latch and the fourth latch of the second storage area in sequence according to the page indication information.

14. The memory device according to claim 13, wherein: The page buffer further includes a second cache latch corresponding to the second storage area, The peripheral circuit is further configured as: Receive a second read instruction; the second read instruction includes read start flag information, to-be-read data column address information, to-be-read data row address information, and read end flag information; In response to the second read instruction, sending the data in the first cache latch to the second buffer latch; as well as The data in the second buffer latch is sent to the first latch, the second latch, the third latch and the fourth latch of the second storage area in sequence.

15. The memory device according to claim 9 or 14, characterized in that The peripheral circuit is further configured as: Receive write instruction; In response to the write instruction, the data in the corresponding latch of the page buffer is written into the storage bit corresponding to the storage unit in the second storage area.

16. A method for operating a memory system, characterized in that: The memory system comprises: a memory device and a memory controller coupled to the memory device; the memory device comprises a first storage area, a second storage area and a page buffer; the storage unit in the first storage area stores N-bit data in a first mode, and the storage unit in the second storage area stores M-bit data in a second mode; one of the page buffers comprises M latches, and the M latches are respectively used to store M pages of data corresponding to the M storage bits of the storage unit; both M and N are positive integers, and N<M; the operation method comprises: The memory controller sends a first read instruction, wherein the first read instruction includes page indication information corresponding to the current data to be transferred when transferring the data in the first storage area to the second storage area; The memory device transfers the to-be-transferred data to a corresponding latch in the page buffer according to the page indication information.

17. The operating method according to claim 16, characterized in that: The first read instruction includes read start flag information, the page indication information, address information of a data row to be read, and read end flag information.

18. The operating method according to claim 16, characterized in that: The page indication information includes Q-bit binary data, and the Q-bit binary data includes 2 Q data states, each data state corresponds to one latch among the M latches; and Q is a positive integer.

19. The operating method according to claim 16, characterized in that: The operation method also includes: The memory controller generates the page indication information indicating the corresponding latches in sequence according to the reading order of the data to be transferred in the first storage area before sending the first read instruction; or, Before sending the first read instruction, the memory controller randomly generates the page indication information of the corresponding latch from the data to be transferred in the first storage area.

20. The operating method according to claim 16, characterized in that: The operation method also includes: The memory controller sends a write instruction; In response to the write instruction, the memory device writes the data in the corresponding latch in the page buffer to the storage bit corresponding to the storage unit in the second storage area.

21. The operating method according to claim 16, characterized in that: The storage cells include four data bits, the storage cells in the first storage area store one bit of data in a first mode, and the storage cells in the second storage area store four bits of data in a second mode; When transferring data of 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes information of any latch of four latches of the page buffer corresponding to each P data in the 4P storage units; P is a positive integer; The page indication information of the page buffer includes two bits of binary data.

22. A storage medium, characterized in that: The storage medium stores executable instructions, and when the executable instructions are executed, the steps of the method according to any one of claims 16 to 21 can be implemented.

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