Memory system and operating method thereof, memory device, and storage medium

Abstract

Embodiments of the present application provide a memory system and an operating method thereof, a memory device and a storage medium, wherein the memory system comprises: a memory device comprising a first storage area, a second storage area and a page buffer; a storage unit in the first storage area stores N-bit data in a first mode, and a storage unit in the second storage area stores M-bit data in a second mode; one page buffer comprises M latches, and the M latches are respectively used to store data of M pages corresponding to M storage bits of the storage unit; M and N are positive integers, and N < M; a memory controller is coupled with the memory device and is configured to: send a first read instruction, the first read instruction comprising page indication information corresponding to current data to be transferred when the data in the first storage area is transferred to the second storage area; and the memory device is configured to: transfer the data to be transferred to a corresponding latch in the page buffer according to the page indication information.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular to a memory system and its operation method, memory device and storage medium. Background Technology

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND flash memory has gradually become the mainstream product in the memory market due to its high storage density, controllable production cost, suitable erasure speed, and retention characteristics.

[0003] However, as people's requirements for storage devices continue to increase, there is still much room for improvement in memory devices and their systems. Summary of the Invention

[0004] According to a first aspect of the embodiments of this application, a memory system is provided, comprising: a memory device including a first storage area, a second storage area, and a page cache; a storage cell in the first storage area stores N bits of data in a first mode, and a storage cell in the second storage area stores M bits of data in a second mode; a page cache includes M latches, the M latches being used to store data of M pages corresponding to the M storage bits of the storage cell; M and N are both positive integers, and N < M; a memory controller coupled to the memory device and configured to: send a first read instruction, the first read instruction including page indication information corresponding to the data to be transferred when transferring data from the first storage area to the second storage area; the memory device being configured to: transfer the data to be transferred to the corresponding latch in the page cache according to the page indication information.

[0005] In the above scheme, the first read instruction includes read start flag information, page indicator information, data line address information to be read, and read end flag information.

[0006] In the above scheme, the page indication information includes Q bits of binary data, and the Q bits of binary data include 2... Q There are M data states, each corresponding to one of the M latches; Q is a positive integer.

[0007] In the above scheme, the memory controller is configured to: before sending the first read instruction, sequentially generate page indication information for the corresponding latches according to the reading order of the data to be transferred in the first memory area; or, before sending the first read instruction, randomly generate page indication information for the corresponding latches from the data to be transferred in the first memory area.

[0008] In the above scheme, the memory controller is further configured to send a write instruction; the memory device is further configured to, in response to the write instruction, write the data in the corresponding latch in the page cache to the storage bit corresponding to the storage cell in the second storage area.

[0009] In the above scheme, the memory device includes at least one memory chip, the memory chip includes at least one memory surface, the memory surface includes multiple memory blocks, the multiple memory blocks are divided into a first memory area and a second memory area, and the first memory area and the second memory area in a memory surface are coupled to a page cache.

[0010] In the above scheme, the storage unit includes four data bits. The storage unit in the first storage area stores one bit of data in the first mode, and the storage unit in the second storage area stores four bits of data in the second mode. When transferring the data of 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes the information of any one of the four latches of the page cache corresponding to each P data in the 4P storage units; P is a positive integer; the page indication information of the page cache includes two binary bits.

[0011] The memory system of any of the above solutions includes a general-purpose flash memory device (UFS), and the memory device includes NAND flash memory.

[0012] According to a second aspect of the embodiments of this application, a memory device is provided, comprising: a memory cell array including a first memory area and a second memory area; memory cells in the first memory area store N bits of data in a first mode, and memory cells in the second memory area store M bits of data in a second mode; M and N are both positive integers, and N < M; peripheral circuitry including a page buffer; a page buffer including M latches; the M latches are respectively used to store data of M pages corresponding to the M memory bits of the memory cells; the peripheral circuitry is coupled to the memory cell array and configured to: receive a first read instruction, the first read instruction including page indication information corresponding to the data to be transferred when transferring data from the first memory area to the second memory area; and transfer the data bits to be transferred to the corresponding latches of the page buffer according to the page indication information.

[0013] In the above scheme, the first read instruction includes read start flag information, page indicator information, data line address information to be read, and read end flag information.

[0014] In the above scheme, the memory device includes at least one memory chip, the memory chip includes at least one memory surface, the memory surface includes multiple memory blocks, the multiple memory blocks are divided into a first memory area and a second memory area, and the first memory area and the second memory area in a memory surface are coupled to a page cache.

[0015] In the above scheme, the storage unit includes four data bits. The storage unit in the first storage area stores one bit of data in the first mode, and the storage unit in the second storage area stores four bits of data in the second mode. When transferring the data of 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes the information of any one of the four latches of the page cache corresponding to each P data in the 4P storage units; P is a positive integer; the page indication information of the page cache includes two binary bits.

[0016] In the above scheme, the page cache includes a first cache latch corresponding to the first storage area, and a first latch, a second latch, a third latch, and a fourth latch corresponding to the second storage area; the peripheral circuit is specifically configured to: in response to the first read instruction, directly send the data in the first cache latch to the first latch, the second latch, the third latch, and the fourth latch in the second storage area in sequence according to the page indication information.

[0017] In the above scheme, the page cache also includes a second cache latch corresponding to the second storage area, and the peripheral circuit is further configured to: receive a second read instruction; the second read instruction includes read start flag information, data column address information to be read, data row address information to be read, and read end flag information; in response to the second read instruction, send the data in the first cache latch to the second cache latch; and send the data in the second cache latch to the first latch, second latch, third latch, and fourth latch in the second storage area in sequence.

[0018] In the above scheme, the peripheral circuit is also configured to: receive write instructions; and in response to the write instructions, write the data in the corresponding latch of the page buffer to the corresponding storage bit of the storage cell in the second storage area.

[0019] According to a third aspect of the embodiments of this application, an operation method for a memory system is provided. The memory system includes: a memory device and a memory controller coupled to the memory device; the memory device includes a first storage area, a second storage area, and a page buffer; a storage cell in the first storage area stores N bits of data in a first mode, and a storage cell in the second storage area stores M bits of data in a second mode; a page buffer includes M latches, the M latches being used to store data of M pages corresponding to the M storage bits of the storage cell; M and N are both positive integers, and N < M; the operation method includes: the memory controller sending a first read instruction, the first read instruction including page indication information corresponding to the data to be transferred when transferring data from the first storage area to the second storage area; the memory device transferring the data to be transferred to the corresponding latch in the page buffer according to the page indication information.

[0020] In the above scheme, the first read instruction includes read start flag information, page indicator information, data line address information to be read, and read end flag information.

[0021] In the above scheme, the page indication information includes Q bits of binary data, and the Q bits of binary data include 2... Q There are M data states, each corresponding to one of the M latches; Q is a positive integer.

[0022] In the above scheme, the operation method further includes: before sending the first read instruction, the memory controller generates page indication information for the corresponding latches in the order of reading the data to be transferred in the first storage area; or, before sending the first read instruction, the memory controller randomly generates page indication information for the corresponding latches from the data to be transferred in the first storage area.

[0023] In the above scheme, the operation method further includes: the memory controller sending a write instruction; and the memory device responding to the write instruction by writing the data in the corresponding latch in the page cache to the storage bit corresponding to the storage cell in the second storage area.

[0024] In the above scheme, the storage unit includes four data bits. The storage unit in the first storage area stores one bit of data in the first mode, and the storage unit in the second storage area stores four bits of data in the second mode. When transferring the data of 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes the information of any one of the four latches of the page cache corresponding to each P data in the 4P storage units; P is a positive integer; the page indication information of the page cache includes two binary bits.

[0025] According to a fourth aspect of the embodiments of this application, a storage medium is provided, which stores executable instructions that, when executed, can implement the steps of any of the above-described operation methods.

[0026] In various embodiments of this application, when transferring data from the first storage area to the second storage area, the page indication information in the first read instruction is used to directly move the data from the first storage area to the corresponding latch in the page buffer, avoiding the step of the data from the first storage area first going to the cache latch in the page buffer and then from the cache latch to the latch corresponding to the page. In other words, the various embodiments of this application save the step of moving the data from the first storage area to the cache latch in the page buffer. Thus, the solution of this application can improve the efficiency of the copy-back operation of the memory system. Attached Figure Description

[0027] Figure 1This is a schematic diagram of an exemplary system having a memory system according to an embodiment of this application;

[0028] Figure 2A This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of this application;

[0029] Figure 2B This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of this application;

[0031] Figure 4 This is a cross-sectional schematic diagram of a memory array including NAND memory strings according to an embodiment of this application;

[0032] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of this application;

[0033] Figure 6A This is a timing diagram of a copy-back read operation of the lower page of a NAND flash memory according to an embodiment of this application.

[0034] Figure 6B This is a timing diagram of a copy-back programming operation of the lower page of a NAND flash memory according to an embodiment of this application.

[0035] Figure 6C This is a timing diagram of a copy-back read operation of a middle page of a NAND type memory according to an embodiment of this application;

[0036] Figure 6D This is a timing diagram of a copy-back programming operation for a middle page of a NAND type memory according to an embodiment of this application.

[0037] Figure 7A This is a timing diagram of a copy-back read operation of page data in a memory system according to an embodiment of this application;

[0038] Figure 7B A timing diagram of the copy-back programming operation for page data in a memory system according to an embodiment of this application;

[0039] Figure 7C A timing diagram of a copy-back read operation of page data in a memory system according to another embodiment of this application;

[0040] Figure 8 This is a schematic diagram showing the correspondence between page instruction information and pages of a NAND flash memory according to an embodiment of this application.

[0041] Figure 9This is a schematic diagram of a NAND flash memory according to an embodiment of the present application, in which page data is directly moved to the page cache latch through a copy-back procedure.

[0042] Figure 10 This is a schematic diagram of a latch in a NAND flash memory, according to another embodiment of this application, where page data is directly moved to the page cache latch via a copy-back procedure.

[0043] Figure 11 This is a schematic diagram of a latch in a NAND flash memory, according to another embodiment of the present application, where page data is directly moved to the page cache latch via a copy-back procedure.

[0044] Figure 12 A block diagram of a readable storage medium provided in an embodiment of this application. Detailed Implementation

[0045] The technical solutions of this application will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary implementation methods of this application are shown in the accompanying drawings, it should be understood that this application can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.

[0046] The present application is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present application will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present application.

[0047] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0048] It should be noted that the technical solutions described in the embodiments of this application can be combined arbitrarily without conflict.

[0049] Figure 1A block diagram of an exemplary system with memory according to some aspects of this application is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0050] Memory device 104 can be any memory claimed in this application. As detailed below, memory device 104 (e.g., NAND flash memory (e.g., three-dimensional (3D) NAND flash memory)) can have reduced leakage current from drive transistors (e.g., string drivers) coupled to unselected word lines during erase operations, which allows for further reduction in the size of the drive transistors.

[0051] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which are used as data storage in mobile devices such as smartphones, tablets, laptops, etc., and in enterprise storage arrays.

[0052] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI High Speed ​​(PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer Small Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronic Devices (IDE) protocol, Firewire protocol, etc.

[0053] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products.

[0054] In such Figure 2A In one example shown, the memory controller 106 and a single memory device 104 may be integrated into a memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card, a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The memory card connector 204 is coupled to the host 108.

[0055] In such Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0056] Figure 3 A schematic circuit diagram of an exemplary device including a memory array and peripheral circuitry according to some aspects of this application is shown. Here, the memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include memory array 301 and peripheral circuitry 302 coupled to memory array 301. Taking memory array 301 as an example of a three-dimensional NAND-type memory array, memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0057] In some implementations, each storage cell 306 is a single-level cell (SLC) having two possible storage states and thus capable of storing one bit of data. For example, a first storage state "0" may correspond to a first voltage range, and a second storage state "1" may correspond to a second voltage range. In some implementations, each storage cell 306 is a multi-level cell (MLC) capable of storing more than one bit of data in more than four storage states. For example, an MLC may store two bits per cell (also referred to as a double-level cell), three bits per cell (also referred to as a trinary-level cell, TLC), four bits per cell (also referred to as a quad-level cell, QLC), five bits per cell (also referred to as a penta-level cell, PLC), or more than five bits per cell. Each MLC may be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of three possible nominal storage values ​​to the cell, with a fourth nominal storage value that can be used for the erase state.

[0058] like Figure 3 As shown, each NAND memory string 308 may include a lower select gate (BSG) 310 at its source end and an upper select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate a selected NAND memory string 308 during read and program operations. In some embodiments, the sources of NAND memory strings 308 within the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 within the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0059] like Figure 3 As shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which can have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is a basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block 304, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block 304 and the unselected memory blocks on the same plane as the selected memory block 304. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which can be coupled with read and programmable voltages V. WL(For example, a read voltage (e.g., 0.3V) and a programming voltage (e.g., 3V)) bias is coupled to the selected word line, selecting which row of memory cell 306 is affected by read and programming operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cell 306, which is the basic data unit used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates.

[0060] Figure 4 A schematic cross-sectional view of an exemplary memory array including NAND memory strings is shown, according to some aspects of this application. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory array 301.

[0061] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0062] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0063] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0064] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 and sensing voltage and / or current signals from each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology.

[0065] Figure 5 A schematic circuit diagram of an exemplary memory device including peripheral circuitry and a memory array according to some aspects of this application is shown. Figure 5 Some exemplary peripheral circuits and memory arrays are shown below in combination. Figure 3 and Figure 5 For understanding purposes, peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a control logic unit 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, it may also include... Figure 5 Additional peripheral circuitry not shown.

[0066] Page buffer / sensor amplifier 504 can be configured to read data from memory array 301 and program (write) data to memory array 301 according to control signals from control logic unit 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic unit 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0067] The row decoder / word line driver 508 can be configured to be controlled by the control logic unit 512 and to select / deselect memory blocks 304 of the memory array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from the voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by the control logic unit 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory array 301.

[0068] In some specific embodiments, the programming operation may include multiple steps. For example, the programming operation may include a bit line setting step, a programming execution step, and a programming recovery step. After the programming operation, a programming verification operation is also required; after the programming verification operation, a programming verification recovery operation is also required. During the bit line setting step of the programming operation, the voltage for unselected word lines can be maintained at ground (GND). During the programming execution step of the programming operation, a pass voltage (Vpass) can be applied to the unselected word lines, and a programming voltage (Vpgm) can be applied to the selected word lines. Therefore, the memory cells connected to the selected word lines can be programmed. During the programming recovery step of the programming operation, the voltage applied to all word lines can be reduced to ground (GND).

[0069] During the programming verification operation, a verification voltage Vvrf can be applied to the selected word line, and a pass voltage Vpass can be applied to the unselected word line.

[0070] During the execution of the programming verification recovery operation, a recovery operation that drops the voltage to ground (GND) can be performed on both unselected and selected word lines.

[0071] Control logic unit 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic unit 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic unit 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic unit 512, as well as to buffer status information received from control logic unit 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0072] refer to Figure 5 In some embodiments, the memory array 301 of the memory device 300 has one or more memory plane structures. Figure 5 (Not shown). For example, the number of storage surfaces can be two, four, or more.

[0073] In NAND flash memory, single-cell storage (SLC) offers fast read / write speeds, high reliability, and long lifespan, but has a small storage capacity. Multi-cell storage (MLC, TLC, QLC, PLC) offers large storage capacity and low cost, but slower read / write speeds. In other words, there is a significant difference in read performance between SLC and PLC when performing read operations, meaning the memory system's read access performance differs considerably between the two. Specifically, when reading data from a single-cell storage unit, the memory system has a fast read speed, short read time, and high data access performance. Conversely, when reading data from a multi-cell storage unit, the memory system has a slow read speed, long read time, and low data access performance.

[0074] Considering that memory devices in SLC mode offer faster and more durable block read / write speeds, some memory blocks in memory devices with multi-bit storage units such as MLC, TLC, QLC, or PLC are configured for SLC mode access as a cache (also known as SLC cache or SLC high-speed cache) to buffer data. When data is written to the memory device, it can be written to the SLC cache first. Later, when the space configured as the SLC cache is full or about to be full, the data in the SLC cache needs to be moved to the MLC, TLC, QLC, or PLC to free up SLC cache space.

[0075] The memory device may include multiple memory blocks, which may be divided into a first memory area and a second memory area. The first memory area includes multiple memory cells that store data in a unit mode, and the second memory area includes multiple memory cells that store data in a multi-bit mode. For example, the memory cells in the first memory area are configured as single-bit memory cells (SLCs), and the memory cells in the second memory area remain ordinary multi-bit memory cells (e.g., MLCs, TLCs, QLCs, PLCs, etc.).

[0076] Taking TLC as an example, the three data bits stored in a TLC are called the upper bit, middle bit, and lower bit, respectively. The page formed by the upper bits of all memory cells coupled to a word line is called the upper page, the page formed by the middle bits is called the middle page, and the page formed by the lower bits is called the lower page.

[0077] First, data is read or written using SLC mode. Then, when the SLC cache space is full or about to be full, the copyback operation (including copyback read and copyback program) is called to transfer the data from the three SLC pages to the top, middle, and bottom pages of one TLC.

[0078] For example, Figure 6A This is a timing diagram of a copy-back read operation of the lower page of a NAND flash memory according to an embodiment of this application. Figure 6B This is a timing diagram of a copy-back programming operation of the lower page of a NAND flash memory according to an embodiment of this application. Figure 6C This is a timing diagram of a copy-back read operation of a middle page of a NAND type memory according to an embodiment of this application; Figure 6D This is a timing diagram of a copy-back programming operation for a middle page of a NAND flash memory according to an embodiment of this application. It should be noted that timing diagrams for the copy-back read operation and programming operation of the upper page of the NAND flash memory are not shown further.

[0079] refer to Figure 6A NAND flash memory reads the lower page data of the first cache latch corresponding to the first memory area through a copy-back read operation and sends it to the second cache latch corresponding to the second memory area. (See reference) Figure 6B NAND flash memory uses a copy-back programming operation to program the lower page data of the second cache latch corresponding to the second memory area into the lower page latch of the page cache corresponding to the second memory area.

[0080] refer to Figure 6C NAND flash memory reads the middle page data of the first cache latch corresponding to the first memory area through a copy-back read operation and sends it to the second cache latch corresponding to the second memory area. (See reference) Figure 6D NAND flash memory uses a copy-back programming operation to read the middle page data of the second cache latch corresponding to the second memory area and program it into the middle page latch of the page cache corresponding to the second memory area.

[0081] Understandably, the NAND flash memory reads the upper page data of the first cache latch corresponding to the first memory area by calling a copy-back read operation and sends it to the second cache latch corresponding to the second memory area. The NAND flash memory then programs the upper page data of the second cache latch corresponding to the second memory area into the upper page latch of the page cache corresponding to the second memory area by calling a copy-back programmable operation.

[0082] In some embodiments, the NAND-type memory is configured to first move page data measured (or read) on the bit line from the sense latch SA of the page cache to the cache latch corresponding to the SLC high-speed memory in the page cache by calling a copy-back procedure operation; then move the data in the cache latch corresponding to the SLC in the page cache to the cache latch corresponding to the TLC in the page cache by calling a copy-back procedure operation; then move the data from the cache latch corresponding to the TLC in the page cache to the page-specific latch in the page cache; and finally, move the data moved to the page-specific latch in the page cache to the storage bits corresponding to the TLC.

[0083] However, when NAND flash memory calls the copy-back procedure to complete this task, the data rotation passes through more latches, resulting in lower efficiency.

[0084] In view of the above, embodiments of this application provide a memory system, a method for operating the same, a memory device, and a storage medium.

[0085] According to a first aspect of the embodiments of this application, a memory system is provided, comprising: a memory device including a first storage area, a second storage area, and a page cache; a storage cell in the first storage area stores N bits of data in a first mode, and a storage cell in the second storage area stores M bits of data in a second mode; a page cache includes M latches, the M latches being used to store data of M pages corresponding to the M storage bits of the storage cell; M and N are both positive integers, and N < M; a memory controller coupled to the memory device and configured to: send a first read instruction, the first read instruction including page indication information corresponding to the data to be transferred when transferring data from the first storage area to the second storage area; the memory device being configured to: transfer the data to be transferred to the corresponding latch in the page cache according to the page indication information.

[0086] refer to Figure 1 The memory system 102 includes one or more memory devices 104 and a memory controller 106. The memory device 104 may be a NAND flash memory, such as a three-dimensional (3D) NAND flash memory. The memory controller 106 is coupled to the memory device 104 and can manage the data stored in the memory device 104. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations.

[0087] In some embodiments, the memory device includes at least one memory chip, the memory chip includes at least one memory surface, the memory surface includes a plurality of memory blocks, the plurality of memory blocks are divided into a first memory region and a second memory region, and the first memory region and the second memory region in a memory surface are coupled to a page cache.

[0088] refer to Figure 5 The memory device 104 includes at least one memory chip, and the memory chip includes at least one memory surface. Figure 5 (Not shown), a storage plane can be divided into multiple storage blocks. Exemplarily, a storage chip includes two storage planes. In some specific embodiments, a first storage area and a second storage area are different storage blocks within a storage plane, and the first and second storage areas within a storage plane are coupled to a page cache.

[0089] Here, the storage cells in the first storage area store N bits of data in a first mode, and the storage cells in the second storage area store M bits of data in a second mode. The first mode can be understood as SLC mode, and the second mode can be understood as MLC mode, TLC mode, or QLC mode, etc. For example, the storage cells in the first storage area store 1 bit of data in SLC mode, and the storage cells in the second storage area store 4 bits of data in QLC mode.

[0090] In some specific embodiments, the memory device is specifically configured such that n pages of data stored in the first memory area are respectively sent to the corresponding n latches of the page cache. Here, n is a natural number.

[0091] In some embodiments, taking the memory cell of the memory device as a QLC as an example, the latches of the page cache may include a first latch D1, a second latch D2, a third latch D3, and a fourth latch DX.

[0092] The first latch D1, the second latch D2, the third latch D3, and the fourth latch DX can be used to store data of the lower page, the middle page, the upper page, and the additional page of the memory device 104, respectively. The page cache also includes a first cache latch SA corresponding to the first memory area, which can store data measured (or read) on the bit line from the first memory area of ​​the memory device 104.

[0093] In some embodiments, page indication information is used to instruct data to be transferred to the corresponding latch in the page cache. The memory system can be configured to move page data from a first storage area directly to the corresponding latch in the page cache based on the page indication information.

[0094] Figure 7A This is a timing diagram of the copy-back read operation of page data in a memory system according to an embodiment of this application. Figure 7B This is a timing diagram of the copy-back programming operation for page data in a memory system according to an embodiment of this application.

[0095] refer to Figure 7AIn some embodiments, the memory system is configured to invoke a copy-back read operation to read data from a first memory area measured (or read) on the bit lines of a first cache latch SA from a page cache, and, according to page indication information, transfer the data read from the first cache latch SA of the page cache to corresponding latches in the page cache. In some specific embodiments, the memory system is configured to invoke a copy-back read operation to read four SLC page data from a first memory area measured (or read) on the bit lines of a first memory area of ​​a page cache, and, according to page indication information, transfer the data read from the four SLC pages to corresponding four latches in the page cache.

[0096] In this application, the memory system can be configured to call a copy-back procedure to move SLC page data directly to the page cache latch, instead of the page cache latch, saving the memory system's data transfer time and improving the efficiency of the memory system's copy-back procedure operation.

[0097] Figure 7C This is a timing diagram of the copy-back read operation of page data in a memory system according to another embodiment of this application.

[0098] refer to Figure 7C In some embodiments, the copy-back read instruction includes read start flag information, data column address information to be read, data row address information to be read, and read end flag information.

[0099] In some specific embodiments, the copy-back read instruction <cmd:00h><ADDR:Column&Row> <cmd:35h>This includes: reading start flag information <cmd:00h>Address information of the data column to be read <addr:column>Address information of the data row to be read <addr:row>And read the end marker information <cmd:35h>For example, copy-back reads four SLC pages of data; copy-back read command. <cmd:00h><ADDR:C1&C2><ADDR:R1&R2&R3&R4> <cmd:35h>This includes: reading start flag information <cmd:00h>Address information of the data column to be read<ADDR:C1&C2> Address information of the data row to be read<ADDR:R1&R2&R3&R4> And read the end marker information <cmd:35h>.

[0100] refer to Figure 7A In some embodiments, the first read instruction includes read start flag information, page indicator information, data line address information to be read, and read end flag information.

[0101] Compared to copy-back read commands (see reference) Figure 7C ),refer to Figure 7A The column address of the first read instruction (the column address information of the data to be read) <addr:column>In fact, it's useless, so the column address is turned into page instruction information for the next programming iteration.<ADDR:RSV&PAGE> It should be noted that, considering efficiency and power consumption, the amount of data copied back is generally not the amount of data corresponding to one or a few storage units, but rather the amount of data corresponding to a large number of storage units, such as the amount of data corresponding to storage units coupled to one or more word lines. Therefore, the information used to specify the column address to read is not needed.

[0102] In some specific embodiments, the first read instruction <cmd:00h><ADDR:RSV&PAGE> <addr:row> <cmd:35h>This includes: reading start flag information <cmd:00h>,<ADDR:RSV&PAGE> Address information of the data row to be read <addr:row>And read the end marker information <cmd:35h>For example, copying back reads four SLC pages of data, the first read instruction... <cmd:00h><ADDR:RSV&PAGE><ADDR:R1&R2&R3&R4> <cmd:35h>This includes: reading start flag information <cmd:00h>Page Indication Information<ADDR:RSV&PAGE> Address information of the data row to be read<ADDR:R1&R2&R3&R4> And read the end marker information <cmd:35h>.

[0103] Figure 8 This is a schematic diagram showing the correspondence between page instruction information and pages of a NAND flash memory according to an embodiment of this application. Figure 9 This is a schematic diagram of a NAND flash memory according to an embodiment of the present application, in which page data is directly moved to the latch of the page cache through a copy-back procedure.

[0104] in, Figure 8 The encoding includes first code 00, second code 01, third code 02, and fourth code 03. A page includes the lower page, middle page, upper page, and extra page (Xp page) of the QCL page data. First code 00, second code 01, third code 02, and fourth code 03 correspond to the lower page, middle page, upper page, and extra page (Xp page) of the QCL page data, respectively.

[0105] in, Figure 9 The latches include a first cache latch SA, a first latch D1, a second latch D2, a third latch D3, and a fourth latch DX. The first cache latch SA, the first latch D1, the second latch D2, the third latch D3, and the fourth latch DX are used to cache the data of the SLC page SLC-CB measured (or read) on the bit line during copy-back operations, the data of the lower page QLC-LP storing QCL page data, the data of the middle page QLC-MP storing QCL page data, the data of the upper page QLC-UP storing QCL page data, and the data of the extra page QLC-XP storing QCL page data.

[0106] In some embodiments, the page indication information includes Q-bit binary data, which includes 2 bits. Q There are M data states, each corresponding to one of the M latches; Q is a positive integer. In some specific embodiments, each latch is used to store data from multiple memory cells within the same memory page.

[0107] refer to Figure 8 and Figure 9 In some specific embodiments, the page indication information includes 2 bits of binary data, which includes 4 data states, each of which ( Figure 8 The first code 00, the second code 01, the third code 02, or the fourth code 03) correspond to a latch ( Figure 8 The four latches are designated as either a first latch D1, a second latch D2, a third latch D3, or a fourth latch DX. Each of the four latches can store four SLC page data. For example, the first code 00 of the page indication information indicates that the data of one SLC page should be stored in the latch corresponding to the lower page (Low page), i.e., the first latch D1; the second code 01 indicates that the data of one SLC page should be stored in the latch corresponding to the middle page (Mid page), i.e., the second latch D2; the third code 02 indicates that the data of one SLC page should be stored in the latch corresponding to the upper page (Up page), i.e., the third latch D3; and the fourth code 03 indicates that the data of one SLC page should be stored in the latch corresponding to the extra page (Xp page), i.e., the fourth latch D4. In other words, the first code 00, the second code 01, the third code 02, and the fourth code 03 of the page indication information can correspond to the first latch D1, the second latch D2, the third latch D3, and the fourth latch DX, respectively.

[0108] It should be noted that, Figure 8 and Figure 9 This explanation uses QLC (Quick Crypt) as an example only and does not limit the type of storage unit in this application. It is understood that for MLC (Multi-Level Cell), any two of the four numbering types can be used to indicate the corresponding latch; for TLC (Temperature-Level Cell), any three of the four numbering types can be used to indicate the corresponding latch.

[0109] In some embodiments, the memory controller is configured to: before sending a first read instruction, sequentially generate page indication information indicating the corresponding latches according to the reading order of the data to be transferred in the first memory area; or, before sending the first read instruction, randomly generate page indication information indicating the corresponding latches from the data to be transferred in the first memory area.

[0110] refer to Figure 8 and Figure 9 In some specific embodiments, the page cache may include a first latch D1, a second latch D2, a third latch D3, and a fourth latch DX. The first latch D1, the second latch D2, the third latch D3, and the fourth latch DX can be used to store data for the lower page, the middle page, the upper page, and the additional page of the memory device 104, respectively. In some specific embodiments, the page cache may include a first cache latch SA. The first cache latch SA can store data for the lower page, the middle page, the upper page, and the additional page measured (or read) on the bit lines from the page cache, and is also referred to as a read latch.

[0111] In some specific embodiments, before sending the first read instruction, the memory controller is configured to generate a first code 00, a second code 01, a third code 02, and a fourth code 03 of page indication information in the order of reading the data to be transferred in the first storage area, and to transfer the data to be transferred in the first storage area to the corresponding first latch D1, second latch D2, third latch D3, and fourth latch DX according to the indication information.

[0112] In some other embodiments, before sending the first read instruction, the memory controller is configured to randomly generate page indication information for multiple data to be transferred in the first memory area (in other words, four types of codes appear randomly), and to transfer the data to be transferred in the first memory area to the corresponding second latch D2, first latch D1, fourth latch DX and third latch D3 according to the indication information.

[0113] refer to Figure 7B In some embodiments, the memory controller is further configured to send a write instruction; and the memory device is further configured to, in response to the write instruction, write data in the corresponding latch in the page cache to the storage bit corresponding to the storage cell in the second storage area.

[0114] refer to Figure 7B The write (copy-back programming) instruction includes programming start flag information, column address information of the data to be programmed, row address information of the data to be programmed, and programming end flag information.

[0115] In some specific embodiments, copy back programming instructions <cmd:85h><ADDR:Column&Row> <cmd:10h>This includes: programming start flag information <cmd:85h>Address information of the data column to be programmed <addr:column>Address information of the data row to be programmed <addr:row>and programming end marker information <cmd:10h>For example, copy-back programming copies and combines four SLC page data into one QLC page data storing four bits of data. The copy-back programming instruction... <cmd:85h><ADDR:C1&C2><ADDR:R1&R2&R3&R4> <cmd:10h>This includes: programming start flag information <cmd:85h>Address information of the data column to be programmed<ADDR:C1&C2> Address information of the data row to be programmed<ADDR:R1&R2&R3&R4> and programming end marker information <cmd:10h>.

[0116] In other specific embodiments, the address information of the data to be programmed is... <addr:column>Address information of the data row to be programmed <addr:row>It can be useless. For example, copy-back programming copies and combines four SLC page data into one QLC page data storing four bits of data; the copy-back programming instruction... <cmd:85h><ADDR:C1&C2><ADDR:R1&R2&R3&R4> <cmd:10h>This includes: programming start flag information <cmd:85h>Address information of the data column to be programmed<ADDR:C1&C2> Address information of the data row to be programmed<ADDR:R1&R2&R3&R4> and programming end marker information <cmd:10h>Among them, the address information of the data column to be programmed.<ADDR:C1&C2> Address information of the data row to be programmed<ADDR:R1&R2&R3&R4> It's useless.

[0117] In some embodiments, the memory system can be configured to invoke a copy-back programming operation to write page data transferred to the corresponding latch in the page cache to a page in a second memory area.

[0118] In this way, the memory system can be configured to first call a copy-back read operation to move multiple SLC page data in the first memory area directly to the latches of the page buffer, and then call a copy-back programming operation to write the multiple SLC page data transferred to the corresponding latches in the page buffer to a page in the second memory area, thus completing the copying and combination of multiple SLC page data into one MLC, TLC or QLC page data.

[0119] In some embodiments, the storage unit includes four data bits, the storage unit in the first storage area stores one bit of data in a first mode, and the storage unit in the second storage area stores four bits of data in a second mode; when transferring data from 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes information from any of the four latches of the page cache corresponding to each P data in the 4P storage units; P is a positive integer; the page indication information of the page cache includes two binary bits.

[0120] In some specific embodiments, data from four storage pages in the first storage area is transferred to one storage page in the second storage area, wherein one storage page includes P storage units.

[0121] In some embodiments, the memory system includes a general-purpose flash memory device (UFS), and the memory device includes NAND-type memory.

[0122] The memory system may include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc.

[0123] In this way, the memory system can be configured to first call a copy-back read operation to move the SLC page data in the first storage area directly to the latch of the page buffer, and then call a copy-back programming operation to write the page data transferred to the corresponding latch in the page buffer to the page in the second storage area, thus completing the copying and combination of multiple SLC page data into one MLC, TLC or QLC page data.

[0124] According to a second aspect of the embodiments of this application, a memory device is provided, comprising:

[0125] The storage cell array includes a first storage area and a second storage area; the storage cells in the first storage area store N bits of data in a first mode, and the storage cells in the second storage area store M bits of data in a second mode; M and N are both positive integers, and N < M;

[0126] The peripheral circuitry includes a page cache; each page cache includes M latches; the M latches are used to store the data of the M pages corresponding to the M storage bits of the storage unit; the peripheral circuitry is coupled to the storage unit array and configured as follows:

[0127] Receive a first read instruction, which includes page indication information corresponding to the data to be transferred when transferring data from the first storage area to the second storage area;

[0128] Based on the page instruction information, the data bits to be transferred are transferred to the corresponding latch in the page buffer.

[0129] Here, the memory device can be understood as Figure 5 The memory device 300. Here, the memory cell array can be understood as... Figure 5 The memory array 301. Here, the peripheral circuit can be understood as... Figure 5 The page cache is coupled to the peripheral circuitry 302 of the memory array 301. Figure 5 Page buffer / sensor amplifier 504.

[0130] In some embodiments, the first read instruction includes read start flag information, page indicator information, data line address information to be read, and read end flag information.

[0131] In some specific embodiments, the first read instruction <cmd:00h><ADDR:RSV&PAGE> <addr:row> <cmd:35h>This includes: reading start flag information <cmd:00h>,<ADDR:RSV&PAGE> Address information of the data row to be read <addr:row>And read the end marker information <cmd:35h>.

[0132] In some embodiments, the memory device includes at least one memory chip, the memory chip includes at least one memory surface, the memory surface includes a plurality of memory blocks, the plurality of memory blocks are divided into a first memory region and a second memory region, and the first memory region and the second memory region in a memory surface are coupled to a page cache.

[0133] Here, a memory chip can be understood as... Figure 5 The memory device 300. The memory chip includes a memory array, which can be divided into multiple memory planes, and a memory plane can be divided into multiple memory blocks.

[0134] In some specific embodiments, the first storage area and the second storage area are different storage blocks in a storage plane. For example, a portion of the storage blocks (one or more storage blocks) in a storage plane is used as the first storage area, and the remaining storage blocks in a storage plane are used as the second storage area.

[0135] In some embodiments, the storage unit includes four data bits, the storage unit in the first storage area stores one bit of data in a first mode, and the storage unit in the second storage area stores four bits of data in a second mode; when transferring data from 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes information from any of the four latches of the page cache corresponding to each P data in the 4P storage units; P is a positive integer; the page indication information of the page cache includes two binary bits.

[0136] In some specific embodiments, data from four storage pages in the first storage area is transferred to one storage page in the second storage area, where the data in one storage page comprises P storage units. Each latch may include P data latches, which are used to store the data in the P storage units of one storage page.

[0137] In some embodiments, the page cache includes a first cache latch SA corresponding to a first storage area, and a first latch D1, a second latch D2, a third latch D4, and a fourth latch DX corresponding to a second storage area; the peripheral circuitry is specifically configured to: in response to a first read instruction, directly send the data in the first cache latch SA to the first latch D1, the second latch D2, the third latch D3, and the fourth latch DX in the second storage area in sequence according to the page indication information.

[0138] In some specific embodiments, the peripheral circuitry is specifically configured to: in response to the first read instruction, send the data in the first cache latch SA (corresponding to the data of the lower page, middle page, upper page, and extra page Xp page) in the sequentially generated page indication information to the corresponding first latch D1, second latch D2, third latch D3, and fourth latch DX.

[0139] In some other specific embodiments, the peripheral circuitry is specifically configured to: in response to a first read instruction, directly send the data in the first cache latch SA (corresponding to the data of the middle page, the lower page, the extra page Xp page, and the upper page) sequentially to the corresponding second latch D2, first latch D1, fourth latch DX, and third latch D3 according to the randomly generated page indication information.

[0140] Figure 10 This is a schematic diagram of a NAND flash memory according to another embodiment of the present application, in which page data is directly moved to the latch of the page cache through a copy-back procedure.

[0141] refer to Figure 10 In some embodiments, the page cache further includes a second cache latch (CA) corresponding to the second storage area, and the peripheral circuitry is further configured to: receive a second read instruction; the second read instruction includes read start flag information, data column address information to be read, data row address information to be read, and read end flag information; in response to the second read instruction, send the data in the first cache latch (SA) to the second cache latch (CA); and send the data in the second cache latch (CA) sequentially to the first latch (D1), the second latch (D2), the third latch (D3), and the fourth latch (DX) in the second storage area.

[0142] refer to Figure 10 The latches may include a first cache latch SA, a second cache latch CA, a first latch D1, a second latch D2, a third latch D3, and a fourth latch DX. The first cache latch SA, the second cache latch CA, the first latch D1, the second latch D2, the third latch D3, and the fourth latch DX are respectively used to cache data for SLC page SCL-CB, cache data for QLC page CA-CB, store data for the lower page QLC-LP of QCL page data, store data for the middle page QLC-MP of QCL page data, store data for the upper page QLC-UP of QCL page data, and store data for the additional page QLC-XP of QCL page data.

[0143] In some embodiments, the second cache latch (CA) stores prohibition information to control whether to prohibit the programming of the memory cell. In some embodiments, the data information stored in the second cache latch (CA) can be used for host read verification or host data correction, and can correct or modify, for example, the possibility of data in the upper page, middle page, lower page, or additional pages.

[0144] Figure 11 This is a schematic diagram of a NAND flash memory, according to another embodiment of the present application, where page data is directly moved to a latch in the page cache via a copy-back procedure.

[0145] In other embodiments, the second cache latch can be functionally merged with the latch corresponding to any page. For example, the second cache latch and the fourth latch DX can be functionally merged into the fourth latch DX. (See reference...) Figure 11 The peripheral circuitry is also configured as follows:

[0146] Receive a second read instruction; the second read instruction includes read start flag information, data column address information to be read, data row address information to be read, and read end flag information;

[0147] In response to the second read instruction, the data in the first cache latch SA is sent to the corresponding fourth latch DX in the second memory area; and

[0148] The data of the fourth latch DX corresponding to the second storage area is sent sequentially to the first latch D1, the second latch D2, and the third latch D3 of the second storage area.

[0149] refer to Figure 11 The latches may include a first cache latch SA, a first latch D1, a second latch D2, a third latch D3, and a fourth latch DX. The first cache latch SA, the first latch D1, the second latch D2, the third latch D3, and the fourth latch DX are used to cache data for SLC page SLC-CB, store data for the lower page QLC-LP of QCL page data, store data for the middle page QLC-MP of QCL page data, store data for the upper page QLC-UP of QCL page data, cache data for QLC page CA-CB, or store data for the additional page QLC-XP of QCL page data. It should be noted that when the first latch D1, the second latch D2, and the third latch D3 have already stored data for the lower page QLC-LP, the middle page QLC-MP, and the upper page QLC-UP of QCL page data, respectively, the fourth latch DX can be used to store data for the additional page QLC-XP of QCL page data.

[0150] refer to Figure 7C The second read instruction (copy-back read instruction) includes read start flag information, data column address information to be read, data row address information to be read, and read end flag information.

[0151] In some specific embodiments, the copy-back read instruction <cmd:00h><ADDR:Column&Row> <cmd:35h>This includes: reading start flag information <cmd:00h>Address information of the data column to be read <addr:column>Address information of the data row to be read <addr:row>And read the end marker information <cmd:35h>For example, copy-back reads four SLC pages of data; copy-back read command. <cmd:00h><ADDR:C1&C2><ADDR:R1&R2&R3&R4> <cmd:35h>This includes: reading start flag information <cmd:00h>Address information of the data column to be read<ADDR:C1&C2> Address information of the data row to be read<ADDR:R1&R2&R3&R4> And read the end marker information <cmd:35h>.

[0152] In some embodiments, the peripheral circuitry is further configured to: receive a write instruction; and in response to the write instruction, write data from the corresponding latch of the page cache to the corresponding storage bit of the storage cell in the second storage area.

[0153] refer to Figure 7B The write instruction (copy-back programming instruction) includes programming start flag information, column address information of the data to be programmed, row address information of the data to be programmed, and programming end flag information.

[0154] In some specific embodiments, copy back programming instructions <cmd:85h><ADDR:Column&Row> <cmd:10h>This includes: programming start flag information <cmd:85h>Address information of the data column to be programmed <addr:column>Address information of the data row to be programmed <addr:row>and programming end marker information <cmd:10h>For example, copy-back programming copies and combines four SLC page data into one QLC page data storing four bits of data. The copy-back programming instruction... <cmd:85h><ADDR:C1&C2><ADDR:R1&R2&R3&R4> <cmd:10h>This includes: programming start flag information <cmd:85h>Address information of the data column to be programmed<ADDR:C1&C2> Address information of the data row to be programmed<ADDR:R1&R2&R3&R4> and programming end marker information <cmd:10h>.

[0155] In this way, the memory device can be configured to first call a copy-back read operation to move multiple SLC page data in the first memory area directly to the latches of the page buffer, and then call a copy-back programming operation to write the multiple SLC page data transferred to the corresponding latches in the page buffer to the pages in the second memory area, thereby completing the copying and combination of multiple SLC page data into one MLC, TLC or QLC page data.

[0156] In various embodiments of this application, when transferring data from the first storage area to the second storage area, the page indication information in the first read instruction is used to directly move the data from the first storage area to the corresponding latch in the page cache, avoiding the step of the data from the first storage area first going to the cache latch in the page cache and then from the cache latch to the latch corresponding to the page. In other words, the various embodiments of this application save the step of moving the data from the first storage area to the cache latch in the page cache. Thus, the solution of this application can improve the efficiency of the copy-back operation of the memory system.

[0157] According to a third aspect of the embodiments of this application, an operation method for a memory system is provided. The memory system includes: a memory device and a memory controller coupled to the memory device; the memory device includes a first storage area, a second storage area, and a page cache; storage cells in the first storage area store N bits of data in a first mode, and storage cells in the second storage area store M bits of data in a second mode; a page cache includes M latches, the M latches being used to store data of M pages corresponding to the M storage bits of the storage cells; M and N are both positive integers, and N < M; the operation method includes:

[0158] The memory controller sends a first read instruction, which includes page indication information corresponding to the data to be transferred when transferring data from the first memory area to the second memory area;

[0159] The memory device transfers the data to be transferred to the corresponding latch in the page cache according to the page instruction information.

[0160] In some embodiments, the first read instruction includes read start flag information, page indicator information, data line address information to be read, and read end flag information.

[0161] In some embodiments, the page indication information includes Q-bit binary data, which includes 2 bits. Q There are M data states, each corresponding to one of the M latches; Q is a positive integer.

[0162] In some embodiments, the operation method further includes: before sending the first read instruction, the memory controller sequentially generates page indication information indicating the corresponding latch according to the reading order of the data to be transferred in the first storage area; or, before sending the first read instruction, the memory controller randomly generates page indication information indicating the corresponding latch from the data to be transferred in the first storage area.

[0163] In some embodiments, the operation method further includes: the memory controller sending a write instruction; and the memory device responding to the write instruction by writing data in the corresponding latch in the page cache to the storage bit corresponding to the storage cell in the second storage area.

[0164] In some embodiments, the storage unit includes four data bits, the storage unit in the first storage area stores one bit of data in a first mode, and the storage unit in the second storage area stores four bits of data in a second mode; when transferring data from 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes information from any of the four latches of the page cache corresponding to each P data in the 4P storage units; P is a positive integer; the page indication information of the page cache includes two binary bits.

[0165] The memory system required for the operation method of the memory system provided in this application embodiment is similar to the memory system in the above embodiments. For technical features not disclosed in detail in this application embodiment, please refer to the above embodiments for understanding, and will not be repeated here.

[0166] Figure 12 A block diagram of a readable storage medium provided in an embodiment of this application. (See reference...) Figure 12 According to a fourth aspect of the embodiments of this application, a storage medium 120 is provided, which stores executable instructions 122. When the executable instructions 122 are executed, the steps of the operation method as described in any of the above embodiments can be implemented.

[0167] The operation method includes: a memory device and a memory controller coupled to the memory device; the memory device includes a first storage area, a second storage area, and a page buffer; a storage cell in the first storage area stores N bits of data in a first mode, and a storage cell in the second storage area stores M bits of data in a second mode; a page buffer includes M latches, the M latches being used to store data of M pages corresponding to the M storage bits of the storage cell; M and N are both positive integers, and N < M; the operation method includes: the memory controller sending a first read instruction, the first read instruction including page indication information corresponding to the data to be transferred when transferring data from the first storage area to the second storage area; the memory device transferring the data to be transferred to the corresponding latch in the page buffer according to the page indication information.

[0168] It should be understood that the phrase "one embodiment" or "an embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this application. Therefore, "in one embodiment" or "in an embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this application, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application. The sequence numbers of the above-described embodiments are merely descriptive and do not represent the superiority or inferiority of the embodiments.

[0169] The above description is only a preferred embodiment of this application and does not limit the patent scope of this application. All equivalent structural transformations made based on the inventive concept of this application and the contents of the specification and drawings of this application, or direct / indirect applications in other related technical fields, are included within the patent protection scope of this application. < / addr:row> < / addr:column> < / addr:row> < / addr:column> < / addr:row> < / addr:row> < / addr:row> < / addr:column> < / addr:row> < / addr:column> < / addr:row> < / addr:row> < / addr:column> < / addr:row> < / addr:column>

Claims

1. A memory system, characterized in that, include: A memory device, including a first memory area, a second memory area, and a page cache; The storage cells in the first storage area store N bits of data in a first mode, and the storage cells in the second storage area store M bits of data in a second mode. A page cache includes M latches, each of which stores data for M pages corresponding to M storage bits of the storage unit; M and N are both positive integers, and N < M; A memory controller, coupled to the memory device and configured to: send a first read instruction, the first read instruction including page indication information corresponding to the data to be transferred when transferring data from the first memory area to the second memory area; the page indication information including Q-bit binary data, the Q-bit binary data including 2 Q Two types of data states, the two Q Each of the M data states corresponds to one of the M latches; Q is a positive integer; The memory device is configured to transfer the data to be transferred to the corresponding latch in the page cache according to the page instruction information.

2. The memory system according to claim 1, characterized in that, The first read instruction includes read start flag information, page indication information, data line address information to be read, and read end flag information.

3. The memory system according to claim 1, characterized in that, The memory controller is configured to: Before sending the first read instruction, page indication information corresponding to the latch is generated sequentially according to the reading order of the data to be transferred in the first storage area; or, Before sending the first read instruction, the page indication information of the latch corresponding to the data to be transferred in the first storage area is randomly generated.

4. The memory system according to claim 1, characterized in that, The memory controller is also configured to send write commands; The memory device is further configured to: in response to the write instruction, write data from the corresponding latch in the page cache to the storage bit corresponding to the storage cell in the second storage area.

5. The memory system according to claim 1, characterized in that, The memory device includes at least one memory chip, the memory chip includes at least one memory surface, the memory surface includes a plurality of memory blocks, the plurality of memory blocks are divided into a first memory area and a second memory area, and the first memory area and the second memory area in one memory surface are coupled to a page cache.

6. The memory system according to claim 1, characterized in that, The storage unit includes four data bits. The storage unit in the first storage area stores one data bit in a first mode, and the storage unit in the second storage area stores four data bits in a second mode. When transferring data from 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes information of any one of the four latches of the page cache corresponding to each of the P data bits in the 4P storage units; where P is a positive integer. The page indicator information of the page cache includes two binary bits.

7. The memory system according to any one of claims 1 to 6, characterized in that, The memory system includes a general-purpose flash memory device (UFS), which includes NAND flash memory.

8. A memory device, characterized in that, include: The storage cell array includes a first storage area and a second storage area; The storage cells in the first storage area store N bits of data in a first mode, and the storage cells in the second storage area store M bits of data in a second mode; where M and N are both positive integers, and N < M; The peripheral circuitry includes a page cache; each page cache includes M latches; the M latches are respectively used to store data of M pages corresponding to M storage bits of the memory cell; the peripheral circuitry is coupled to the memory cell array and configured as follows: A first read instruction is received, the first read instruction containing page indication information corresponding to the data to be transferred when transferring data from the first storage area to the second storage area; the page indication information includes Q-bit binary data, the Q-bit binary data including 2 Q Two types of data states, the two Q Each of the M data states corresponds to one of the M latches; Q is a positive integer; According to the page instruction information, the data to be transferred is transferred to the corresponding latch of the page cache.

9. The memory device according to claim 8, characterized in that, The first read instruction includes read start flag information, page indication information, data line address information to be read, and read end flag information.

10. The memory device according to claim 8, characterized in that, The memory device includes at least one memory chip, the memory chip includes at least one memory surface, the memory surface includes a plurality of memory blocks, the plurality of memory blocks are divided into a first memory area and a second memory area, and the first memory area and the second memory area in one memory surface are coupled to a page cache.

11. The memory device according to claim 8, characterized in that, The storage unit includes four data bits. The storage unit in the first storage area stores one data bit in a first mode, and the storage unit in the second storage area stores four data bits in a second mode. When transferring data from 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes information about any one of the four latches of the page cache corresponding to each of the P data in the 4P storage units; where P is a positive integer. The page indicator information of the page cache includes two binary bits.

12. The memory device according to claim 11, characterized in that, The page cache includes a first cache latch corresponding to the first storage area, and a first latch, a second latch, a third latch, and a fourth latch corresponding to the second storage area; The peripheral circuit is specifically configured as follows: In response to the first read instruction, the data in the first cache latch is sent sequentially to the first latch, second latch, third latch and fourth latch in the second storage area according to the page indication information.

13. The memory device according to claim 12, characterized in that, The page cache also includes a second cache latch corresponding to the second storage area. The peripheral circuit is also configured to: Receive a second read instruction; the second read instruction includes read start flag information, data column address information to be read, data row address information to be read, and read end flag information; In response to the second read instruction, the data in the first cache latch is sent to the second cache latch; as well as The data in the second cache latch is sequentially sent to the first latch, second latch, third latch and fourth latch in the second storage area.

14. The memory device according to claim 8 or 13, characterized in that, The peripheral circuit is also configured to: Receive write command; In response to the write instruction, the data in the corresponding latch of the page cache is written to the storage bit corresponding to the storage cell in the second storage area.

15. A method for operating a memory system, characterized in that, The memory system includes: a memory device and a memory controller coupled to the memory device; the memory device includes a first storage area, a second storage area, and a page cache; the storage cells in the first storage area store N bits of data in a first mode, and the storage cells in the second storage area store M bits of data in a second mode; each page cache includes M latches, the M latches being used to store data for M pages corresponding to the M storage bits of the storage cell; M and N are both positive integers, and N < M; the operation method includes: The memory controller sends a first read instruction, which includes page indication information corresponding to the data to be transferred when transferring data from the first storage area to the second storage area; the page indication information includes Q-bit binary data, which includes 2 bits. Q Two types of data states, the two Q Each of the M data states corresponds to one of the M latches; Q is a positive integer; The memory device transfers the data to be transferred to the corresponding latch in the page cache according to the page instruction information.

16. The operating method according to claim 15, characterized in that, The first read instruction includes read start flag information, page indication information, data line address information to be read, and read end flag information.

17. The operating method according to claim 15, characterized in that, The operation method further includes: Before sending the first read instruction, the memory controller generates page indication information for the corresponding latch in the order of reading the data to be transferred in the first memory area. or, Before sending the first read instruction, the memory controller randomly generates page indication information for the latch corresponding to the data to be transferred in the first storage area.

18. The operating method according to claim 15, characterized in that, The operation method further includes: The memory controller sends a write command; In response to the write instruction, the memory device writes the data in the corresponding latch in the page cache to the storage bit corresponding to the storage cell in the second storage area.

19. The operating method according to claim 15, characterized in that, The storage unit includes four data bits. The storage unit in the first storage area stores one data bit in a first mode, and the storage unit in the second storage area stores four data bits in a second mode. When transferring data from 4P storage units in the first storage area to P storage units in the second storage area, the page indication information includes information about any one of the four latches of the page cache corresponding to each of the P data in the 4P storage units; where P is a positive integer. The page indicator information of the page cache includes two binary bits.

20. A storage medium, characterized in that, The storage medium stores executable instructions, which, when executed, can implement the steps of the method according to any one of claims 15 to 19.

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