Concurrent processing method of operation request, flash memory device and storage medium

Abstract

The invention relates to the field of storage device application, and discloses an operation request concurrent processing method, a flash memory device and a storage medium, and the method comprises the steps: determining a first maximum bare chip number according to a bandwidth rate corresponding to a single bare chip; determining a second maximum bare chip number according to the maximum power consumption threshold value of the flash memory device; determining the maximum bare chip number corresponding to the concurrent group according to the total bare chip number, the first maximum bare chip number and the second maximum bare chip number of the flash memory device; determining a plurality of concurrent groups according to the maximum number of bare chips corresponding to the concurrent groups; and obtaining the operation request sent by the host, and carrying out concurrent processing on the operation request based on the concurrent group, so that the performance of the flash memory equipment can be improved under the condition of realizing concurrent processing of the operation request.

Description

Technical Field

[0001] The embodiments of the present application relate to the application field of storage devices, and in particular to a concurrent processing method for operation requests, a flash memory device, and a storage medium. Background Art

[0002] Flash memory devices refer to storage devices manufactured based on flash memory technology. Flash memory is an electronic storage medium that uses electric current to store and read data in semiconductor transistors. For example, NAND flash memory is a type of flash memory composed of multiple storage cells, each of which can store a data bit (0 or 1). Flash memory devices can be independent storage units, such as USB flash drives, solid state drives (SSDs), etc., or they can be storage modules embedded in other devices, such as eMMC or UFS storage in smartphones.

[0003] With the development of nand flash manufacturing technology and the requirements for single-disk storage capacity in scenarios such as AI and data centers, the capacity of single-disk SSDs is getting larger and larger, and is developing towards 64TB, 128TB, and even larger. The current mainstream nand flash storage density is still 512Gb / 1Tb / 2Tb per die, so large-capacity disks will have 128Die, 256Die, 512Die, or even more Die configurations.

[0004] In the existing technical solutions, the following problems exist in the implementation process of large-capacity disks: if multiple dies on the disk undergo E / P / R (E, erase; P, program; R, read) at the same time, the power consumption of the SSD will be particularly large, resulting in the inability of the power module on the disk to meet the supply; a full-frame server may experience instantaneous current overload; in the general SSD FTL (Flash Translation layer) technology, we will select a block in each die to form a concurrent set (usually called a super block in the industry) to ensure write concurrency; at the same time, other algorithms such as wear leveling, bad block management, and garbage collection based on this super block strategy will not be applicable on such large-capacity disks; in the usual SSD algorithms, the Raid algorithm will be implemented, often an N+1 raid algorithm, such as a 128-Die disk. Usually 127 dies are used to store user data, and the remaining die is used to store redundant protection data. When the disk is used in a large-capacity disk, this strategy will weaken the protection capability. In summary, the various strategies of the existing technical solutions will have defects when there are multiple dies on a large-capacity disk. Summary of the invention

[0005] The embodiments of the present application provide a method for concurrent processing of operation requests, a flash memory device, and a storage medium, by determining a first maximum number of bare chips according to a bandwidth rate corresponding to a single bare chip; determining a second maximum number of bare chips according to a maximum power consumption threshold of the flash memory device; determining a maximum number of bare chips corresponding to a concurrent group according to a total number of bare chips of the flash memory device, a first maximum number of bare chips, and a second maximum number of bare chips; determining multiple concurrent groups according to the maximum number of bare chips corresponding to the concurrent groups; obtaining operation requests sent by a host, and concurrently processing the operation requests based on the concurrent groups. The present application can improve the performance of the flash memory device while realizing concurrent processing of operation requests.

[0006] The embodiments of the present application provide the following technical solutions:

[0007] In a first aspect, an embodiment of the present application provides a concurrent processing method for operation requests, which is applied to a flash memory device, the flash memory device being communicatively connected to a host, and the method comprising:

[0008] Get the total number of dies of the flash device;

[0009] Determining a first maximum number of bare chips according to a bandwidth rate corresponding to a single bare chip;

[0010] Determining a second maximum number of bare chips according to a maximum power consumption threshold of the flash memory device;

[0011] Determine a maximum number of dies corresponding to the concurrent group according to the total number of dies of the flash memory device, the first maximum number of dies, and the second maximum number of dies;

[0012] Determine multiple concurrent groups according to the maximum number of bare chips corresponding to the concurrent groups;

[0013] Get the operation requests sent by the host and process the operation requests concurrently based on the concurrent group.

[0014] In some embodiments, the die includes multiple planes, the plane includes multiple pages, and determining the first maximum number of dies according to a bandwidth rate corresponding to a single die includes:

[0015] Obtaining the time required by the flash memory device to write data to the page to determine the first time;

[0016] Determine the maximum data storage capacity corresponding to each write of the die according to the number of planes in the die and the maximum data storage capacity of each page;

[0017] Obtaining a bandwidth rate corresponding to a single die according to the first time and the maximum data storage capacity corresponding to each write of the die;

[0018] According to the bandwidth rate corresponding to a single die and the preset bandwidth requirement, a first maximum number of die in each concurrent group is determined, wherein the first maximum number of die=preset bandwidth requirement / bandwidth rate corresponding to a single die.

[0019] In some embodiments, determining the second maximum number of dies according to a maximum power consumption threshold of the flash memory device includes:

[0020] Get the power consumption value of the flash memory device when performing a write operation;

[0021] The second maximum number of bare chips in each concurrent group is determined according to the preset maximum power consumption threshold and the power consumption value when the flash memory device performs a write operation, wherein the second maximum number of bare chips = the preset maximum power consumption threshold / the power consumption value when the flash memory device performs a write operation.

[0022] In some embodiments, determining the maximum number of dies corresponding to the concurrent group according to the total number of dies of the flash memory device, the first maximum number of dies, and the second maximum number of dies includes:

[0023] When the total number of bare chips of the flash memory device is an exponent of 2, the number of bare chips after multiple equal divisions is determined according to the multiple equal division coefficients and the total number of bare chips of the flash memory device, wherein the equal division coefficient is an exponent of 2, and the total number of bare chips = the number of channels * the number of chip select lines included in each channel * the logical unit number;

[0024] According to the first maximum number of die and the second maximum number of die, the maximum number of die corresponding to the concurrent group is determined from the equally divided number of die, wherein the maximum number of die is greater than or equal to the first maximum number of die and less than or equal to the second maximum number of die.

[0025] In some embodiments, the method further comprises:

[0026] When the total number of dies of the flash memory device is not an exponent of 2, determining a first number of dies, wherein the first number of dies is 2 N , the total number of dies in the flash device is greater than 2 N-1 , and is less than the first die quantity;

[0027] Determine the number of dies after multiple equal divisions according to multiple equal division coefficients and the first number of dies, wherein the equal division coefficient is an exponent of 2;

[0028] According to the first maximum number of bare chips and the second maximum number of bare chips, determine the maximum number of bare chips corresponding to the concurrent group from the equally divided number of bare chips, wherein the maximum number of bare chips is greater than or equal to the first maximum number of bare chips and is less than or equal to the second maximum number of bare chips;

[0029] Obtaining an equal division coefficient corresponding to the maximum number of bare chips, and determining the second number of bare chips according to the equal division coefficient, wherein the second number of bare chips = the first number of bare chips / the equal division coefficient;

[0030] A difference between the maximum number of dies and the second number of dies is obtained to determine a first number of unusable dies in each concurrent group, wherein the first number is equal to the difference.

[0031] In some embodiments, the method further comprises:

[0032] Set a die number for each die in a concurrent group, where the maximum value of the die number is the number of concurrent groups in the flash memory device * the maximum number of die corresponding to the concurrent group;

[0033] Based on the concurrent group, a scheduling linked list corresponding to the concurrent group is set, wherein the number of the scheduling linked lists is equal to the maximum number of bare chips corresponding to the concurrent group;

[0034] Obtaining an operation request sent by the host, wherein the operation request includes a bare chip number corresponding to the operation request;

[0035] According to the maximum number of bare chips corresponding to the concurrent group, the bare chip number corresponding to the operation request is modulo operation to obtain the sequence number of the scheduling list;

[0036] Insert the operation request into the scheduling list according to the sequence number of the scheduling list.

[0037] In some embodiments, the method further comprises:

[0038] Each time the operation request in the scheduling chain list is distributed, the operation request at the head of the scheduling chain list is obtained;

[0039] After the operation request at the head of the scheduling linked list is distributed, the operation request is deleted from the scheduling linked list.

[0040] In some embodiments, inserting the operation request into the scheduling chain list according to the sequence number of the scheduling chain list includes:

[0041] Get the time when the scheduling chain table receives the operation request;

[0042] Determine the expected scheduling time corresponding to the operation request according to the time when the operation request is received, wherein the expected scheduling time = the time when the operation request is received + the preset scheduling time interval;

[0043] In descending order of the expected scheduling time, the operation request corresponding to the expected scheduling time is inserted into the scheduling chain list corresponding to the sequence number of the scheduling chain list.

[0044] In some embodiments, determining the expected scheduling time corresponding to the operation request according to the time when the operation request is received includes:

[0045] When the operation request is a read request, setting the preset scheduling time interval to a first time interval, and determining an expected scheduling time corresponding to the read request according to the first time interval and the time when the operation request is received;

[0046] When the operation request is a write request or an erase request, a first execution time of the write request and a second execution time of the erase request are obtained; a larger value of the first execution time and the second execution time is determined as a second time interval; a preset scheduling time interval is set to the second time interval, and an expected scheduling time corresponding to the write request or the erase request is determined according to the second time interval and the time when the operation request is received, wherein the second time interval is greater than the first time interval.

[0047] In some embodiments, the operation request includes a read request during data migration, and the method further includes:

[0048] Create a response list;

[0049] Get the expected completion time corresponding to each read request, where expected completion time = the time when the scheduling linked list receives the read request + the preset delay time;

[0050] In descending order of expected completion time, read requests corresponding to the expected completion time are inserted into the response linked list.

[0051] In some embodiments, the method further comprises:

[0052] At fixed intervals, the response list is polled to obtain the read request currently at the head of the response list and the first expected completion time corresponding to the read request;

[0053] Determine, based on the first expected completion time and the current time, whether the first expected completion time is less than or equal to the current time;

[0054] If the first expected completion time is less than or equal to the current time, sending response information corresponding to the read request to the firmware module, so that the firmware performs a write operation after receiving the response information;

[0055] After sending the response information corresponding to the read request to the firmware module, the read request is deleted from the response linked list.

[0056] In a second aspect, an embodiment of the present application provides a flash memory device, including:

[0057] A processor and a memory, the processor is used to execute the executable program code in the memory, and when the executable program code is executed, the processor executes the instructions of the concurrent processing method of the operation request of the first aspect.

[0058] In a third aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program is executed, the concurrent processing method of operation requests as in the first aspect is implemented.

[0059] The beneficial effects of the embodiments of the present application are as follows: different from the prior art, the embodiments of the present application provide a method for concurrent processing of operation requests, which is applied to a flash memory device, and the flash memory device is communicatively connected to a host, and the method includes: obtaining the total number of bare chips of the flash memory device; determining a first maximum number of bare chips according to a bandwidth rate corresponding to a single bare chip; determining a second maximum number of bare chips according to a maximum power consumption threshold of the flash memory device; determining a maximum number of bare chips corresponding to a concurrent group according to the total number of bare chips of the flash memory device, the first maximum number of bare chips, and the second maximum number of bare chips; determining multiple concurrent groups according to the maximum number of bare chips corresponding to the concurrent groups; obtaining operation requests sent by the host, and concurrently processing the operation requests based on the concurrent groups.

[0060] By determining a first maximum number of bare chips according to a bandwidth rate corresponding to a single bare chip; determining a second maximum number of bare chips according to a maximum power consumption threshold of a flash memory device; determining a maximum number of bare chips corresponding to a concurrent group according to a total number of bare chips of the flash memory device, a first maximum number of bare chips, and a second maximum number of bare chips; determining multiple concurrent groups according to the maximum number of bare chips corresponding to a concurrent group; obtaining operation requests sent by a host, and concurrently processing the operation requests based on the concurrent groups, the present application can improve the performance of a flash memory device while realizing concurrent processing of operation requests. BRIEF DESCRIPTION OF THE DRAWINGS

[0061] One or more embodiments are exemplarily described by corresponding drawings, which do not constitute limitations on the embodiments. Elements with the same reference numerals in the drawings represent similar elements, and the figures in the drawings do not constitute proportional limitations unless otherwise stated.

[0062] Figure 1 It is a schematic diagram of the structure of a package provided in an embodiment of the present application;

[0063] Figure 2 This is a schematic diagram of the relationship between Die, CH, CE, and LUN provided in an embodiment of the present application;

[0064] Figure 3 It is a flowchart of a concurrent processing method of operation requests provided in an embodiment of the present application;

[0065] Figure 4 yes Figure 3 A detailed flow chart of step S302 in FIG.

[0066] Figure 5 yes Figure 3A detailed flow chart of step S303 in FIG.

[0067] Figure 6 yes Figure 3 A detailed flow chart of step S304 in FIG.

[0068] Figure 7 It is a schematic diagram of a process of constructing a scheduling linked list provided in an embodiment of the present application;

[0069] Figure 8 is a schematic diagram of a scheduling linked list provided in an embodiment of the present application;

[0070] Fig. 9 yes Figure 7 A detailed flow chart of step S705 in FIG.

[0071] Fig.10 yes Fig. 9 A detailed flow chart of step S752 in FIG.

[0072] Fig.11 A schematic diagram of a process for deleting an operation request from a scheduling linked list provided in an embodiment of the present application;

[0073] Fig.12 A schematic diagram of data migration provided in an embodiment of the present application;

[0074] Fig.13 A schematic diagram of a process for creating a response linked list provided in an embodiment of the present application;

[0075] Fig.14 A schematic diagram of a response linked list provided in an embodiment of the present application;

[0076] Fig.15 A schematic diagram of a flow chart for determining whether a first expected completion time is less than or equal to a current time provided in an embodiment of the present application;

[0077] Fig.16 It is a structural schematic diagram of a flash memory device provided in an embodiment of the present application.

[0078] Description of Figure Numbers:

[0079] Label name Label name 160 Flash memory devices 161 processor 162 Memory DETAILED DESCRIPTION

[0080] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0081] In addition, the technical features involved in each embodiment of the present application described below can be combined with each other as long as they do not conflict with each other.

[0082] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used in this specification and in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application. The term "and / or" used in this specification includes any and all combinations of one or more of the related listed items.

[0083] The technical solution of the present application is described in detail below in conjunction with the accompanying drawings:

[0084] See also Figure 1 , Figure 1 It is a schematic diagram of the structure of a package provided in an embodiment of the present application;

[0085] like Figure 1 As shown, the package in the flash memory device refers to the physical packaging unit of the NAND Flash, which is a whole package of the NAND Flash chip and can contain one or more Targets.

[0086] In the embodiment of the present application, the packaging form of Package includes HDP, and HDP (Hexadeca Die Package) refers to a NAND Flash packaging form in which each package contains 16 Dies. HDP is the abbreviation of Hexadeca Die Package, which refers to a NAND Flash packaging form in which each package contains 16 Dies. This packaging form improves the storage density and capacity of NAND Flash, so that more storage units can be accommodated in the same physical space.

[0087] Specifically, each Target contains multiple Dies (chips), which are the basic components of NAND Flash and are used to store data. Package, as the physical package of NAND Flash, provides a protective shell for Die, enabling it to work more stably and reliably. At the same time, Package also facilitates the installation and replacement of NAND Flash. A Target contains one or more Dies, and one or more Dies of a Target share a set of data signals. Die is the smallest unit in NAND Flash that can independently execute commands and report status, and corresponds one-to-one with a logic unit. In a Target, one or more LUNs share a set of data signals, and each Target is controlled by a CE pin (chip select), where LUN (Die) and logic unit (logic unit) correspond one-to-one in NAND Flash, which means that each LUN (Die) can be regarded as an independent logical storage unit for performing operations such as read, write and erase.

[0088] A Die is an independent flash memory chip that contains multiple blocks for data storage. In a multi-channel SSD, each Die can perform read, write, or erase operations independently, allowing parallel processing to improve performance. A Plane is an independent storage unit within a flash memory chip that is used to store and manage data. Each Die usually contains multiple Planes, and further, each Plane is composed of multiple Blocks, and each Block contains multiple Pages. The main advantage of planes is that they can perform read, write, and erase operations independently, thereby improving the performance of the SSD.

[0089] Multiple Planes make up a Die. This means that within an independent flash memory chip (Die), there will be multiple Planes to share the task of data storage and management. This structure helps to improve storage density and performance because more data can be accommodated in a smaller physical space and the read and write speeds can be increased by processing multiple data blocks in parallel.

[0090] In actual application scenarios, multi-plane operations utilize the parallelism of NAND flash memory to perform read and write tasks on multiple planes in the same Die at the same time, thereby significantly improving the data transmission rate. Asynchronous plane operations provide higher operational independence, allowing read tasks on different planes to be performed independently without waiting for the completion of operations on other planes, thereby improving the response speed of random reads.

[0091] Please refer to Figure 2 , Figure 2This is a schematic diagram of the relationship between Die, CH, CE, and LUN provided in an embodiment of the present application;

[0092] like Figure 2 As shown, the main controller of SSD adopts multi-channel (hereinafter referred to as CH) design. Each CH has a common data transmission line, and each CH has multiple CE (Chip enable) lines inside. The CE line corresponds to the target inside the flash. When a specific Die needs to be operated, the CH and CE lines can be selected through the hardware, and then a specific LUN in the target can be selected through the software. For example, when Die0 on the disk needs to be selected, CH0 can be selected first, CE0 can be pulled down, and then LUN0 can be selected to operate CH0-CE0-LUN0, that is, Die0 on the disk.

[0093] See also Figure 3 , Figure 3 It is a flowchart of a concurrent processing method of operation requests provided in an embodiment of the present application;

[0094] The concurrent processing method of operation requests is applied to a flash memory device, which includes a plurality of bare chips. Specifically, the execution subject of the concurrent processing method of operation requests is one or more controllers of the flash memory device.

[0095] like Figure 3 As shown, the concurrent processing method of the operation request includes:

[0096] Step S301: Obtain the total number of bare chips of the flash memory device;

[0097] Specifically, the flash memory device includes multiple dies, and the total number of dies of the flash memory device is obtained, wherein the total number of dies of the flash memory device=the number of channels*the number of chip select lines included in each channel*the logical unit number.

[0098] Step S302: determining a first maximum number of bare chips according to a bandwidth rate corresponding to a single bare chip;

[0099] For details, please refer to Figure 4 , Figure 4 yes Figure 3 A detailed flow chart of step S302 in FIG.

[0100] like Figure 4 As shown, step S302: determining a first maximum number of bare chips according to a bandwidth rate corresponding to a single bare chip, including:

[0101] Step S321: Obtain the time required for the flash memory device to write data to the page to determine the first time;

[0102] Specifically, the bare chip includes multiple planes, and the plane includes multiple pages. The time required for the flash memory device to write data to the page is obtained to determine the first time. For example, if the tProgram of a certain NAND is 400us, the first time is 400us.

[0103] Step S322: determining the maximum data storage capacity corresponding to each write of the die according to the number of planes in the die and the maximum data storage capacity of each page written at a time;

[0104] Specifically, the number of planes in the die and the maximum data storage capacity of each page that can be written at a single time are obtained, and the product of the number of planes in the die and the maximum data storage capacity of each page that can be written at a single time is calculated to obtain the maximum data storage capacity corresponding to each write of the die. For example, if the number of planes in the die is 4 planes, and the maximum data storage capacity of each page that can be written at a single time (single-plane page) is 16kB, then the data volume of the multi-plane page is 64kB, that is, the maximum data storage capacity corresponding to each write of the die is 64kB.

[0105] Step S323: Obtaining a bandwidth rate corresponding to a single die according to the first time and the maximum data storage capacity corresponding to each write of the die;

[0106] Specifically, the bandwidth rate corresponding to a single bare chip is obtained according to the first time and the maximum data storage capacity corresponding to each write of the bare chip, wherein the bandwidth rate corresponding to a single bare chip = the maximum data storage capacity corresponding to each write of the bare chip / the first time. For example, assuming that the first time is 400us, the maximum data storage capacity corresponding to each write of the bare chip is 64KB, then the bandwidth rate corresponding to the single bare chip is 64kB / 400us=0.076Gb / s.

[0107] It should be noted that the calculation of bandwidth rate ignores the time it takes to transfer data to the NAND Flash, because the transmission time will be different for different transmission configurations.

[0108] Step S324: determining a first maximum number of bare chips for each concurrent group according to the bandwidth rate corresponding to a single bare chip and a preset bandwidth requirement;

[0109] Specifically, a preset bandwidth requirement is set, for example, the bandwidth requirement is set to 8GB / s. It should be noted that the preset bandwidth requirement can be set according to actual needs, and this application does not limit this. According to the bandwidth rate corresponding to a single die and the preset bandwidth requirement, the first maximum number of die in each concurrent group is determined, where the first maximum number of die = preset bandwidth requirement / bandwidth rate corresponding to a single die. For example, assuming that the preset bandwidth requirement is 8GB / s and the bandwidth rate corresponding to a single die is 0.076Gb / s, the first maximum number of die is 8GB / s÷0.076Gb / s≈105.26, which is approximately 106 Dies.

[0110] Step S303: determining a second maximum number of bare chips according to a maximum power consumption threshold of the flash memory device;

[0111] Specifically, Figure 5 yes Figure 3 A detailed flow chart of step S303 in FIG.

[0112] like Figure 5 As shown, step S303: determining a second maximum number of bare chips according to a maximum power consumption threshold of the flash memory device, including:

[0113] Step S331: Obtain the power consumption value of the flash memory device when performing a write operation;

[0114] Specifically, the power consumption value when the flash memory device performs a write operation, that is, the power consumption value when the flash is programmed, can be obtained through actual measurement or by checking the nand spec.

[0115] Step S332: determining a second maximum number of bare chips for each concurrent group according to a preset maximum power consumption threshold and a power consumption value when the flash memory device performs a write operation;

[0116] Specifically, a preset maximum power consumption threshold is set, which is the power consumption threshold of the entire SSD disk. According to the preset maximum power consumption threshold and the power consumption value of the flash memory device when performing a write operation, the second maximum number of bare chips for each concurrent group is determined, wherein the second maximum number of bare chips = preset maximum power consumption threshold / power consumption value of the flash memory device when performing a write operation. For example, the maximum power consumption threshold of the entire SSD disk is generally around 20w, and the maximum power consumption threshold of a large-capacity disk can be relaxed to within 25w. After deducting the power consumption of other devices such as cache and master control on the disk, the power consumption left for the flash memory is generally 19-20w. Therefore, when the maximum power consumption threshold is 20w and the power consumption value of the flash memory device when performing a write operation is 0.15w, 20 / 0.15=133 Dies.

[0117] Step S304: determining the maximum number of dies corresponding to the concurrent group according to the total number of dies of the flash memory device, the first maximum number of dies, and the second maximum number of dies;

[0118] Specifically, Figure 6 yes Figure 3 A detailed flow chart of step S304 in FIG.

[0119] like Figure 6 As shown, step S304: determining the maximum number of dies corresponding to the concurrent group according to the total number of dies of the flash memory device, the first maximum number of dies, and the second maximum number of dies, includes:

[0120] Step S341: Obtain the total number of bare chips of the flash memory device;

[0121] Specifically, the flash memory device includes multiple dies, and the total number of dies of the flash memory device is obtained, wherein the total number of dies of the flash memory device=the number of channels*the number of chip select lines included in each channel*the logical unit number.

[0122] Step S342: determining whether the total number of bare chips in the flash memory device is an exponent of 2;

[0123] Specifically, determine whether the total number of bare chips of the flash memory device is an exponent of 2. If it is determined that the total number of bare chips of the flash memory device is an exponent of 2, proceed to step S343; if it is determined that the total number of bare chips of the flash memory device is not an exponent of 2, proceed to step S345.

[0124] Step S343: determining the number of dies after the multiple equal divisions according to the multiple equal division coefficients and the total number of dies in the flash memory device;

[0125] Specifically, if it is determined that the total number of bare chips of the flash memory device is an exponent of 2, then the number of bare chips after multiple equal divisions is determined based on multiple equal division coefficients and the total number of bare chips of the flash memory device, wherein the equal division coefficients are 2, 4, and 8. The total number of bare chips of the flash memory device is divided by each equal division coefficient respectively to obtain the number of bare chips after three equal divisions. For example, assuming that the total number of bare chips of the flash memory device is 512, the number of bare chips after equal division is 256, 128, and 64.

[0126] Step S344: determining the maximum number of dies corresponding to the concurrent group from the equally divided number of dies according to the first maximum number of dies and the second maximum number of dies;

[0127] Specifically, the first maximum number of bare chips and the second maximum number of bare chips, among multiple equally divided numbers of bare chips, select the equally divided number of bare chips that meets the preset condition, and determine the equally divided number of bare chips that meets the preset condition as the maximum number of bare chips corresponding to the concurrent group, wherein the preset condition is greater than or equal to the first maximum number of bare chips and less than or equal to the second maximum number of bare chips. If there are multiple equally divided numbers of bare chips that meet the preset condition, then obtain the maximum value of the multiple equally divided numbers of bare chips, and determine the maximum value as the maximum number of bare chips corresponding to the concurrent group.

[0128] Step S345: determining the number of first bare chips;

[0129] Specifically, if it is determined that the total number of bare chips of the flash memory device is not an exponent of 2, a first number of bare chips is determined, wherein the first number of bare chips is 2 to the power of N, and the total number of bare chips of the flash memory device is greater than 2 to the power of N-1 and less than the first number of bare chips.

[0130] Step S346: determining the number of dies after the multiple equal divisions according to the multiple equal division coefficients and the first number of dies;

[0131] Specifically, the number of dies after multiple equal divisions is determined based on multiple equal division coefficients and the number of first dies, wherein the equal division coefficient is an exponent of 2. For example, assuming the equal division coefficients are 2, 4, and 8, the number of first dies of the flash memory device is divided by each equal division coefficient respectively to obtain the number of dies after three equal divisions. For example, assuming the number of first dies of the flash memory device is 512, the number of dies after equal division is 256, 128, and 64.

[0132] Step S347: determining the maximum number of dies corresponding to the concurrent group from the equally divided number of dies according to the first maximum number of dies and the second maximum number of dies;

[0133] Specifically, the first maximum number of bare chips and the second maximum number of bare chips, among multiple equally divided numbers of bare chips, select the equally divided number of bare chips that meets the preset condition, and determine the equally divided number of bare chips that meets the preset condition as the maximum number of bare chips corresponding to the concurrent group, wherein the preset condition is greater than or equal to the first maximum number of bare chips and less than or equal to the second maximum number of bare chips. If there are multiple equally divided numbers of bare chips that meet the preset condition, then obtain the maximum value of the multiple equally divided numbers of bare chips, and determine the maximum value as the maximum number of bare chips corresponding to the concurrent group.

[0134] Based on the above configuration, this application also makes some corresponding designs in software coding, including: setting a die number (DieId) for each die in a concurrent group, the maximum value of the die number is the number of concurrent groups in the flash device * the maximum number of die corresponding to the concurrent group, establishing a relationship between DieId and CH, CE, and LUN, combining the use of union syntax and bit fields, converting DieId to CH, CE, and LUN, and the union of DieId contains a uint16_t type DieId and an anonymous structure, which uses bit fields to define CH, CE, and LUN. That is, if you know DieId, you can directly get CH, CE, and LUN; vice versa. Taking the previous configuration of 16CH*8CE*4LUN as an example, CH uses 4 bits, CE uses 3 bits, and LUN uses 2 bits, a total of 9 bits. The CH value is 0 to 15, which can be represented by 4 bits. CH_BITS takes 4; similarly, CE_BITS takes 3, and LUN_BITS takes 2. For example, when dieId = 0, CH, CE, CE: 0-0-0.

[0135] In the embodiment of the present application, the code to implement the union structure is as follows:

[0136] struct{

[0137] union{

[0138] struct{

[0139] unsigned int channel:CH_BITS; / / channel

[0140] unsigned int ce:CE_BITS; / / chip select line

[0141] unsigned int lun:LUN_BITS; / / Logical unit

[0142] };

[0143] unsigned intdieId: DIE_BITS;

[0144] };

[0145] };

[0146] Step S348: obtaining the equal division coefficient corresponding to the maximum number of bare chips, and determining the second number of bare chips according to the equal division coefficient;

[0147] Specifically, the equal division coefficient corresponding to the maximum number of bare chips is obtained, and the second number of bare chips is determined according to the equal division coefficient. For example, assuming that the equal division coefficient corresponding to the maximum number of bare chips is 2, the second number of bare chips is determined according to the equal division coefficient, wherein the second number of bare chips = the first number of bare chips / the equal division coefficient.

[0148] Step S349: Obtain the difference between the maximum number of bare chips and the second number of bare chips to determine a first number of unusable bare chips in each concurrent group;

[0149] Specifically, the second number of bare chips is subtracted from the maximum number of bare chips to obtain a difference between the maximum number of bare chips and the second number of bare chips, and the difference is determined as a first number to determine a first number of unusable bare chips in each concurrent group, that is, the status of the first number of bare chips is set to an unusable state.

[0150] For example, when the Die on the disk is not an exponent of 2, such as some configurations are 31 HDP (Hexadeca DiePackage, 16 Dies in one package) disks, there are 496 Dies on the disk at this time, and we still calculate according to the above configuration of 512 Dies. For the master control, there will be one or two CHs with 8CEs that are not fully used. Normally, all 8CEs are fully used. For example, when CH-XCE-Y is not used, the corresponding LUNs under CH-x CE-Y on the disk are unavailable and in the default state. The default Die position is marked as inValid, which cannot be used and E / P / R operations are not distributed. At this time, each Parallel Group still has 128 Dies, but 124 Dies can be used, and 4 are inValid.

[0151] Step S305: determining a plurality of concurrent groups according to the maximum number of bare chips corresponding to the concurrent groups;

[0152] Specifically, multiple concurrent groups are determined according to the maximum number of dies corresponding to the concurrent groups, wherein the number of dies in each concurrent group is the same, and the number of concurrent groups = the total number of dies in the flash memory device / the maximum number of dies corresponding to the concurrent groups.

[0153] Step S306: obtaining the operation request sent by the host, and concurrently processing the operation request based on the concurrent group;

[0154] Specifically, the flash memory device is communicatively connected to the host, receives multiple operation requests sent by the host, and concurrently processes the operation requests based on concurrent groups.

[0155] Please refer to Figure 7 , Figure 7 It is a schematic diagram of a process of constructing a scheduling linked list provided in an embodiment of the present application;

[0156] like Figure 7 As shown in the figure, the process of building a scheduling list includes:

[0157] Step S701: setting a die number for each die in a concurrent group;

[0158] Specifically, a die number is set for the die in each concurrent group, wherein one die number corresponds to one die. Assuming there are four concurrent groups and the maximum number of die in each concurrent group is 128, the die numbers of the first concurrent group are 1 to 128, the die numbers of the second concurrent group are 129 to 256, the die numbers of the third concurrent group are 267 to 384, and the die numbers of the first concurrent group are 385 to 512.

[0159] Step S702: Based on the concurrent group, a scheduling linked list corresponding to the concurrent group is set;

[0160] Specifically, based on the concurrent group, a scheduling linked list corresponding to the concurrent group is set, wherein the number of the scheduling linked lists is equal to the maximum number of bare chips.

[0161] Step S703: Obtaining an operation request sent by the host;

[0162] Specifically, the host sends an operation request to the flash memory device, wherein the operation request includes but is not limited to a read request, a write request and an erase request.

[0163] Step S704: performing a modulo operation on the die number corresponding to the operation request according to the maximum die number corresponding to the concurrent group, and obtaining the sequence number of the scheduling linked list;

[0164] Specifically, the operation request includes its corresponding die number, the die number corresponding to the operation request is obtained, and a modulo operation is performed on the die number corresponding to the operation request according to the maximum number of die corresponding to the concurrent group to obtain the sequence number of the scheduling linked list, wherein each scheduling linked list corresponds to a sequence number, for example, assuming that the die number corresponding to the operation request is 12, and the maximum number of die corresponding to the concurrent group is 128, then a modulo operation is performed on the die number corresponding to the operation request according to the maximum number of die corresponding to the concurrent group to obtain a remainder of 12, and the remainder is determined as the sequence number of the scheduling linked list.

[0165] Step S705: inserting the operation request into the scheduling chain list according to the sequence number of the scheduling chain list;

[0166] For details, please refer to Figure 8 , Figure 8 yes Figure 7 A detailed flow chart of step S705 in FIG.

[0167] like Figure 8 As shown, step S705: inserting the operation request into the scheduling chain table according to the sequence number of the scheduling chain table, including:

[0168] Step S751: Obtain the time when the scheduling linked list receives the operation request;

[0169] Specifically, when the scheduling linked table obtains the operation request, the time when the scheduling linked table receives the operation request is recorded.

[0170] Step S752: determining an expected scheduling time corresponding to the operation request according to the time when the operation request is received;

[0171] For details, please refer to Fig. 9 , Fig.10 yes Fig. 9 A detailed flow chart of step S752 in FIG.

[0172] Step S7521: Obtaining an operation request;

[0173] Specifically, obtain the operation request sent by the host.

[0174] Step S7522: Determine whether the operation request is a read request;

[0175] Specifically, determine whether the operation request is a read request. If the operation request is a read request, proceed to step S7523; if the operation request is not a read request, proceed to step S7524.

[0176] Step S7523: setting the preset scheduling time interval as the first time interval, and determining the expected scheduling time corresponding to the read request according to the first time interval and the time when the operation request is received;

[0177] Specifically, if the operation request is a read request, the preset scheduling time interval is set to a first time interval, and the expected scheduling time corresponding to the read request is determined based on the first time interval and the time when the operation request is received, wherein the first time interval can be set according to actual needs. To ensure that the read request is scheduled first, preferably, the first time interval is set to 0, and the expected scheduling time corresponding to the read request is determined by adding the first time interval and the time when the operation request is received, wherein the expected scheduling time corresponding to the read request = the first time interval + the time when the operation request is received.

[0178] Step S7524: Obtain the first execution time of the write request and the second execution time of the erase request;

[0179] Specifically, if the operation request is not a read request, it is determined that the operation request is a write request or an erase request, and a first execution time of the write request and a second execution time of the erase request are acquired.

[0180] Step S7525: Determine the larger value of the first execution time and the second execution time as the second time interval;

[0181] Specifically, according to obtaining the first execution time of the write request and the second execution time of the erase request, a larger value of the first execution time and the second execution time is determined as the second time interval.

[0182] Step S7526: setting the preset scheduling time interval as the second time interval, and determining the expected scheduling time corresponding to the write request or the erase request according to the second time interval and the time when the operation request is received;

[0183] Specifically, the preset scheduling time interval is set to a second time interval, and the expected scheduling time corresponding to the write request or the erase request is determined by adding the second time interval and the time when the operation request is received, wherein the expected scheduling time corresponding to the write request or the erase request = the second time interval + the time when the operation request is received, and the second time interval is greater than the first time interval. The second time can be set according to actual needs, for example, the second time interval is set to 100ms.

[0184] Step S753: inserting the operation request corresponding to the expected scheduling time into the scheduling chain table corresponding to the sequence number of the scheduling chain table in descending order of the expected scheduling time;

[0185] Specifically, the operation requests corresponding to the expected scheduling time are sorted in descending order of the expected scheduling time, and the operation requests corresponding to the expected scheduling time are inserted into the scheduling chain list corresponding to the sequence number of the scheduling chain list in the sorted order.

[0186] Please refer to Fig.10 , Fig.10 is a schematic diagram of a scheduling linked list provided in an embodiment of the present application;

[0187] like Fig.10 As shown in the figure, the number of Dies contained in each concurrent group Parallel Group is equal, recorded as ParallelCnt, which is to divide the total number of Dies equally. Set Parallel Cnt scheduling lists List, there are Parallel Cnt Dies in Parallel Group, use DieOffn to represent the nth Die in Parallel Group, the sequence number of each scheduling list corresponds to DieOff one by one, the scheduling list includes a head and a tail, and the smaller the expected scheduling time is, the closer it is to the head of the scheduling list.

[0188] Please refer to Fig.11 , Fig.11 A schematic diagram of a process for deleting an operation request from a scheduling linked list provided in an embodiment of the present application;

[0189] Step S1101: each time the operation request in the scheduling chain list is distributed, the operation request at the head of the scheduling chain list is obtained;

[0190] Specifically, each time the operation requests in the scheduling chain list are distributed, the operation request at the head of the scheduling chain list is obtained first.

[0191] Step S1102: after distributing the operation request at the head of the scheduling chain list, deleting the operation request from the scheduling chain list;

[0192] Specifically, each time a Dispatch Req is distributed, the operation request at the head of the dispatch list List is distributed first, and after the operation request at the head of the dispatch list List is distributed, the operation request is removed from the dispatch list List.

[0193] Please refer to Fig.12 , Fig.12 A schematic diagram of data migration provided in an embodiment of the present application;

[0194] like Fig.12 As shown, the data migration of SSD generally follows the following strategies: 1) Read data from the source address of Mv to the cache, i.e., MvRd; 2) Then write data from the cache to the target address of Mv, i.e., MvWr; 3) Enterprise-level SSD has an important performance indicator, the random write performance in steady state, at which the user write volume and the speed of garbage collection are in a fixed ratio, i.e., HostWr and MvWr are in a certain speed ratio (this is a common practice in the industry and is not within the scope of this patent design) 4) Step 2 can only be performed after Step 1 is completed. If there are many E / Ps above a certain DieOff, MvRd will not be distributed for a long time. Therefore, in the previous strategy, the migration speed of Mv is accidental, especially when the full Die is divided into four equal parts, this randomness will be enhanced; if MvRd cannot be dispatched in time, the firmware will wait for MvRd to complete before performing MvWr, resulting in MvWr speed fluctuations, thereby causing HostWr performance fluctuations.

[0195] Based on this, this application designs a strategy: 1) The time when Req is received is recorded as Treq, and the time when Req is expected to be scheduled is recorded as Texp, Texp = Treq + EXP; for Flash, the read tRead is generally very short, at the microsecond level (typically, TLC: 45us, QLC: 80us), and the erase tErase and write tProrgam are both in the millisecond level. So for reading, EXPrd = 0; for erase / write, you can take Max(tErase, tProrgam), for example, take the empirical value EXPProgram = 10ms; EXPErase = 10ms; 2) According to Texp, insert them into the List corresponding to DieOff from large to small to ensure that Req with small Texp is distributed first

[0196] In the embodiment of the present application, the above strategy ensures that MvRd is scheduled first; at the same time, it prevents extreme scenarios where reads are always inserted in front of erase / write requests, resulting in the erase / write requests not being scheduled and being starved to death.

[0197] Please refer to Fig.13 , Fig.13 A schematic diagram of a process for creating a response linked list provided in an embodiment of the present application;

[0198] like Fig.13 As shown, the process of creating a response list includes:

[0199] Step S1301: Create a response linked list;

[0200] Specifically, create a response list, and after MvRd is completed on Flash, hang it on the response list and delay the Ack time.

[0201] Step S1302: Obtain the expected completion time corresponding to each read request;

[0202] Specifically, the expected completion time corresponding to each read request is obtained, wherein the expected completion time = the time when the scheduling linked list receives the read request + the preset delay time, and the preset delay time tDelay can be set according to actual conditions, for example, tDelay is set to tProrgam / 2.

[0203] Step S1303: inserting read requests corresponding to expected completion times into a response linked list in descending order of expected completion times;

[0204] Specifically, the read requests corresponding to the expected completion time are sorted in descending order of the expected completion time, and the read requests corresponding to the expected completion time are inserted into the response linked list in the sorted order.

[0205] Please refer to Fig.14, Fig.14 A schematic diagram of a response linked list provided in an embodiment of the present application;

[0206] like Fig.14 As shown, the scheduling chain table includes a head and a tail, and the smaller the expected completion time, the closer it is to the head of the scheduling chain table. The response information corresponding to the read request is sent to the firmware module, so that the firmware performs a write operation after receiving the response information; after sending the response information corresponding to the read request to the firmware module, the read request is deleted from the response chain table.

[0207] Please refer to Fig.15 , Fig.15 A schematic diagram of a flow chart for determining whether a first expected completion time is less than or equal to a current time provided in an embodiment of the present application;

[0208] like Fig.15 As shown, the process of determining whether the first expected completion time is less than or equal to the current time includes:

[0209] Step S1501: polling the response linked list at fixed intervals to obtain the read request currently at the head of the response linked list, and obtain the first expected completion time corresponding to the read request;

[0210] Specifically, a fixed time is set through a timer, for example, the fixed time is set to 10 microseconds, and the response list is quickly polled at fixed intervals to obtain the read request currently at the head of the response list and obtain the first expected completion time corresponding to the read request.

[0211] In the embodiment of the present application, the present application provides a strategy for processing requests and responses, especially in the scenario where a large number of requests need to be processed efficiently and timely responses are ensured. The strategy includes: when processing requests, priority should be given to those requests that have reached or exceeded the expected completion time, and response information / confirmation information (Ack) should be given immediately, so that the request that reaches the expected completion time can be Acked at the first time, which means that the system has an expected completion time or deadline. For each request, when its processing time reaches or exceeds this expected time, the system should immediately send a response message (Ack) to the requester, and the requester includes a firmware module, indicating that the request has been processed or completed. Doing so can ensure that the requester obtains feedback in a timely manner, reduces waiting time, and improves the response speed and efficiency of the system.

[0212] At the same time, create a response list AckList, which is a list for storing requests to be confirmed. Each time a new request is inserted into the response list (AckList), the head of the list must be checked to see if there is a request that requires cq. cq represents a special processing queue or channel for processing requests with higher priority or that require special attention.

[0213] In the embodiment of the present application, the strategy for efficiently processing requests not only ensures timely response to requests, but also takes into account the priority and special processing requirements, which helps to improve the overall performance of the system.

[0214] Step S1502: judging whether the first expected completion time is less than or equal to the current time according to the first expected completion time and the current time;

[0215] Specifically, based on the first expected completion time and the current time, determine whether the first expected completion time is less than or equal to the current time, that is, by comparing the first expected completion time and the current time, determine whether the first expected completion time is less than or equal to the current time. If the first expected completion time is less than or equal to the current time, enter step S1503; if the first expected completion time is greater than the current time, stop this polling, return to step S1501, and wait for the next fixed time interval to start the next polling.

[0216] For example, periodically poll the AckList, compare the TAck of the Req at the head of the AckList with the current Tcurrent, if TAck<=Tcurrent, return Req Ack, remove Req at the same time, and then check the next Req on the AckList, until TAck>Tcurrent, then exit this polling.

[0217] Step S1503: Sending response information corresponding to the read request to the firmware module, so that the firmware performs a write operation after receiving the response information;

[0218] Specifically, if the first expected completion time is less than or equal to the current time, a response message corresponding to the read request is sent to the firmware module, so that the firmware performs a write operation after receiving the response message, wherein the write operation refers to a write operation performed by data migration.

[0219] Step S1504: after sending the response information corresponding to the read request to the firmware module, the read request is deleted from the response linked list;

[0220] Specifically, after sending the response information corresponding to the read request to the firmware module, the read request needs to be deleted from the response linked list and wait for the next polling.

[0221] In an embodiment of the present application, the present application provides a concurrent processing method for operation requests, which is applied to a flash memory device, and the flash memory device is connected to a host in communication. The method includes: obtaining the total number of bare chips of the flash memory device; determining the first maximum number of bare chips according to the bandwidth rate corresponding to a single bare chip; determining the second maximum number of bare chips according to the maximum power consumption threshold of the flash memory device; determining the maximum number of bare chips corresponding to a concurrent group according to the total number of bare chips, the first maximum number of bare chips, and the second maximum number of bare chips of the flash memory device; determining multiple concurrent groups according to the maximum number of bare chips corresponding to the concurrent group; obtaining the operation request sent by the host, and concurrently processing the operation request based on the concurrent group. By determining the first maximum number of bare chips according to the bandwidth rate corresponding to a single bare chip; determining the second maximum number of bare chips according to the maximum power consumption threshold of the flash memory device; determining the maximum number of bare chips corresponding to the concurrent group according to the total number of bare chips, the first maximum number of bare chips, and the second maximum number of bare chips of the flash memory device; determining multiple concurrent groups according to the maximum number of bare chips corresponding to the concurrent group; obtaining the operation request sent by the host, and concurrently processing the operation request based on the concurrent group, the present application can improve the performance of the flash memory device while realizing concurrent processing of operation requests.

[0222] Please refer to Fig.16 , Fig.16 is a structural schematic diagram of a flash memory device provided in an embodiment of the present application;

[0223] like Fig.16 As shown, the flash memory device 160 includes one or more processors 161 and a memory 162. Fig.16 A processor 161 is taken as an example.

[0224] The processor 161 and the memory 162 may be connected via a bus or other means. Fig.16 The example of connecting through bus is taken in the following.

[0225] The processor 161 is used to provide computing and control capabilities to control the flash memory device 160 to perform corresponding tasks, for example, a concurrent processing method for controlling the flash memory device 160 to execute an operation request in any one of the above method embodiments is applied to a flash memory device, and the flash memory device is communicated with a host. The method includes: obtaining the total number of bare chips of the flash memory device; determining a first maximum number of bare chips according to a bandwidth rate corresponding to a single bare chip; determining a second maximum number of bare chips according to a maximum power consumption threshold of the flash memory device; determining a maximum number of bare chips corresponding to a concurrent group according to the total number of bare chips of the flash memory device, the first maximum number of bare chips, and the second maximum number of bare chips; determining multiple concurrent groups according to the maximum number of bare chips corresponding to the concurrent group; obtaining operation requests sent by the host, and concurrently processing the operation requests based on the concurrent groups.

[0226] By determining a first maximum number of bare chips according to a bandwidth rate corresponding to a single bare chip; determining a second maximum number of bare chips according to a maximum power consumption threshold of a flash memory device; determining a maximum number of bare chips corresponding to a concurrent group according to a total number of bare chips of the flash memory device, a first maximum number of bare chips, and a second maximum number of bare chips; determining multiple concurrent groups according to the maximum number of bare chips corresponding to a concurrent group; obtaining operation requests sent by a host, and concurrently processing the operation requests based on the concurrent groups, the present application can improve the performance of a flash memory device while realizing concurrent processing of operation requests.

[0227] The processor 161 may be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip or any combination thereof; it may also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a programmable logic device (PLD) or a combination thereof. The above-mentioned PLD may be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL) or any combination thereof.

[0228] The memory 162 is a non-transient computer-readable storage medium, which can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the concurrent processing method of operation requests in the embodiment of the present application. The processor 161 can implement the concurrent processing method of operation requests in any of the above method embodiments by running the non-transient software programs, instructions and modules stored in the memory 162. Specifically, the memory 162 may include a volatile memory (VM), such as a random access memory (RAM); the memory 162 may also include a non-volatile memory (NVM), such as a read-only memory (ROM), a flash memory, a hard disk drive (HDD) or a solid-state drive (SSD) or other non-transient solid-state storage device; the memory 162 may also include a combination of the above types of memories.

[0229] The memory 162 may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage devices. In some embodiments, the memory 162 may optionally include a memory remotely arranged relative to the processor 161, and these remote memories may be connected to the processor 161 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0230] One or more modules are stored in the memory 162, and when executed by one or more processors 161, the concurrent processing method of the operation request in any of the above method embodiments is executed, for example, the above described concurrent processing method is executed. Figure 3 The steps shown.

[0231] In the embodiment of the present application, the flash memory device 160 may also have components such as a wired or wireless network interface, a keyboard, and an input / output interface for input and output. The flash memory device 160 may also include other components for realizing device functions, which will not be described in detail here.

[0232] The embodiment of the present application also provides a non-volatile computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor to complete the concurrent processing method of the operation request in the above embodiment. For example, the non-volatile computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0233] The present application also provides a non-volatile computer-readable storage medium, such as a memory including a program code, and the program code can be executed by a processor to complete the concurrent processing method of the operation request in the above embodiment. For example, the non-volatile computer-readable storage medium can be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), a magnetic tape, a floppy disk, and an optical data storage device.

[0234] The present application also provides a computer program product, which includes one or more program codes, which are stored in a non-volatile computer-readable storage medium. The processor of the flash memory device reads the program code from the non-volatile computer-readable storage medium, and the processor executes the program code to complete the method steps of the concurrent processing method of the operation request provided in the above embodiment.

[0235] A person skilled in the art will appreciate that all or part of the steps for implementing the above embodiments may be accomplished by hardware or by hardware associated with a program code, and the program may be stored in a non-volatile computer-readable storage medium, and the above-mentioned storage medium may be a read-only memory, a disk or an optical disk, etc.

[0236] Through the description of the above implementation methods, a person of ordinary skill in the art can clearly understand that each implementation method can be implemented by means of software plus a general hardware platform, and of course, can also be implemented by hardware. A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a non-volatile computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM) or a random access memory (RAM), etc.

[0237] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Under the concept of the present application, the technical features in the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other changes in different aspects of the present application as mentioned above, which are not provided in detail for the sake of simplicity. Although the present application has been described in detail with reference to the aforementioned embodiments, a person of ordinary skill in the art should understand that the technical solutions described in the aforementioned embodiments can still be modified, or some of the technical features can be replaced by equivalents. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for concurrently processing operation requests, characterized in that: Applied to a flash memory device, the flash memory device is communicatively connected to a host, and the method comprises: Obtaining the total number of bare chips of the flash memory device; Determining a first maximum number of bare chips according to a bandwidth rate corresponding to a single bare chip; Determining a second maximum number of bare chips according to a maximum power consumption threshold of the flash memory device; Determine a maximum number of dies corresponding to a concurrent group according to the total number of dies of the flash memory device, the first maximum number of dies, and the second maximum number of dies; Determine a plurality of concurrent groups according to a maximum number of bare chips corresponding to the concurrent groups; An operation request sent by the host is obtained, and the operation request is concurrently processed based on the concurrent group.

2. The method according to claim 1, characterized in that: The die includes a plurality of planes, the plane includes a plurality of pages, and determining the first maximum number of die according to a bandwidth rate corresponding to a single die includes: Obtaining the time required for the flash memory device to write data to the page to determine the first time; Determine the maximum data storage capacity corresponding to each write of the die according to the number of planes in the die and the maximum data storage capacity of each page written at a time; According to the first time and the maximum data storage capacity corresponding to each write of the die, obtain the bandwidth rate corresponding to the single die; According to the bandwidth rate corresponding to the single die and the preset bandwidth requirement, a first maximum number of die in each concurrent group is determined, wherein the first maximum number of die=the preset bandwidth requirement / the bandwidth rate corresponding to the single die.

3. The method according to claim 1, characterized in that The determining, according to the maximum power consumption threshold of the flash memory device, a second maximum number of bare chips comprises: Obtaining a power consumption value when the flash memory device performs a write operation; The second maximum number of bare chips in each concurrent group is determined based on a preset maximum power consumption threshold and the power consumption value when the flash memory device performs a write operation, wherein the second maximum number of bare chips = the preset maximum power consumption threshold / the power consumption value when the flash memory device performs a write operation.

4. The method according to claim 1, characterized in that: Determining the maximum number of dies corresponding to the concurrent group according to the total number of dies of the flash memory device, the first maximum number of dies, and the second maximum number of dies includes: When the total number of dies of the flash memory device is an exponent of 2, determining the number of dies after multiple equal divisions according to multiple equal division coefficients and the total number of dies of the flash memory device, wherein the equal division coefficient is an exponent of 2, and the total number of dies = the number of channels * the number of chip select lines included in each channel * the logical unit number; According to the first maximum number of bare chips and the second maximum number of bare chips, the maximum number of bare chips corresponding to the concurrent group is determined from the equally divided number of bare chips, wherein the maximum number of bare chips is greater than or equal to the first maximum number of bare chips and is less than or equal to the second maximum number of bare chips.

5. The method according to claim 4, characterized in that The method further comprises: When the total number of dies of the flash memory device is not an exponent of 2, determining a first number of dies, wherein the first number of dies is 2 N , the total number of dies in the flash memory device is greater than 2 N-1 , and is less than the first number of bare chips; Determine the number of dies after multiple equal divisions according to multiple equal division coefficients and the first number of dies, wherein the equal division coefficient is an exponent of 2; Determine a maximum number of dies corresponding to a concurrent group from the equally divided number of dies according to the first maximum number of dies and the second maximum number of dies, wherein the maximum number of dies is greater than or equal to the first maximum number of dies and less than or equal to the second maximum number of dies; Obtaining an equal division coefficient corresponding to the maximum number of bare chips, and determining a second number of bare chips according to the equal division coefficient, wherein the second number of bare chips=the first number of bare chips / the equal division coefficient; A difference between the maximum number of dies and the second number of dies is obtained to determine a first number of unusable dies in each concurrent group, wherein the first number is equal to the difference.

6. The method according to claim 1, characterized in that The method further comprises: Setting a die number for each die in the concurrent group, wherein a maximum value of the die number is the number of concurrent groups in the flash memory device*the maximum number of die corresponding to the concurrent group; Based on the concurrent group, setting a scheduling linked list corresponding to the concurrent group, wherein the number of the scheduling linked lists is equal to the maximum number of bare chips corresponding to the concurrent group; Obtaining an operation request sent by the host, wherein the operation request includes a die number corresponding to the operation request; According to the maximum number of bare chips corresponding to the concurrent group, a modulo operation is performed on the bare chip number corresponding to the operation request to obtain the sequence number of the scheduling linked list; The operation request is inserted into the scheduling chain list according to the sequence number of the scheduling chain list.

7. The method according to claim 6, characterized in that The method further comprises: Each time the operation request in the scheduling chain list is distributed, the operation request at the head of the scheduling chain list is obtained; After distributing the operation request at the head of the scheduling linked list, the operation request is deleted from the scheduling linked list.

8. The method according to claim 6, characterized in that The step of inserting the operation request into the scheduling chain list according to the sequence number of the scheduling chain list comprises: Obtaining the time when the scheduling linked table receives the operation request; Determine the expected scheduling time corresponding to the operation request according to the time when the operation request is received, wherein the expected scheduling time = the time when the operation request is received + the preset scheduling time interval; In descending order of the expected scheduling time, the operation request corresponding to the expected scheduling time is inserted into the scheduling chain table corresponding to the sequence number of the scheduling chain table.

9. The method according to claim 8, characterized in that The determining, according to the time at which the operation request is received, an expected scheduling time corresponding to the operation request includes: When the operation request is a read request, setting the preset scheduling time interval to a first time interval, and determining an expected scheduling time corresponding to the read request according to the first time interval and the time when the operation request is received; When the operation request is a write request or an erase request, a first execution time of the write request and a second execution time of the erase request are obtained; a larger value of the first execution time and the second execution time is determined as a second time interval; the preset scheduling time interval is set to a second time interval, and an expected scheduling time corresponding to the write request or the erase request is determined according to the second time interval and the time when the operation request is received, wherein the second time interval is greater than the first time interval.

10. The method according to claim 8, characterized in that The operation request includes a read request during data migration, and the method further includes: Create a response list; Obtaining the expected completion time corresponding to each of the read requests, wherein the expected completion time = the time when the scheduling linked table receives the read request + the preset delay time; The read requests corresponding to the expected completion time are inserted into the response linked list in descending order of the expected completion time.

11. The method according to claim 10, characterized in that The method further comprises: At fixed intervals, the response linked list is polled to obtain a read request currently located at the head of the response linked list, and a first expected completion time corresponding to the read request; Determining, according to the first expected completion time and the current time, whether the first expected completion time is less than or equal to the current time; If the first expected completion time is less than or equal to the current time, sending response information corresponding to the read request to the firmware module, so that the firmware performs a write operation after receiving the response information; After sending the response information corresponding to the read request to the firmware module, the read request is deleted from the response linked list.

12. A flash memory device, characterized in that: include: A processor and a memory, wherein the processor is used to execute an executable program code in the memory, and when the executable program code is executed, the processor executes instructions of the concurrent processing method for operation requests as described in any one of claims 1 to 11.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed, the concurrent processing method for operation requests according to any one of claims 1 to 11 is implemented.

Images