Flash memory data read-write processing method, device and equipment

Abstract

The invention provides a read-write processing method, device and equipment for flash memory data, belongs to the technical field of computer information processing, and solves the problems of low data read-write efficiency and long time delay due to the fact that an existing flash memory adopts a sequential access read-write mode. The method comprises the following steps: acquiring flash memory data to be written into a storage block; segmenting the flash memory data to obtain a plurality of segmented data blocks; dividing each segmented data block in the plurality of segmented data blocks into a plurality of sub-data blocks, wherein the plurality of sub-data blocks have the same physical block address; generating a verification sub-data block according to the plurality of sub-data blocks; and writing the plurality of sub-data blocks and the verification sub-data blocks into a plurality of different read-write channels of the storage area of the storage block. According to the scheme, non-blocking concurrent read-write of the flash memory data is realized, waiting caused by read-write conflicts is avoided, the read-write performance of the flash memory is improved, and time delay is optimized.

Description

Technical Field

[0001] The present invention relates to the technical field of computer information processing, and in particular to a flash memory data reading and writing processing method, device and equipment. Background Art

[0002] Flash memory (NAND) is usually used for high-performance data operations with the host, including data storage and reading. The host interface hardware will receive jobs from the host, split the jobs into sub-jobs, and then dispatch them to the corresponding input and output command distributors. When the flash memory needs to be operated, the input and output commands are converted into flash memory operation instructions to read and operate the flash memory.

[0003] The defects of the existing flash memory read and write operation method are: the device reads and writes the flash memory according to the input and output commands of the front end, adopts a sequential access mode, and the next instruction must wait for the previous instruction to be executed before it can be executed. If there is an access conflict, additional waiting processing is required, which will result in performance degradation and increased latency. Summary of the invention

[0004] The present invention provides a flash memory data read and write processing method, device and equipment, which solves the problem that the existing flash memory adopts a sequential access read and write method, has low data read and write efficiency and long delay

[0005] In order to solve the above technical problems, the technical solution of the present invention is as follows:

[0006] An embodiment of the present invention provides a method for reading and writing flash memory data, comprising:

[0007] Obtaining flash memory data to be written into a storage block;

[0008] Segmenting the flash memory data to obtain a plurality of segmented data blocks;

[0009] Dividing each of the plurality of divided data blocks into a plurality of sub-data blocks, wherein the plurality of sub-data blocks have the same physical block address;

[0010] generating a check sub-data block according to the plurality of sub-data blocks;

[0011] The multiple sub-data blocks and the check sub-data block are written into multiple different read-write channels of the storage area of ​​the storage block.

[0012] Optionally, the flash memory data is segmented to obtain a plurality of segmented data blocks, including:

[0013] The flash memory data is segmented according to a first preset threshold value to obtain a plurality of segmented data blocks, wherein the storage spaces occupied by the plurality of segmented data blocks are all equal in size.

[0014] Optionally, dividing each of the plurality of segmented data blocks into a plurality of sub-data blocks comprises:

[0015] Each of the plurality of divided data blocks is divided according to a second preset threshold to obtain a plurality of sub-data blocks, wherein the storage space occupied by the plurality of sub-data blocks is equal in size, and the second preset threshold is less than the first preset threshold.

[0016] Optionally, generating a check sub-data block according to the multiple sub-data blocks includes:

[0017] according to: Get the check sub data block;

[0018] Among them, b is the check sub-data block, a1 is the first sub-data block, a2 is the second sub-data block, and a n is the nth sub-data block, n is a natural number, is an XOR operator; the size of the check sub-data block is equal to the size of the sub-data block.

[0019] Optionally, writing the multiple sub-data blocks and the check sub-data block into multiple different read-write channels of the storage area of ​​the storage block includes:

[0020] The multiple sub-data blocks and the check sub-data block are sequentially written or randomly written into multiple different read / write channels of the storage area of ​​the storage block according to the physical addresses of the multiple sub-data blocks and the physical address of the check sub-data block.

[0021] Optionally, the flash memory data reading and writing processing method further includes:

[0022] Receiving physical addresses of a plurality of sub-data blocks;

[0023] The multiple sub-data blocks are sequentially read or randomly read from multiple different read and write channels of the storage area of ​​the storage block according to the physical addresses of the multiple sub-data blocks.

[0024] Optionally, if any read or write channel is unavailable, via:

[0025]

[0026] Get the subdata block of the unavailable read / write channel;

[0027] Among them, b is the check sub-data block, a1 is the first sub-data block, a2 is the second sub-data block, and a n is the nth sub-data block, n is a natural number, a i The sub-data block is an unavailable read / write channel.

[0028] The embodiment of the present invention further provides a flash memory data read and write processing device, comprising:

[0029] An acquisition module, used for acquiring flash memory data to be written into a storage block;

[0030] A processing module, configured to segment the flash memory data to obtain a plurality of segmented data blocks; divide each of the plurality of segmented data blocks into a plurality of sub-data blocks, wherein the plurality of sub-data blocks have the same physical block address; and generate a check sub-data block according to the plurality of sub-data blocks;

[0031] The read / write module is used to write the multiple sub-data blocks and the check sub-data block into multiple different read / write channels of the storage area of ​​the storage block.

[0032] An embodiment of the present invention further provides a computing device, comprising: a processor and a memory storing a computer program, wherein the computer program executes the above method when executed by the processor.

[0033] An embodiment of the present invention further provides a computer-readable storage medium storing instructions, which, when executed on a computer, enable the computer to execute the above method.

[0034] The technical solution of the present invention includes at least the following effects:

[0035] The above-mentioned scheme of the present invention obtains the flash memory data to be written into the storage block; segments the flash memory data to obtain multiple segmented data blocks; divides each of the multiple segmented data blocks into multiple sub-data blocks, and the multiple sub-data blocks have the same physical block address; generates a check sub-data block according to the multiple sub-data blocks; writes the multiple sub-data blocks and the check sub-data block into multiple different read-write channels of the storage area of ​​the storage block; realizes non-blocking concurrent reading and writing of flash memory data, avoids waiting due to read-write conflicts, improves the read-write performance of the flash memory and optimizes the delay. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Figure 1 is a flow chart of a flash memory data reading and writing processing method provided by an embodiment of the present invention;

[0037] Figure 2 It is a schematic diagram of a data stripe disk array structure of a flash memory data read and write processing method provided by an embodiment of the present invention;

[0038] Figure 3 It is a schematic diagram of data arrangement of a flash memory data reading and writing processing method provided by an embodiment of the present invention;

[0039] Figure 4is a structural diagram of a flash memory data read and write processing device provided by an embodiment of the present invention;

[0040] Figure 5 It is a schematic diagram of the structure of a computing device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0041] The exemplary embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present invention are shown in the accompanying drawings, it should be understood that the present invention can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided in order to enable a more thorough understanding of the present invention and to enable the scope of the present invention to be fully communicated to those skilled in the art.

[0042] like Figure 1 As shown, an embodiment of the present invention provides a method for reading and writing flash memory data, comprising:

[0043] Step 11, obtaining the flash memory data to be written into the storage block;

[0044] Step 12, segmenting the flash memory data to obtain a plurality of segmented data blocks;

[0045] Step 13, dividing each of the plurality of divided data blocks into a plurality of sub-data blocks, wherein the plurality of sub-data blocks have the same physical block address;

[0046] Step 14, generating a check sub-data block according to the multiple sub-data blocks;

[0047] Step 15: write the multiple sub-data blocks and the check sub-data block into multiple different read-write channels of the storage area of ​​the storage block.

[0048] In this embodiment, firstly, the flash memory data to be written into the storage block is read from the flash memory device, and the data includes files, database records, system logs or other information;

[0049] In order to realize multi-channel reading and writing processing of flash memory data, it is necessary to divide the data into smaller data blocks to obtain multiple divided data blocks, and then divide each divided data block again to obtain multiple sub-data blocks; although the contents of these sub-data blocks are different, they are logically assigned the same physical block address, or called logical block address, to indicate that they belong to different parts of the same divided data block; the above setting helps all sub-data blocks to correctly read and reassemble the original data after writing; the number of sub-data blocks can be determined based on the size of the data, the limitation of the transmission channel, and the processing capacity of the device; for example, if each transmission channel can only process data packets of a fixed size at a time, the divided data block can be divided into multiple sub-data blocks of such size;

[0050] In order to ensure the integrity and accuracy of the flash memory data to be written into the storage block during the writing process, it is necessary to generate verification data, namely, the verification sub-data block; the verification sub-data block is obtained by calculating the multiple sub-data blocks of a split data block according to a preset mathematical function (such as a hash function, a CRC check code, etc.); each of the multiple sub-data blocks of the split data block can generate a corresponding verification value, and these verification values ​​can be used to verify whether the written data block is complete and has not been tampered with;

[0051] After obtaining multiple sub-data blocks and generating check sub-data blocks, multiple parallel data transmission channels are used to write multiple sub-data blocks and check sub-data blocks; the speed and efficiency of flash memory data reading and writing can be significantly improved because multiple channels can work simultaneously instead of transmitting sequentially; each transmission channel has the same bandwidth, delay and reliability; after multiple sub-data blocks and check sub-data blocks are written, the check sub-data blocks can be used to verify the integrity of the data; when reading, multiple sub-data blocks can be reorganized into original data according to the physical block address.

[0052] The above technical solution of the present invention can achieve non-blocking concurrent reading and writing by optimizing the flash memory data transmission mode, avoiding waiting due to read-write conflicts, improving the flash memory reading and writing performance and optimizing the delay.

[0053] In an optional embodiment, the embodiment of the present invention provides that step 12 may include:

[0054] Step 121 , segmenting the flash memory data according to a first preset threshold value to obtain a plurality of segmented data blocks, wherein the storage space occupied by the plurality of segmented data blocks are all equal in size.

[0055] In this embodiment, in order to realize multi-channel reading and writing of flash memory data, it is necessary to divide the data into smaller data blocks; first, a preset value is determined according to factors such as the size of the data, the limitation of the read and write channels, and the processing capability of the device, and the flash memory data to be read and written is divided according to the preset value to obtain multiple divided data blocks; for example, for a 1MB flash memory data, it is divided according to the size of each divided data block of 4KB, and 256 divided data blocks of equal size can be obtained.

[0056] In an optional embodiment, the embodiment of the present invention provides that step 13 may include:

[0057] Step 131, segment each of the multiple segmented data blocks according to a second preset threshold to obtain multiple sub-data blocks, wherein the storage space occupied by the multiple sub-data blocks is equal in size, and the second preset threshold is less than the first preset threshold.

[0058] In this embodiment, the multiple segmented data blocks obtained in step 121 are segmented again to obtain multiple sub-data blocks; for example, for a segmented data block of 4KB in size, each sub-data block is segmented into 1KB in size to obtain 4 sub-data blocks of equal size.

[0059] In an optional embodiment, the embodiment of the present invention provides that step 14 may include:

[0060] Step 141, according to: b = a1 ⊕ a2 ... ⊕ a n , get the check sub data block;

[0061] Among them, b is the check sub-data block, a1 is the first sub-data block, a2 is the second sub-data block, and a n is the nth sub-data block, n is a natural number, ⊕ is an exclusive-OR operator; the size of the check sub-data block is equal to the size of the sub-data block.

[0062] In this embodiment, the check sub-data block b is obtained by performing an XOR operation on the multiple sub-data blocks obtained in step 131, and the specific formula is b=a1⊕a2……⊕a n ; The check sub-data block can be used to reconstruct the split data block that failed to read or write.

[0063] In an optional embodiment, the embodiment of the present invention provides that step 15 may include:

[0064] Step 151, sequentially or randomly write the multiple sub-data blocks and the check sub-data block into multiple different read / write channels of the storage area of ​​the storage block according to the physical addresses of the multiple sub-data blocks and the physical address of the check sub-data block.

[0065] In this embodiment, in order to write multiple sub-data blocks and their corresponding check sub-data blocks into the storage area of ​​a specified storage block, a sequential writing or random writing method can be adopted according to system requirements, wherein sequential writing means that the sub-data blocks and the check sub-data blocks will be written into the storage area in sequence according to their respective physical address sequences; random writing allows the data blocks to be written in any order, and the writing sequence can be determined according to preset rules; for each sub-data block and check sub-data block, its corresponding physical address is included; these physical addresses are unique identifiers of the data block in the storage area, which are used to locate and access data; the storage area of ​​the storage block includes multiple different read-write channels, which can process data read and write operations in parallel; according to the physical address of the data block, the architecture of the storage system and possible load balancing strategies, one or more suitable read-write channels are selected to write the data block, and the specific process includes writing each sub-data block sequentially or randomly into the selected read-write channel; similarly, the check sub-data block is also written into the corresponding read-write channel.

[0066] The embodiment of the present invention provides an optional embodiment, wherein the flash memory data reading and writing processing method further includes:

[0067] Step 16, receiving physical addresses of multiple sub-data blocks;

[0068] Step 17: sequentially or randomly read the multiple sub-data blocks from multiple different read / write channels of the storage area of ​​the storage block according to the physical addresses of the multiple sub-data blocks.

[0069] In this embodiment, when reading flash memory data, it is first necessary to obtain the physical addresses of multiple sub-data blocks, which are accurate positioning identifiers of data blocks in the storage area of ​​the flash memory storage block; after receiving the accurate physical addresses, it is then necessary to read the corresponding data blocks from the storage area of ​​the flash memory storage block according to these addresses;

[0070] The storage area of ​​a flash memory block usually contains multiple read and write channels, which can process data read and write operations in parallel, thereby improving the overall performance of the storage system;

[0071] If multiple sub-data blocks are physically stored continuously, or data blocks need to be read sequentially according to the requirements of the application scenario, then the sequential reading method can be used. This method can maximize the bandwidth of the read and write channels and improve the reading efficiency.

[0072] If multiple sub-data blocks are physically dispersed and stored, or need to be read according to a specific algorithm or strategy, random reading can be used; although this method may reduce reading efficiency, it can flexibly access any location in the storage area.

[0073] The embodiment of the present invention proposes an optional embodiment, if any read / write channel is unavailable, by:

[0074]

[0075] Get the subdata block of the unavailable read / write channel;

[0076] Among them, b is the check sub-data block, a1 is the first sub-data block, a2 is the second sub-data block, and a n is the nth sub-data block, n is a natural number, a i The sub-data block is an unavailable read / write channel.

[0077] In this embodiment, when a certain read / write channel is unavailable, the sub-data block transmitted in the unavailable read / write channel can be obtained by processing the check sub-data block and other available sub-data blocks. The specific formula includes:

[0078]

[0079] A specific embodiment of the flash memory data read and write processing method provided by the embodiment of the present invention is:

[0080] Step 1, obtaining the flash memory data to be written into the storage block;

[0081] Step 2, segmenting the flash memory data to obtain a plurality of segmented data blocks;

[0082] Specifically, taking a flash memory data with a size of 1MB as an example, the flash memory data is divided according to the size of each divided data block being 4KB, and 256 divided data blocks can be obtained.

[0083] Step 3, dividing each of the plurality of divided data blocks into a plurality of sub-data blocks, wherein the plurality of sub-data blocks have the same physical block address;

[0084] Specifically, taking a 4KB split data block as an example, the 4KB split data block can be divided into four 1KB sub-data blocks and placed in four different flash memory (NAND) channels; all sub-data blocks have the same physical block address.

[0085] Step 4: Generate a check sub-data block according to the multiple sub-data blocks.

[0086] Specifically, a 1KB check sub-data block is generated according to the four 1KB sub-data blocks and stored in the fifth flash memory channel;

[0087] Step 5: write the multiple sub-data blocks and the check sub-data block into multiple different read-write channels of the storage area of ​​the storage block.

[0088] Specifically, to read a 4KB split data block, all 4 channels can be read simultaneously and the data can be put together; if one of the data channels is unavailable, the 1KB sub-data block of this channel can be reconstructed through the 1KB parity sub-data block and any 3 1KB sub-data blocks; therefore, any 4 1KB sub-data blocks in 5 channels can be read to obtain a 4KB split data block;

[0089] The above five channels implement a 4+1 redundant arrays of independent disks (RAID) channel. Figure 2 As shown; Data stripe 4+1RAID lays the foundation for NAND non-blocking write characteristics; Since any of the 4 channels can be used to read data at full speed, one data channel can also be used for write traffic; As long as the write traffic does not exceed the capacity of one channel, reads and writes can be performed concurrently; To complete the write of a 4KB split data block, a 1KB sub-data block needs to be written to each channel, and a 1KB check sub-data block needs to be written to the parity channel; For full-channel write mode, all 5 channels are written at the same time, and parity is dynamically generated from the 4 data blocks; When accessing a 4KB split data block, an identical physical block address is sent to each of the 4 / 5 NAND drives; Each 1KB sub-data block requires a physical block address, which is the same for the entire RAID, so it is equivalent to having one address for each 4KB split data block;

[0090] The data is arranged in an independent 4KB RAID (4+1) structure as follows Figure 3 shown; from Figure 3 It can be seen that each 4KB split data block is placed in a NAND channel instead of being distributed on 4 NANDs; 4 NAND channels contain data, while the 5th NAND channel contains check information; the check information is generated by XORing the data in the other 4 NANDs with the same physical block address; the 4 NAND channels can be read in parallel with different physical block addresses; each channel can contain multiple NAND chips; every 5 channels are combined into a RAID channel; the RAID channel consists of multiple RAID groups; the RAID group consists of 5 NAND chips, 4 of which are used for data and 1 for check; all RAID groups in the same RAID channel must run in the same working mode; the working modes include: full channel read, full channel write, and mixed read and write combination (i.e. 4 channel read + single channel write);

[0091] On random reads, random read performance is improved, with 4x efficiency gained due to reading split data blocks of 4KB from each NAND. If data is written randomly and read back sequentially, the behavior is similar to a random read because the physical block addresses of these requests are random.

[0092] Similarly, if data is written sequentially but read back randomly, this also exhibits random behavior; a sequential read here means that data is written sequentially in both the logical block address and the physical block address, and read back sequentially in the logical block address (the physical block address will automatically be written sequentially); for a standalone 4K RAID, the performance of a sequential read will be as good as the best random read; the best random read means that requests are evenly distributed among all NANDs with few conflicts; both sequential and random reads make full use of the flash bus, so performance can be maximized;

[0093] In a RAID group, data blocks and check blocks with the same physical block address are bound as a group; therefore, no additional data structure is required to track the grouping; this also makes error recovery easy; if data reading fails, just read the other 4 channels using the same physical block address and reconstruct the missing data through XOR; some data blocks may become invalid after being overwritten by the host to the logical block address space; for example, if the same logical address is written twice, the new data will be written to a new physical address location, and the data at the old physical address location will become obsolete; however, this will not affect the validity of the parity check; as long as the invalid data is not erased, the parity check is valid and can be used for data recovery; when garbage collection is performed, the valid data will be moved to a new location and a new copy will be generated.

[0094] In the mixed read-write mode, four channels are used for reading and the remaining channel is used for writing. Reading and writing can be performed simultaneously, which implements non-blocking writing.

[0095] The flash memory data read and write processing method proposed by the present invention realizes non-blocking concurrent reading and writing of the flash memory data, avoids waiting due to read and write conflicts, improves the read and write performance of the flash memory and optimizes the delay.

[0096] like Figure 4 As shown, the embodiment of the present invention further provides a flash memory data read and write processing device 40, comprising:

[0097] An acquisition module 41 is used to acquire the flash memory data to be written into the storage block;

[0098] The processing module 42 is used to segment the flash memory data to obtain a plurality of segmented data blocks; divide each of the plurality of segmented data blocks into a plurality of sub-data blocks, wherein the plurality of sub-data blocks have the same physical block address; and generate a check sub-data block according to the plurality of sub-data blocks;

[0099] The read / write module 43 is configured to write the plurality of sub-data blocks and the check sub-data block into a plurality of different read / write channels of the storage area of ​​the storage block.

[0100] Optionally, the processing module 42 is specifically used for:

[0101] The flash memory data is segmented according to a first preset threshold value to obtain a plurality of segmented data blocks, wherein the storage space occupied by the segmented data blocks is equal in size.

[0102] Optionally, the processing module 42 is further specifically configured to:

[0103] Each of the plurality of divided data blocks is divided according to a second preset threshold to obtain a plurality of sub-data blocks, wherein the storage space occupied by the plurality of sub-data blocks is equal in size, and the second preset threshold is less than the first preset threshold.

[0104] Optionally, the processing module 42 is further specifically configured to:

[0105] according to: Get the check sub data block;

[0106] Among them, b is the check sub-data block, a1 is the first sub-data block, a2 is the second sub-data block, and a n is the nth sub-data block, n is a natural number, is an XOR operator; the size of the check sub-data block is equal to the size of the sub-data block.

[0107] Optionally, the read-write module 43 is specifically used for:

[0108] The multiple sub-data blocks and the check sub-data block are sequentially written or randomly written into multiple different read / write channels of the storage area of ​​the storage block according to the physical addresses of the multiple sub-data blocks and the physical address of the check sub-data block.

[0109] Optionally, the flash memory data reading and writing processing device 40 further includes:

[0110] The acquisition module 41 is further used to receive the physical addresses of the plurality of sub-data blocks;

[0111] The read / write module 43 is further configured to sequentially or randomly read the multiple sub-data blocks from multiple different read / write channels of the storage area of ​​the storage block according to the physical addresses of the multiple sub-data blocks.

[0112] Optionally, if any read or write channel is unavailable, via:

[0113]

[0114] Get the subdata block of the unavailable read / write channel;

[0115] Among them, b is the check sub-data block, a1 is the first sub-data block, a2 is the second sub-data block, and a n is the nth sub-data block, n is a natural number, a i The sub-data block is an unavailable read / write channel.

[0116] It should be noted that the device is a device corresponding to the above-mentioned flash memory data read and write processing method, and all implementation methods in the above-mentioned method embodiment are applicable to this embodiment and can achieve the same technical effect.

[0117] like Figure 5 As shown, the embodiment of the present invention further provides a computing device 50, including a processor 51, a memory 52, and a program or instruction stored in the memory 52 and executable on the processor 51. When the program or instruction is executed by the processor 51, each process of the above-mentioned flash memory data read and write processing method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. It should be noted that the computing device in the embodiment of the present invention includes the above-mentioned mobile electronic device and non-mobile electronic device.

[0118] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0119] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the systems, devices and units described above can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0120] In the embodiments provided by the present invention, it should be understood that the disclosed devices and methods can be implemented in other ways. For example, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or units, which can be electrical, mechanical or other forms.

[0121] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0122] In addition, each functional unit in each embodiment of the present invention may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0123] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the methods of various embodiments of the present invention. The aforementioned storage medium includes: various media that can store program codes, such as USB flash drives, mobile hard disks, ROM, RAM, magnetic disks, or optical disks.

[0124] In addition, it should be noted that in the apparatus and method of the present invention, it is obvious that each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent schemes of the present invention. Moreover, the steps of performing the above-mentioned series of processing can naturally be performed in chronological order according to the order of description, but it is not necessary to perform them in chronological order, and some steps can be performed in parallel or independently of each other. For those of ordinary skill in the art, it is understood that all or any steps or components of the method and apparatus of the present invention can be implemented in any computing device (including processors, storage media, etc.) or a network of computing devices in hardware, firmware, software or a combination thereof, which can be achieved by those of ordinary skill in the art using their basic programming skills after reading the description of the present invention.

[0125] Therefore, the purpose of the present invention can also be achieved by running a program or a group of programs on any computing device. The computing device can be a well-known general-purpose device. Therefore, the purpose of the present invention can also be achieved by simply providing a program product containing a program code for implementing a method or device. That is to say, such a program product also constitutes the present invention, and a storage medium storing such a program product also constitutes the present invention. Obviously, the storage medium can be any well-known storage medium or any storage medium developed in the future. It should also be pointed out that in the device and method of the present invention, it is obvious that each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent schemes of the present invention. In addition, the steps of performing the above-mentioned series of processing can naturally be performed in chronological order according to the order of description, but it is not necessary to perform them in chronological order. Some steps can be performed in parallel or independently of each other.

[0126] The above are preferred embodiments of the present invention. It should be pointed out that, for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as within the scope of protection of the present invention.

Claims

1. A method for reading and writing flash memory data, characterized in that: include: Obtaining flash memory data to be written into a storage block; Segmenting the flash memory data to obtain a plurality of segmented data blocks; Dividing each of the plurality of divided data blocks into a plurality of sub-data blocks, wherein the plurality of sub-data blocks have the same physical block address; generating a check sub-data block according to the plurality of sub-data blocks; The multiple sub-data blocks and the check sub-data block are written into multiple different read-write channels of the storage area of ​​the storage block.

2. The flash memory data reading and writing processing method according to claim 1, characterized in that: The flash memory data is segmented to obtain a plurality of segmented data blocks, including: The flash memory data is segmented according to a first preset threshold value to obtain a plurality of segmented data blocks, wherein the storage spaces occupied by the plurality of segmented data blocks are all equal in size.

3. The flash memory data reading and writing processing method according to claim 2, characterized in that: Dividing each of the plurality of divided data blocks into a plurality of sub-data blocks comprises: Each of the plurality of divided data blocks is divided according to a second preset threshold to obtain a plurality of sub-data blocks, wherein the storage space occupied by the plurality of sub-data blocks is equal in size, and the second preset threshold is less than the first preset threshold.

4. The flash memory data reading and writing processing method according to claim 1, characterized in that: Generating a check sub-data block according to the multiple sub-data blocks includes: According to: b = a1 ⊕ a2 … ⊕ a n , get the check sub data block; Among them, b is the check sub-data block, a1 is the first sub-data block, a2 is the second sub-data block, and a n is the nth sub-data block, n is a natural number, ⊕ is an XOR operator; the size of the check sub-data block is equal to the size of the sub-data block.

5. The flash memory data reading and writing processing method according to claim 1, characterized in that: Writing the plurality of sub-data blocks and the check sub-data block into a plurality of different read-write channels of the storage area of ​​the storage block comprises: The multiple sub-data blocks and the check sub-data block are sequentially written or randomly written into multiple different read / write channels of the storage area of ​​the storage block according to the physical addresses of the multiple sub-data blocks and the physical address of the check sub-data block.

6. The flash memory data reading and writing processing method according to claim 1, characterized in that: Also includes: Receiving physical addresses of a plurality of sub-data blocks; The multiple sub-data blocks are sequentially read or randomly read from multiple different read and write channels of the storage area of ​​the storage block according to the physical addresses of the multiple sub-data blocks.

7. The flash memory data reading and writing processing method according to claim 1, characterized in that: If any read or write channel is unavailable, Get the subdata block of the unavailable read / write channel; Among them, b is the check sub-data block, a1 is the first sub-data block, a2 is the second sub-data block, and a n is the nth sub-data block, n is a natural number, a i The sub-data block is an unavailable read / write channel.

8. A flash memory data read and write processing device, characterized in that: include: An acquisition module, used for acquiring flash memory data to be written into a storage block; A processing module, used for segmenting the flash memory data to obtain a plurality of segmented data blocks; Dividing each of the plurality of divided data blocks into a plurality of sub-data blocks, wherein the plurality of sub-data blocks have the same physical block address; and generating a check sub-data block according to the plurality of sub-data blocks; The read / write module is used to write the multiple sub-data blocks and the check sub-data block into multiple different read / write channels of the storage area of ​​the storage block.

9. A computing device, characterized in that include: A processor and a memory storing a computer program, wherein when the computer program is executed by the processor, the method according to any one of claims 1 to 7 is performed.

10. A computer-readable storage medium, characterized in that: Instructions are stored, and when the instructions are executed on a computer, the computer is caused to execute the method according to any one of claims 1 to 7.

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