Microoperation extraction method and device based on physical memory protection and electronic equipment

Abstract

The invention discloses a microoperation extraction method, and particularly relates to a microoperation extraction method and device based on physical memory protection and electronic equipment. The method comprises the steps of performing matching in a microoperation cache based on an instruction virtual address in an instruction fetching request, and obtaining a corresponding target physical address based on a target cache virtual address under the condition that the target cache virtual address is obtained from the microoperation cache through matching; checking the access authority of the target physical address; and extracting the target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address under the condition that the target physical address or the target cache virtual address is checked to be legal. According to the method, physical address permission check is added in a system using the instruction virtual address to index the micro-operation cache, so that the problem that the cache hit rate is reduced due to the fact that the micro-operation cache needs to be refreshed when a traditional micro-operation cache modifies the physical memory access permission can be solved.

Description

Technical Field

[0001] The present invention belongs to the technical field of micro-operation extraction, and in particular relates to a micro-operation extraction method, device and electronic equipment based on physical memory protection. Background Art

[0002] In modern high-performance processor designs, a processor executes program code instructions, or more simply, instructions that cause the processor to perform corresponding operations. For example, a processor, such as a central processing unit (CPU), can execute instructions from a software application, an operating system, firmware, etc. Some processors are capable of executing one or more specific micro-operation instructions or "macro-instructions" decomposed by an instruction decoder. Each micro-operation is a simpler low-level processor instruction that, when executed by the processor, causes the processor execution unit to further decode the corresponding portion of the entire operation of the micro-operation instruction. When the processor executes an instruction, the steps of extracting the instruction to be executed from the instruction cache or memory subsystem and decoding the extracted instruction into a micro-operation for execution take a relatively long time and consume a lot of energy. Therefore, designers have proposed techniques for accelerating the acquisition of micro-operations from instructions. One of these techniques is to use a cache memory called a micro-operation cache (Micro-Op / uop Cache) to save a copy of the micro-operations decoded from the instruction. For this technology, the micro-operation decoded from the instruction is forwarded to the execution unit in the processor for execution, and the processor saves a copy of the micro-operation in the micro-operation cache together with the operation. When the instruction whose copy of the micro-operation is stored in the micro-operation cache is encountered again, the processor can directly obtain the micro-operation from the micro-operation cache, without having to obtain the instruction code from the instruction cache or memory subsystem again and perform complex decoding operations.

[0003] The micro-operation cache is mainly indexed by virtual addresses. When the instruction virtual address hits the micro-operation cache, the processor can quickly obtain the corresponding micro-operation information from the micro-operation cache without complex instruction decoding. The kernel of a modern operating system needs to be isolated from the user space to prevent user programs from directly accessing the kernel memory; especially in a multi-tasking operating system, multiple processes run at the same time, and each process also needs to set up independent memory space and access rights, which will involve the physical memory protection (PMP) permission allocation and modification process.

[0004] The existing micro-operation cache uses the VIVT (Virtual Index Virtual Tag) indexing method, so only the virtual address needs to be recorded. When the PMP permissions are modified, in order to ensure that the execution permissions of the instructions after hitting the micro-operation cache are correct, the entire micro-operation cache needs to be refreshed. The direct refresh of the micro-operation cache will cause the cache hit rate to decrease, thereby affecting the performance and power consumption of the processor. Summary of the invention

[0005] The technical problem to be solved by the present invention is that when the PMP permissions are modified, the above-mentioned method commonly used in the prior art needs to refresh the entire micro-operation cache, resulting in a decrease in the cache hit rate, thereby affecting the performance and power consumption of the processor. In order to solve the above-mentioned problem, the present invention provides a micro-operation extraction method, device and electronic device based on physical memory protection.

[0006] The content of the present invention includes: In a first aspect, an embodiment of the present invention provides a micro-operation extraction method based on physical memory protection, comprising: Matching in a micro-operation cache based on the instruction virtual address in the instruction fetch request, the micro-operation cache including multiple groups of cache data, each group of cache data including a cache virtual address, a cache physical address and cache micro-operation information; In case a target cache virtual address is matched from the micro-operation cache, a corresponding target physical address is acquired based on the target cache virtual address; Checking access rights to the target physical address; When the legality is checked, the target micro-operation is extracted from the micro-operation cache based on the target physical address or the target cache virtual address.

[0007] Optionally, acquiring a corresponding target physical address based on the target cache virtual address includes: The physical address corresponding to the target cache virtual address is determined as the target physical address.

[0008] Optionally, matching in a micro-operation cache based on an instruction virtual address in an instruction fetch request comprises: Matching the virtual page number in the instruction virtual address with the virtual page number in the cache virtual address; In the case where the first cache virtual address is obtained by matching, determining whether the page offset in the instruction virtual address is the same as the page offset in the first cache virtual address; The first cache virtual address having the same in-page offset as the instruction virtual address is determined as the target cache address, otherwise the match is unsuccessful.

[0009] Optionally, after matching the instruction virtual address in the instruction fetch request in the micro-operation cache, the method further comprises: In case of no successful match from the micro-operation cache, converting the instruction virtual address to a corresponding target physical address; performing a match in an instruction cache based on the target physical address; If the match is successful, obtaining an instruction operation code based on the target physical address; A corresponding micro-operation and information about the micro-operation are acquired based on the instruction opcode.

[0010] Optionally, after acquiring the corresponding micro-operation and the information of the micro-operation based on the instruction opcode, the method further includes: The information of the micro-operation, the instruction virtual address corresponding to the micro-operation and the target physical address corresponding to the micro-operation are stored in the micro-operation cache.

[0011] Optionally, matching in an instruction cache based on the target physical address comprises: Checking access rights to the target physical address; In the case of checking legality, a match is performed in the instruction cache based on the target physical address.

[0012] In a second aspect, an embodiment of the present invention further provides a micro-operation extraction device based on physical memory protection, comprising: A first matching module, configured to match in a micro-operation cache based on an instruction virtual address in an instruction fetch request, wherein the micro-operation cache includes a plurality of groups of cache data, each group of cache data includes a cache virtual address, a cache physical address and cache micro-operation information; A first acquisition module, configured to acquire a corresponding target physical address based on the target cache virtual address when a target cache virtual address is matched from the micro-operation cache; A checking module, used for checking the access rights of the target physical address; The extraction module is used to extract the target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address when checking for legality.

[0013] In a third aspect, an embodiment of the present invention further provides a device for implementing physical memory protection in a micro-operation cache, comprising: A micro-operation cache, wherein the micro-operation cache is used to store multiple groups of cache data, each group of cache data includes a cache virtual address, a cache physical address and cache micro-operation information; A processor instruction fetch queue, the processor instruction fetch queue is used to match the instruction virtual address in the micro-operation cache based on the instruction fetch request; An MMU unit, wherein the MMU unit is used to obtain a corresponding target physical address based on the target cache virtual address when the target cache virtual address is matched from the micro-operation cache; A PMP unit, wherein the PMP unit is used to check access rights of the target physical address.

[0014] In a fourth aspect, an embodiment of the present invention provides an electronic device, comprising: a memory, a processor, and a program stored in the memory and executable on the processor; the processor is used to read the program in the memory to implement the steps in the micro-operation extraction method based on physical memory protection as described in the first aspect.

[0015] In a fifth aspect, an embodiment of the present invention provides a readable storage medium for storing a program, which, when executed by a processor, implements the steps in the micro-operation extraction method based on physical memory protection as described in the first aspect.

[0016] The beneficial effect of the present invention is that, in an embodiment of the present invention, a match is performed in the micro-operation cache based on the instruction virtual address in the instruction fetch request; when the target cache virtual address is matched from the micro-operation cache, the corresponding target physical address is obtained based on the target cache virtual address; the access rights of the target physical address are checked; and when the check is legal, the target micro-operation is extracted from the micro-operation cache based on the target physical address. The method provided by the present invention adds a physical address permission check to a system that uses an instruction virtual address to index a micro-operation cache, which can reduce the refresh of micro-operations caused by the modification of physical memory protection permissions, improve the hit rate of the micro-operation cache, effectively reduce processor power consumption, improve processor performance, and has the advantages of low overhead, easy implementation, and flexible use. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Attached Figure 1 One of the flow charts of the micro-operation extraction method based on physical memory protection provided by an embodiment of the present invention; Attached Figure 2 A schematic diagram of a device for implementing physical memory protection in a micro-operation cache provided by an embodiment of the present invention; Attached Figure 3 A schematic diagram of a virtual address and a physical address structure provided by an embodiment of the present invention; Attached Figure 4 The second flowchart of the micro-operation extraction method based on physical memory protection provided by an embodiment of the present invention; Attached Figure 5A schematic diagram of a micro-operation extraction device based on physical memory protection provided by an embodiment of the present invention; Attached Figure 6 A schematic diagram of the structure of an electronic device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0018] In the embodiments of the present application, the term "and / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. In the embodiments of the present application, the term "multiple" refers to two or more, and other quantifiers are similar. The terms "first", "second", etc. in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the terms used in this way can be interchangeable under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described here, and the objects distinguished by "first" and "second" are generally of the same type, and the number of objects is not limited. For example, the first object can be one or more.

[0019] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0020] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0021] The embodiments of the present application provide a micro-operation extraction method, device and electronic device based on physical memory protection, aiming to solve the problem of a decrease in cache hit rate caused by the need to refresh the micro-operation cache when modifying physical memory access rights in a traditional micro-operation cache.

[0022] See also Figure 1 , Figure 1 A flow chart of a micro-operation extraction method based on physical memory protection provided by an embodiment of the present invention is provided. The method specifically comprises the following steps: Step 101, matching is performed in a micro-operation cache based on an instruction virtual address in an instruction fetch request, wherein the micro-operation cache includes multiple groups of cache data, each group of cache data includes a cache virtual address, a cache physical address and cache micro-operation information.

[0023] Step 102: when a target cache virtual address is obtained by matching from the micro-operation cache, a corresponding target physical address is obtained based on the target cache virtual address.

[0024] Step 103: Check the access rights of the target physical address.

[0025] Step 104 : if the check is legal, extract the target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address.

[0026] In the embodiments of the present application, the present invention adds a check of access rights of the physical address to a system that uses the instruction virtual address to index the micro-operation cache, which can solve the problem of a decrease in cache hit rate caused by the need to refresh the micro-operation cache when modifying the physical memory access rights of the traditional micro-operation cache, and has significant technical advantages and application value.

[0027] like Figure 2 As shown, an embodiment of the present invention further provides a device for implementing physical memory protection in a micro-operation cache for implementing the micro-operation extraction method based on physical memory protection. The device for implementing physical memory protection in a micro-operation cache includes: A micro-operation cache 201, wherein the micro-operation cache 201 is used to store multiple groups of cache data, each group of cache data includes a cache virtual address, a cache physical address and cache micro-operation information; A processor instruction fetch queue 202, the processor instruction fetch queue 202 is used to send instruction fetch requests and match the instructions in the micro-operation cache based on the instruction virtual address in the instruction fetch request; An MMU unit 203, wherein the MMU unit 203 is used to obtain a corresponding target physical address based on the target cache virtual address when the target cache virtual address is matched from the micro-operation cache; The PMP unit 204 is configured to check access rights to the target physical address.

[0028] Specifically, the processor instruction fetch queue issues an instruction fetch request, which includes the instruction virtual address, and indexes the micro-operation cache through the instruction virtual address (Virtual Address, VA) PC (Program Counter). In step 101, a cache virtual address matching the instruction virtual address is searched in the micro-operation cache. If the match is successful, the target cache virtual address can be obtained, and the corresponding target physical address (Physical Address, PA) is obtained through the target cache virtual address.

[0029] It should be understood that there are multiple groups of cache data cached in the micro-operation cache, and each group of cache data is composed of a cache virtual address, a cache physical address and cache micro-operation information. In some embodiments, the micro-operation cache includes VA cache entries and PA cache entries.

[0030] For example, Figure 3 As shown in the figure, in SV48 mode, the virtual address (VA) includes the virtual page number (VPN) part and the page offset (page offset) corresponding to the virtual address. The bit range of the virtual address in the processor is as follows: VA[49:0]. The physical address (PA) includes the physical page number (PPN) part and the page offset (page offset) corresponding to the physical address. The bit range of the physical address in the processor is as follows: PA[39:12].

[0031] Optionally, in some embodiments, step 101 includes: Matching the virtual page number in the instruction virtual address with the virtual page number in the cache virtual address; In the case where the first cache virtual address is obtained by matching, determining whether the page offset in the instruction virtual address is the same as the page offset in the first cache virtual address; The first cache virtual address having the same in-page offset as the instruction virtual address is determined as the target cache address, otherwise the match is unsuccessful.

[0032] like Figure 3 As shown, specifically, the virtual page number is a cache unit in the virtual address used to cache the virtual page number (Physic Page Number, PPN). The page offset (page offset) can also be called a tag value, which is generally the lower 12 bits of the virtual address.

[0033] In this embodiment, the virtual page number part in the virtual address is first matched, and in the case of matching, the offset part in the page is matched. As a specific embodiment, the matching process of step 102 includes two stages: in the first stage, it is determined whether the virtual page number of the instruction virtual address is hit. If there is no match in the micro-operation cache, vact_hit is set to 0 and the match is unsuccessful. If there is any match and the first cache virtual address is obtained, vact_hit is set to 1; in the second stage, it is determined whether the tag value in the first cache virtual address is the same as the tag value in the instruction virtual address. If the tags are not the same, mtag_hit is set to 0 and the match is unsuccessful. If the tag hits, mtag_hit is set to 1 to obtain the target cache address.

[0034] Optionally, in some embodiments, acquiring the corresponding target physical address based on the target cache virtual address includes: The physical address corresponding to the target cache virtual address is determined as the target physical address.

[0035] In this embodiment, the cache physical address corresponding to the cache data to which the target cache virtual address belongs is determined as the target physical address. Exemplarily, the target physical address is the cache physical address corresponding to the vact_hit hit item in the process of matching in the micro-operation cache based on the instruction virtual address. In the above manner, there is no need to perform additional conversion between virtual and real addresses, thereby improving the efficiency of obtaining the corresponding target address.

[0036] As a specific embodiment, the memory management unit (MMU) performs step 103 to complete the virtual-to-real address conversion and obtain the target physical address. Exemplarily, the MMU includes a translation lookaside buffer (TLB) and a PTW (Page Table Walk) component, and the virtual-to-real page table translation mechanism involved includes SV39 / SV48 / SV57 modes.

[0037] In step 103, after obtaining the target physical address, the access rights of the target physical address are checked. As a specific embodiment, step 103 is executed by the PMP unit to check the access rights of the target physical address. In some embodiments, the PMP unit includes a set of configurable registers, specifically including 8 PMP configuration registers (denoted as pmpcfg0-pmpcfg8) and 8 PMP address registers (denoted as pmpaddr0-pmpaddr7). In other embodiments, it can be expanded to more PMP configuration registers. In the above embodiment, the minimum protected physical memory granularity is 4KB, which is the same as the minimum granularity of the MMU translation page table. Each area can configure three memory access attributes, namely X (executable), R (readable) and W (writable).

[0038] Specifically, there are three ways to represent the PMP protection area: TOR, NA4, and NAPOT. TOR uses two pmpadr registers to represent the start address and end address of the protected address space, and the protection area is located between these two addresses. NA4 indicates that the 4 bytes aligned to the corresponding pmpadr address are the protection space. NAPOT indicates that the pmpadr address starts and the maximum is 2. (XLEN+3) The byte-aligned area is the protection space, where XLEN is the bit width of the integer register in the RISC-V instruction set architecture, which is usually consistent with the address space size. Exemplarily, XLEN is 32, 64 or 128.

[0039] Optionally, in some embodiments, after step 101, the method further includes: In case of no successful match from the micro-operation cache, converting the instruction virtual address to a corresponding target physical address; performing a match in an instruction cache based on the target physical address; If the match is successful, obtaining an instruction operation code based on the target physical address; A corresponding micro-operation and information about the micro-operation are acquired based on the instruction opcode.

[0040] Optionally, in some embodiments, matching in an instruction cache based on the target physical address comprises: Checking access rights to the target physical address; In the case of checking legality, a match is performed in the instruction cache based on the target physical address.

[0041] In this embodiment, by checking the access rights of the target physical address, there is no need to perform micro-operation cache refresh when the system modifies the physical memory access rights, thereby improving the cache hit rate and processor performance. It has the advantages of low overhead, easy implementation, low implementation cost, and flexible use, and can be flexibly applied to existing processor designs.

[0042] like Figure 2 As shown, in some embodiments, the device for implementing physical memory protection in the micro-operation cache further includes: An instruction cache 205, wherein the instruction cache 205 is used to cache multiple groups of instruction data, each group of the instruction data includes an instruction cache physical address and a corresponding instruction opcode; The decoding unit 206 is used to obtain the corresponding micro-operation and the information of the micro-operation based on the instruction operation code.

[0043] Specifically, the decoding unit splits the instruction opcode into one or more micro-operations and decodes information of each micro-operation.

[0044] Alternatively, if Figure 2 As shown, in some embodiments, the device for implementing physical memory protection in the micro-operation cache further includes a register renaming unit 207, and the register renaming unit 207 is used to perform register renaming. In a specific implementation, after extracting the target micro-operation from the micro-operation cache based on the target physical address, the acquired target micro-operation is sent to the register renaming unit for register renaming.

[0045] Optionally, in some embodiments, after acquiring the corresponding micro-operation and the information of the micro-operation based on the instruction opcode, the method further includes: The information of the micro-operation, the instruction virtual address corresponding to the micro-operation and the target physical address corresponding to the micro-operation are stored in the micro-operation cache.

[0046] In this embodiment, the uncached micro-operations can be added to the micro-operation cache in the above manner, and there is no need to decode again when extracting the micro-operations subsequently, thereby improving the efficiency of micro-operation extraction.

[0047] The following takes a specific embodiment as an example to illustrate the specific implementation process of the micro-operation extraction method based on physical memory protection provided by the embodiment of the present invention. Figure 2 and Figure 4 As shown, as a specific embodiment, the micro-operation extraction method based on physical memory protection specifically includes the following steps: S0: The processor instruction fetch queue 202 issues an instruction fetch request and indexes the micro-operation cache through the instruction virtual address PC.

[0048] In one case, if the search in S0 hits and obtains the target cache virtual address, the following steps S1-S3 are executed: S1: According to the target cache virtual address PC obtained in S0, the cache entry in the micro-operation cache 201 is indexed to obtain the corresponding target physical address PA.

[0049] S2: Send the target physical address PA obtained in S1 to the PMP unit 204 for access permission check. If the permission check is legal, jump to S3 for execution. If the permission check is illegal, an access error is generated, the instruction fetch request is terminated, and the system is reported for exception handling.

[0050] S3: extracting the target micro-operation cached in the micro-operation cache 201 according to the target cache virtual address, and sending the acquired target micro-operation to the register renaming unit 207 for register renaming.

[0051] In another case, if the search in step S0 fails, the process jumps from step S0 to execute the following steps S4-S8: S4: The MMU unit 203 completes the virtual-to-real address translation, and obtains the target physical address PA corresponding to the instruction virtual address PC.

[0052] S5: The PMP unit 204 performs an access permission check on the target physical address PA obtained in S21. If the permission check is legal, the process jumps to step S6. If the check is illegal, an access error is generated, the instruction fetch request is terminated, and the system is reported for exception handling.

[0053] S6: Index the instruction cache 205 through the target physical address PA and extract the instruction operation code.

[0054] S7: The decoding unit 206 splits the instruction opcode into one or more micro-operations and decodes information of each micro-operation.

[0055] S8: Send the micro-operation obtained in S7 to the register renaming unit 207 to perform register renaming; at the same time, cache the micro-operation information obtained in S7, and the physical address and virtual address corresponding to the micro-operation information into the micro-operation cache 201.

[0056] The method provided by the embodiment of the present invention can improve the cache hit rate by adding a physical memory protection check to the index of the micro-operation cache. When the system modifies the physical memory access rights, there is no need to perform a micro-operation cache refresh action. At the same time, the method provided by the embodiment of the present invention has a small overhead. It only needs to increase a small amount of cache space when caching VA corresponding to caching PA. The PMP unit only needs to instantiate the PMP module that has been implemented in the system without special processing.

[0057] like Figure 5 As shown, the embodiment of the present invention further provides a micro-operation extraction device 500 based on physical memory protection, comprising: A first matching module 501, configured to match in a micro-operation cache based on an instruction virtual address in an instruction fetch request, wherein the micro-operation cache includes multiple groups of cache data, each group of cache data includes a cache virtual address, a cache physical address and cache micro-operation information; A first acquisition module 502 is used to acquire a corresponding target physical address based on the target cache virtual address when the target cache virtual address is matched from the micro-operation cache; A checking module 503, configured to check access rights to the target physical address; The extraction module 504 is used to extract the target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address when checking for legality.

[0058] Optionally, acquiring a corresponding target physical address based on the target cache virtual address includes: The physical address corresponding to the target cache virtual address is determined as the target physical address.

[0059] Optionally, the matching module 501 includes: A matching unit, configured to match a virtual page number in the instruction virtual address with a virtual page number in the cache virtual address; A judging unit, configured to judge whether the page offset in the instruction virtual address is the same as the page offset in the first cache virtual address when the first cache virtual address is matched; The determination unit is used to determine the first cache virtual address whose in-page offset is the same as the instruction virtual address as the target cache address, otherwise the match is unsuccessful.

[0060] Optionally, the micro-operation extraction device 500 based on physical memory protection further includes: A conversion module, used for converting the instruction virtual address into a corresponding target physical address when no match is successful from the micro-operation cache; A second matching module, configured to perform matching in an instruction cache based on the target physical address; A second acquisition module is used to acquire the instruction operation code based on the target physical address when the match is successful; The third acquisition module is used to acquire the corresponding micro-operation and the information of the micro-operation based on the instruction operation code.

[0061] Optionally, the micro-operation extraction device 500 based on physical memory protection further includes: The storage module is used to store the information of the micro-operation, the instruction virtual address corresponding to the micro-operation and the target physical address corresponding to the micro-operation in the micro-operation cache.

[0062] Optionally, the second matching module is specifically used to: Checking access rights to the target physical address; In the case of checking legality, a match is performed in the instruction cache based on the target physical address.

[0063] The micro-operation extraction device 500 based on physical memory protection provided in the embodiment of the present application can execute the above method embodiment, and its implementation principle and technical effect are similar, which will not be repeated in this embodiment.

[0064] It should be noted that the division of units in the embodiments of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation. In addition, each functional unit in each embodiment of the present application may be integrated into a processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0065] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a processor-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, server, or network device, etc.) or a processor (processor) to execute all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: U disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access Memory, RAM), disk or optical disk and other media that can store program codes.

[0066] like Figure 6As shown, an embodiment of the present application provides an electronic device 600, comprising: a memory 602, a processor 601, and a program stored in the memory 602 and executable on the processor 601; the processor 601 is used to read the program in the memory 602 to implement the steps in the micro-operation extraction method based on physical memory protection as described above.

[0067] An embodiment of the present application also provides a readable storage medium, on which a program is stored. When the program is executed by a processor, the various processes of the above-mentioned micro-operation extraction method embodiment based on physical memory protection are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here. Among them, the readable storage medium can be any available medium or data storage device that can be accessed by the processor, including but not limited to magnetic storage (such as floppy disk, hard disk, magnetic tape, magneto-optical disk (MO), etc.), optical storage (such as compact disk (CD), digital video disc (DVD), Blu-ray Disc (BD), high-definition versatile disc (HVD), etc.), and semiconductor storage (such as read-only memory (ROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read only memory (EEPROM), non-volatile memory (NAND FLASH), solid-state drive (Solid State Disk or Solid State Drive, SSD)), etc.

[0068] It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0069] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal (which can be a mobile phone, computer, server, air conditioner, or network equipment, etc.) to execute the methods described in each embodiment of the present application.

[0070] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A micro-operation extraction method based on physical memory protection, characterized in that: include: Matching in a micro-operation cache based on the instruction virtual address in the instruction fetch request, the micro-operation cache including multiple groups of cache data, each group of cache data including a cache virtual address, a cache physical address and cache micro-operation information; In case a target cache virtual address is matched from the micro-operation cache, a corresponding target physical address is acquired based on the target cache virtual address; Checking access rights to the target physical address; When the legality is checked, the target micro-operation is extracted from the micro-operation cache based on the target physical address or the target cache virtual address.

2. The method according to claim 1, characterized in that: The acquiring the corresponding target physical address based on the target cache virtual address includes: The physical address corresponding to the target cache virtual address is determined as the target physical address.

3. The method according to claim 1, characterized in that: The matching in the micro-operation cache based on the instruction virtual address in the instruction fetch request includes: Matching the virtual page number in the instruction virtual address with the virtual page number in the cache virtual address; In the case where the first cache virtual address is obtained by matching, determining whether the page offset in the instruction virtual address is the same as the page offset in the first cache virtual address; The first cache virtual address having the same in-page offset as the instruction virtual address is determined as the target cache address, otherwise the match is unsuccessful.

4. The method according to claim 1, characterized in that: After matching the instruction virtual address in the instruction fetch request in the micro-operation cache, the method further comprises: In case of no successful match from the micro-operation cache, converting the instruction virtual address to a corresponding target physical address; performing a match in an instruction cache based on the target physical address; If the match is successful, obtaining an instruction operation code based on the target physical address; A corresponding micro-operation and information about the micro-operation are acquired based on the instruction opcode.

5. The method according to claim 4, characterized in that: After acquiring the corresponding micro-operation and the information of the micro-operation based on the instruction operation code, the method further includes: The information of the micro-operation, the instruction virtual address corresponding to the micro-operation and the target physical address corresponding to the micro-operation are stored in the micro-operation cache.

6. The method according to claim 4, characterized in that: The matching in the instruction cache based on the target physical address comprises: Checking access rights to the target physical address; In the case of checking legality, a match is performed in the instruction cache based on the target physical address.

7. A micro-operation extraction device based on physical memory protection, characterized in that: include: A first matching module, configured to match in a micro-operation cache based on an instruction virtual address in an instruction fetch request, wherein the micro-operation cache includes a plurality of groups of cache data, each group of cache data includes a cache virtual address, a cache physical address and cache micro-operation information; A first acquisition module, configured to acquire a corresponding target physical address based on the target cache virtual address when a target cache virtual address is matched from the micro-operation cache; A checking module, used for checking the access rights of the target physical address; The extraction module is used to extract the target micro-operation from the micro-operation cache based on the target physical address or the target cache virtual address when checking for legality.

8. A device for implementing physical memory protection in a micro-operation cache, characterized in that: include: A micro-operation cache, wherein the micro-operation cache is used to store multiple groups of cache data, each group of cache data includes a cache virtual address, a cache physical address and cache micro-operation information; A processor instruction fetch queue, the processor instruction fetch queue is used to match the instruction virtual address in the micro-operation cache based on the instruction fetch request; An MMU unit, wherein the MMU unit is used to obtain a corresponding target physical address based on the target cache virtual address when the target cache virtual address is matched from the micro-operation cache; A PMP unit, wherein the PMP unit is used to check access rights of the target physical address.

9. An electronic device, comprising: A memory, a processor, and a program stored in the memory and executable on the processor; wherein the processor is used to read the program in the memory to implement the steps in the micro-operation extraction method based on physical memory protection as described in any one of claims 1 to 6.

10. A readable storage medium for storing a program, characterized in that: When the program is executed by a processor, the steps in the micro-operation extraction method based on physical memory protection as claimed in any one of claims 1 to 6 are implemented.

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