Host instruction processing system, method, memory chip and storage medium

Abstract

This application relates to the field of data processing technology and discloses a host instruction processing system, method, memory chip, and storage medium. The system involves a microcontroller sending instruction string indexes and data indexes to a hardware module, enabling the hardware module to receive these indices. Based on the instruction string indexes and data indexes, a flash memory interface signal corresponding to the instruction string is generated and sent to the flash memory device, causing the flash memory device to execute the operation corresponding to the flash memory interface signal. This application enables the hardware module to offload some of the work previously handled by the microcontroller, reducing the number of instructions sent by the microcontroller, freeing up microcontroller resources, improving microcontroller processing efficiency, and ultimately improving the overall system performance.

Description

Technical Field

[0001] This application relates to the field of data processing technology, and in particular to a host instruction processing system, method, memory chip, and storage medium. Background Technology

[0002] MCU (Micro Control Unit) is a microcontroller unit, also known as a single-chip microcomputer or microcontroller. It emerged with the advent and development of large-scale integrated circuits, integrating a computer's CPU, RAM, ROM, timer / counter, and various I / O interfaces onto a single chip, forming a chip-level computer that can perform different combinations of control for different applications.

[0003] In embedded systems, the MCU plays a central role, controlling various hardware components, including Flash memory chips. When manipulating Flash memory chips, the MCU issues commands to instruct the hardware to generate corresponding interface signals. To support flexible control of Flash memory chips, a microcontroller (MCU) is needed to manage the relevant hardware. The MCU instructs the hardware to generate Flash memory interface signals by issuing commands.

[0004] Currently, the existing technical solution is for the MCU to issue one instruction at a time, sending all instruction strings one by one. However, when the instruction string is too long, the task of sending the instruction string will continuously occupy the MCU resources, and the speed at which the MCU sends the instruction string is relatively slow, which does not match the execution speed of the hardware and can easily become a performance bottleneck. In addition, when the control scenario becomes more complex, the number of instructions that the MCU needs to send will increase significantly, and the MCU will not be able to process the instructions that need to be sent in time, resulting in a decrease in the overall performance of the system. Summary of the Invention

[0005] This application provides a host instruction processing system, method, memory chip, and memory medium. A microcontroller sends instruction string indexes and data indexes to a hardware module, enabling the hardware module to receive these indices. Based on the instruction string indexes and data indexes, a flash memory interface signal corresponding to the instruction string is generated and sent to the flash memory device, causing the flash memory device to execute the operation corresponding to the flash memory interface signal. This application can offload some of the work previously handled by the microcontroller through the hardware module, reducing the number of instructions issued by the microcontroller, freeing up microcontroller resources, improving microcontroller processing efficiency, and thus improving the overall system performance.

[0006] The embodiments of this application provide the following technical solutions:

[0007] In a first aspect, embodiments of this application provide a host instruction processing system, the system comprising:

[0008] The microcontroller, which communicates with the hardware module, is used to acquire commands from the preceding level; generate instruction string indexes based on the operation type of the preceding level commands, where one instruction string index corresponds to one operation type; generate data indexes based on the preceding level commands; and send the instruction string indexes and data indexes to the hardware module.

[0009] The hardware module is connected to the microcontroller. It receives instruction string indices and data indices from the microcontroller, generates flash interface signals corresponding to the instruction strings based on the instruction string indices and sends the flash interface signals to the flash memory device so that the flash memory device can execute the operation corresponding to the flash interface signals.

[0010] In some embodiments, the system further includes a first cache space;

[0011] When the microcontroller receives a command from a previous stage for the first time, it parses the command to obtain the instruction string corresponding to the previous stage command; writes the instruction string into the first cache space and generates an instruction string index corresponding to the instruction string; and sends the instruction string index to the hardware module. When the microcontroller receives a command from a previous stage for the next time, it directly sends the instruction string index to the hardware module so that the hardware module can retrieve the instruction string from the first cache space according to the instruction string index.

[0012] In some embodiments, the microcontroller is further configured to store instruction strings into a first cache space; divide the first cache space into multiple index spaces according to the operation type of the instruction strings, wherein each index space corresponds to an operation type; and store instruction strings with the same operation type into the same index space;

[0013] The hardware module is used to, after receiving the instruction string index, determine the index space corresponding to the instruction string index, and obtain the instruction string from the index space; parse the instruction string to obtain the instruction type of each instruction in the instruction string; obtain the instruction data of the instruction according to the instruction type; and generate the flash interface signal corresponding to the instruction string according to the operation type and instruction data of the instruction string.

[0014] In some embodiments, the system includes a template cache space for storing a template set of multiple templates; the instruction type includes a first instruction type; the instruction data corresponding to the first instruction type is divided into multiple sub-data, wherein one sub-data corresponds to one field unit, and each field unit corresponds to one template, the template including an end identifier, a data source identifier, a data source index, and a data destination index;

[0015] The microcontroller is also used to obtain sub-data corresponding to the first identifier and sub-data corresponding to the second identifier according to the previous-level command, and store the sub-data corresponding to the first identifier in the variable cache space and store the sub-data corresponding to the second identifier in the internal storage module. The sub-data corresponding to the first identifier is the instruction data obtained by the microcontroller through calculation of the previous-level command, and the sub-data corresponding to the second identifier is the instruction data obtained by the microcontroller by copying the data in the previous-level command.

[0016] In some embodiments, the system includes a variable cache space; the instruction type includes a second instruction type;

[0017] The microcontroller is also used to store instruction data corresponding to the second instruction type into a variable cache space and to obtain the storage address of the instruction data in the variable cache space.

[0018] In some embodiments, the data index includes a variable cache space storage address;

[0019] The hardware module is also used to obtain the instruction type of the instruction in the instruction string and determine whether the instruction type is the first instruction type; if the instruction type is the first instruction type, the starting address of the template set corresponding to the instruction is obtained; if the instruction is not the first instruction type, the instruction data corresponding to the instruction is obtained according to the variable cache space storage address, wherein the variable cache space storage address is the storage address of the instruction data corresponding to the second instruction type in the variable cache space.

[0020] In some embodiments, the hardware module is further configured to, when the instruction type of the instruction is a first instruction type, sequentially obtain multiple templates in the template set according to the starting address of the template set corresponding to the instruction, until a template with an end identifier is found; and construct instruction data corresponding to the instruction based on the template.

[0021] In some embodiments, the microcontroller includes an internal storage module, and the data source identifier includes a first identifier and a second identifier;

[0022] The hardware module is used to determine the storage location of instruction data based on the data source identifier. The storage location of instruction data includes a variable cache space and an internal storage module. If the data source identifier is a first identifier, the storage location of instruction data is determined to be the variable cache space, and instruction data is retrieved from the variable cache space according to the data source index. If the data source identifier is a second identifier, the storage location of instruction data is determined to be the internal storage module, and instruction data is retrieved from the internal storage module according to the data source index.

[0023] In some embodiments, each field unit corresponds to a unit identifier number, and the data destination index includes the unit identifier number;

[0024] The hardware module is also used to obtain the data destination index in the template corresponding to the sub-data after obtaining the sub-data; and to write the sub-data into the field cell corresponding to the cell identifier in the data destination index to construct instruction data.

[0025] In some embodiments, the hardware module includes:

[0026] The instruction string acquisition unit is communicatively connected to the microcontroller and the instruction data acquisition unit. The instruction string acquisition unit is used to receive the instruction string index issued by the microcontroller; to acquire the instruction string from the first cache space according to the instruction string index; and to obtain the instruction type of each instruction in the instruction string by parsing the instruction string.

[0027] The instruction data acquisition unit is communicatively connected to the microcontroller and the instruction execution unit, respectively. It is used to acquire instruction data according to the instruction type of the instruction. If the instruction type of the instruction is a first instruction type, it acquires the sub-data corresponding to the first identifier from the variable cache space and the sub-data corresponding to the second identifier from the internal storage module. If the instruction type of the instruction is a second instruction type, it acquires the instruction data from the internal storage module.

[0028] The instruction execution unit is communicatively connected to the instruction string acquisition unit and the instruction data acquisition unit. The instruction execution unit generates a flash interface signal corresponding to the instruction string based on the operation type and instruction data of the instruction string, and sends the flash interface signal to the flash device so that the flash device can execute the operation corresponding to the flash interface signal.

[0029] Secondly, embodiments of this application provide a host instruction processing method applied to a memory chip, the memory chip including a microcontroller and a hardware module, the method including:

[0030] The microcontroller obtains commands from the preceding stage; based on the operation type of the preceding stage command, it generates an instruction string index, where one operation type corresponds to one instruction string index; based on the preceding stage command, it generates a data index; and it sends the instruction string index and data index to the hardware module.

[0031] The hardware module receives the instruction string index and data index from the microcontroller; based on the instruction string index and data index, it generates the flash interface signal corresponding to the instruction string and sends the flash interface signal to the flash device so that the flash device can execute the operation corresponding to the flash interface signal.

[0032] Thirdly, embodiments of this application provide a memory chip, comprising:

[0033] The processor and memory; the processor is used to execute executable program code in memory; when the executable program code is executed, the processor executes instructions such as the host instruction processing method of the second aspect.

[0034] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed, implements the host instruction processing method as described in any of the second aspects.

[0035] The beneficial effects of the embodiments of this application are as follows: Unlike the prior art, the embodiments of this application provide a host instruction processing system, comprising: a microcontroller and a communication connection hardware module. The microcontroller is used to acquire preceding commands; generate an instruction string index according to the operation type of the preceding commands, wherein one operation type corresponds to one instruction string index; generate a data index according to the preceding commands; and send the instruction string index and data index to the hardware module. The hardware module is used to receive the instruction string index and data index sent by the microcontroller; generate a flash memory interface signal corresponding to the instruction string according to the instruction string index and data index, and send the flash memory interface signal to the flash memory device so that the flash memory device executes the operation corresponding to the flash memory interface signal.

[0036] The microcontroller sends instruction string indexes and data indexes to the hardware module, enabling the hardware module to receive these indices. Based on the instruction string indexes and data indexes, the microcontroller generates flash interface signals corresponding to the instruction string and sends these signals to the flash memory device, allowing the flash memory device to execute the corresponding operations. This application enables the hardware module to offload some of the work previously handled by the microcontroller, reducing the number of instructions issued by the microcontroller, freeing up microcontroller resources, improving microcontroller processing efficiency, and ultimately enhancing the overall system performance. Attached Figure Description

[0037] One or more embodiments are illustrated by way of example with reference to the accompanying drawings. These illustrations do not constitute a limitation on the embodiments. Elements having the same reference numerals in the drawings are denoted as similar elements. Unless otherwise stated, the figures in the drawings are not to be limited by scale.

[0038] Figure 1 This is a schematic diagram of a host issuing instructions according to an embodiment of this application;

[0039] Figure 2 This is a schematic diagram of the structure of a host instruction processing system provided in an embodiment of this application;

[0040] Figure 3 This is a schematic diagram illustrating the connection relationship between a front-end module, a microcontroller, and a hardware module, provided in an embodiment of this application.

[0041] Figure 4 This is a schematic diagram of the internal overall structure of the host instruction processing system provided in the embodiments of this application;

[0042] Figure 5 This is a schematic diagram of an instruction structure provided in an embodiment of this application;

[0043] Figure 6 This is a schematic diagram illustrating the acquisition of sub-data provided in an embodiment of this application;

[0044] Figure 7 This is a schematic diagram of a field unit provided in this application;

[0045] Figure 8 This is a schematic diagram of a template provided in this application;

[0046] Figure 9 This is a schematic diagram of a template set provided in this application;

[0047] Figure 10 This is a schematic diagram of the internal structure of a hardware module provided in this application;

[0048] Figure 11 This is a flowchart illustrating a host instruction processing method provided in an embodiment of this application;

[0049] Figure 12 This is a schematic diagram of the structure of a memory chip provided in an embodiment of this application.

[0050] Explanation of icon numbers:

[0051] label name label name 100 Host instruction processing system 10 microcontroller 20 hardware module 120 memory chip 121 processor 122 memory Detailed Implementation

[0052] To facilitate understanding of this application, a more detailed description is provided below with reference to the accompanying drawings and specific embodiments. It should be noted that when an element is described as "fixed to" another element, it can be directly on the other element, or one or more intermediate elements may exist between them. When an element is described as "connected to" another element, it can be directly connected to the other element, or one or more intermediate elements may exist between them. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this specification are for illustrative purposes only.

[0053] Unless otherwise defined, all technical and scientific terms used in this specification have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this specification includes any and all combinations of one or more of the associated listed items.

[0054] The technical solution of this application is described in detail below with reference to the accompanying drawings:

[0055] Please see Figure 1 , Figure 1 This is a schematic diagram of a host issuing instructions according to an embodiment of this application;

[0056] like Figure 1 As shown, MCU (Micro Control Unit) is a microcontroller unit, also known as a single-chip microcomputer or microcontroller. With the advent and development of large-scale integrated circuits, it integrates a computer's CPU, RAM, ROM, timer / counter, and various I / O interfaces onto a single chip, forming a chip-level computer that can perform different combinations of control for different applications. The MCU plays a core role in embedded systems, responsible for controlling various hardware components, including Flash memory chips. When manipulating Flash memory chips, the MCU issues instructions to guide the hardware to generate corresponding interface signals. To support flexibility in controlling Flash memory chips, a microcontroller (MCU) is needed to control the relevant hardware. The MCU instructs the relevant hardware to generate Flash memory interface signals by issuing instructions.

[0057] Specifically, when operating the Flash memory chip, the front-end module sends commands to the MCU. The MCU temporarily stores these commands in its internal Data Core Coupled Memory (DCCM), reads these commands from the DCCM, processes them through the core, and converts them into hardware-executable instruction strings, which consist of multiple instructions.

[0058] DCCM is a tightly coupled memory within the MCU, offering fast access speeds and ensuring the MCU's speed in accessing temporarily stored commands. Core processing is software-controlled, guaranteeing flexibility in command parsing and instruction string generation.

[0059] Each time the MCU generates an instruction, it sends it to the relevant hardware through a specific transmission channel. Upon receiving the instruction, the relevant hardware parses it and generates the corresponding Flash interface signal.

[0060] Instructions in an instruction string can be of various types, including Start, End, and others. The Start-End instruction represents the beginning and end of an instruction string.

[0061] In this embodiment, the MCU issues one instruction at a time, sending the entire instruction string one by one. However, when the instruction string is too long, the task of sending the instruction string will continuously occupy MCU resources, and the speed at which the MCU sends the instruction string is slow, which is mismatched with the hardware execution speed and can easily become a performance bottleneck. In addition, when the control scenario becomes more complex, the number of instructions that the MCU needs to send will increase significantly, and the MCU will not be able to process the instructions that need to be sent in time, resulting in a decrease in the overall performance of the system. Therefore, this method has the drawbacks of sending a large number of instruction strings, consuming MCU resources, and resulting in low overall system performance.

[0062] To address the aforementioned shortcomings, this application provides a host instruction processing system. The microcontroller sends instruction string indices and data indices to a hardware module, enabling the hardware module to receive these indices. Based on the instruction string indices and data indices, the system generates flash interface signals corresponding to the instruction strings and sends these signals to the flash memory device, allowing the flash memory device to execute the operations corresponding to the flash interface signals. This application enables the hardware module to offload some of the work previously handled by the microcontroller, reducing the number of instructions issued by the microcontroller, freeing up microcontroller resources, improving microcontroller processing efficiency, and ultimately enhancing the overall system performance.

[0063] Please see Figure 2 , Figure 2 This is a schematic diagram of the structure of a host instruction processing system provided in an embodiment of this application;

[0064] like Figure 2 As shown, the host instruction processing system includes:

[0065] The microcontroller 10 is connected to the hardware module 20. The microcontroller 10 is used to acquire the previous command; parse the previous command to obtain the instruction string of different operation types, and generate the instruction string index corresponding to the instruction string, wherein one operation type corresponds to one instruction string index; generate the data index corresponding to the instruction based on the instruction data of the instruction string; and send the instruction string index and data index to the hardware module.

[0066] Specifically, the microcontroller communication connection front-end module refers to the collective term for multiple modules through which the data flow passes from the host to the Flash chip. When the host operates on the Flash chip, it issues initial operation commands and operation data. These initial operation commands and operation data are processed by multiple front-end modules before finally being sent to the microcontroller for further processing. The microcontroller receives the front-end commands sent by the front-end modules, parses them to obtain instruction strings of different operation types, and generates instruction string indices corresponding to the instruction strings. Each operation type corresponds to one instruction string index. For example, the operation types include, but are not limited to, Start, End, read operation, write operation, address assignment, and info assignment. Based on the operation type of the instruction string, the microcontroller generates the corresponding instruction string index. For example, assuming there is an instruction string of operation type read and an instruction string of operation type write, the instruction string index of the read operation instruction string can be set to 0, and the instruction string index of the write operation instruction string can be set to 1. It can be understood that when the microcontroller issues instruction string indices to the hardware modules, it only needs to issue 0 or 1, which effectively reduces the length of the instruction strings.

[0067] In addition to the operation type, each instruction string also includes a data portion, namely instruction data. The microcontroller uses the instruction data in the instruction string to generate the data index corresponding to the instruction. The data portion of the instruction string has two sources: the first is that the MCU generates instruction data through complex calculations based on the preceding command; the second is that the MCU directly copies specific fields from the preceding command to the instruction data portion, or generates instruction data through simple calculations. Each instruction includes a first instruction type and a second instruction type. The first instruction type includes Info instructions, and the second instruction type refers to other instructions that are not Info instructions. This application sets up two different storage methods for the instruction data corresponding to the instructions of the first and second instruction types.

[0068] For instructions corresponding to the first instruction type, the instruction data length of the Info instruction is relatively long, requiring the microcontroller to issue multiple times. Therefore, for instructions corresponding to the first instruction type, the microcontroller will pre-set a template, which is used to store instruction information. The template is stored in the template cache space, and the address of the template in the template cache space is sent to the hardware module so that the hardware module can obtain the instruction information stored in the template according to the address and generate instruction data according to the information.

[0069] For instructions corresponding to the second instruction type, the amount of data corresponding to other non-Info instructions is smaller than that of Info instructions. The MCU writes the instruction data corresponding to the second instruction type into the variable buffer space (variable_buffer), and then sends the corresponding address (data_idx) to the hardware module, which is the variable buffer space storage address. This allows the hardware module to retrieve the corresponding instruction data from the variable buffer space storage address when it parses the relevant instruction.

[0070] Hardware module 20 is communicatively connected to microcontroller 10. Hardware module 20 is used to receive instruction string index and data index issued by microcontroller; obtain instruction string according to instruction string index and data index; obtain instruction type of each instruction in instruction string by parsing instruction string; obtain instruction data of instruction according to instruction type; generate flash interface signal corresponding to instruction string according to operation type and instruction data of instruction string, and send flash interface signal to flash device to enable flash device to execute operation corresponding to flash interface signal. The instruction type includes first instruction type and second instruction type, and the operation type of instruction string includes but is not limited to read operation and write operation.

[0071] Please refer to the following: Figure 3 , Figure 3 This is a schematic diagram illustrating the connection relationship between a front-end module, a microcontroller, and a hardware module, provided in an embodiment of this application.

[0072] like Figure 3 As shown, the microcontroller communicates with the front-end modules, which collectively refer to the multiple modules through which the data flow passes from the host to the Flash chip. When the host operates on the Flash chip, it issues initial operation commands and operation data. These initial operation commands and operation data are processed by multiple front-end modules and finally sent to the microcontroller for further processing. The microcontroller obtains the instruction strings sent by the front-end modules and the operation type corresponding to each instruction string. The instruction string includes multiple operation types, such as Start, End, read operation, write operation, address assignment, and info assignment. Based on the operation type of the instruction string, the microcontroller generates an instruction string index corresponding to the instruction string and sends the instruction string index to the hardware module. The hardware module generates the flash interface signal corresponding to the instruction string based on the instruction string index and sends the flash interface signal to the flash device so that the flash device executes the operation corresponding to the flash interface signal.

[0073] Please refer to the following: Figure 4 , Figure 4 This is a schematic diagram of the internal overall structure of the host instruction processing system provided in the embodiments of this application;

[0074] like Figure 4 As shown, the host instruction processing system also includes a first cache space (Code_buffer), a variable cache space (variable_buffer), and a template cache space (template_buffer);

[0075] When the microcontroller receives a command from a previous stage for the first time, it parses the command to obtain the instruction string corresponding to the previous stage command; writes the instruction string into the first cache space and generates an instruction string index corresponding to the instruction string; and sends the instruction string index to the hardware module. When the microcontroller receives a command from a previous stage for the next time, it directly sends the instruction string index to the hardware module so that the hardware module can retrieve the instruction string from the first cache space according to the instruction string index.

[0076] The microcontroller is also used to divide the first cache space into multiple index spaces according to the operation type of the instruction string, where each index space corresponds to an operation type; and to store instruction strings with the same operation type into the same index space. Specifically, the microcontroller divides the first cache space into multiple index spaces according to the operation type of the instruction string, where each index space corresponds to an operation type. For example, assuming there are currently read operation instruction strings and write operation instruction strings, the first cache space is divided into two index spaces: a first index space and a second index space. The instruction string corresponding to the read operation is stored in the first index space, and the instruction string corresponding to the write operation is stored in the second index space.

[0077] Please refer to the following: Figure 4 and Figure 5 , Figure 5 This is a schematic diagram of an instruction structure provided in an embodiment of this application;

[0078] like Figure 5 As shown, each instruction consists of two parts: operation type (Type) and instruction data (Data). The operation type of the instruction includes, but is not limited to, write and read operations. The instruction data refers to the content information of the instruction. The hardware module generates different signals to interact with the Flash chip based on the instruction data. Even with the same Type, the Data will differ depending on the command.

[0079] In this embodiment, the hardware module, upon receiving an instruction string index, determines the index space corresponding to the instruction string index and retrieves the instruction string from the index space. For example, assuming the instruction string corresponding to a read operation is stored in the first index space, the instruction string corresponding to a write operation is stored in the second index space, the instruction string index corresponding to a read operation is 0, and the instruction string index corresponding to a write operation is 1, then when the instruction string index issued by the microcontroller is 0, the hardware module determines the index space corresponding to the instruction string as the first index space based on the instruction string index, and then retrieves the instruction string from the first index space; when the instruction string index issued by the microcontroller is 1, the hardware module determines the index space corresponding to the instruction string as the second index space based on the instruction string index, and then retrieves the instruction string from the second index space.

[0080] In this embodiment of the application, the system includes a template cache space for storing multiple template sets, wherein each template set includes multiple templates; the instruction type includes a first instruction type; the instruction data corresponding to the first instruction type is divided into multiple sub-data, wherein one sub-data corresponds to one field unit, wherein each field unit corresponds to one template, and each template includes an end identifier, a data source identifier, a data source index, and a data destination index.

[0081] Please refer to the following: Figure 4 In this embodiment, MCU is a microcontroller, code_buffer is a first cache space, template_buffer is a template cache space, variable_buffer is a variable cache space, DCCM is an internal storage module, DCCM_idx is the address of instruction data in the internal storage module, and the value of DCCM_idx comes from the data source index when the data source identifier in the template is the second identifier.

[0082] like Figure 4As shown in ① and ②, a first buffer space (code_buffer) and a template buffer space (template_buffer) are pre-configured via the bus. These two buffers store instruction strings and templates, respectively. Both the first buffer space (code_buffer) and the template buffer space (template_buffer) are SRAM-implemented cache structures. The bus can fill data into the space corresponding to a specific address in this buffer by configuring read / write signals / addresses / data. For example, in the template_buffer, the bus can, according to the SRAM usage specifications, write the first template info_code0 to the initial address of a template set, the second template info_code1 to the address of the initial address + 1, and the third template info_code2 to the address of the initial address + 2. Therefore, it can be understood that during the template acquisition process, once the hardware obtains the initial address (index) of the template set, it can read all the corresponding template info_codes based on the initial address.

[0083] like Figure 4 As shown in ③, when the MCU receives the command from the previous stage, it first calculates the data generated by the MCU and writes this data into the variable buffer space variable_buffer. It then obtains the storage address of the variable buffer space corresponding to the data to generate a data index, where the data index includes the storage address of the variable buffer space.

[0084] In this embodiment, the reason for requiring the MCU to generate data is that this instruction data cannot be directly obtained from the preceding commands; this data possesses flexibility. For example, if complex logical operations need to be performed on certain data in the preceding commands, and the operation process is flexible and variable, then the MCU needs to participate. Software code can guide the MCU to generate relevant data; this code is modifiable and relatively flexible. If implemented in hardware, it cannot be modified after being fabricated into a chip.

[0085] like Figure 4 As shown in ④, for the currently received command, the MCU sends the instruction string index and the data index of each instruction to the hardware.

[0086] like Figure 4As shown in ⑤, after receiving the instruction string index, the hardware performs the following operations: (1) According to the instruction string index, the instruction string is obtained from the first cache space code_buf; (2) The instructions in the instruction string are parsed one by one, and different operations are performed on different instructions; (3) For instructions other than info, the corresponding data is obtained from the variable cache space variable_buffer according to the data index (variable cache space storage address, data_idx) of the instruction; (4) For the info instruction, the instruction string includes the starting address of the template set corresponding to each instruction. The hardware first obtains the template from the template cache space template_buffer through channel 4 according to the starting address of the template set in the instruction string, starting from the template info_code corresponding to the starting address, and ending with the info_code with the end identifier (is_end=1). The hardware assembles Data according to the instructions of info_code in sequence: if the data is copied from the previous level command, the hardware accesses the instruction data in the internal storage module DCCM in the microcontroller through channel 3 according to DCCM_idx; if the data is obtained from the value generated by the MCU, the hardware obtains the instruction data from the variable cache space variable_buffer through channel 5.

[0087] Please refer to the following: Figure 6 , Figure 6 This is a schematic diagram illustrating the acquisition of sub-data provided in an embodiment of this application;

[0088] like Figure 6 As shown, the instruction data (i.e., the Data part) in the instruction includes several sub-data. The sub-data comes from two sources: one is that the MCU generates the sub-data corresponding to the first identifier through a relatively complex calculation based on the previous command; the other is that the MCU directly copies a specific field from the previous command to the field unit, or generates the sub-data corresponding to the second identifier through a simple calculation. In each instruction, the Data corresponding to the Info instruction (i.e., the Type field in the instruction is info) mostly has the above characteristics, and the instruction data corresponding to the info instruction is relatively long, requiring the MCU to issue it multiple times.

[0089] Please refer to the following: Figure 7 and Figure 8 , Figure 7 This is a schematic diagram of a field unit provided in this application; Figure 8 This is a schematic diagram of a template provided in this application;

[0090] like Figure 7As shown, based on the characteristics of the Info instruction, the microcontroller divides the instruction data (Data) corresponding to the first instruction type into multiple sub-data, where each sub-data corresponds to a field unit; for example... Figure 8 As shown, a template is set for each field unit. Each field unit corresponds to one template. The template includes an end identifier, a data source identifier, a data source index, and a data destination index. The data source identifier includes a first identifier and a second identifier. The first identifier indicates that the sub-data corresponding to the field unit comes from the value generated by the MCU, and the second identifier indicates that the sub-data corresponding to the field unit comes from the previous command. The data source index refers to the storage address of the sub-data, and the data destination index refers to the field unit corresponding to the template.

[0091] In this embodiment of the application, a template set is generated based on multiple templates. The template set includes multiple templates corresponding to the instruction data. Since each field unit corresponds to one template, the number of templates in each template set is equal to the number of field units in the instruction data.

[0092] In this embodiment, the instruction type includes a second instruction type. The microcontroller is further configured to store the instruction data corresponding to the second instruction type in a variable buffer space and obtain the storage address of the instruction data in the variable buffer space. Specifically, for the Data portion of other non-Info instructions, since the Data amount is small, the MCU writes the corresponding Data into the variable buffer space variable_buffer, and then sends the storage address (data_idx) of the instruction data in the variable buffer space to the hardware module. When the hardware parses the relevant instruction, it obtains the instruction data corresponding to the second instruction type from the variable_buffer based on the storage address.

[0093] In this embodiment of the application, the system includes a variable cache space; the instruction type includes a second instruction type; the microcontroller is further configured to store the instruction data corresponding to the second instruction type into the variable cache space, and obtain the storage address of the instruction data in the variable cache space.

[0094] The data index includes the variable cache space storage address; the hardware module is also used to obtain the instruction type of the instruction in the instruction string and determine whether the instruction type is the first instruction type; if the instruction type is the first instruction type, the starting address of the template set corresponding to the instruction is obtained; if the instruction is not the first instruction type, the variable cache space storage address corresponding to the instruction data of the instruction is obtained, wherein the variable cache space storage address is the storage address of the instruction data corresponding to the second instruction type in the variable cache space.

[0095] The hardware module is also used to, when the instruction type is the first instruction type, sequentially obtain multiple templates in the template set according to the starting address of the template set corresponding to the instruction, until a template with an end identifier is found; and construct the instruction data corresponding to the instruction based on the template. Specifically, for instructions corresponding to the first instruction type, the instruction data corresponding to the Info instruction is relatively long and needs to be sent multiple times by the microcontroller. Therefore, for instructions corresponding to the first instruction type, the microcontroller will pre-set the template set corresponding to each Info instruction, store the template set in the template cache space, and send the starting address of the template set in the template cache space to the hardware module. The hardware module will then sequentially obtain multiple templates in the template set according to the starting address, until a template with an end identifier is found. It can be understood that when a template with an end identifier is found, it means that all templates in the template set have been traversed. Finally, the instruction data corresponding to the instruction is constructed based on the data source identifier, data source index, and data destination index in the template.

[0096] In this embodiment, the microcontroller includes an internal storage module, and the data source identifier includes a first identifier and a second identifier. The hardware module is used to determine the storage location of instruction data based on the data source identifier, wherein the storage location of the instruction data includes a variable cache space and the internal storage module. If the data source identifier is the first identifier, the storage location of the instruction data is determined to be the variable cache space, and the instruction data is retrieved from the variable cache space according to the data source index. If the data source identifier is the second identifier, the storage location of the instruction data is determined to be the internal storage module, and the instruction data is retrieved from the internal storage module according to the data source index, wherein the data source index includes the storage address of the instruction data in the variable cache space or the internal storage module. It is understood that the storage location of the instruction data can be determined based on the data source identifier and the data source index, so that the hardware module can retrieve the instruction data from the corresponding storage location.

[0097] In this embodiment, each field unit corresponds to a unit identifier, and the data destination index includes the unit identifier. The hardware module is further configured to obtain the data destination index in the template corresponding to the sub-data after obtaining the sub-data; and to write the sub-data into the field unit corresponding to the unit identifier according to the unit identifier in the data destination index to construct instruction data. Specifically, assuming there is an instruction data that includes 4 field units: Unit0, Unit1, Unit2, and Unit3, then the unit identifier corresponding to Unit0 is 0, the unit identifier corresponding to Unit1 is 1, the unit identifier corresponding to Unit2 is 2, and the unit identifier corresponding to Unit3 is 0. The unit identifier is 3. When the hardware module detects that the data destination index of a certain sub-data is 0, the sub-data is filled into field unit Unit0. When the hardware module detects that the data destination index of a certain sub-data is 1, the sub-data is filled into field unit Unit1. When the hardware module detects that the data destination index of a certain sub-data is 2, the sub-data is filled into field unit Unit2. When the hardware module detects that the data destination index of a certain sub-data is 3, the sub-data is filled into field unit Unit3. Then, all the sub-data corresponding to the instruction data are written into the corresponding field units to construct the instruction data.

[0098] Please refer to the following: Figure 9 , Figure 9 This is a schematic diagram of a template set provided in this application;

[0099] like Figure 9 As shown, assuming the data corresponding to a certain info instruction is divided into 4 unit fields, and these 4 units are known to store values ​​generated by the MCU and values ​​from the preceding command, then the process of setting the template set for this info instruction is as follows:

[0100] Step (1): Formulate a template. Since the info instruction is divided into 4 field units, which are used to store sub-data of the instruction data, it can be determined that the template set corresponding to the command consists of 4 templates info_code, corresponding to 4 field units. The value in info_code can be predicted in advance according to the application scenario.

[0101] Step (2): Fill the template with the end identifier, data source identifier, data source index, and data destination index respectively. The end identifier is used to determine whether the template is at the end of the template set. For example, when the end identifier is 1, it means that the template is the last template in the template set. When the end identifier is 0, it means that the template is not the last template in the template set. The data source identifier indicates that the data comes from the previous command / MCU generated value. For example, when type = 0, the data source identifier is determined to be the first identifier, that is, the value generated by the MCU. When type = 1, the data source identifier is determined to be the second identifier, that is, the value generated by the previous command. The data source index refers to the storage address of the sub-data, and the data destination index refers to the field unit corresponding to the template.

[0102] Step (3): Generate multiple templates to determine the template set. It can be understood that the template set is a set of operation guidelines. The hardware completes the assignment of unit0-unit3 according to the template set and generates complete instruction data.

[0103] In this embodiment of the application, the template info_code can be understood as an operation guide, for example, Figure 9 The first line of the template, info_code, means that the data at position src_idx in the value generated by the MCU is copied to unit0 in the instruction data. The hardware module will perform the corresponding operation according to the guidance of this info_code.

[0104] It is understandable that the info type includes both read and write types. Different info types have different data lengths, different numbers of units, and different numbers of info_codes in the template. For the same info type, the content of its info_code will also be different in different application scenarios.

[0105] Please refer to the following: Figure 10 , Figure 10 This is a schematic diagram of the internal structure of a hardware module provided in this application;

[0106] like Figure 10 As shown, hardware module 20 includes: an instruction acquisition unit, an instruction data acquisition unit, and an instruction execution unit;

[0107] The instruction string fetch unit (code_fetch) is a communication connection between the microcontroller and the instruction data fetch unit. The instruction string fetch unit is used to receive the instruction string index issued by the microcontroller; retrieve the instruction string from the first cache space according to the instruction string index; and obtain the instruction type of each instruction in the instruction string by parsing the instruction string.

[0108] The instruction data acquisition unit (get_data) is communicatively connected to the microcontroller and the instruction execution unit, respectively. It is used to acquire instruction data according to the instruction type of the instruction. If the instruction type of the instruction is a first instruction type, it acquires the sub-data corresponding to the first identifier from the variable cache space and the sub-data corresponding to the second identifier from the internal storage module. If the instruction type of the instruction is a second instruction type, it acquires the instruction data from the internal storage module.

[0109] The instruction execution unit (code_exec) is communicatively connected to the instruction string acquisition unit and the instruction data acquisition unit. The instruction execution unit is used to generate flash interface signals corresponding to the instruction string according to the operation type and instruction data of the instruction string, and send the flash interface signals to the flash device so that the flash device can execute the operation corresponding to the flash interface signals.

[0110] Specifically, the hardware modules also include, Figure 10 Each module shown is a hardware structure. The instruction string acquisition unit (code_fetch) is used to retrieve the instruction string corresponding to the instruction string index from the code_buffer according to the instruction string index; info_code_fetch is responsible for retrieving template info_codes one by one from the template_buffer according to the template index; the instruction execution unit (code_exec) is used to parse and execute each instruction in the instruction string; info_code_exec is responsible for parsing and executing each info_code.

[0111] Upon receiving the index from the MCU, the code_fetch module performs initial processing. This module retrieves instructions sequentially from the code_buffer based on the instruction string index and sends the instructions to the code_exec module for execution.

[0112] The get_data module is responsible for retrieving the preceding command based on DCCM_idx (the preceding command is stored in DCCM, which is a data storage module that can read the data in the corresponding space through the index), and retrieving the data in variable_buffer based on data_idx.

[0113] After the `code_fetch` and `get_data` modules retrieve the relevant data, `code_exec` begins execution. For instructions other than `info` instructions, i.e., instructions corresponding to the second instruction type, this module will generate `data` from the data retrieved from `variable_buffer` according to the instruction type. For `info` type instructions, i.e., instructions corresponding to the first instruction type, this module will generate `data` through `info_code_fetch` and `info_code_exec`.

[0114] Based on different instruction types and corresponding data, code_exec operates other hardware logic to control the Flash chip. The other hardware is used to convert the signals generated by code_exec into complex signals that conform to the characteristics of the Flash chip interface.

[0115] The Info_code_fetch module retrieves the info_code from the template_buffer and then sends it to info_code_exec for execution. Info_code_exec then uses the info_code to retrieve data from the preceding command or variable_buffer to generate the corresponding data.

[0116] Among them, code_exec / info_code_exec / code_fetch / info_code_fetch are all hardware modules, internally controlled by a state machine (FSM) logic. When different instructions are received, they will jump to different states and execute different operations.

[0117] In this embodiment, a host instruction processing system is provided, comprising: a microcontroller and a hardware module for communication connection. The microcontroller is used to acquire preceding commands; generate an instruction string index based on the operation type of the preceding commands, wherein one instruction string index corresponds to one operation type; generate a data index based on the preceding commands; and send the instruction string index and data index to the hardware module. The hardware module is also connected to the microcontroller and is used to receive the instruction string index and data index sent by the microcontroller; generate a flash memory interface signal corresponding to the instruction string based on the instruction string index and data index, and send the flash memory interface signal to the flash memory device so that the flash memory device executes the operation corresponding to the flash memory interface signal.

[0118] The microcontroller sends instruction string indexes and data indexes to the hardware module, enabling the hardware module to receive these indices. Based on the instruction string indexes and data indexes, the microcontroller generates flash interface signals corresponding to the instruction string and sends these signals to the flash memory device, allowing the flash memory device to execute the corresponding operations. This application enables the hardware module to offload some of the work previously handled by the microcontroller, reducing the number of instructions issued by the microcontroller, freeing up microcontroller resources, improving microcontroller processing efficiency, and ultimately enhancing the overall system performance.

[0119] Please see Figure 11 , Figure 11 This is a flowchart illustrating a host instruction processing method provided in an embodiment of this application;

[0120] This host instruction processing method is applied to a memory chip; specifically, the execution subject of this method is one or more processors of the memory chip.

[0121] like Figure 11 As shown, the flow of the host instruction processing method includes:

[0122] Step S1101: Obtain the preceding command through the microcontroller; generate an instruction string index according to the operation type of the preceding command, wherein one operation type corresponds to one instruction string index; generate a data index according to the preceding command; and send the instruction string index and data index to the hardware module.

[0123] Specifically, the microcontroller communication connection front-end module refers to the collective term for multiple modules through which the data flow passes from the host to the Flash chip. When the host operates on the Flash chip, it issues initial operation commands and operation data. These initial operation commands and operation data are processed by multiple front-end modules before finally being sent to the microcontroller for further processing. The microcontroller receives the front-end commands sent by the front-end modules, parses them to obtain instruction strings of different operation types, generates instruction string indices corresponding to the instruction strings, and obtains the operation type corresponding to each instruction string. For example, the operation type includes, but is not limited to, Start, End, read operation, write operation, address assignment, and info assignment. Based on the operation type of the instruction string, the microcontroller generates the instruction string index corresponding to the instruction string. One operation type corresponds to one instruction string index. For example, assuming there is an instruction string of operation type read and an instruction string of operation type write, the instruction string index of the read operation instruction string can be set to 0, and the instruction string index of the write operation instruction string can be set to 1. It can be understood that when the microcontroller issues instruction string indices to the hardware modules, it only needs to issue 0 or 1, which effectively reduces the length of the instruction strings.

[0124] In addition to the operation type, each instruction string also includes a data portion, namely instruction data. The microcontroller uses the instruction data in the instruction string to generate the data index corresponding to the instruction. The data portion of the instruction string has two sources: the first is that the MCU generates instruction data through complex calculations based on the preceding command; the second is that the MCU directly copies specific fields from the preceding command to the instruction data portion, or generates instruction data through simple calculations. Each instruction includes a first instruction type and a second instruction type. The first instruction type includes Info instructions, and the second instruction type refers to other instructions that are not Info instructions. This application sets up two different storage methods for the instruction data corresponding to the instructions of the first and second instruction types.

[0125] For instructions corresponding to the first instruction type, the instruction data length of the Info instruction is relatively long, requiring the microcontroller to issue multiple times. Therefore, for instructions corresponding to the first instruction type, the microcontroller will pre-set a template, which is used to store instruction information. The template is stored in the template cache space, and the address of the template in the template cache space is sent to the hardware module so that the hardware module can obtain the instruction information stored in the template according to the address and generate instruction data according to the information.

[0126] For instructions corresponding to the second instruction type, the amount of data corresponding to other non-Info instructions is smaller than that of Info instructions. The MCU writes the instruction data corresponding to the second instruction type into the variable buffer space (variable_buffer), and then sends the corresponding address (data_idx) to the hardware module so that when the hardware module parses the relevant instruction later, it can retrieve the corresponding instruction data from the variable_buffer according to the address.

[0127] Step S1102: Receive the instruction string index and data index issued by the microcontroller through the hardware module; generate the flash interface signal corresponding to the instruction string according to the instruction string index, and send the flash interface signal to the flash device so that the flash device can execute the operation corresponding to the flash interface signal;

[0128] Specifically, after the hardware module receives the instruction string index, it determines the corresponding index space based on the instruction string index and retrieves the instruction string from the index space. For example, assuming the instruction string corresponding to a read operation is stored in the first index space and the instruction string corresponding to a write operation is stored in the second index space, with the index of the instruction string corresponding to the read operation being 0 and the index of the instruction string corresponding to the write operation being 1, then when the microcontroller issues an instruction string with an index of 0, the hardware module will determine the corresponding index space as the first index space based on this index and retrieve the instruction string from the first index space; when the microcontroller issues an instruction string with an index of 1, the hardware module will determine the corresponding index space as the second index space based on this index and retrieve the instruction string from the second index space. The instruction string is parsed to obtain the instruction type of each instruction in the instruction string; based on the instruction type, the instruction data of the instruction is obtained; based on the operation type and instruction data of the instruction string, a flash memory interface signal corresponding to the instruction string is generated and sent to the flash memory device so that the flash memory device executes the operation corresponding to the flash memory interface signal.

[0129] In this embodiment, a host instruction processing method is provided, applied to a memory chip. The method includes: acquiring a preceding command through a microcontroller; generating an instruction string index based on the operation type of the preceding command, wherein one operation type corresponds to one instruction string index; generating a data index based on the preceding command; sending the instruction string index and data index to a hardware module; receiving the instruction string index and data index sent by the microcontroller through the hardware module; generating a flash interface signal corresponding to the instruction string based on the instruction string index and data index, and sending the flash interface signal to the flash memory device to enable the flash memory device to execute the operation corresponding to the flash interface signal. By sending the instruction string index and data index to the hardware module through the microcontroller, enabling the hardware module to receive the instruction string index and data index sent by the microcontroller; and generating a flash interface signal corresponding to the instruction string based on the instruction string index and data index, and sending the flash interface signal to the flash memory device to enable the flash memory device to execute the operation corresponding to the flash interface signal, this application can offload some of the work handled by the microcontroller through the hardware module, reducing the number of instructions sent by the microcontroller, releasing the microcontroller's resources, improving the microcontroller's processing efficiency, and thus improving the overall performance of the system.

[0130] Please refer to the following: Figure 12 , Figure 12 This application provides a schematic diagram of the structure of a memory chip;

[0131] In this embodiment, the memory chip includes a DPU chip. A DPU (Data Processing Unit) is a chip specifically designed to handle network transmission, data security, and infrastructure tasks in data centers. The DPU is designed to reduce the burden on the CPU in tasks such as data transmission, encryption, and storage, allowing it to focus on core computing tasks and thus improve the efficiency of the entire system.

[0132] like Figure 12 As shown, the memory chip 120 includes one or more processors 121 and a memory 122. Wherein, Figure 12 Take a processor 121 as an example.

[0133] Processor 121 and memory 122 can be connected via a bus or other means. Figure 12 Taking the example of a connection between China and Israel via a bus.

[0134] Processor 121 is configured to provide computing and control capabilities to control the transmitting end to perform corresponding tasks, such as controlling the transmitting end to perform the aforementioned tasks. Figure 11The host instruction processing method, applied to a flash memory device, includes: obtaining a preceding command through a microcontroller; generating an instruction string index based on the operation type of the preceding command, wherein one instruction string index corresponds to one operation type; generating a data index based on the preceding command; sending the instruction string index and data index to a hardware module; receiving the instruction string index and data index sent by the microcontroller through the hardware module; generating a flash memory interface signal corresponding to the instruction string based on the instruction string index and data index, and sending the flash memory interface signal to the flash memory device so that the flash memory device executes the operation corresponding to the flash memory interface signal.

[0135] The microcontroller sends instruction string indexes and data indexes to the hardware module, enabling the hardware module to receive these indices. Based on the instruction string indexes and data indexes, the microcontroller generates flash interface signals corresponding to the instruction string and sends these signals to the flash memory device, allowing the flash memory device to execute the corresponding operations. This application enables the hardware module to offload some of the work previously handled by the microcontroller, reducing the number of instructions issued by the microcontroller, freeing up microcontroller resources, improving microcontroller processing efficiency, and ultimately enhancing the overall system performance.

[0136] Processor 121 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), a hardware chip, or any combination thereof; it can also be a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The aforementioned PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof.

[0137] Memory 122, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the host instruction processing method in the embodiments of this application. Processor 121 can implement the host instruction processing method in any of the above method embodiments by running the non-transitory software programs, instructions, and modules stored in memory 122. Specifically, memory 122 may include volatile memory (VM), such as random access memory (RAM); memory 122 may also include non-volatile memory (NVM), such as read-only memory (ROM), flash memory, hard disk drive (HDD), solid-state drive (SSD), or other non-transitory solid-state storage devices; memory 122 may also include combinations of the above types of memory.

[0138] Memory 122 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device, flash memory device, or other non-volatile solid-state storage device. In some embodiments, memory 122 may optionally include memory remotely located relative to processor 121, and such remote memory may be connected to processor 121 via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.

[0139] One or more modules are stored in memory 122. When executed by one or more processors 121, they perform the host instruction processing method in any of the above method embodiments, for example, the method described above. Figure 11 The steps shown.

[0140] In this embodiment, the storage chip 120 may also have wired or wireless network interfaces, a keyboard, and input / output interfaces for input and output. The storage chip 120 may also include other components for implementing device functions, which will not be described in detail here.

[0141] This application also provides a non-volatile computer-readable storage medium, such as a memory including program code, which can be executed by a processor to complete the host instruction processing method in the above embodiments. For example, the non-volatile computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CDROM), magnetic tape, floppy disk, and optical data storage device, etc.

[0142] This application also provides a computer program product comprising one or more lines of program code stored in a non-volatile computer-readable storage medium. A processor of an electronic device reads the program code from the non-volatile computer-readable storage medium and executes the program code to complete the method steps of the host instruction processing method provided in the above embodiments.

[0143] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware, or by a program or program code related to hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0144] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented using software plus a general-purpose hardware platform, or of course, using hardware. Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a non-volatile computer-readable storage medium, and when executed, the program can include the processes of the embodiments of the above methods. The non-volatile computer-readable storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc.

[0145] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and not to limit them; under the concept of this application, the technical features of the above embodiments or different embodiments can also be combined, the steps can be implemented in any order, and there are many other variations as described above in different aspects of this application, which are not provided in detail for the sake of brevity; although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A host instruction processing system, characterized in that, The system, applied to memory chips, includes: A microcontroller, communicating with a hardware module, is used to acquire commands from a preceding stage; generate an instruction string index based on the operation type of the preceding stage command, wherein one operation type corresponds to one instruction string index; generate a data index based on the preceding stage command; and send the instruction string index and the data index to the hardware module. A hardware module is communicatively connected to the microcontroller. The hardware module is used to receive instruction string index and data index issued by the microcontroller; generate flash interface signal corresponding to the instruction string based on the instruction string index and the data index; and send the flash interface signal to the flash device so that the flash device executes the operation corresponding to the flash interface signal. The system also includes a first cache space; The microcontroller is configured to, upon receiving a preceding command for the first time, parse the preceding command to obtain the instruction string corresponding to the preceding command; write the instruction string into a first cache space, generate an instruction string index corresponding to the instruction string, and issue the instruction string index to the hardware module; upon receiving the preceding command again, directly issue the instruction string index to the hardware module so that the hardware module can retrieve the instruction string from the first cache space according to the instruction string index.

2. The system according to claim 1, characterized in that, The microcontroller is further configured to store the instruction string into a first cache space; divide the first cache space into multiple index spaces according to the operation type of the instruction string, wherein each index space corresponds to an operation type; and store instruction strings with the same operation type into the same index space; The hardware module is used to, after receiving the instruction string index, determine the index space corresponding to the instruction string index, and obtain the instruction string from the index space; parse the instruction string to obtain the instruction type of each instruction in the instruction string; obtain the instruction data of the instruction according to the instruction type; and generate the flash interface signal corresponding to the instruction string according to the operation type and instruction data of the instruction string.

3. The system according to claim 2, characterized in that, The system includes a template cache space for storing a template set of multiple templates; the instruction type includes a first instruction type; the instruction data corresponding to the first instruction type is divided into multiple sub-data, wherein each sub-data corresponds to a field unit, and each field unit corresponds to a template, wherein the template includes an end identifier, a data source identifier, a data source index, and a data destination index; The microcontroller is further configured to obtain sub-data corresponding to the first identifier and sub-data corresponding to the second identifier according to the preceding command, and store the sub-data corresponding to the first identifier in a variable cache space and store the sub-data corresponding to the second identifier in an internal storage module, wherein the sub-data corresponding to the first identifier is instruction data obtained by the microcontroller through calculation of the preceding command, and the sub-data corresponding to the second identifier is instruction data obtained by the microcontroller by copying the data in the preceding command.

4. The system according to claim 3, characterized in that, The system includes a variable cache space; the instruction type includes a second instruction type; The microcontroller is also configured to store the instruction data corresponding to the second instruction type into the variable cache space, and obtain the storage address of the instruction data in the variable cache space.

5. The system according to claim 4, characterized in that, The data index includes variable cache space storage addresses; The hardware module is further configured to obtain the instruction type of the instruction in the instruction string and determine whether the instruction type is a first instruction type; if the instruction type is a first instruction type, then obtain the starting address of the template set corresponding to the instruction; if the instruction is not a first instruction type, then obtain the instruction data corresponding to the instruction according to the variable cache space storage address, wherein the variable cache space storage address is the storage address of the instruction data corresponding to the second instruction type in the variable cache space.

6. The system according to claim 5, characterized in that, The hardware module is further configured to, when the instruction type of the instruction is a first instruction type, sequentially obtain multiple templates in the template set according to the starting address of the template set corresponding to the instruction, until a template with an end identifier is found; and construct instruction data corresponding to the instruction based on the template.

7. The system according to claim 6, characterized in that, The microcontroller includes an internal storage module, and the data source identifier includes a first identifier and a second identifier; The hardware module is used to determine the storage location of the instruction data according to the data source identifier, wherein the storage location of the instruction data includes a variable cache space and an internal storage module; if the data source identifier is a first identifier, the storage location of the instruction data is determined to be the variable cache space, and the instruction data is obtained from the variable cache space according to the data source index; if the data source identifier is a second identifier, the storage location of the instruction data is determined to be the internal storage module, and the instruction data is obtained from the internal storage module according to the data source index.

8. The system according to claim 7, characterized in that, Each of the aforementioned field units corresponds to a unit identifier number, and the data destination index includes the unit identifier number; The hardware module is further configured to, after acquiring the sub-data, acquire the data destination index in the template corresponding to the sub-data; and, based on the unit identifier in the data destination index, write the sub-data into the field unit corresponding to the unit identifier to construct the instruction data.

9. The system according to claim 8, characterized in that, The hardware module includes: The instruction string acquisition unit is communicatively connected to the microcontroller and the instruction data acquisition unit, respectively. The instruction string acquisition unit is used to receive the instruction string index issued by the microcontroller; acquire the instruction string from the first cache space according to the instruction string index; and obtain the instruction type of each instruction in the instruction string by parsing the instruction string. The instruction data acquisition unit is communicatively connected to the microcontroller and the instruction execution unit, respectively, and is used to acquire instruction data of the instruction according to the instruction type of the instruction; if the instruction type of the instruction is a first instruction type, then the sub-data corresponding to the first identifier is acquired from the variable cache space, and the sub-data corresponding to the second identifier is acquired from the internal storage module; if the instruction type of the instruction is a second instruction type, then the instruction data in the internal storage module is acquired. The instruction execution unit is communicatively connected to the instruction string acquisition unit and the instruction data acquisition unit. The instruction execution unit generates a flash interface signal corresponding to the instruction string according to the operation type and instruction data of the instruction string, and sends the flash interface signal to the flash device so that the flash device executes the operation corresponding to the flash interface signal.

10. A host instruction processing method, characterized in that, Applied to a memory chip, the memory chip including a microcontroller and hardware modules, and a first cache space, the method includes: The microcontroller obtains the preceding command; based on the operation type of the preceding command, it generates an instruction string index, wherein one operation type corresponds to one instruction string index; based on the preceding command, it generates a data index; and sends the instruction string index and the data index to the hardware module. The hardware module receives the instruction string index and data index issued by the microcontroller; generates the flash interface signal corresponding to the instruction string based on the instruction string index, and sends the flash interface signal to the flash device so that the flash device executes the operation corresponding to the flash interface signal; Upon receiving a preceding command for the first time, the microcontroller parses the preceding command to obtain the instruction string corresponding to the preceding command; writes the instruction string into the first cache space and generates an instruction string index corresponding to the instruction string, and sends the instruction string index to the hardware module; upon receiving the preceding command again, the microcontroller directly sends the instruction string index to the hardware module so that the hardware module can retrieve the instruction string from the first cache space according to the instruction string index.

11. A memory chip, characterized in that, include: A processor and a memory, the processor being configured to execute executable program code in the memory, and when the executable program code is executed, the processor executing instructions of the host instruction processing method as described in claim 10.

12. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed, implements the host instruction processing method as described in claim 10.

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