Task scheduling method and device based on multi-core processor, electronic equipment, storage medium, system and computer program product

Abstract

The invention provides a task scheduling method and device based on a multi-core processor, electronic equipment, a storage medium, a system and a computer program product, and the method comprises the steps: obtaining a first scheduling parameter, a second scheduling parameter and a first operation parameter in response to a task ready event; obtaining a ready task affinity between each processor core and the ready task based on the first scheduling parameter and the first operation parameter, and obtaining a current task affinity between each processor core and the current task based on the second scheduling parameter and the first operation parameter; at least one processor core is selected from the multi-core processor to serve as at least one alternative processor core, and the ready task affinity of the at least one processor core is higher than the current task affinity; selecting the processor core with the highest ready task affinity from the at least one alternative processor core as a target processor core; and scheduling the ready task to the target processor core for operation.

Description

Technical Field

[0001] The present disclosure relates to the field of computing systems, and in particular to a task scheduling method, device, electronic device, storage medium, system and computer program product based on a multi-core processor. Background Art

[0002] With the development of science and technology, all walks of life have higher and higher requirements for processor performance. Single-core processors can no longer meet the requirements of high performance, and symmetric multi-processing systems (a multi-processor computer hardware architecture, also known as a multi-core processor) using multi-core processors have become the mainstream choice for high-performance systems. The issue of processor power consumption has received increasing attention from users and suppliers. In the embedded field, the low power consumption characteristics of processors have even become a key factor in product competitiveness.

[0003] Related task scheduling research programs for symmetric multi-processing systems all reduce power consumption by allocating processor resources and utilizing hardware-supported low-power solutions (such as DVFS, Dynamic voltage and frequency scaling). Summary of the invention

[0004] The multi-core processor-based task scheduling method, device, electronic device, storage medium, system and computer program product provided by the exemplary embodiments of the present disclosure can at least solve the above-mentioned technical problems and other technical problems not mentioned above.

[0005] According to one aspect of the present disclosure, a task scheduling method based on a multi-core processor including multiple processor cores is provided, the method comprising: in the event of a task ready event, obtaining a first scheduling parameter, a second scheduling parameter, and a first operating parameter, wherein the first scheduling parameter is a scheduling parameter of a ready task corresponding to the task ready event, the second scheduling parameter is a scheduling parameter of a current task currently running in each of the multiple processor cores in the multi-core processor, and the first operating parameter is an operating parameter of each of the multiple processor cores, the operating parameter including a continuous idle time of each of the multiple processor cores; based on the first scheduling parameter and the first operating parameter, obtaining a ready task affinity between each of the multiple processor cores and the ready task, wherein the affinity of each processor core to the ready task is obtained. The ready task affinity of the processor core includes running the ready task on each processor core, and the ready task affinity indicates the degree of optimization of power consumption when each processor core runs the ready task; based on the second scheduling parameter and the first operating parameter, obtaining the current task affinity of each processor core in the multiple processor cores and the current task, wherein each processor core runs the corresponding current task or is in an idle state; selecting at least one processor core from the multi-core processor as at least one candidate processor core, wherein the ready task affinity of the at least one processor core selected as the at least one candidate processor core is higher than the current task affinity; selecting a processor core with the highest ready task affinity from the at least one candidate processor core as a target processor core; and scheduling the ready task to run on the target processor core.

[0006] Optionally, the continuous idle time of each processor core is inversely correlated with the affinity of the ready task or the affinity of the current task.

[0007] Optionally, the operating parameters also include the number of times each processor core switches tasks in the current operating cycle.

[0008] Optionally, the number of times each processor core switches tasks in the current operation cycle is positively correlated with the ready task affinity or the current task affinity of each processor core.

[0009] Optionally, the scheduling parameters include at least one of a priority of the task and a waiting time of the task.

[0010] Optionally, each of the priority of the ready task or the current task and the waiting time of the ready task or the current task is positively correlated with the affinity of the ready task or the current task, respectively.

[0011] Optionally, the task scheduling method also includes: when there is no processor core in the multi-core processor whose affinity of the ready task is higher than the affinity of the current task, adding the ready task to the global ready task list; when a time slice exhaustion event occurs, obtaining a second operating parameter, a third scheduling parameter and a fourth scheduling parameter, wherein the second operating parameter is the current operating parameter of the processor core to be assigned requesting task scheduling, the third scheduling parameter is the scheduling parameter of the task currently running on the processor core to be assigned, and the fourth scheduling parameter is the scheduling parameter of the alternative task, and the alternative task is the task with the highest priority in the global ready task list; based on the second operating parameter and the third scheduling parameter, obtaining a first affinity when the processor core to be assigned runs the currently running task; based on the second operating parameter and the fourth scheduling parameter, obtaining a second affinity when the processor core to be assigned runs the alternative task; when the second affinity is higher than the first affinity, scheduling the alternative task to run on the processor core to be assigned.

[0012] According to another aspect of the present disclosure, a task scheduling device based on a multi-core processor including multiple processor cores is provided, the device comprising: a parameter acquisition unit, configured to: in the event of a task ready event, acquire a first scheduling parameter, a second scheduling parameter, and a first operating parameter, wherein the first scheduling parameter is a scheduling parameter of a ready task corresponding to the task ready event in the multi-core processor, the second scheduling parameter is a scheduling parameter of a current task currently running in each of the multiple processor cores in the multi-core processor, the first operating parameter is an operating parameter of each of the multiple processor cores, and the operating parameter includes a continuous idle time of each of the multiple processor cores; an affinity calculation unit, configured to: based on the first scheduling parameter and the first operating parameter, obtain a ready task affinity between each of the multiple processor cores and the ready task; degree, wherein obtaining the ready task affinity of each processor core includes running the ready task on each processor core, and the ready task affinity represents the degree of optimization of power consumption when each processor core runs the ready task; based on the second scheduling parameter and the first operating parameter, obtaining the current task affinity of each processor core in the multiple processor cores and the current task, wherein each processor core runs the corresponding current task or is in an idle state; a task scheduling unit is configured to: select at least one processor core from the multi-core processor as at least one candidate processor core, wherein the ready task affinity of the at least one processor core selected as the at least one candidate processor core is higher than the current task affinity; select a processor core with the highest ready task affinity from the at least one candidate processor core as a target processor core; and schedule the ready task to run on the target processor core.

[0013] Optionally, the continuous idle time of each processor core is inversely correlated with the affinity of the ready task or the affinity of the current task.

[0014] Optionally, the operating parameters also include the number of times each processor core switches tasks in the current operating cycle.

[0015] Optionally, the number of times each processor core switches tasks in the current operation cycle is positively correlated with the affinity of the ready task or the affinity of the current task.

[0016] Optionally, the scheduling parameters include at least one of a priority of the task and a waiting time of the task.

[0017] Optionally, each of the priority of the ready task or the current task and the waiting time of the ready task or the current task is positively correlated with the affinity of the ready task or the current task, respectively.

[0018] Optionally, the task scheduling device also includes: an alternative task preparation unit, which is configured to: when there is no processor core in the multi-core processor whose affinity of the ready task is higher than the affinity of the current task, add the ready task to the global ready task list; when a time slice exhaustion event occurs, obtain a second operating parameter, a third scheduling parameter and a fourth scheduling parameter, wherein the second operating parameter is the current operating parameter of the processor core to be assigned to which the task scheduling is requested, the third scheduling parameter is the scheduling parameter of the task currently running on the processor core to be assigned, and the fourth scheduling parameter is the scheduling parameter of the alternative task. affinity parameter, the alternative task is the task with the highest priority in the global ready task list; wherein the affinity calculation unit is further configured to: based on the second operating parameter and the third scheduling parameter, obtain a first affinity when the processor core to be assigned runs the currently running task; based on the second operating parameter and the fourth scheduling parameter, obtain a second affinity when the processor core to be assigned runs the alternative task; wherein the task scheduling unit is further configured to: when the second affinity is higher than the first affinity, schedule the alternative task to run on the processor core to be assigned.

[0019] According to another aspect of an embodiment of the present disclosure, an electronic device is also provided, comprising: at least one processor; and at least one memory storing computer executable instructions, wherein when the computer executable instructions are executed by the at least one processor, the at least one processor is prompted to execute any of the above-described task scheduling methods based on a multi-core processor comprising multiple processor cores.

[0020] According to another aspect of an embodiment of the present disclosure, a computer-readable storage medium storing instructions is also provided. When the instructions are executed by at least one processor, the at least one processor is prompted to execute any of the task scheduling methods described above based on a multi-core processor including multiple processor cores.

[0021] According to another aspect of an embodiment of the present disclosure, a system is also provided, comprising at least one computing device and at least one storage device storing instructions, wherein when the instructions are executed by the at least one computing device, the at least one computing device is prompted to execute any of the above-described task scheduling methods based on a multi-core processor comprising multiple processor cores.

[0022] According to another aspect of an embodiment of the present disclosure, a computer program product is also provided, including a computer program / instruction, which, when executed by a processor, implements the task scheduling method based on a multi-core processor including multiple processor cores as described in any one of the above.

[0023] The technical solution provided by the embodiments of the present disclosure brings at least the following beneficial effects: According to the multi-core processor-based task scheduling method, device, electronic device, storage medium, system and computer program product disclosed in the present invention, since the power consumption saving of a single processor core will be greater than the sum of the power consumption saving of multiple processor cores when the idle time of a single processor core is equal to the cumulative idle time of multiple processor cores, the idle time of multiple cores in a symmetric multi-processing system can be integrated from the level of system task scheduling to keep the idle processor cores in an idle state as much as possible, so that the idle time of the processor cores can be integrated to the greatest extent by improving the operating density of the processor cores without affecting the operating efficiency of the system.

[0024] In addition, unnecessary migration of tasks between different cores can be minimized, and frequent switching of tasks can be avoided to reduce power consumption caused by task switching while ensuring task execution efficiency.

[0025] In addition, from the perspective of task scheduling, conditions are provided for supporting hardware low-power solutions to optimize the power consumption of symmetric multi-processing systems. By comprehensively considering the scheduling parameters of tasks and the hardware characteristics that affect the processor power consumption, low-power task scheduling of symmetric multi-processing systems is proposed for load balancing, and the affinity representation of tasks and processor cores is proposed to determine the optimal scheduling scheme for power consumption optimization by comparing the affinity of each processor core and the task during task scheduling. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings herein are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the description are used to explain the principles of the present disclosure, and do not constitute improper limitations on the present disclosure.

[0027] Figure 1 A schematic diagram showing the structure of a multi-core processor in the related art is shown; Figure 2 A flowchart showing a task scheduling method based on a multi-core processor in an exemplary embodiment of the present disclosure is shown; Figure 3 A schematic diagram showing a global ready task list in an exemplary embodiment of the present disclosure; Figure 4 A block diagram showing a module for executing a task scheduling method based on a multi-core processor in an exemplary embodiment of the present disclosure; Figure 5 A diagram showing the relationship between the idle time and mode of a processor core in an exemplary embodiment of the present disclosure; Figure 6 A schematic diagram showing the operation of a multi-core processor corresponding to a task scheduling solution in the related art; Figure 7 A schematic diagram showing the operation of a multi-core processor corresponding to a task scheduling solution in an exemplary embodiment of the present disclosure is shown; Figure 8 A block diagram showing a task scheduling device based on a multi-core processor in an exemplary embodiment of the present disclosure is shown; Fig. 9 A block diagram illustrating an electronic device according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] In order to enable ordinary persons in the art to better understand the technical solutions of the present disclosure, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the accompanying drawings.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of the present disclosure and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present disclosure described herein can be implemented in an order other than those illustrated or described herein. The implementation methods described in the following examples do not represent all implementation methods consistent with the present disclosure. Instead, they are merely examples of devices and methods consistent with some aspects of the present disclosure as detailed in the attached claims.

[0030] It should be noted that the phrase "at least one of the items" in the present disclosure includes three types of parallel situations: "any one of the items", "a combination of any number of the items", and "all of the items". For example, "including at least one of A and B" includes the following three parallel situations: (1) including A; (2) including B; (3) including A and B. Another example is "executing at least one of step 1 and step 2" which means the following three parallel situations: (1) executing step 1; (2) executing step 2; (3) executing step 1 and step 2.

[0031] The low power consumption of a processor is an important competitive advantage for a product. For example, the Advanced RISC Machine (ARM) processor was designed with low power consumption in mind. When it evolved to the ARM11, the ARMv7-based Cortex-M even included hardware support for sleep mode.

[0032] In recent years, low-power solutions for processor systems have become increasingly mature.

[0033] First, low-power technology at the hardware level has made great progress, and dynamic voltage and frequency scaling (DVFS) technology has been widely used. DVFS can be used to adjust the voltage and frequency according to the performance and power consumption requirements of the chip, so that the requirements can be achieved with the minimum power consumption in various different working requirements.

[0034] The embedded operating system FreeRTOS supports optional low-power modes, allowing the hardware to switch to low-power modes when the system enters idle state.

[0035] At the same time, the research on low-power technology of symmetric multi-processing systems mainly focuses on two angles: processor resource allocation and the use of DVFS technology.

[0036] For example, by using OSCAR API to directly use DVFS technology to reduce system power consumption when writing multi-task programs; or by dividing tasks into multiple segments according to the control flow, the time required for the task to run is obtained according to the different control flows of the tasks, and the operating frequency and voltage are adjusted through DVFS technology to minimize power consumption while meeting real-time requirements. For example, when writing multi-task programs, the OSCAR API can be used to directly apply DVFS technology to reduce system power consumption. In addition, tasks can be divided into multiple parts according to their control flow to determine the execution time required for each part. In this way, the operating frequency and voltage can be adjusted through DVFS to minimize power consumption while ensuring real-time performance.

[0037] For another example, it is found that tasks with high processor core utilization can often improve performance by increasing the number of processor cores, and tasks with a smaller number of processor cores can improve performance by increasing the processor frequency. Therefore, it is proposed that tasks with higher processor core utilization should receive additional processor cores first, while tasks with a smaller number of processor cores should increase the DVFS level processing strategy first, thereby improving the performance-power ratio.

[0038] Through the analysis of the above-mentioned related technologies, it is found that the low-power solutions of symmetric multi-processing systems all reduce power consumption by allocating processor resources and utilizing hardware-supported low-power solutions (such as DVFS). However, in terms of utilizing hardware-supported low-power solutions, no research has been conducted from the perspective of processor idleness.

[0039] As for the method of reducing power consumption by putting the processor in an idle state, the longer the idle time of a single core, the better the power consumption reduction effect.

[0040] Since the relevant symmetric multi-processing task scheduling scheme does not take power consumption into consideration, it cannot integrate the idle states of multiple cores from the level of system task scheduling. The operating states of the cores change randomly according to the changes in system tasks, the idle states of multiple cores also appear randomly, and the idle windows of multiple cores are highly random, which is not conducive to reducing power consumption.

[0041] In order to solve the above problems, the present disclosure provides a task scheduling method, device, electronic device, storage medium, system and computer program product based on a multi-core processor, which can integrate the idle time of multiple cores in a symmetric multi-processing system from the level of system task scheduling, so as to keep the idle processor cores in an idle state as much as possible, so as to maximize the integration of the processor core's idle time by improving the operating density of the processor core without affecting the system operation efficiency.

[0042] Next, we will refer to Figures 1 to 9 The present invention specifically describes a multi-core processor-based task scheduling method, device, electronic device, storage medium, system, and computer program product.

[0043] Figure 1 A schematic diagram of the structure of a multi-core processor in the related art is shown.

[0044] Reference Figure 1In a multi-core processor, for example, processor cores 0 to N, where N is an integer greater than 1, each processor core can contain a first-level cache (high-speed cache memory), and the cores can share a second-level cache to reduce the dependence on the main memory, and each processor core can be placed in an independent power domain. A power domain refers to a part of an integrated circuit (IC) or a system on a chip (SoC) that can independently control the power supply. Different power domains can selectively turn on or off power or adjust voltage and frequency in specific areas of the chip to optimize power consumption. In a system with multiple power domains, each power domain can be managed separately, thereby implementing energy-saving technologies such as dynamic voltage and frequency scaling (DVFS) and power gating. These technologies are essential for modern processors and embedded systems to balance performance requirements and energy efficiency. Each processor core in a multi-core processor can support multiple low-power modes, and the processor core and its cache can be powered off independently. For a single processor core, different power modes can be selected for different idle times. If the idle time is longer, a power mode with lower power consumption can be selected. In this way, when the idle time of a single processor core is equal to the accumulated idle time of multiple processor cores, the power consumption saved by the single processor core will be greater than the sum of the power consumption saved by the multiple processor cores.

[0045] Figure 2 A flowchart of a task scheduling method based on a multi-core processor in an exemplary embodiment of the present disclosure is shown.

[0046] Reference Figure 2 In step 201, when a task ready event occurs, a first scheduling parameter, a second scheduling parameter, and a first operating parameter may be obtained. The first scheduling parameter is a scheduling parameter of a ready task corresponding to the task ready event, and the second scheduling parameter is a scheduling parameter of a task currently being run by each processor core in a multi-core processor. In an embodiment, the second scheduling parameter is a scheduling parameter of a task currently being run by at least one processor core (i.e., a scheduling parameter of a current task). The first operating parameter is an operating parameter currently corresponding to each processor core. The operating parameter may include a continuous idle time of a processor core.

[0047] According to an exemplary embodiment of the present disclosure, when a task ready event occurs, the optimal scheduling destination processor core (i.e., target processor core) can be calculated by acquiring the scheduling parameters of each task and the operating parameters of each processor core. The first scheduling parameter acquired can be the scheduling parameter of the ready task corresponding to the task ready event, and the second scheduling parameter can be the scheduling parameter of the task currently being run by each processor core in the multi-core processor. In an embodiment, the second scheduling parameter is the scheduling parameter of the task currently being run by at least one processor core. For example, when a multi-core processor has four processor cores, three processor cores run a task, and the remaining processor core is in an idle state, the acquired second scheduling parameter can be the scheduling parameter of the task currently being run by the three processor cores. If the three processor cores are currently running different tasks, the acquired second scheduling parameter may include the scheduling parameters of the three different tasks. In an embodiment, the acquired second scheduling parameter may include the scheduling parameters of no task currently being run. The first operating parameter may be the operating parameter of each processor core. The operating parameter may include the continuous idle duration of the processor core. By acquiring the operating parameter including the continuous idle duration of the processor core, the idle duration of a single processor core can be integrated as a target to select the target processor core. For example, three processor cores currently running tasks have values ​​indicating no continuous idle duration, while the remaining one processor core now in an idle state has a value indicating the duration of the idle state. When selecting a target processor core for a ready task, the operating parameters of each processor core including its continuous idle duration may be considered.

[0048] In step 202, the affinity of each processor core when running the ready task can be obtained based on the first scheduling parameter and the first operating parameter. The affinity indicates the degree of optimization of power consumption when the current processor core runs the current task. For example, the ready task can be simulated as the current task execution based on the first scheduling parameter and the first operating parameter, thereby determining the affinity of each processor core.

[0049] According to an exemplary embodiment of the present disclosure, the degree of optimization of power consumption when any processor core runs any task can be estimated / expressed by defining the affinity between the processor core and the task, and the value of the affinity can be calculated by obtaining the scheduling parameters of the task and the operating parameters of the processor core. The first scheduling parameter and the first operating parameter can calculate the affinity between each processor core and the ready task when each processor core simulates running the ready task.

[0050] According to an exemplary embodiment of the present disclosure, the continuous idle time length of the processor core is inversely correlated with the affinity.

[0051] According to an exemplary embodiment of the present disclosure, in order to integrate the idle time of a single processor core, when affinity is used to estimate / represent the degree of optimization of power consumption when any processor core runs any task, the parameter of the continuous idle time of the processor core can be inversely correlated with the value of affinity. For example, when estimating the degree of optimization of power consumption of each processor core, the idle time of each processor core can be considered.

[0052] In step 203, the affinity of each processor core when running the currently running task is obtained based on the second scheduling parameter and the first operating parameter. For example, the affinity of each processor core can be determined by simulating the execution of the current task based on the second scheduling parameter and the first operating parameter.

[0053] According to an exemplary embodiment of the present disclosure, the second scheduling parameter and the first operating parameter can calculate the affinity between each processor core and the task it is currently running when each processor core runs the task it is currently running. When there is a processor core that is not currently running a task, the affinity between the processor core and the state of not currently running a task can still be calculated.

[0054] It is understandable that there is no execution order between step 202 and step 203 .

[0055] According to an exemplary embodiment of the present disclosure, the operating parameters may also include, but are not limited to: the number of times the processor core switches tasks in the current operating cycle. In a multi-core processor, an "operating cycle" refers to how the processor manages tasks or instructions between its multiple cores. Each core runs in cycles, and each cycle includes a series of steps to process instructions, such as instruction acquisition, instruction decoding, execution, and memory access. Each processor core in a multi-core processor can run independent cycles at the same time, which means that different cores can execute instructions at different stages of the pipeline. Task scheduling (usually handled by the operating system) ensures that different processes or threads are distributed among the available cores. If the task is parallelizable (multi-threaded), multiple cores can process different parts of the same task at the same time.

[0056] According to an exemplary embodiment of the present disclosure, the cache can improve the execution efficiency of the code, but if the task switching is frequently performed on a processor core, the cache hit rate will be greatly reduced and the resource consumption of the task switching will increase, thereby increasing the power consumption. Therefore, it is necessary to avoid frequent switching of tasks while satisfying the task execution efficiency, so as to reduce the power consumption caused by task switching. By considering the number of times the processor core switches tasks in the current operating cycle as the operating parameter of the processor core, a scheduling strategy with better power consumption optimization results can be obtained in the task scheduling of a multi-core processor. For example, in the task scheduling of a multi-core processor, a more energy-saving scheduling strategy can be implemented by taking the number of task switches of the processor core in the current operating cycle as an operating parameter.

[0057] According to an exemplary embodiment of the present disclosure, the number of times a processor core switches tasks in the current operation cycle is positively correlated with affinity. It is understandable that the goal of the present disclosure is to reduce the overall number of switching of each processor core in a multi-core processor, so as to avoid frequent switching of tasks of the processor core as a whole while meeting the task execution efficiency, so as to reduce the power consumption caused by task switching, but the number of task switching of a certain processor core may increase.

[0058] According to an exemplary embodiment of the present disclosure, in order to avoid frequent task switching of the processor core, when affinity is used to estimate / represent the degree of optimization of power consumption when any processor core runs any task, when estimating the affinity, the parameter of the number of times the processor core switches tasks in the current operating cycle can be made positively correlated with the value of the affinity.

[0059] According to an exemplary embodiment of the present disclosure, the scheduling parameters may include but are not limited to: at least one of the priority of the task and the waiting time of the task. For example, the waiting time of the task indicates how long has passed since the task ready event of the task occurred.

[0060] According to an exemplary embodiment of the present disclosure, for the scheduling parameters of a task, one or more of the priority of the task and the waiting time of the task may be considered to obtain the affinity between any processor core and any task. It is understandable that the scheduling parameters of a task are not limited to the two listed above.

[0061] According to an exemplary embodiment of the present disclosure, each of the priority of a task and the waiting time of a task may be positively correlated with the affinity.

[0062] According to an exemplary embodiment of the present disclosure, since affinity is used to estimate / represent the degree of optimization of power consumption when any processor core runs any task, in order to meet task execution efficiency and avoid task delayed scheduling, the two parameters of task priority and task waiting time can be made positively correlated with the affinity value.

[0063] In step 204, a processor core whose affinity when running a ready task (i.e., the ready task affinity) is higher than its affinity when running a current task (i.e., the current task affinity) is selected from the multi-core processor as a candidate processor core, and a processor core with the highest affinity when running a ready task is selected from the candidate processor cores as a target processor core, and the ready task can be scheduled to run on the target processor core.

[0064] According to an exemplary embodiment of the present disclosure, for each processor core, the affinity of the processor core when running the currently running task and the ready task can be compared. For example, the affinity value of the ready task and the affinity value of the current task of each processor core can be compared. If there is a processor core whose affinity when running the ready task is higher than its affinity when running the currently running task, and its affinity when running the ready task is the highest among all processor cores, that is, when there is a processor core with the highest affinity when running the ready task, this processor core can be used as the target processor core, and the ready task can be scheduled to run on this target processor core. For example, if a processor core has a higher affinity for the ready task than the currently running task, and the affinity is the highest among all processor cores, then the processor core can be selected as the target processor core, and the ready task can be scheduled to run on the target processor core.

[0065] According to the exemplary embodiments of the present disclosure, according to the characteristics of the processor, a scheduling principle for low-power load balancing in a symmetric multi-processing system can be proposed in combination with various embodiments: (1) Try to keep idle processor cores in an idle state as long as possible; (2) Minimize unnecessary migration / switching of tasks between different cores; In order to implement the above low-power load balancing scheduling principle, as an example only, the following state parameters of processor cores and tasks can be considered at the same time:

[0066] You can define processor cores With the task Affinity as follows: (Formula-1) The definition of the parameter mapping relationship defined in formula-1 can be shown in the following table:

[0067] The affinity value calculated according to formula-1 The higher the value, the better it is for scheduling task j to the processor core. It will be more in line with the above-mentioned low-power load balancing scheduling principle defined in this disclosure.

[0068] When the task When ready, each processor core can be acquired The current operating parameters and the tasks currently running on each processor core Scheduling parameters; can calculate the tasks on each processor core and the corresponding processor core Affinity between ; Each processor core can be calculated and ready tasks Affinity between ; For each processor core , which can be compared as well as ,like Greater than Then you can Add to Alternative Set .

[0069] If the collection If it is not empty, you can take the collection The maximum value in Corresponding processor core As a ready task The scheduling core (target processor core) of . Then you can put the ready task Dispatching to target processor core .

[0070] According to an exemplary embodiment of the present disclosure, the above-mentioned task scheduling method may further include the following steps: when there is no processor core in the multi-core processor whose affinity when running the ready task is higher than the affinity when running the current task, the ready task may be added to a preset global ready task list; when a time slice exhaustion event occurs, the second operating parameter, the third scheduling parameter and the fourth scheduling parameter may be obtained, wherein the second operating parameter may be the current operating parameter of the processor core to be assigned that actively requests task scheduling. For example, when the time slice of a task processed by a processor core is exhausted, the processor core becomes a processor core to be assigned and needs to switch to a new task. At this time, the processor core will actively request task scheduling, that is, the processor core will send a request to the operating system to request task scheduling. For example, in the case where no target processor core is selected, in response to a time slice exhaustion event occurring in the processor core, the processor core may request task scheduling using the global ready task list. The third scheduling parameter may be a scheduling parameter for a task running on the processor core to be assigned, and the fourth scheduling parameter may be a scheduling parameter for an alternative task, which may be a task with the highest priority in the global ready task list; the affinity of the processor core to be assigned when running the currently running task may be obtained based on the second operating parameter and the third scheduling parameter; the affinity of the processor core to be assigned when running the alternative task may be obtained based on the second operating parameter and the fourth scheduling parameter; when the affinity of the processor core to be assigned when running the alternative task is higher than the affinity of the processor core to be assigned when running the currently running task, the alternative task may be scheduled to run on the processor core to be assigned.

[0071] According to an exemplary embodiment of the present disclosure, when there is no processor core in the multi-core processor whose affinity when running the ready task is higher than the affinity when running the current task, it can also be said that when there is no target processor core with the highest affinity when running the ready task, it can also be said that if the above set If it is empty, the ready task can be Add to the global ready task list.

[0072] Figure 3 A schematic diagram showing a global ready task list in an exemplary embodiment of the present disclosure.

[0073] Reference Figure 3 According to an exemplary embodiment of the present disclosure, after the processor system is initialized, a global ready task list can be pre-established, and a corresponding empty linked list header can be generated for each priority in the global ready task list and placed in the task queue.

[0074] According to an exemplary embodiment of the present disclosure, tasks of the same priority in an embedded system can be executed in turn using a polling method. When the task time slice is exhausted, a time slice exhaustion event occurs, and the processor core needs to switch to a new task. At this time, the processor core will actively request task scheduling. For example, in order to realize multi-task concurrent processing, a scheduling algorithm such as round-robin can be used. Each task can be assigned a time slice, which is a fixed time period. During this time period, the processor core can specifically process the task; when a task runs on the processor core and its allocated time slice is exhausted, it means that the execution time of the task in the current round has ended. Since the time slice is exhausted, the processor core can no longer continue to process the current task (it can not continue in the current round), but can start to process other tasks waiting to be executed; in order to be able to switch to a new task, the processor core can determine which task should be executed next through the operating system's scheduler; therefore, when the time slice is exhausted, the processor core can send a request to the operating system to request task scheduling; after receiving the request, the operating system's scheduler can select a suitable new task and assign it to the processor core to be assigned for execution.

[0075] When a processor core The current task time slice is exhausted, the processor core When actively requesting task scheduling, a new task switch can be performed or no task switch processing can be performed based on the calculation result of affinity.

[0076] The specific steps may be as follows: In response to the time slice exhaustion event, the processor core The operating parameters corresponding to the current state and the current running on the processor core Tasks on The scheduling parameters of the processor core can be calculated Tasks on Corresponding processor core Affinity between ; You can take the first task in the highest priority list of the global ready task list as the candidate task , and can calculate alternative tasks and processor core Affinity between ;like Greater than , then you can add alternative tasks Switch scheduling to processor core Otherwise, no task switching is performed. For example, task j currently running on processor core i i Can be switched to tasks , and the task It can be scheduled to run on processor core i. It can be understood that the first task can represent the earliest ready task with the same priority level based on the concept of time queuing.

[0077] Figure 4 A block diagram showing a module for executing a task scheduling method based on a multi-core processor in an exemplary embodiment of the present disclosure is shown.

[0078] Reference Figure 4 According to an exemplary embodiment of the present disclosure, the above-mentioned task scheduling method based on a multi-core processor can be coordinated and executed by multiple modules, for example, it can be coordinated and executed by an initialization module 401, a scheduler module 402 and a load balancing module 403.

[0079] It can be understood that each module can be software, hardware, firmware or any combination of the above items that perform corresponding functions.

[0080] The initialization module 401 may be responsible for initializing the environment required by the load balancing module 403. The scheduler module 402 may call the relevant interface of the load balancing module 403 upon receiving a task ready event or a time slice exhaustion event. The load balancing module 403 may calculate and compare the affinity values ​​of each processor core and each task, and may return to the scheduler module 402 whether task switching is required and the best target processor core for switching. If task switching is required, the scheduler module 402 may schedule the target task to the target processor core. If task switching is not required, the scheduler module 402 may add the target task to the global ready task list.

[0081] According to an exemplary embodiment of the present disclosure, the above-mentioned task scheduling method based on a multi-core processor can be divided into two processes: initialization and scheduling processing.

[0082] Initialization module 401 can establish the low-power load balancing scheduling environment of the present disclosure, and after the processor system is initialized, pre-establish a global ready task list, and can also initialize the continuous running time for each processor core. , and the number of task switches in the processor core within the most recent fixed period T .

[0083] After the initialization is completed, the scheduler module 402 can wait for the occurrence of corresponding events (task ready event, time slice exhaustion event), and apply the multi-core processor-based task scheduling method described in the present disclosure to perform scheduling according to the corresponding events.

[0084] When task k is ready, the scheduler module 402 can call the interface of the load balancing module 403 to calculate the optimal scheduling destination processor core. The scheduler module 402 can add the ready task to the global ready task list or schedule the task to the destination processor core according to the calculation result.

[0085] According to the exemplary embodiments of the present disclosure, the proposed low-power load balancing solution for a symmetric multiprocessing system can obtain an optimal selection of the processor core by comprehensively considering the status of tasks and processor cores, such as the running time of the processor core and the number of task switching, the priority and waiting time of the current running task of the processor core, etc., when scheduling tasks in the symmetric multiprocessing system. It can maximize the integration of the idle time of the processor core by improving the running density of the processor core without affecting the operating efficiency of the system. The load balancing solution of the exemplary embodiments of the present disclosure can maximize the integration of the idle state of the processor core from the perspective of system operation, and can effectively reduce the total power consumption of the symmetric multiprocessing system by combining hardware low-power technology.

[0086] According to an exemplary embodiment of the present disclosure, the rationality and effectiveness of a multi-core processor-based task scheduling method described in the present disclosure can be demonstrated through the following specific scheduling scenarios.

[0087] Take a 4-core processor as an example. Assume that each processor core has 4 power consumption operation modes, which are marked as M0, M1, M2, and M3 from high to low. The corresponding power consumption levels of the 4 operation modes can be marked as P 0 , P 1 , P 2 , P 3 , the energy consumption level can have the following relationship, P 0 >P 1 >P 2 >P 3 .

[0088] The task scheduling method based on a multi-core processor described in the present disclosure can maximize the integration of the idle time of the processor core to reduce power consumption. For example, the idle time of the processor core can be considered in the task scheduling method to reduce power consumption. According to the low-power scheme of the current mainstream processor, the processor can enter different power consumption modes under different idle time lengths. When defining 1 unit time as T, the processor core idle time can be defined as 0, 1 T, 2 At T, the corresponding processor core operation mode is adjusted to M1, M2, M3, and the processor core operation mode is M0 when not idle (RUN), as shown in the following table.

[0089]

[0090] Figure 5 A diagram showing the relationship between the idle time and mode of a processor core in an exemplary embodiment of the present disclosure is shown.

[0091] Then, for a processor core, as its idle time increases, the change of its processor mode can be referred to Figure 5 That is, when the processor core is not idle, the operating mode is M0, and the corresponding power consumption is P 0 ; The processor core starts to idle and idle 1 Within T, the operation mode is M1, and the corresponding power consumption is P 1 ; Processor core idle 1 After T and 2 Within T, the operation mode is M2, and the corresponding power consumption is P 2 ; Processor core idle 2 After T and 3 Within T, the operation mode is M3, and the corresponding power consumption is P 3 .

[0092] Figure 6 A schematic diagram showing the operation of a multi-core processor corresponding to a task scheduling solution in the related art is shown.

[0093] Reference Figure 6 , we can assume that the symmetric multi-processing system includes four processor cores core0, core1, core2, and core3. In the scheduling scheme based on the ordinary task priority preemption in the related art, each processor core runs tasks task1, task2, task3, and task4 respectively in 4 unit times. Figure 6 The total power consumption of this task scheduling scheme is shown as according to Figure 6 Calculation can be = ,Right now = .

[0094] Next, you can Figure 6 The task scheduling scheme shown adopts the low-power load balancing method for symmetric multi-processing systems proposed in the present disclosure (ie, a task scheduling method based on a multi-core processor in the present disclosure) to optimize power consumption.

[0095] The function in formula 1 can be Implemented as:

[0096] And, in formula 1, we can take , that is, the following formula-2 is obtained: (Formula-2) Figure 6 in At T, task3 is ready. According to the above formula-2 and The implementation can calculate the parameter values ​​required for the affinity between each processor core and each task. When a processor core is processing a task, its continuous idle time is the continuous time of processing the task and can be negative, and its task priority can be 16. The final calculation results can be shown in the following table:

[0097] According to a task scheduling method based on a multi-core processor disclosed in the present invention, the candidate set in the above situation can be obtained as follows: , and the maximum value in the candidate set is , so task3 can be scheduled to processor core core0.

[0098] Figure 6 in At T, task1 is ready again. According to formula-2 and The implementation method can calculate the parameter values ​​required for the affinity between each processor core and each task after scheduling task3 to processor core core0, and the final calculation results can be shown in the following table:

[0099] According to the task scheduling method based on a multi-core processor described in the present disclosure, the candidate set in the above situation can be obtained as follows: , and the maximum value in the candidate set is , so task1 can be scheduled to processor core core1.

[0100] Figure 6 When t=3 At T, task2 is ready again. According to formula-2 and The implementation method can calculate the parameter values ​​and final calculation results required for the affinity between each processor core and each task after scheduling task1 to processor core core1, which can be shown in the following table:

[0101] According to the task scheduling method based on a multi-core processor described in the present disclosure, the candidate set in the above situation can be obtained as follows: , therefore, task2 can be scheduled to processor core 2.

[0102] In summary, the scheduling scheme after using the multi-core processor-based task scheduling method described in the present disclosure can be shown in the following table:

[0103] Combined with the above table, after using the task scheduling method based on a multi-core processor described in this disclosure, Figure 6 The shown schedule can be optimized as Figure 7 The scheduling scheme shown.

[0104] Figure 7 FIG. 1 shows a schematic diagram of the operation of a multi-core processor corresponding to a task scheduling solution in an exemplary embodiment of the present disclosure. Task 3, which started running on core 2 at time T, is scheduled to run on core 0. Task 1, which starts running on core 1 at time T, is scheduled to run on core 1. Task2, which started running on core1 at time T, is scheduled to run on core2.

[0105] Total power consumption using a task scheduling scheme in an exemplary embodiment of the present disclosure Can be based on Figure 7 calculate, = .Right now = .

[0106] because ,so ,Right now Therefore, using a task scheduling scheme in an exemplary embodiment of the present disclosure can reduce the power consumption of a symmetric multi-processing system.

[0107] According to the exemplary embodiments of the present disclosure, the present disclosure can optimize the power consumption of a symmetric multi-processing system from the perspective of task scheduling. By considering the hardware characteristics that affect the power consumption of the processor, a low-power task scheduling principle for a symmetric multi-processing system is proposed. Based on this principle, a method for calculating the affinity between tasks and processor cores is proposed, and the best scheduling scheme can be determined by affinity during scheduling. And through experimental verification in actual task scheduling scenarios, and comparison with ordinary task priority preemptive scheduling schemes, it can be seen that the low-power load balancing method for a symmetric multi-processing system proposed in the present disclosure can effectively integrate the idle time of multiple cores in a symmetric multi-processing system, and provide conditions for supporting hardware low-power schemes from the perspective of task scheduling, thereby reducing the power consumption of the symmetric multi-processing system.

[0108] Figure 8 A block diagram of a task scheduling device based on a multi-core processor in an exemplary embodiment of the present disclosure is shown.

[0109] Reference Figure 8 The exemplary embodiment of the present disclosure further provides a multi-core processor-based task scheduling device 800 , which may include but is not limited to a parameter acquisition unit 801 , an affinity calculation unit 802 , and a task scheduling unit 803 .

[0110] The parameter acquisition unit 801 can acquire a first scheduling parameter, a second scheduling parameter, and a first operating parameter when a task ready event occurs, wherein the first scheduling parameter can be a scheduling parameter of a ready task corresponding to the task ready event, the second scheduling parameter can be a scheduling parameter of a task currently running on each processor core in a multi-core processor, the first operating parameter can be an operating parameter for each processor core, and the operating parameter can include but is not limited to a continuous idle time of a processor core.

[0111] The affinity calculation unit 802 can obtain the affinity of each processor core when running a ready task based on the first scheduling parameter and the first operating parameter, wherein the affinity can indicate the degree of optimization of power consumption when the current processor core runs the current task; based on the second scheduling parameter and the first operating parameter, the affinity of each processor core when running the currently running task can be obtained.

[0112] The task scheduling unit 803 selects a processor core whose affinity when running a ready task is higher than the affinity when running the current task from the multi-core processor as a candidate processor core, selects a processor core with the highest affinity when running a ready task from the candidate processor cores as a target processor core, and schedules the ready task to run on the target processor core.

[0113] According to an exemplary embodiment of the present disclosure, in the above-mentioned task scheduling device 800 based on a multi-core processor, the continuous idle time of the processor core may be inversely correlated with the affinity.

[0114] According to an exemplary embodiment of the present disclosure, in the above-mentioned task scheduling device 800 based on a multi-core processor, the operating parameters may also include but are not limited to the number of times the processor core switches tasks in the current operating cycle.

[0115] According to an exemplary embodiment of the present disclosure, in the above-mentioned task scheduling device 800 based on a multi-core processor, the number of times a processor core switches tasks in a current operation cycle may be positively correlated with the affinity.

[0116] According to an exemplary embodiment of the present disclosure, in the above-mentioned multi-core processor-based task scheduling device 800, the scheduling parameters may include but are not limited to at least one of the priority of the task and the waiting time of the task.

[0117] According to an exemplary embodiment of the present disclosure, in the multi-core processor-based task scheduling device 800 , each of the task priority and the task waiting time may be positively correlated with the affinity.

[0118] According to an exemplary embodiment of the present disclosure, the above-mentioned task scheduling device 800 based on a multi-core processor may also include but is not limited to: an alternative task preparation unit (not shown in the figure), which can add the ready task to a preset global ready task list when there is no processor core in the multi-core processor whose affinity when running the ready task is higher than the affinity when running the current task; a parameter acquisition unit 801, which can also acquire a second operating parameter, a third scheduling parameter and a fourth scheduling parameter when a time slice exhaustion event occurs, wherein the second operating parameter can be the current operating parameter of the processor core to be assigned that actively requests task scheduling, and the third scheduling ... The fourth scheduling parameter may be a scheduling parameter for a task on the processor core to be assigned, and the alternative task may be a task with the highest priority in the global ready task list; the affinity calculation unit 802 may also obtain the affinity of the processor core to be assigned when running the currently running task based on the second operating parameter and the third scheduling parameter; the affinity of the processor core to be assigned when running the alternative task is obtained based on the second operating parameter and the fourth scheduling parameter; the task scheduling unit 803 may also schedule the alternative task to run on the processor core to be assigned when the affinity of the processor core to be assigned when running the alternative task is higher than the affinity of the currently running task.

[0119] It is understandable that in the exemplary embodiment of the above-mentioned task scheduling device 800 based on a multi-core processor, the specific implementation process is roughly the same as the exemplary embodiment of the task scheduling method based on a multi-core processor, and will not be repeated here. The task scheduling device 800 based on a multi-core processor can be configured as software, hardware, firmware or any combination of the above items to perform specific functions. For example, these devices may correspond to dedicated integrated circuits, pure software codes, or modules that combine software and hardware. In addition, one or more functions implemented by these devices can also be uniformly executed by components in physical entity devices (for example, processors, clients or servers, etc.).

[0120] Fig. 9 A block diagram illustrating an electronic device according to an exemplary embodiment of the present disclosure.

[0121] Reference Fig. 9The electronic device 900 includes at least one memory 901 and at least one processor 902, wherein the at least one memory 901 stores a set of computer executable instructions. When the computer executable instruction set is executed by the at least one processor 902, a task scheduling method based on a multi-core processor according to an exemplary embodiment of the present disclosure is executed.

[0122] As an example, the electronic device 900 may be a PC, a tablet device, a personal digital assistant, a smart phone, or other device capable of executing the above instruction set. Here, the electronic device 900 is not necessarily a single electronic device, but may also be any device or circuit collection capable of executing the above instructions (or instruction sets) individually or in combination. The electronic device 900 may also be part of an integrated control system or system manager, or may be configured as a portable electronic device interconnected with a local or remote (e.g., via wireless transmission) interface.

[0123] In the electronic device 900, the processor 902 may include a central processing unit (CPU), a graphics processing unit (GPU), a programmable logic device, a dedicated processor system, a microcontroller or a microprocessor. As an example and not limitation, the processor may also include an analog processor, a digital processor, a microprocessor, a multi-core processor, a processor array, a network processor, etc.

[0124] The processor 902 may execute instructions or codes stored in the memory 901, wherein the memory 901 may also store data. Instructions and data may also be sent and received over a network via a network interface device, wherein the network interface device may employ any known transmission protocol.

[0125] The memory 901 may be integrated with the processor 902, for example, by placing RAM or flash memory within an integrated circuit microprocessor or the like. In addition, the memory 901 may include a separate device, such as an external disk drive, a storage array, or any other storage device that can be used by a database system. The memory 901 and the processor 902 may be operatively coupled, or may communicate with each other, such as through an I / O port, a network connection, etc., so that the processor 902 can read files stored in the memory.

[0126] In addition, the electronic device 900 may further include a video display (such as a liquid crystal display) and a user interaction interface (such as a keyboard, a mouse, a touch input device, etc.) All components of the electronic device 900 may be connected to each other via a bus and / or a network.

[0127] According to an exemplary embodiment of the present disclosure, a computer-readable storage medium storing instructions may also be provided, wherein when the instructions are executed by at least one computing device, the at least one computing device is prompted to execute the above-mentioned task scheduling method based on a multi-core processor.

[0128] Examples of computer-readable storage media include read-only memory (ROM), random-access programmable read-only memory (PROM), electrically erasable programmable read-only memory (EEPROM), random-access memory (RAM), dynamic random-access memory (DRAM), static random-access memory (SRAM), flash memory, nonvolatile memory, CD-ROM, CD-R, CD+R, CD-RW, CD+RW, DVD-ROM, DVD-R, DVD+R, DVD-RW, DVD+RW, DVD-RAM, BD-ROM, BD-R, BD-R LTH, BD-RE, Blu-ray or optical disk storage, hard disk drive (HDD), solid state drive (SSD), card storage (such as, multimedia card, secure digital (SD) card or extreme digital (XD) card), magnetic tape, floppy disk, magneto-optical data storage device, optical data storage device, hard disk, solid state disk and any other device, any other device is configured to store computer programs and any associated data, data files and data structures in a non-transitory manner and provide the computer programs and any associated data, data files and data structures to a processor or computer so that the processor or computer can execute the computer program. The computer program in the above-mentioned computer-readable storage medium can be run in an environment deployed in a computer device such as a client, a host, an agent device, a server, etc. In addition, in one example, the computer program and any associated data, data files and data structures are distributed on a networked computer system, so that the computer program and any associated data, data files and data structures are stored, accessed and executed in a distributed manner by one or more processors or computers. It should be noted that the instructions can also be used to execute additional steps in addition to the above steps or to perform more specific processing when executing the above steps. The contents of these additional steps and further processing have been mentioned in the description of the relevant methods, so they will not be repeated here to avoid repetition.

[0129] Another embodiment of the present disclosure relates to a system including at least one computing device and at least one storage device storing instructions, wherein the instructions, when executed by the at least one computing device, prompt the at least one computing device to execute the above-mentioned task scheduling method based on a multi-core processor.

[0130] It should be noted that the system according to the exemplary embodiments of the present disclosure can completely rely on the execution of computer programs or instructions to realize corresponding functions, that is, each unit corresponds to each step in the functional architecture of the computer program, so that the entire system is called through a special software package (e.g., lib library) to realize the corresponding functions.

[0131] On the other hand, when the above-mentioned system is implemented in software, firmware, middleware or microcode, the program code or code segment for performing the corresponding operation can be stored in a computer-readable medium such as a storage medium, so that at least one processor or at least one computing device can perform the corresponding operation by reading and running the corresponding program code or code segment.

[0132] According to an exemplary embodiment of the present disclosure, the storage device may be integrated with the computing device, for example, RAM or flash memory is arranged within an integrated circuit microprocessor, etc. In addition, the storage device may include an independent device, such as an external disk drive, a storage array, or any other storage device that can be used by a database system. The storage device and the computing device may be operationally coupled, or may communicate with each other, such as through an I / O port, a network connection, etc., so that the computing device can read instructions stored in the storage device.

[0133] Another embodiment of the present disclosure relates to a computer program product, including a computer program / instruction, which, when executed by a processor, implements any of the above-described multi-core processor-based task scheduling methods.

[0134] According to the multi-core processor-based task scheduling method, device, electronic device, storage medium, system and computer program product provided by the present disclosure, when the idle time of a single processor core is equal to the cumulative idle time of multiple processor cores, the power consumption saving of a single processor core will be greater than the sum of the power consumption saving of multiple processor cores. Therefore, the idle time of multiple cores in a symmetric multi-processing system can be integrated from the level of system task scheduling to keep the idle processor cores in an idle state as much as possible, so that the idle time of the processor cores can be integrated to the greatest extent by improving the operating density of the processor cores without affecting the operating efficiency of the system.

[0135] In addition, unnecessary migration of tasks between different cores can be minimized, and frequent switching of tasks can be avoided to reduce power consumption caused by task switching while ensuring task execution efficiency.

[0136] In addition, from the perspective of task scheduling, conditions are provided for supporting hardware low-power solutions to optimize the power consumption of symmetric multi-processing systems. By comprehensively considering the scheduling parameters of tasks and the hardware characteristics that affect the processor power consumption, low-power task scheduling of symmetric multi-processing systems is proposed for load balancing, and the affinity representation of tasks and processor cores is proposed to determine the optimal scheduling scheme for power consumption optimization by comparing the affinity of each processor core and the task during task scheduling.

[0137] The above describes various exemplary embodiments of the present disclosure, and it should be understood that the above description is only exemplary and not exhaustive, and the present disclosure is not limited to the disclosed exemplary embodiments. Without departing from the scope and spirit of the present disclosure, many modifications and changes are obvious to those of ordinary skill in the art. Therefore, the scope of protection of the present disclosure should be based on the scope of the claims.

Claims

1. A task scheduling method based on a multi-core processor including multiple processor cores, characterized in that: The method comprises: In the event that a task ready event occurs, obtaining a first scheduling parameter, a second scheduling parameter, and a first operating parameter, wherein the first scheduling parameter is a scheduling parameter of a ready task corresponding to the task ready event, the second scheduling parameter is a scheduling parameter of a current task currently running in each of the multiple processor cores in the multi-core processor, and the first operating parameter is an operating parameter of each of the multiple processor cores, and the operating parameter includes a continuous idle time length of each of the multiple processor cores; Based on the first scheduling parameter and the first running parameter, obtaining a ready task affinity between each processor core of the multiple processor cores and the ready task, wherein obtaining the ready task affinity of each processor core includes running the ready task on each processor core, and the ready task affinity indicates a degree of optimization of power consumption when each processor core runs the ready task; Based on the second scheduling parameter and the first operating parameter, obtaining a current task affinity between each processor core of the multiple processor cores and the current task, wherein each processor core runs a corresponding current task or is in an idle state; Selecting at least one processor core from the multi-core processor as at least one candidate processor core, wherein the ready task affinity of the at least one processor core selected as the at least one candidate processor core is higher than the current task affinity; Selecting a processor core having the highest ready task affinity from the at least one candidate processor core as a target processor core; The ready task is scheduled to run on the target processor core.

2. The task scheduling method according to claim 1, characterized in that: The continuous idle time of each processor core is inversely correlated with the affinity of the ready task or the affinity of the current task.

3. The task scheduling method according to claim 1, characterized in that: The operation parameters also include the number of times each processor core switches tasks in the current operation cycle.

4. The task scheduling method according to claim 3, characterized in that: The number of times each processor core switches tasks in the current operation cycle is positively correlated with the ready task affinity or the current task affinity of each processor core.

5. The task scheduling method according to claim 1, characterized in that: The scheduling parameters include at least one of a priority of the task and a waiting time of the task.

6. The task scheduling method according to claim 5, characterized in that: Each of the priority of the ready task or the current task and the waiting time of the ready task or the current task is positively correlated with the affinity of the ready task or the current task, respectively.

7. The task scheduling method according to claim 1, characterized in that: The task scheduling method further includes: When there is no processor core in the multi-core processor whose affinity of the ready task is higher than the affinity of the current task, adding the ready task to the global ready task list; In the event of a time slice exhaustion event, obtaining a second operating parameter, a third scheduling parameter, and a fourth scheduling parameter, wherein the second operating parameter is the current operating parameter of the processor core to be allocated that requests task scheduling, the third scheduling parameter is the scheduling parameter of the task currently running on the processor core to be allocated, and the fourth scheduling parameter is the scheduling parameter of the candidate task, and the candidate task is the task with the highest priority in the global ready task list; Based on the second operating parameter and the third scheduling parameter, obtaining a first affinity of the processor core to be allocated when running the currently running task; Based on the second operating parameter and the fourth scheduling parameter, obtaining a second affinity of the processor core to be assigned when running the candidate task; When the second affinity is higher than the first affinity, the candidate task is scheduled to run on the processor core to be allocated.

8. A task scheduling device based on a multi-core processor including multiple processor cores, characterized in that: The device comprises: A parameter acquisition unit, configured to: acquire, in the event of a task ready event, a first scheduling parameter, a second scheduling parameter, and a first operating parameter, wherein the first scheduling parameter is a scheduling parameter of a ready task corresponding to the task ready event in the multi-core processor, the second scheduling parameter is a scheduling parameter of a current task currently running in each of the multiple processor cores in the multi-core processor, and the first operating parameter is an operating parameter of each of the multiple processor cores, and the operating parameter includes a continuous idle time length of each of the multiple processor cores; The affinity calculation unit is configured as follows: Based on the first scheduling parameter and the first running parameter, obtaining a ready task affinity between each processor core of the multiple processor cores and the ready task, wherein obtaining the ready task affinity of each processor core includes running the ready task on each processor core, and the ready task affinity indicates a degree of optimization of power consumption when each processor core runs the ready task; Based on the second scheduling parameter and the first operating parameter, obtaining a current task affinity between each processor core of the multiple processor cores and the current task, wherein each processor core runs a corresponding current task or is in an idle state; The task scheduling unit is configured as follows: Selecting at least one processor core from the multi-core processor as at least one candidate processor core, wherein the ready task affinity of the at least one processor core selected as the at least one candidate processor core is higher than the current task affinity; Selecting a processor core having the highest ready task affinity from the at least one candidate processor core as a target processor core; The ready task is scheduled to run on the target processor core.

9. An electronic device, characterized in that: include: at least one processor; at least one memory storing computer executable instructions, When the computer executable instructions are executed by the at least one processor, the at least one processor is prompted to execute the task scheduling method based on a multi-core processor including multiple processor cores as described in any one of claims 1 to 7.

10. A computer-readable storage medium storing instructions, characterized in that: When the instruction is executed by at least one processor, the at least one processor is prompted to execute the task scheduling method based on a multi-core processor including multiple processor cores according to any one of claims 1 to 7.

11. A system comprising at least one computing device and at least one storage device storing instructions, characterized in that: When the instructions are executed by the at least one computing device, the at least one computing device is prompted to execute the task scheduling method based on a multi-core processor including multiple processor cores as described in any one of claims 1 to 7.

12. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instruction is executed by the processor, the task scheduling method based on a multi-core processor including multiple processor cores as described in any one of claims 1 to 7 is implemented.

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