A prototype verification method and device, electronic equipment and storage medium

Abstract

Embodiments of the present application provide a prototype verification method and device, electronic equipment and storage medium, the method comprises: when the verification instruction for the to-be-tested chip is acquired, the connection between the to-be-tested chip and the verification chip can be established based on the verification instruction; the verification chip is a chip that has completed prototype verification; when the connection is successful, the to-be-tested chip is subjected to prototype verification based on the verification chip. In this way, by utilizing the reusability of the interface protocol, prototype verification is realized for different interface protocols of the to-be-tested chip under the limitation of fixed hardware connection, the prototype verification completeness of these interface protocols is improved, and a large number of hardware interfaces do not need to be used.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor technology, and in particular to a prototype verification method and device, an electronic device, and a storage medium. BACKGROUND

[0002] A chip is a core component in modern electronic devices, which integrates multiple electronic systems or functions (such as processors, memories, peripheral interfaces, etc.) onto a single chip. In order to enhance the flexibility and scalability of the chip, the chip usually has a rich variety of external interfaces. These interfaces enable the chip to efficiently communicate and exchange data with other chips, modules, or external devices.

[0003] In the verification work of the chip, prototype verification is an important verification link. The chip usually integrates multiple complex interface protocols. The correct implementation of these interface protocols is the basis for the normal operation of the chip. In the prototype verification phase, through strict interface protocol verification, the functional correctness of these protocol interfaces can be ensured, thereby avoiding design iteration and cost increase caused by functional defects found in the later stage.

[0004] Among them, the interface protocol not only requires functional correctness, but also needs to meet certain performance requirements, such as transmission rate, delay, throughput, etc. In the prototype verification phase, by testing and verifying the performance indicators of the interface protocol, it can be ensured that the chip can meet the performance requirements of the system in actual application. In the prototype verification phase, by simulating different application scenarios and test environments, the compatibility of the interface protocol of the chip can be verified to meet the requirements, thereby avoiding compatibility problems in actual application.

[0005] In the prior art, the prototype verification of different interfaces in the chip needs to connect the corresponding interface protocol hardware to complete, as shown in Figure 1 When verifying the interfaces of different protocols of the chip, the corresponding functional modules in the chip need to be controlled to operate the specific external hardware interface, and the judgment of whether the function is verified is made according to the corresponding hardware reaction behavior.

[0006] The disadvantage of this method is that since the external hardware is designed and completed, the connected peripherals are fixed and difficult to change, so it is difficult to verify the reuse of the corresponding chip completely.

[0007] And the fixedness of the external hardware also has a great limitation on the completeness of the verification of the specific protocol. Even with the programmability of the chip in the prototype verification, the connection of different peripherals is expanded by changing the pins to ensure complete verification, which brings huge pin requirements. Because the external hardware is fixed, different pins must be used to meet the requirements of the hardware peripherals required for verification in different scenarios, as shown in Figure 2 .

[0008] But this processing mode needs to occupy a large number of pins, because each change of an interface configuration needs to exclusively connect the corresponding hardware peripheral to support a specific prototype verification scene. The external interface of a chip is highly integrated, and there are often two, three or more multiplexing situations. If each configuration is separately mapped to an independent pin, the demand for pins is very large, and the prototype verification hardware platform is difficult to meet.

[0009] In summary, the prior art cannot guarantee the integrity of the prototype verification of the chip interface, and a large amount of hardware peripheral cost and effort is needed. SUMMARY

[0010] In view of the above problems, the embodiments of the present application are proposed to provide a prototype verification method, device, electronic equipment and storage medium which overcome the above problems or at least partially solve the above problems.

[0011] In a first aspect, the embodiments of the present application disclose a prototype verification method, which comprises:

[0012] obtaining a verification instruction for a to-be-tested chip; the to-be-tested chip comprises at least one group of interfaces, each group of interfaces corresponds to at least one interface protocol; the verification instruction comprises a target interface identifier to be verified and a target interface protocol identifier, the target interface identifier corresponds to an interface belonging to the at least one group of interfaces, and the target interface protocol identifier corresponds to an interface protocol belonging to the at least one interface protocol;

[0013] establishing a connection between the to-be-tested chip and a verification chip based on the verification instruction; the verification chip is a chip that has completed prototype verification, and the verification chip comprises a group of verification interfaces, and the verification interfaces correspond to at least one interface protocol;

[0014] when the connection is successful, performing prototype verification on the to-be-tested chip based on the verification chip.

[0015] Optionally, the step of establishing the connection between the to-be-tested chip and the verification chip based on the verification instruction comprises:

[0016] obtaining the target interface identifier and the target interface protocol identifier from the verification instruction;

[0017] obtaining corresponding target interface configuration information from a preset interface configuration information library based on the target interface identifier;

[0018] obtaining corresponding target interface protocol configuration information from a preset interface protocol configuration information library based on the target interface protocol identifier;

[0019] updating the current configuration of the target interface by using the target interface protocol configuration information to obtain an updated target interface;

[0020] updating a current configuration of the verification interface by using the target interface protocol configuration information, to obtain an updated verification interface;

[0021] establishing a connection between the updated target interface and the updated verification interface based on the target interface protocol.

[0022] Optionally, the type of the at least one interface protocol includes an interface protocol having a master mode and a slave mode.

[0023] Optionally, the width of the at least one group of interfaces is 8 bits.

[0024] Optionally, the method further comprises:

[0025] when the connection fails, generating prompt information indicating that the interface protocol of the verification chip and the chip under test do not match.

[0026] In a second aspect, an embodiment of the present application discloses a prototype verification device, and the device comprises:

[0027] an obtaining module, configured to obtain a verification instruction for a chip under test; the chip under test comprises at least one group of interfaces, each group of interfaces corresponding to at least one interface protocol; the verification instruction comprises a target interface identifier to be verified and a target interface protocol identifier, the target interface identifier corresponding to an interface belonging to the at least one group of interfaces, and the target interface protocol identifier corresponding to an interface protocol belonging to the at least one interface protocol;

[0028] a connecting module, configured to establish a connection between the chip under test and a verification chip based on the verification instruction; the verification chip is a chip that has completed prototype verification, and the verification chip comprises a group of verification interfaces, the verification interfaces corresponding to at least one interface protocol;

[0029] a verifying module, configured to, when the connection is successful, perform prototype verification on the chip under test based on the verification chip.

[0030] In a third aspect, the present application further discloses an electronic device, comprising a processor, a memory, and a computer program stored on the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the steps of the prototype verification method described above.

[0031] In a fourth aspect, the present application further discloses a computer readable storage medium, wherein the computer readable storage medium stores a computer program, and the computer program, when executed by a processor, implements the steps of the prototype verification method described above.

[0032] Embodiments of the present application have the following advantages:

[0033] When the verification instruction for the to-be-tested chip is acquired, the connection between the to-be-tested chip and a verification chip can be established based on the verification instruction; the verification chip is a chip that has completed prototype verification; when the connection is successful, the to-be-tested chip is subjected to prototype verification based on the verification chip. In this way, the reusability of the interface protocol is utilized to implement the prototype verification of different interface protocols of the to-be-tested chip under the limitation of fixed hardware connection, improve the prototype verification completeness of the interface protocols, and meanwhile, a large number of hardware interfaces do not need to be used. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is a structure diagram of prototype verification of different interfaces in the prior art;

[0035] Figure 2 is a structure diagram of prototype verification using different pins in the prior art;

[0036] Figure 3 is a step flowchart of a prototype verification method provided by an embodiment of the present application;

[0037] Figure 4 is a structure diagram of prototype verification provided by an embodiment of the present application;

[0038] Figure 5 is a structure block diagram of an electronic device provided by an embodiment of the present application;

[0039] Figure 6 is a structure block diagram of a computer readable storage medium provided by an embodiment of the present application. DETAILED DESCRIPTION

[0040] In order to make the above objectives, characteristics and advantages of the present application more apparent and easy to understand, the present application is further described in detail below with reference to the drawings and specific embodiments.

[0041] As Figure 3 shown is a step flowchart of a prototype verification method provided by an embodiment of the present application, the object of prototype verification can be a to-be-tested chip, and the topology of prototype verification can be as shown in Figure 4 , wherein the to-be-tested chip is connected with a verification chip, and the verification chip is a chip that has passed prototype verification.

[0042] The to-be-tested chip can include at least one group of interfaces (interfaces A and B are taken as examples in the figure), each group of interfaces corresponds to at least one interface protocol (interfaces A correspond to a first interface protocol and a second interface protocol, and interface B corresponds to a first interface protocol and a third interface protocol, which are taken as examples in the figure), and one group of interfaces adopts one interface protocol when prototype verification is performed, that is, each group of interfaces can reuse multiple interface protocols.

[0043] For example, interface A corresponds to the first interface protocol and the second interface protocol, and interface A can respectively perform prototype verification on the first interface protocol and the second interface protocol. However, interface A uses the first interface protocol or the second interface protocol for each prototype verification, and the two cannot be simultaneously subjected to prototype verification.

[0044] For another example, interface B corresponds to the first interface protocol and the third interface protocol, and interface B can respectively perform prototype verification on the first interface protocol and the third interface protocol. However, interface B uses the first interface protocol or the third interface protocol for each prototype verification, and the two cannot be simultaneously subjected to prototype verification.

[0045] In addition, the interface protocols corresponding to each group of interfaces can be the same or different. For example, interface A corresponds to the first interface protocol, the second interface protocol and the third interface protocol, and interface B can correspond to the first interface protocol, the second interface protocol and the third interface protocol, or can correspond to the first interface protocol and the third interface protocol. That is, in actual application, the interface protocols corresponding to each group of interfaces can be set according to actual requirements, and the embodiments of the present application do not limit this.

[0046] Further, the chip to be tested can further include a processor and a bus, the processor interacts with the bus, the bus interacts with each group of interfaces, each group of interfaces is provided with a multiplexing selection controller for multiplexing selection of the interface protocol currently required for prototype verification of each group of interfaces. The multiplexing selection controller of each group of interfaces is connected with the verification chip, so as to realize data interaction between the chip to be tested and the verification chip.

[0047] The verification chip can include a group of interfaces (for convenience, denoted as "verification interface"), and the verification interface corresponds to at least one interface protocol (for example, the first interface protocol, the second interface protocol and the third interface protocol in the figure). That is, each group of interfaces in the chip to be tested is connected with the verification interface in the verification chip, and each group of interfaces and the verification interface can be set to 8-bit width. In this way, each group of interfaces in the chip to be tested can be subjected to prototype verification through the group of interfaces in the verification chip.

[0048] For example, the chip to be tested includes interface A, interface B and interface C, and interface A, interface B and interface C are all 8-bit width. If the existing prototype verification method is used, corresponding hardware needs to be reserved for interface A, interface B and interface C, that is, 24 hardware edges (i.e. 24-bit width) need to be set to complete prototype verification of interface A, interface B and interface C. In the embodiments of the present application, interface A, interface B and interface C are all connected with the group of interfaces in the verification chip, that is, only 8 hardware edges (i.e. 8-bit width) need to be set to complete prototype verification of interface A, interface B and interface C, which greatly reduces the hardware cost, and the effect is more obvious when there are more interfaces.

[0049] Further, since the to-be-tested chip is connected with the chip which has passed the prototype verification, in the embodiment of the present application, the type of the interface protocol which is subjected to the prototype verification can be the interface protocol with the master mode and the slave mode. For example, when a certain interface protocol is subjected to the prototype verification, the to-be-tested chip can be set as the master mode and the verification chip can be set as the slave mode, or the to-be-tested chip can be set as the slave mode and the verification chip can be set as the master mode. Thus, the prototype verification of the bidirectional function of the interface protocol is realized.

[0050] The method can comprise the following steps:

[0051] In step 301, a verification instruction for the to-be-tested chip is acquired.

[0052] In actual application, the user can initiate the verification instruction for the prototype verification of the to-be-tested chip through an interactive interface. The interactive interface can be a visual interface, a command line window or other interfaces. The form of the interactive interface can be set according to actual demand, and the embodiment of the present application does not limit this.

[0053] The verification instruction comprises a target interface identifier and a target interface protocol identifier. That is, the user can specify the interface (denoted as "target interface") which needs to be subjected to the prototype verification and the interface protocol (denoted as "target interface protocol") which needs to be subjected to the prototype verification through the verification instruction. The identifier of the interface which needs to be subjected to the prototype verification is the target interface identifier, for example, the "interface A" is the target interface identifier. The identifier of the interface protocol which needs to be subjected to the prototype verification is the target interface protocol identifier, for example, the "first interface protocol" is the target interface protocol identifier.

[0054] It should be noted that since the to-be-tested chip and the verification chip have the same multiple groups of interfaces and multiple interface protocols, the target interface belongs to one of the groups of interfaces, and the target interface protocol also belongs to one of the interface protocols, otherwise, the prototype verification of the to-be-tested chip cannot be performed.

[0055] In step 302, the connection between the to-be-tested chip and the verification chip is established based on the verification instruction.

[0056] After the verification instruction is acquired, the target interface and the target interface protocol which need to be subjected to the prototype verification can be determined according to the target interface identifier and the target interface protocol identifier in the verification instruction, and then the connection between the to-be-tested chip and the verification chip is established by using the target interface and the target interface protocol.

[0057] In one embodiment, the connection between the to-be-tested chip and the verification chip is established based on the verification instruction, comprising:

[0058] obtain the target interface identifier and the target interface protocol identifier from the verification instruction;

[0059] obtain corresponding target interface configuration information from a preset interface configuration information library based on the target interface identifier;

[0060] obtain corresponding target interface protocol configuration information from a preset interface protocol configuration information library based on the target interface protocol identifier;

[0061] update the current configuration of the target interface using the target interface protocol configuration information to obtain an updated target interface;

[0062] update the current configuration of the verification interface using the target interface protocol configuration information to obtain an updated verification interface;

[0063] establish a connection between the updated target interface and the updated verification interface based on the target interface protocol.

[0064] Specifically, after obtaining the verification instruction, the target interface identifier and the target interface protocol identifier can be extracted from the verification instruction, and then the target interface protocol identifier is matched with the preset interface configuration information library to determine the interface configuration information (denoted as "target interface configuration information") corresponding to the target interface protocol identifier.

[0065] The interface configuration information library stores the configuration information corresponding to each interface protocol, such as interface protocol configuration information A corresponding to the first interface protocol, interface protocol configuration information B corresponding to the second interface protocol, and interface protocol configuration information C corresponding to the third interface protocol. The configuration information corresponding to any interface protocol can record the interface configuration information of the interface in the chip under test, and the interface configuration information of the interface in the verification chip.

[0066] After obtaining the target interface protocol configuration information, the current configuration of the target interface can be updated using the target interface configuration information to obtain an updated target interface, and the current configuration of the verification interface can be updated using the target interface configuration information to obtain an updated verification interface.

[0067] For example, when prototyping the interface A, the first interface protocol corresponds to the interface protocol configuration information A, and the interface protocol configuration information A records: setting the interface A in the chip under test to host mode and setting the interface in the verification chip to slave mode. After obtaining the interface protocol configuration information A, the interface A in the chip under test can be set to host mode and the interface in the verification chip can be set to slave mode.

[0068] Of course, in addition to setting the master-slave mode, in actual applications, the specific content of the interface protocol configuration information can be set according to actual needs, and the embodiments of the present application do not limit this.

[0069] After the setting is completed, the connection between the updated target interface and the updated verification interface can be established by using the target interface protocol. For example, in the above example, after the interface A in the DUT is set to the host mode and the interface in the verification chip is set to the slave mode, the connection between the interface A in the DUT and the interface in the verification chip can be established by using the first interface protocol.

[0070] In this way, by using the reusability of the interface protocol, the prototype verification of different interface protocols of the DUT under the limitation of fixed hardware connection is realized, the completeness of the prototype verification of these interface protocols is improved, and a large number of hardware interfaces do not need to be used.

[0071] Step 303, when the connection is successful, performing prototype verification on the DUT based on the verification chip.

[0072] When the connection between the updated target interface and the updated verification interface is successfully established by using the target interface protocol, the prototype verification on the target interface and the target interface protocol in the DUT can be performed by using the verification chip.

[0073] In an embodiment, when the connection fails, prompt information that the interface protocols of the verification chip and the DUT do not match is generated.

[0074] Specifically, when the connection between the updated target interface and the updated verification interface fails by using the target interface protocol, it indicates that the interface protocols of the updated target interface and the updated verification interface do not match, which may be that the target interface in the DUT does not configure the corresponding interface protocol, or the interface in the verification chip does not configure the corresponding interface protocol. At this time, prompt information that the interface protocols of the verification chip and the DUT do not match can be generated. In this way, the user can detect and repair the target interface in the DUT and the interface in the verification chip according to the prompt information.

[0075] For the convenience of understanding, the embodiments of the present application take Figure 4 as an example to illustrate the complete flow of the prototype verification. The DUT includes an interface A and an interface B, the interface A corresponds to a first interface protocol and a second interface protocol, the interface B corresponds to the first interface protocol and a third interface protocol, the verification chip includes an interface C, the interface C corresponds to the first interface protocol, the second interface protocol and the third interface protocol. The prototype verification on the interface A and the first interface protocol needs to be performed, and the prototype verification on the interface B and the third interface protocol needs to be performed.

[0076] Firstly, the user can initiate a verification instruction through an interactive interface, and the verification instruction can include the identification of interface A and the identification of the first interface protocol. At this time, the interface configuration information corresponding to the first interface protocol can be obtained according to the identification of the first interface protocol, and then the current configuration of interface A is updated according to the interface configuration information to obtain the updated interface A, and the current configuration of interface C is updated according to the interface configuration information to obtain the updated interface C, and the connection between the updated interface A and the updated interface C is established by using the first interface protocol, and when the connection is successfully established, the updated interface C can be used to prototype the updated interface A.

[0077] Then, the user can initiate a verification instruction through an interactive interface, and the verification instruction can include the identification of interface B and the identification of the third interface protocol. At this time, the interface configuration information corresponding to the third interface protocol can be obtained according to the identification of the third interface protocol, and then the current configuration of interface B is updated according to the interface configuration information to obtain the updated interface B, and the current configuration of interface C is updated according to the interface configuration information to obtain the updated interface C, and the connection between the updated interface B and the updated interface C is established by using the third interface protocol, and when the connection is successfully established, the updated interface C can be used to prototype the updated interface B.

[0078] At this time, the prototype verification of interface A and the first interface protocol, and the prototype verification of interface B and the third interface protocol have been completed.

[0079] In the embodiment of the application, when the verification instruction for the to-be-tested chip is obtained, the connection between the to-be-tested chip and the verification chip can be established based on the verification instruction; the verification chip is a chip that has completed prototype verification; and when the connection is successful, the to-be-tested chip is subjected to prototype verification based on the verification chip. In this way, by using the reusability of the interface protocol, the prototype verification of different interface protocols of the to-be-tested chip is realized under the limitation of fixed hardware connection, the prototype verification completeness of these interface protocols is improved, and a large number of hardware interfaces do not need to be used.

[0080] The application further provides a prototype verification device, which comprises:

[0081] An acquisition module is configured to acquire a verification instruction for a to-be-tested chip; the to-be-tested chip comprises at least one group of interfaces, each group of interfaces corresponds to at least one interface protocol; the verification instruction comprises a target interface identification and a target interface protocol identification to be verified, the target interface identification corresponds to an interface belonging to the at least one group of interfaces, and the target interface protocol identification corresponds to an interface protocol belonging to the at least one interface protocol;

[0082] A connection module is configured to establish a connection between the to-be-tested chip and a verification chip based on the verification instruction, wherein the verification chip is a chip that has completed prototype verification, and the verification chip comprises a set of verification interfaces corresponding to at least one interface protocol;

[0083] A verification module is configured to perform prototype verification on the to-be-tested chip based on the verification chip when the connection is successful.

[0084] In an embodiment, the connection module is specifically configured to:

[0085] obtain the target interface identifier and the target interface protocol identifier from the verification instruction;

[0086] obtain corresponding target interface configuration information from a preset interface configuration information library based on the target interface identifier;

[0087] obtain corresponding target interface protocol configuration information from a preset interface protocol configuration information library based on the target interface protocol identifier;

[0088] update the current configuration of the target interface using the target interface protocol configuration information to obtain an updated target interface;

[0089] update the current configuration of the verification interface using the target interface protocol configuration information to obtain an updated verification interface;

[0090] establish a connection between the updated target interface and the updated verification interface based on the target interface protocol.

[0091] In an embodiment, the type of the at least one interface protocol includes an interface protocol having a host mode and a slave mode.

[0092] In an embodiment, the width of the at least one set of interfaces is 8 bits.

[0093] In an embodiment, the method further comprises:

[0094] A prompt module is configured to generate prompt information indicating that the interface protocol of the verification chip does not match the to-be-tested chip when the connection fails.

[0095] As Figure 5 shown in FIG. 1, an embodiment of the present application provides a structural block diagram of an electronic device 50, which comprises:

[0096] The processor 501, the memory 502, and the computer program 5021 stored in the memory 502 and capable of running on the processor 501, when executed by the processor 501, implement the various processes of the above-mentioned prototype verification method embodiment, and can achieve the same technical effects. To avoid repetition, details are not described here.

[0097] As Figure 6 A structural block diagram of a computer readable storage medium 60 is shown, and a computer program 601 is stored in the computer readable storage medium 60. The computer program 601, when executed by a processor, implements the various processes of the above-mentioned prototype verification method embodiment, and can achieve the same technical effects. To avoid repetition, details are not described here.

[0098] Each embodiment in the specification is described in a progressive manner, and each embodiment focuses on the difference from other embodiments. The same and similar parts between the embodiments can be referred to each other.

[0099] Those skilled in the art should understand that the embodiments of the present embodiment can be provided as a method, device, or computer program product. Therefore, the embodiments of the present embodiment can be in the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the embodiments of the present embodiment can be in the form of a computer program product implemented on one or more computer usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer usable program code.

[0100] The embodiments of the present embodiment are described with reference to the flowcharts and / or block diagrams according to the method, terminal device (system), and computer program product of the present embodiment. It should be understood that each flow and / or block in the flowchart and / or block diagram, and the combination of the flows and / or blocks in the flowchart and / or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to produce a machine, so that the instructions executed by the computer or other programmable data processing terminal device produce a device for implementing the functions specified in the flow Figure 1 The device for implementing the functions specified in one flow or multiple flows and / or blocks Figure 1 The device for implementing the functions specified in one flow or multiple flows and / or blocks

[0101] These computer program instructions can also be stored in a computer readable storage medium that can guide the computer or other programmable data processing terminal device to work in a specific way, so that the instructions stored in the computer readable storage medium produce a manufactured product including instruction devices that implement the functions specified in the flow Figure 1 The device for implementing the functions specified in one flow or multiple flows and / or blocksFigure 1 the function specified in the one or more blocks.

[0102] These computer program instructions can also be loaded into a computer or other programmable data processing terminal device, so that a series of operational steps are performed on the computer or other programmable terminal device to generate a computer-implemented process, thus the instructions executed on the computer or other programmable terminal device provide a process for implementing the flowchart Figure 1 the flowchart or flowcharts and / or a block Figure 1 the steps of the function specified in the one or more blocks.

[0103] Although the preferred embodiments of the present application have been described, those skilled in the art will be able to make additional changes and modifications to these embodiments once they grasp the fundamental inventive concept. Therefore, the appended claims are intended to cover all changes and modifications falling within the scope of the embodiments of the present application.

[0104] Finally, it should be noted that, in the present text, relational terms such as first and second and the like can merely be used to distinguish one entity or action from another, without necessarily requiring or implying any such actual relationship or order between or among the entities or actions. Also, the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, so that a process, method, article, or terminal device that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or terminal device. Without more limitations, an element defined by the statement "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or terminal device that includes the element.

[0105] The above provides a detailed introduction to the prototype verification method, device, electronic equipment and storage medium provided by the present application. The principles and implementation manners of the present application are described by applying specific examples in the present text. The above description of the embodiments is only used to help understand the method of the present application and its core idea; at the same time, for those skilled in the art, according to the idea of the present application, there will be changes in the specific implementation manners and application ranges; in view of the above, the content of the present description should not be understood as a limitation of the present application.

Claims

1. A prototype verification method, characterized in that, The method includes: Obtain verification instructions for the chip under test; the chip under test includes at least one set of interfaces, each set of interfaces corresponding to at least one interface protocol; the verification instructions include a target interface identifier and a target interface protocol identifier to be verified, each interface is provided with a multiplexing selection controller, used to select the interface protocol that needs to be prototype verified for each set of interfaces, the multiplexing selection controller of the interface is connected to the verification chip, used to realize data interaction between the chip under test and the verification chip, the interface corresponding to the target interface identifier belongs to the at least one set of interfaces, and the interface protocol corresponding to the target interface protocol identifier belongs to the at least one interface protocol; A connection is established between the chip under test and the verification chip based on the verification command; the verification chip is a chip that has completed prototype verification, and the verification chip includes a set of verification interfaces, each verification interface corresponding to at least one interface protocol; When the connection is successful, prototype verification of the chip under test is performed based on the verification chip.

2. The prototype verification method according to claim 1, characterized in that, The process of establishing a connection between the chip under test and the verification chip based on the verification command includes: Obtain the target interface identifier and the target interface protocol identifier from the verification command; Based on the target interface identifier, obtain the corresponding target interface configuration information from the preset interface configuration information database; Based on the target interface protocol identifier, the corresponding target interface protocol configuration information is obtained from the preset interface protocol configuration information database; The current configuration of the target interface is updated using the target interface protocol configuration information to obtain the updated target interface; The current configuration of the verification interface is updated using the target interface protocol configuration information to obtain the updated verification interface; A connection is established between the updated target interface and the updated verification interface based on the target interface protocol.

3. The prototype verification method according to claim 2, characterized in that, The type of the at least one interface protocol includes interface protocols with host mode and slave mode.

4. The prototype verification method according to claim 2, characterized in that, The width of at least one set of interfaces is 8 bits.

5. The prototype verification method according to claim 1, characterized in that, Also includes: When the connection fails, a prompt message is generated indicating that the interface protocol of the verification chip and the chip under test is incompatible.

6. A prototype verification device, characterized in that, The device includes: An acquisition module is used to acquire verification instructions for the chip under test; the chip under test includes at least one set of interfaces, each set of interfaces corresponding to at least one interface protocol; the verification instructions include a target interface identifier and a target interface protocol identifier to be verified, each interface is provided with a multiplexing selection controller, used to select the interface protocol that needs to be prototype verified for each set of interfaces, the multiplexing selection controller of the interface is connected to the verification chip, used to realize data interaction between the chip under test and the verification chip, the interface corresponding to the target interface identifier belongs to the at least one set of interfaces, and the interface protocol corresponding to the target interface protocol identifier belongs to the at least one interface protocol; A connection module is used to establish a connection between the chip under test and the verification chip based on the verification command; the verification chip is a chip that has completed prototype verification, and the verification chip includes a set of verification interfaces, each verification interface corresponding to at least one interface protocol; The verification module is used to perform prototype verification of the chip under test based on the verification chip when the connection is successful.

7. The prototype verification device according to claim 6, characterized in that, The chip under test includes at least one set of interfaces, each set of interfaces corresponds to at least one interface protocol, and the verification instruction includes a target interface identifier and a target interface protocol identifier to be verified; the verification chip includes a set of verification interfaces, each verification interface corresponds to at least one interface protocol; the interface corresponding to the target interface identifier belongs to the at least one set of interfaces, and the interface protocol corresponding to the target interface protocol identifier belongs to the at least one interface protocol. The connection module is specifically used for: Obtain the target interface identifier and the target interface protocol identifier from the verification command; Based on the target interface identifier, obtain the corresponding target interface configuration information from the preset interface configuration information database; Based on the target interface protocol identifier, the corresponding target interface protocol configuration information is obtained from the preset interface protocol configuration information database; The current configuration of the target interface is updated using the target interface protocol configuration information to obtain the updated target interface; The current configuration of the verification interface is updated using the target interface protocol configuration information to obtain the updated verification interface; A connection is established between the updated target interface and the updated verification interface based on the target interface protocol.

8. The prototype verification device according to claim 7, characterized in that, The type of the at least one interface protocol includes interface protocols with host mode and slave mode.

9. An electronic device, characterized in that, include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein the computer program, when executed by the processor, implements the steps of the prototype verification method as described in any one of claims 1-5.

10. A computer-readable storage medium, characterized in that, A computer program is stored on the computer-readable storage medium, which, when executed by a processor, implements the steps of the prototype verification method as described in any one of claims 1-5.

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