Automatic integration method and device for system-on-chip design

Abstract

The invention discloses an automatic integration method and device for system-on-chip design. The method comprises the following steps: carrying out interface packaging on each IP module by adopting a signal group as an interface, and generating a corresponding interface packaging file; constructing a system hierarchical structure file for describing a system hierarchical structure relationship and module composition; performing information extraction on the system hierarchical structure file and the interface packaging file by adopting automatic integration software, and performing automatic instantiation and interface connection on the system hierarchical structure and an IP module to generate a system Verilog code file; and after the Verilog code file is subjected to preliminary verification, a final system Verilog code file is output. According to the integration method, the efficiency of system design and the accuracy and standardization of system integration are improved, and the interface packaging of the IP module has reusability and can be repeatedly used in SoC system integration of different projects.

Description

Technical Field

[0001] The present invention relates to an automated integration method for system-level chip design, and also relates to a corresponding automated integration device, belonging to the technical field of chip design. Background Art

[0002] System-on-chip or System on Chip is referred to as SoC. SoC design includes the whole process of determining system functions, software and hardware module design, system integration, packaging and testing. In the SoC design process, integrating various Verilog IP modules is a very important key link, which usually involves a large number of integration operations in multiple steps, such as interface configuration, module connection and functional verification. Especially in some large and complex SoC designs, such as CPU, GPU, communication chips, projects that require fast iterative design or systems with high reliability requirements, the integration operation of a large number of Verilog IP modules in SoC is more cumbersome.

[0003] In the existing SoC design, the integration of each Verilog IP module mainly relies on manual operation. First, it is necessary to extract the system hierarchy and module interface information from the design document, and then manually instantiate each module according to the design requirements, and connect these modules together according to the design requirements to form a complete SoC system. In addition, it is necessary to manually verify the correctness of the interface connection through a simulation tool, and then manually modify it if a problem is found. This manual integration operation method is not only time-consuming and inefficient, but also very easy to introduce errors. In addition, since different operators may use different naming rules and configuration methods, inconsistencies in the design are caused, which not only increases the complexity of verification, but also may cause problems in subsequent maintenance, especially when dealing with complex SoC designs. The above problems are more prominent. Therefore, how to avoid the above problems and provide an automated integration method for SoC design to meet the high efficiency, high reliability and standardization requirements of system integration has always been a very important technical research topic in this field.

[0004] In the Chinese patent application with application number 202110945596.2, a SoC integration method is disclosed. The method includes: when receiving an IP file set, generating a corresponding configuration file set according to the IP file set; generating a corresponding port information file set according to the configuration file set; generating an SoC top-level file and an IP top-level file set according to the port information file set, and integrating the corresponding SoC system according to the SoC top-level file and the IP top-level file set. Summary of the invention

[0005] The primary technical problem to be solved by the present invention is to provide an automated integration method for system-level chip design.

[0006] Another technical problem to be solved by the present invention is to provide an automated integrated device for system-on-chip design.

[0007] In order to achieve the above object, the present invention adopts the following technical solutions:

[0008] According to a first aspect of an embodiment of the present invention, there is provided an automated integration method for system-on-chip design, comprising the following steps:

[0009] (1) Using the signal group as the interface to perform interface encapsulation on each IP module, and generating a corresponding interface encapsulation file; wherein the process includes the following sub-steps:

[0010] (11) dividing the multiple scattered signals of each IP module into one or more signal groups, defining the signal groups, and generating corresponding signal group definition files;

[0011] (12) performing interface encapsulation on each IP module according to the signal group and the signal group definition file, and generating the corresponding interface encapsulation file;

[0012] (2) Construct a system hierarchy file to describe the system hierarchy relationship and module composition;

[0013] (3) extracting information from the system hierarchical structure file using automated integration software to obtain the system hierarchical structure relationship and the module composition of each level;

[0014] (4) Based on the system hierarchical structure relationship and the interface encapsulation file of the IP module, the automated integration software is used to automatically instantiate and interface the system hierarchical structure and the IP module, and generate a Verilog code file after system integration; wherein the following sub-steps are included:

[0015] (41) reading the interface encapsulation file of the IP module to obtain interface information of each IP module;

[0016] (42) starting from the bottom of the system hierarchy tree and in a bottom-up order, instantiating modules in each system hierarchy structure and generating corresponding Verilog code files according to the system hierarchy structure relationship and module composition;

[0017] (43) performing interface connection on the IP modules in each system hierarchy structure according to the system hierarchy structure relationship and the interface information of the IP modules, and generating corresponding Verilog code files;

[0018] (5) Using the automated integration software to perform preliminary verification on the Verilog code file after system integration, and outputting the system Verilog code file after the preliminary verification passes.

[0019] Preferably, in step (11), when the multiple scattered signals of the IP module are divided into one or more signal groups, the division principle includes:

[0020] First, the signal groups are divided based on the protocol standards specified in the industry;

[0021] Secondly, the signal groups are divided based on the interface standards customized within the team.

[0022] Preferably, in step (11), the signal group definition file includes relevant information of all signals in the signal group, and the relevant information includes at least signal name, direction and bit width.

[0023] Preferably, in step (12), the interface encapsulation file includes instantiation description information of each interface of the IP module, wherein each interface instantiation name adopts a unified format.

[0024] Preferably, the unified format of each interface instantiation name in the interface encapsulation file is: the protocol name corresponding to the interface is used as a prefix, and the attributes of the host or slave of the interface is used as a suffix.

[0025] Preferably, in step (2), the system hierarchy file is in a unified table format, and the main fields of the table include at least module name, subsystem, and peripheral name; wherein,

[0026] The description content of one row of the table represents the composition relationship of the subsystem and its modules: the module name column is the actual name of the IP module, the peripheral name column is the instantiation module name corresponding to the IP module, and the subsystem column is the name of the subsystem where the instantiation module is located.

[0027] Preferably, in step (43), the interface connection of the IP modules in each system hierarchy structure includes the following sub-steps:

[0028] (431) Select a system hierarchy structure at the bottom of the system hierarchy tree as a start;

[0029] (432) Interface connection is performed on the current system hierarchy structure, specifically including:

[0030] First, the IP modules identify and connect interfaces through the prefix and suffix of the interface instance name in the interface encapsulation file;

[0031] Secondly, if there is an unconnected interface, it is directly led to the port of the current system hierarchy structure;

[0032] Next, determine whether the current system hierarchy structure is the topmost layer in the system hierarchy tree, if so, proceed to step (434), if not, proceed to the next step;

[0033] (433) Jump to the previous system hierarchy structure and determine the interface connection status of the subsystem included in the current system hierarchy structure:

[0034] If there is a subsystem that has not been interfaced, jump to the subsystem and proceed to step (432) to interface the subsystem;

[0035] If there is no subsystem that has not been interfaced, then under the current system hierarchy structure, the process proceeds to step (432) to perform interface connection on the current system hierarchy structure;

[0036] (434) The connection is completed and the corresponding Verilog code file is generated.

[0037] Preferably, the automated integration software is written in Python and is used to parse the signal group definition file, the interface encapsulation file and the system hierarchy file to obtain the module interface and corresponding signals, module connection relationships and system topology information to automatically complete system integration.

[0038] Preferably, in step (5), the items of the preliminary verification include signal type, signal bit width, and input and output direction.

[0039] According to a second aspect of an embodiment of the present invention, there is provided an automated integration device for system-on-chip design, comprising a processor and a memory, wherein the processor and the memory are coupled; wherein the memory is used to store a computer program; and the processor is used to run the computer program stored in the memory to execute the automated integration method for system-on-chip design.

[0040] Compared with the prior art, the automated integration method for system-level chip design provided by the present invention first performs interface encapsulation of IP modules and constructs system hierarchical structure files based on basic design documents respectively, then uses automated integration software tools to extract relevant information by parsing each design document file, and automatically instantiates and interfaces the system hierarchical structure and IP modules, generates a Verilog code file after system integration, and finally outputs the system Verilog code file after preliminary verification. The automated integration method improves system design efficiency, system integration accuracy and standardization, and the interface encapsulation of the IP module is reusable, and the module encapsulation can be reused in SoC system integration of different projects, further improving the efficiency of related SoC system integration, and solving the problems of inefficiency, inconsistent standards, easy errors, and non-reusability caused by manual integration methods. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] Figure 1 A flow chart of an automated integration method for system-on-chip design provided by the present invention;

[0042] Figure 2 A schematic diagram of dividing dispersed signals of an IP module into signal groups in an embodiment of the present invention;

[0043] Figure 3 A schematic diagram of a connection method between signal groups between IP modules in an embodiment of the present invention;

[0044] Figure 4 A schematic diagram of a system hierarchical structure relationship in an embodiment of the present invention;

[0045] Figure 5 A schematic diagram of the connection sequence of IP module interfaces in multiple hierarchical structures in an embodiment of the present invention;

[0046] Figure 6 A schematic diagram of an automated integrated device for system-on-chip design provided by the present invention. DETAILED DESCRIPTION

[0047] The technical content of the present invention is described in detail below with reference to the accompanying drawings and specific embodiments.

[0048] Verilog IP module, hereinafter referred to as IP (Intellectual Property) module, refers to a hardware function module that has been designed and can be repeatedly called based on the open source hardware description language Verilog. The present invention proposes a method for automatically integrating IP modules to form a SoC system based on a design document, by parsing the design document, extracting the interface information and connection information of each module, automatically instantiating each module, and connecting each module according to predefined integration rules, and checking the connection relationship, and finally generating the Verilog code corresponding to the SoC system required by the design document.

[0049] like Figure 1 As shown, an automated integration method for system-on-chip design provided by an embodiment of the present invention includes the following steps:

[0050] S1: Use the signal group as the interface to encapsulate each IP module and generate the corresponding interface encapsulation file.

[0051] In a SoC system, each IP module has multiple input / output signals. In the integration method of the prior art, IP modules are connected through a scalar or vector signal. Although this method is direct, it is labor-intensive and difficult to reuse in different SoC systems. There are a large number of signal interfaces with standardized protocols in the SoC system, such as CHI, AXI, AHB, APB, etc. Therefore, in an embodiment of the present invention, a unified file format is first used to package scattered signals serving the same function into a signal group, and use it as an interface of the IP module to improve the abstraction level and facilitate recognition and processing by software tools. The IP module is encapsulated using a signal group as an interface, which specifically includes the following sub-steps:

[0052] S11: Divide the multiple scattered signals of each IP module into one or more signal groups, define the signal groups, and generate corresponding signal group definition files.

[0053] When dividing multiple scattered signals of an IP module into signal groups, the following principles are mainly followed:

[0054] First, grouping is based on industry-standard protocol standards, such as CHI, AXI, AHB, APB, etc. Second, grouping is based on the interface standards customized by the team, such as DMA module request interface, interrupt interface, low-power control interface, etc. According to the above principles, all interface types that are repeatedly used need to be divided and packaged into signal groups to improve integration efficiency.

[0055] like Figure 2As shown, IP module A has multiple input / output signals, which are grouped to form four signal groups (i.e., interfaces), namely, signal group 1, signal group 2, signal group 3, and signal group 4. After defining each signal group, a corresponding signal group definition file is generated, and the signal group definition file contains relevant information of all signals in the signal group.

[0056] The naming of the signal group definition file (i.e., the definition of Inteface) is divided according to the functional protocol corresponding to the signal, and the file name adopts a unified format. In this embodiment, taking the UART interface as an example, the UART protocol stipulates that four signals, RXD, TXD, CTS, and RTS, are required to implement the UART function. The four signals are packaged into a signal group as an interface, and the signal group definition file generated by defining the signal group is uart_interface.itf, and the specific content is as follows:

[0057] interface_name UART{

[0058] -port RXD-direction fromSlave-size 1

[0059] -port TXD-direction fromMaster-size 1

[0060] -port CTS-direction fromSlave-size 1

[0061] -port RTS-interface fromMaster-size 1

[0062] }

[0063] Among them, "interface_name" specifies the interface name as UART; the "{}" braces describe the composition of the interface. The composition signal description of the interface includes the name, direction and bit width information of the four signals RXD, TXD, CTS and RTS. For example, in the first line, "-portRXD" specifies the specific signal name, "-direction" specifies the signal direction, and "-Size 1" specifies the bit width of the signal as 1.

[0064] For another example, for the APB bus, ARM stipulates that the protocol consists of PSEL, PADDR, PWDATA, PRDATA, PWRITE and other signals. These signals are packaged into a signal group as an interface. The signal group definition file generated by defining the signal group is apb_interface.itf. The specific content is as follows:

[0065] interface_name APB{

[0066] -port PSEL-direction fromMaster-size 1

[0067] -port PADDR-direction fromMaster-size 32

[0068] -port PWDATA-direction fromMaster-size 32

[0069] -port PRDATA-interface fromSlave-size 32 .....

[0071] }

[0072] S12: performing interface encapsulation on each IP module according to the signal group and the signal group definition file, and generating a corresponding interface encapsulation file.

[0073] The interface encapsulation of the IP module is to encapsulate and instantiate the interface signal. The specific process is to describe the correspondence between the interface signal of the IP module and the signal in the signal group in the interface encapsulation file. The interface encapsulation file includes the instantiation description information of each interface of the IP module. When encapsulating the IP module interface, according to different interface protocol definitions, each interface instantiation name adopts a unified format, with the interface corresponding protocol name as the prefix and the host or slave attribute of the interface as the suffix. In this embodiment, taking the interface encapsulation of the apb_uart IP module as an example, the generated interface encapsulation file is apb_uart.packet, and the specific content is as follows:

[0074]

[0075] Among them, "current_design" specifies the interface encapsulation of the IP module apb_uart; the {} braces contain the instantiation of each interface of the IP module. For example, in the first paragraph, "uart_master" uses the UARTinterface described in 8.1 to package the module UART communication related signals, thereby completing the interface encapsulation instantiation of the IP dispersed signal. It should be noted that the naming of the interface instantiation name "uart_master" should comply with the unified format, with the interface corresponding protocol as the instantiation name prefix such as "uart_", and the host or slave attribute of the interface as the suffix such as "_master". The naming rule of the interface instantiation is to facilitate the automatic connection during subsequent integration. The automation software will connect the Master and Slave with the same interface function at the same system level. For another example, in the second paragraph, "apb_slave" is the encapsulation instantiation of the APB bus related signals. The naming rule of the interface instantiation name "apb_slave" is the same as the above "uart_master".

[0076] After the interface is encapsulated, the IP module has three different categories of document files, namely IP design code files, signal group definition files and interface encapsulation files.

[0077] Step S1 is to divide the multiple signals of each IP module into one or more signal groups, that is, to bind multiple signals together to form an interface, so that in the system integration process, Figure 3 As shown in the figure, the original signal-to-signal connection between modules is converted into the signal group-to-signal connection between modules. This method redefines the original module port (signal level) through the signal group definition file without affecting the original circuit design (RTL level).

[0078] Improving the abstraction level and realizing port connection at a higher dimension (signal group level) greatly reduces the workload of system integration and is a basis for completing the automated integration of the SoC system in this embodiment. At the same time, the method has the feature of reusability. Each IP module only needs to be packaged once, and the module package can be reused in SoCs of different projects.

[0079] The content description and file naming of the above signal group definition file and interface encapsulation file adopt a unified format, which can reflect the connection relationship of the interface and facilitate the automatic connection of the subsequent integration software. The interface encapsulation method is universal and applicable to different types of interfaces, including but not limited to USB, DDR, AHB bus, etc.

[0080] S2: Build a system hierarchy file to describe the system hierarchy relationship and module composition.

[0081] In the prior art, the system hierarchy structure is mostly built with the help of manual or graphical interface tools, and the later system integration work still needs to be manually integrated according to the system hierarchy block diagram, which requires a large amount of manual work and takes a long time. Therefore, the embodiment of the present invention adopts a unified table method, by describing the system hierarchy relationship and module composition in the table, so that the system hierarchy information can be extracted by automated integration software tools in the later stage, and the system hierarchy relationship required for system design can be formed. Finally, the instantiation and signal connection of IP modules in each level are realized through automated integration software tools. Compared with the method of using pictures to describe the system hierarchy structure, the difficulty of writing subsequent software scripts is greatly reduced, and work efficiency is improved.

[0082] In this embodiment, as shown in Table 1, the main fields of the table in the system hierarchy file (i.e., the names of the columns) include at least module name, subsystem, and peripheral name; wherein each row describes the composition relationship between a subsystem and its modules, or the hierarchical relationship between a subsystem and its upper-level subsystem. For example, in one row of the table, the "module name" column contains the actual name (module name) of the IP module; the "peripheral name" column contains the instantiation name corresponding to the IP module, and the "subsystem" column contains the subsystem name where the peripheral (i.e., the peripheral referred to by the instantiation name) is located. When in a row of the table, both the "peripheral name" column and the "subsystem" column contain subsystem names, it indicates the hierarchical relationship between the two subsystems. It should be noted that in the system hierarchy tree, a subsystem represents one of the system hierarchy structures or the next system hierarchy structure of the current system hierarchy structure.

[0083] For example, in the last row of Table 1, the name of the peripheral instantiated by the IP module apb_uart is UART1, and the subsystem it belongs to is APB2; subsystem APB2 belongs to the subsystem of AHB1, subsystem AHB1 belongs to the subsystem of LDO_CORE, and subsystem LDO_CORE belongs to the subsystem of the top-level LDO_TOP of the system. The system hierarchy structure is fully described in the above table, and the system hierarchy structure file is used as the carrier of the system hierarchy structure information for subsequent extraction of the system hierarchy structure information through automated integration software tools. The main fields of the table in the system hierarchy structure file can also include relevant information such as the start address, end address, interface connection, clock gating, and soft reset as needed.

[0084] Table 1 System hierarchy file (Example 1)

[0085]

[0086] The above system hierarchical structure file adopts a unified system description format, which can reflect the hierarchical structure and module composition of the system, and facilitate the subsequent extraction of system hierarchical structure information through integrated software. It should be noted that the names of each subsystem cannot be the same as those of other peripherals to avoid information parsing errors; the description information of the "module name" in the table has nothing to do with the system hierarchical structure, and it describes the actual IP module name used by the system design module (instantiated module).

[0087] S3: Use automated integration software to extract information from the system hierarchical structure file to obtain the system hierarchical structure relationship and the module composition of each level.

[0088] In one embodiment of the present invention, it is assumed that the constructed system hierarchy file is as shown in Table 2, wherein the main fields of the table include module name, subsystem and peripheral name.

[0089] Table 2 System hierarchy file (Example 2)

[0090] Peripheral Name Subsystem Module Name FMC AXI axi_fmc XSPI1 AXI axi_xspi XSPI2 AXI axi_xspi SRAM1X AXI ahb_sramc SRAM1H AHB ahb_sramc SRAM2H AHB ahb_sramc GPIOB APB apb_gpio GPIOA APB apb_gpio AXI TOP # AHB TOP # APB TOP #

[0091] In Table 2, the first four rows describe that peripheral modules FMC, XSPI1, XSPI2 and SRAM1X all belong to subsystem AXI; the fifth and sixth rows describe that peripheral modules SRAM1H and SRAM2H belong to subsystem AHB; the seventh and eighth rows describe that peripheral modules GPIOA and GPIOB belong to subsystem APB; the ninth to eleventh rows describe that subsystems AXI, AHB and APB are all top-level subsystems of the system; the system hierarchy file comprehensively describes the system hierarchy relationship and the module composition of each level.

[0092] The automation integration software is a self-written special software program that can recognize the system hierarchy description and interface description in a unified format document. The automation integration software tool first reads the system hierarchy file, automatically obtains the system hierarchy relationship and the module composition information of each level, and parses the architecture of each system hierarchy and the relationship between modules. Figure 4 As shown in the figure, in the system hierarchy relationship obtained after parsing, the top level of the system TOP includes subsystems AXI, AHB and APB. Subsystem AXI includes peripheral modules FMC, XSPI1, XSPI2 and SRAM1X. Subsystem AHB includes peripheral modules SRAM1H and SRAM2H. Subsystem APB includes peripheral modules GPIOA and GPIOB. By comparison, it can be seen that Figure 4 The system hierarchy relationship shown is completely one-to-one corresponding to the system hierarchy described in Table 2.

[0093] S4: Based on the system hierarchy relationship and the interface encapsulation file of the IP module, the automated integration software is used to automatically instantiate and interface the system hierarchy and IP module, and generate the Verilog code file after system integration. Specifically, it includes the following sub-steps:

[0094] S41: Read the interface encapsulation file of the IP module to obtain the interface information of each IP module.

[0095] The interface encapsulation file of the IP module, including the associated signal group definition file, is read through the automated integration software tool to obtain the interface information of each IP module, including the interface type and quantity, so as to facilitate subsequent automated connection.

[0096] In one embodiment of the present invention, the automated integration software tool can be written in Python, which parses the signal group definition file (e.g., uart_interface.itf), the interface encapsulation file (e.g., apb_uart.packet), and the system hierarchy file to obtain information such as the module interface and the corresponding signal, the module connection relationship, and the system topology structure, and instantiates and interfaces the IP modules and subsystems in a bottom-up order, and generates a Verilog code file at the same time.

[0097] S42: Based on the system hierarchy relationship and module composition, starting from the bottom of the system hierarchy tree, in a bottom-up order, instantiate the modules in each system hierarchy structure and generate corresponding Verilog code files.

[0098] For example: for the system hierarchy relationship shown in Table 1, first instantiate the module of the lowest level system hierarchy structure APB2 and generate the corresponding Verilog code file; then instantiate the module of the upper level system hierarchy structure AHB1 and generate the corresponding Verilog code file; then follow the bottom-up order → LDO_CORE → LDO_TOP, instantiate the modules and generate the Verilog code files for each level in turn.

[0099] S43: According to the system hierarchy relationship and the interface information of the IP module, the IP modules in each system hierarchy are interfaced and a corresponding Verilog code file is generated. The interface connection of the IP modules in each system hierarchy specifically includes the following sub-steps:

[0100] S431: Select a system hierarchy structure at the bottom of the system hierarchy tree as a start.

[0101] S432: Perform interface connection on the current system hierarchy structure;

[0102] First, the IP modules identify and connect interfaces through the prefix and suffix of the interface instance name in the interface encapsulation file; second, if there is an unconnected interface, it is directly connected to the port of the current system hierarchy structure; third, it is determined whether the current system hierarchy structure is the top level in the system hierarchy tree. If so, go to step S434, if not, go to the next step.

[0103] For example, after using apb interface to encapsulate and instantiate the apb bus related signals of the apb_uart module, the interface instantiation name is apb_slave, indicating that the interface is the slave type of the APB bus. When connecting the interface, the automation integration software automatically connects apb_slave to the module with apb master.

[0104] S433: Jump to the previous system hierarchy structure and determine the interface connection status of the subsystem included in the current system hierarchy structure;

[0105] If there is a subsystem that has not been interfaced, after jumping to the subsystem, the process goes to step S432 to perform interface connection on the subsystem;

[0106] If there is no subsystem that has not been interfaced, then under the current system hierarchy structure, the process proceeds to step S432 to perform interface connection on the current system hierarchy structure;

[0107] S434: The connection is completed and the corresponding Verilog code file is generated.

[0108] In this embodiment, Figure 5 A simple system hierarchy structure is shown as an example to illustrate the interface connection method and process in step S43. In the system hierarchy tree, system hierarchy structures APB1 and APB2 are subsystems of system hierarchy structure APB; system hierarchy structures AXI, AHB and APB are all subsystems of the top level TOP. Figure 5 In the figure, the numbers in brackets in the box of each system hierarchy structure indicate the order of interface connection of the hierarchy structure; the numbers in the arrows between two system hierarchy structures indicate the jump order between the hierarchy structures during the connection process.

[0109] Step S431 first selects the bottom-level system hierarchy structure APB1 in the system hierarchy tree as the start, and connects the IP module interface in the system hierarchy structure APB1 according to the method of step S432. After the connection is completed, jump to the upper-level system hierarchy structure APB according to step S433. At this time, the system hierarchy structure APB is used as the current system hierarchy structure. It is found through judgment that there is a subsystem APB2 that has not been interfaced. Therefore, after jumping to the subsystem APB2, go to step S432 to connect the subsystem APB2 with an interface; then jump to the upper-level system hierarchy structure APB. At this time, it is found through judgment that there is no subsystem that has not been interfaced. Therefore, on the system hierarchy structure APB, go to step S432 to connect the system hierarchy structure APB with an interface; after the connection is completed, jump to the upper-level system hierarchy structure TOP, and then and so on, in the order of →AHB→TOP→AXI→TOP, interface each system hierarchy structure in turn, until the interface connection of all system hierarchy structures in the system hierarchy tree is completed.

[0110] Step S4 is to use an automated integration software tool to automatically identify the system description and interface description in the design document, automatically instantiate and interface the IP module, and complete the automated integration of the SoC system. In the above automated integration process, firstly, the modules are instantiated and interfaced in each hierarchical structure to generate the Verilog code of each hierarchical subsystem; secondly, the subsystems of each hierarchical structure are instantiated and interconnected to generate the Verilog code file after the entire SoC system is integrated.

[0111] It should be noted that in the IP module interface connection of step S43, the interface level pre-connection is first performed to form a topology diagram for the designer to confirm and adjust. When the designer confirms that the interface level connection is correct, the automated integration software extracts the specific signals in each interface, performs signal level connection, and generates the corresponding Verilog code.

[0112] S5: Use automated integration software to perform preliminary verification on the Verilog code file after system integration, and output the system Verilog code file after the preliminary verification passes.

[0113] The items to be verified mainly include signal type, signal width, input and output direction, etc., to verify whether they match the design. Through preliminary verification, it is ensured that the interface connections of all modules are correct, and finally the verified system Verilog code files are output, which provides important technical support for the subsequent physical design and product production of SoC systems.

[0114] The above describes in detail the operation steps of an automated integration method for system-on-chip design provided by an embodiment of the present invention. The automated integration method first uses a signal group as an interface to perform interface encapsulation on each IP module, and generates a corresponding interface encapsulation file; secondly, a system hierarchical structure file is constructed to describe the system hierarchical structure relationship and module composition. Then, an automated integration software tool is used to extract relevant information by parsing each design document file, automatically instantiate and interface the system hierarchical structure and IP modules, and generate a Verilog code file after system integration, and finally output the system Verilog code file after preliminary verification. During the integration process, the automated integration method reduces human intervention and reduces the risk of errors in manual operation through unified interface encapsulation, naming rules and system description format, so that the accuracy of system integration is improved. At the same time, the automated integration software tool is used to realize the rapid integration and connection of the system hierarchical structure and IP modules, reduce manual operation, and significantly improve the efficiency of design and verification. In addition, through standardized processes and tools, the consistency of operations between different designers is ensured, thereby improving the maintainability and long-term reliability of the design. For the increasingly large-scale SoC chip design and system integration, the high efficiency, high accuracy and standardization of this automated integration method are particularly significant and important. In addition, the interface packaging of the IP module is reusable, and the module packaging can be reused in the SoC system integration of different projects, further improving the efficiency of related SoC system integration.

[0115] Based on the above-mentioned automated integration method for system-level chip design, the embodiment of the present invention further provides an automated integration device for system-level chip design. Figure 6 As shown, the automated integration device includes one or more processors and a memory, wherein the memory is coupled to the processor and is used to store one or more computer programs, and when the computer programs are executed by the processor, the processor implements the automated integration method for system-level chip design in the above embodiment.

[0116] Among them, the processor is used to control the overall operation of the automation integration device to complete all or part of the steps of the automation integration method of the above-mentioned system-level chip design. The processor module can be a central processing unit (CPU), a graphics processing unit (GPU), a field programmable gate array (FPGA), an application-specific integrated circuit (ASIC), a digital signal processing (DSP) chip, etc. The memory is used to store various types of data to support operations on the automation integration device, and these data may include, for example, instructions for any application or method for operating the automation integration device, and application-related data. The memory module can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as a static random access memory (SRAM), an electrically erasable programmable read-only memory (EEPROM), an erasable programmable read-only memory (EPROM), a programmable read-only memory (PROM), a read-only memory (ROM), a magnetic memory, a flash memory, etc.

[0117] In summary, compared with the prior art, the automated integration method for system-level chip design provided by the present invention first performs interface encapsulation of IP modules and constructs system hierarchical structure files based on basic design documents, then uses automated integration software tools to extract relevant information by parsing each design document file, and automatically instantiates and interfaces the system hierarchical structure and IP modules, generates a Verilog code file after system integration, and finally outputs the system Verilog code file after preliminary verification. The automated integration method improves the efficiency of system design, the accuracy and standardization of system integration, and the interface encapsulation of the IP module is reusable, and the module encapsulation can be reused in the SoC system integration of different projects, further improving the efficiency of related SoC system integration. It solves the problems of inefficiency, inconsistent standards, easy errors, and non-reusability caused by manual integration methods.

[0118] It should be noted that the above multiple embodiments are only examples. The technical solutions of the various embodiments can be combined, all within the protection scope of the present invention. In addition, in the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically limited.

[0119] The above is a detailed description of the automated integrated method and device for system-level chip design provided by the present invention. For those skilled in the art, any obvious changes made to it without departing from the essence of the present invention will constitute an infringement of the patent right of the present invention and will bear corresponding legal responsibilities.

Claims

1. An automated integration method for system-level chip design, characterized in that The steps include: (1) Using the signal group as the interface to perform interface encapsulation on each IP module, and generating a corresponding interface encapsulation file; wherein the process includes the following sub-steps: (11) dividing the multiple scattered signals of each IP module into one or more signal groups, defining the signal groups, and generating corresponding signal group definition files; (12) performing interface encapsulation on each IP module according to the signal group and the signal group definition file, and generating the corresponding interface encapsulation file; (2) Construct a system hierarchy file to describe the system hierarchy relationship and module composition; (3) extracting information from the system hierarchical structure file using automated integration software to obtain the system hierarchical structure relationship and the module composition of each level; (4) Based on the system hierarchical structure relationship and the interface encapsulation file of the IP module, the automated integration software is used to automatically instantiate and interface the system hierarchical structure and the IP module, and generate a Verilog code file after system integration; wherein the following sub-steps are included: (41) reading the interface encapsulation file of the IP module to obtain interface information of each IP module; (42) starting from the bottom of the system hierarchy tree and in a bottom-up order, instantiating modules in each system hierarchy structure and generating corresponding Verilog code files according to the system hierarchy structure relationship and module composition; (43) performing interface connection on the IP modules in each system hierarchy structure according to the system hierarchy structure relationship and the interface information of the IP modules, and generating corresponding Verilog code files; (5) Using the automated integration software to perform preliminary verification on the Verilog code file after system integration, and outputting the system Verilog code file after the preliminary verification passes.

2. The automated integration method for system-on-chip design as claimed in claim 1, characterized in that In step (11), when the multiple scattered signals of the IP module are divided into one or more signal groups, the division principles include: First, the signal groups are divided based on the protocol standards specified in the industry; Secondly, the signal groups are divided based on the interface standards customized within the team.

3. The automated integration method for system-on-chip design as claimed in claim 1, characterized in that In step (11), the signal group definition file includes relevant information of all signals in the signal group, and the relevant information includes at least signal name, direction and bit width.

4. The automated integration method for system-on-chip design as claimed in claim 1, characterized in that In step (12), the interface encapsulation file includes instantiation description information of each interface of the IP module, wherein each interface instantiation name adopts a unified format.

5. The automated integration method for system-on-chip design as claimed in claim 4, characterized in that: The unified format of each interface instantiation name in the interface encapsulation file is: the protocol name corresponding to the interface is used as a prefix, and the host or slave attribute of the interface is used as a suffix.

6. The automated integration method for system-on-chip design as claimed in claim 1, characterized in that In step (2), the system hierarchy file adopts a unified table format, and the main fields of the table include at least module name, subsystem, and peripheral name; wherein, The description content of one row of the table represents the composition relationship of the subsystem and its modules: the module name column is the actual name of the IP module, the peripheral name column is the instantiation module name corresponding to the IP module, and the subsystem column is the name of the subsystem where the instantiation module is located.

7. The automated integration method for system-on-chip design as claimed in claim 1, characterized in that In step (43), the interface connection of the IP modules in each system hierarchy structure includes the following sub-steps: (431) Select a system hierarchy structure at the bottom of the system hierarchy tree as a start; (432) Interface connection is performed on the current system hierarchy structure, specifically including: First, the IP modules identify and connect interfaces through the prefix and suffix of the interface instance name in the interface encapsulation file; Secondly, if there is an unconnected interface, it is directly led to the port of the current system hierarchy structure; Next, determine whether the current system hierarchy structure is the topmost layer in the system hierarchy tree, if so, proceed to step (434), if not, proceed to the next step; (433) Jump to the previous system hierarchy structure and determine the interface connection status of the subsystem included in the current system hierarchy structure: If there is a subsystem that has not been interfaced, jump to the subsystem and proceed to step (432) to interface the subsystem; If there is no subsystem that has not been interfaced, then under the current system hierarchy structure, the process proceeds to step (432) to perform interface connection on the current system hierarchy structure; (434) The connection is completed and the corresponding Verilog code file is generated.

8. The automated integration method for system-on-chip design as claimed in claim 1, characterized in that: The automated integration software is written in Python and is used to parse the signal group definition file, the interface encapsulation file and the system hierarchy file to obtain the module interface and corresponding signals, module connection relationships and system topology information to automatically complete system integration.

9. The automated integration method for system-on-chip design as claimed in claim 1, characterized in that In step (5), the items of the preliminary verification of the row include signal type, signal bit width, and input and output direction.

10. An automated integrated device for system-level chip design, characterized in that It comprises a processor and a memory, wherein the processor and the memory are coupled; wherein the memory is used to store a computer program; and the processor is used to run the computer program stored in the memory to execute the automated integration method for system-level chip design as claimed in any one of claims 1 to 9.

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