Joint verification method, device and equipment of usart and dma, and medium

Abstract

This invention relates to a joint verification method, apparatus, device, and medium for USART and DMA. The method is applied to a verification platform including verification environment components and a design under test (DUT). The DUT includes a memory, multiple DMAs, and multiple USARTs. The method includes: reading first data to be transmitted from the memory via a first DMA, and transmitting the first data to a first USART via a pre-configured first channel in the first DMA; establishing a transmission connection between the first USART and a second USART via the verification environment components to transmit second data to the second USART; transmitting the second data from the second USART to the second DMA via a second channel, so that the second DMA writes the second data into the memory; and comparing the first and second data via the verification environment components to generate a verification result. This method achieves joint verification of USART and DMA, improving verification efficiency while ensuring the correctness and stability of the verification.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, apparatus, device, and medium for joint verification of USART and DMA. Background Technology

[0002] With the continuous advancement of semiconductor technology and the increasing complexity of integrated circuits, system-level verification has become a crucial step in ensuring the correctness and stability of digital systems. In digital systems, Universal Synchronous / Asynchronous Receiver / Transmitter (USART) and Direct Memory Access (DMA) are two important functional modules. USART handles serial data communication, supporting both synchronous and asynchronous communication modes, and is widely used in various communication interfaces. DMA enables rapid data transfer between memory and external devices without the involvement of the Central Processing Unit (CPU), significantly improving system data transfer efficiency.

[0003] In system-level verification, traditional verification methods are often unable to meet the verification requirements of complex systems. Therefore, there is an urgent need to provide a verification method that can perform joint verification of USART and DMA at the system level, verifying the functionality of each module in USART and DMA as well as the interaction between USART and DMA. Summary of the Invention

[0004] To address the aforementioned technical problems, this disclosure provides a method, apparatus, device, and medium for joint verification of USART and DMA.

[0005] In a first aspect, embodiments of this disclosure provide a joint verification method using USART and DMA, applied to a verification platform including verification environment components and a design under test, wherein the design under test includes memory, multiple DMAs, and multiple USARTs, and the method includes:

[0006] The first data to be sent is read from the memory through the first DMA of multiple DMAs, and the first data is transmitted to the first USART of multiple USARTs based on the first channel pre-configured for data transmission in the first DMA.

[0007] A transmission connection is established between a first USART and a second USART among a plurality of USARTs using a verification environment component, so as to transmit the second data to the second USART; wherein the second data is obtained based on the first data;

[0008] The second data in the second USART is transmitted to the second DMA among multiple DMAs via the second channel, so that the second DMA writes the second data into memory; wherein, the second channel is a pre-configured channel in the second DMA for data reception;

[0009] The verification environment component compares the first and second data to generate verification results.

[0010] The verification environment component includes an interface component and a driver component. The interface component predefines multiple interfaces, which are connected to multiple corresponding ports. These ports refer to multiple USART ports. The multiple interfaces include a transmit interface and a receive interface. The driver component is used to connect the transmit interface and the receive interface.

[0011] Optionally, a transmission connection is established between the first USART and a second USART among multiple USARTs using the verification environment component, including:

[0012] A transmission connection between a first transmitting interface and a first receiving interface is established using a driver component; wherein, the first transmitting interface corresponds to the first transmitting port of a first USART, and the first receiving interface corresponds to the first receiving port of a second USART among multiple USARTs, and the multiple interfaces include the first transmitting interface and the first receiving interface.

[0013] Optionally, establishing a transmission connection between the first transmitting interface and the first receiving interface using a driver component includes:

[0014] The verification requirements reflect the verification functionality and / or the timing of verification.

[0015] The target time for establishing a transmission connection between the first transmitting interface and the first receiving interface is determined based on the verification requirements.

[0016] The driver component is used to establish a transmission connection between the first transmitting interface and the first receiving interface at the target time.

[0017] Optionally, before reading the first data to be transmitted from memory via the first DMA of a plurality of DMAs, the method further includes:

[0018] Register configuration is performed on multiple DMAs such that multiple channels for data transmission included in at least one of the multiple DMAs are connected to at least one of the multiple USARTs for transmission; wherein the register configuration includes at least one setting of channel selection, transmission direction, transmission mode and data width;

[0019] Configure the memory for read / write operations so that data can be written to and read from the memory in a preset language.

[0020] Optionally, the validation environment components include monitoring components, a reference model, and a scoreboard component. These components compare the first and second data to generate validation results, including:

[0021] The monitoring component receives second data read from memory using a preset language and transmits it to the scoreboard component as actual data.

[0022] The configuration file is read from the reference model and transmitted to the scoreboard component as expected data. The configuration file is generated by extracting stimulus data in a preset language. The configuration file includes register configuration and first data obtained by writing the stimulus data into memory.

[0023] The scoreboard component compares the actual data with the expected data to generate verification results.

[0024] Optionally, before reading the first data to be transmitted from memory via the first DMA of a plurality of DMAs, the method further includes:

[0025] Verification combinations are configured between multiple DMAs and multiple USARTs according to verification requirements to perform joint verification of USARTs and DMAs under the verification combinations; wherein, the verification combinations include the first combination, the second combination, the third combination, and the fourth combination, wherein:

[0026] The first combination refers to the first DMA and the second DMA being the same DMA, and the first USART and the second USART being different USARTs;

[0027] The second combination refers to the first DMA and the second DMA being the same DMA, and the first USART and the second USART being the same USART;

[0028] The third combination refers to the first DMA and the second DMA being different DMAs, and the first USART and the second USART being different USARTs;

[0029] The fourth combination refers to the first DMA and the second DMA being different DMAs, and the first USART and the second USART being the same USART.

[0030] Optionally, when multiple DMAs need to read data from memory and / or write data to memory, the method further includes:

[0031] Obtain the pre-defined first priority of each DMA among multiple DMAs;

[0032] Reading the first data to be sent from memory through the first DMA of multiple DMAs includes:

[0033] First data is read from memory according to a first priority via the first DMA;

[0034] The second DMA writes the second data into memory, including:

[0035] The second DMA writes the second data into the memory according to the first priority.

[0036] Optionally, the first DMA includes multiple pre-configured transmission channels for data transmission. When the first DMA transmits data to at least two USARTs through the multiple transmission channels, transmitting the first data to the first USART among the multiple USARTs based on the pre-configured first channel for data transmission in the first DMA includes:

[0037] Obtain the pre-set second priority of each of the multiple transmission channels;

[0038] According to the second priority, the first data is transmitted to the first USART based on the first channel; wherein, multiple transmission channels include the first channel, and at least two USARTs include the first USART.

[0039] Optionally, the second DMA includes multiple receive channels. When at least two USARTs need to transmit data to the second DMA through multiple receive channels, the second data in the second USART is transmitted to the second DMA among the multiple DMAs based on the second channel, including:

[0040] Obtain the pre-set third priority of each of the multiple receiving channels;

[0041] According to the third priority, the second data belonging to the second USART is transmitted to the second DMA based on the second channel; wherein, multiple receive channels include the second channel, and at least two USARTs include the second USART.

[0042] Secondly, embodiments of this disclosure provide a joint verification apparatus for USART and DMA, applied to a verification platform including verification environment components and a design under test, wherein the design under test includes memory, multiple DMAs, and multiple USARTs, and the apparatus includes:

[0043] The first transmission unit is used to read the first data to be transmitted from the memory through the first DMA among multiple DMAs, and to transmit the first data to the first USART among multiple USARTs based on the first channel pre-configured for data transmission in the first DMA.

[0044] A connection establishment unit is used to establish a transmission connection between a first USART and a second USART among a plurality of USARTs using a verification environment component, so as to transmit the second data to the second USART; wherein the second data is obtained based on the first data;

[0045] The second transmission unit is used to transmit the second data in the second USART to the second DMA among multiple DMAs based on the second channel, so that the second DMA writes the second data into its memory; wherein, the second channel is a pre-configured channel in the second DMA for data reception;

[0046] The verification unit is used to compare the first data and the second data through the verification environment components and generate verification results.

[0047] Thirdly, embodiments of this disclosure provide an electronic device, including:

[0048] Memory;

[0049] Processor; and

[0050] Computer programs;

[0051] The computer program is stored in memory and configured to be executed by a processor to implement the method described in the first aspect above.

[0052] Fourthly, embodiments of this disclosure provide a computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the steps of the method as described in the first aspect.

[0053] The joint verification method of USART and DMA disclosed herein is applied to a verification platform including verification environment components and a design under test. The design under test includes memory, multiple DMAs, and multiple USARTs. The method includes: reading first data to be transmitted from memory through a first DMA among the multiple DMAs, and transmitting the first data to a first USART among the multiple USARTs based on a pre-configured first channel for data transmission in the first DMA; establishing a transmission connection between the first USART and a second USART among the multiple USARTs using the verification environment components to transmit second data to the second USART; wherein the second data is obtained based on the first data; transmitting the second data from the second USART to the second DMA among the multiple DMAs based on a second channel, so that the second DMA writes the second data into memory; wherein the second channel is a pre-configured channel for data reception in the second DMA; and comparing the first data and the second data through the verification environment components to generate a verification result. The method provided in this application performs joint verification of multiple USARTs and multiple DMAs at the system level, ensuring the correctness and stability of system-level verification while also improving verification efficiency. Attached Figure Description

[0054] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure.

[0055] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, for those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0056] Figure 1 This is a schematic diagram of the structure of a conventional verification system provided in an embodiment of the present disclosure;

[0057] Figure 2 A flowchart illustrating a joint verification method using USART and DMA provided in this embodiment of the disclosure;

[0058] Figure 3 This is a schematic diagram of the structure of a verification platform provided in an embodiment of the present disclosure;

[0059] Figure 4 A schematic diagram of the structure of a joint verification device for USART and DMA provided in an embodiment of this disclosure;

[0060] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0061] To better understand the above-mentioned objectives, features, and advantages of this disclosure, the solutions disclosed herein will be further described below. It should be noted that, unless otherwise specified, the embodiments and features described herein can be combined with each other.

[0062] Numerous specific details are set forth in the following description in order to provide a full understanding of this disclosure, but this disclosure may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only some, and not all, of the embodiments of this disclosure.

[0063] Specifically, system-level verification aims to ensure the simultaneous and efficient operation of multiple USARTs and DMAs. However, system-level verification is complex. Specifically, with the rapid development of integrated circuit (IC) technology and the increasing demand for complex digital systems in fields such as digital communication, the integration scale and functional complexity of chips are growing exponentially. An integrated circuit is a miniature electronic device that integrates multiple electronic components (such as transistors, resistors, and capacitors) and their interconnections onto a small semiconductor substrate. In actual chip operation, there are scenarios where multiple USARTs and multiple DMAs jointly transmit data. To cover the functionalities of these scenarios, system-level verification becomes extremely complex. Therefore, an efficient and comprehensive verification method is needed to ensure the correctness and stability of system-level verification. Furthermore, traditional verification methods for system-level verification have limitations. Specifically, traditional verification methods, such as those based on directional testing, suffer from poor reusability and low verification efficiency. When jointly verifying multiple USARTs and multiple DMAs at the system level, multiple slave or master devices corresponding to the USARTs are needed to receive data from the USARTs or drive data acquired from the DMAs and transmit it to the USARTs. This traditional verification structure makes the overall system-level verification framework more complex. The timing of stimulus-driven and detection events during joint verification becomes more difficult to control. Furthermore, the presence of multiple master / slave machines during verification debugging makes it difficult to quickly locate the problem, thus reducing verification efficiency. For an example, see... Figure 1 , Figure 1 This is a schematic diagram of the structure of a conventional verification system provided in an embodiment of this disclosure, such as... Figure 1The traditional structure shown involves the master driver acquiring data from the DMA, for example, driving stimulus data into waveforms according to timing and sending them to the USART. The slave monitors the data received from the USART, for example, reconstructing the received waveforms into data according to timing. However, the timing of driving and monitoring during master / slave joint verification is difficult to control. The slave scoring board uses the data monitored by the slave as the actual data and the data extracted from the slave reference model according to the configuration file as the expected data, comparing the actual data and the expected data to determine the correctness and stability of the design under test. Correspondingly, the master reference model uses the data driven by the master as the expected data, and the master scoring board uses the data received from the design under test as the actual data, comparing the actual data and the expected data to determine the correctness and stability of the design under test. This master / slave verification makes the verification structure more complex. In addition, multiple USARTs may correspond to multiple masters / slaves. During verification and debugging, the presence of multiple masters / slaves makes it difficult to quickly locate the problematic component, thus reducing verification efficiency.

[0064] In summary, existing system-level verification methods have the following problems:

[0065] (1) Mismatch between technical complexity and verification requirements

[0066] With the increasing demand for verification, it is difficult to perform joint simulation of multiple modules (multiple USARTs and multiple DMAs) at the system level. Existing verification methods may not be able to fully cover all possible test scenarios, resulting in insufficient verification completeness.

[0067] (2) Difficulty in building and debugging the verification environment

[0068] System-level verification involves multiple modules and components (such as...) Figure 1 The interaction between the proxy components, scoreboards, and reference models (such as those in the system) and the construction and debugging of the verification environment require a lot of time and resources, resulting in low efficiency in building the verification environment and the possibility of hard-to-detect errors, which affects the accuracy of verification.

[0069] To address the aforementioned technical problems, this disclosure provides a joint verification method for USART and DMA, constructing a verification platform based on the Universal Verification Methodology (UVM). Leveraging the component-based structure of UVM, multiple USARTs and multiple DMAs are combined for overall functional verification, aligning with real-world application scenarios and covering more functionalities, thereby improving the completeness of system-level joint verification of multiple USARTs and multiple DMAs. Secondly, as... Figure 1The existing methods described require the host driver to convert data into waveforms based on timing, and the slave monitoring system to reconstruct the waveforms back into data based on timing. Therefore, if both the host and slave systems are built, timing issues between them must be considered. This application eliminates the need to build a host / slave system in the verification platform, thus avoiding the need for additional attention to timing issues during the driver or monitoring process. This facilitates the construction and debugging of the verification environment, reducing its complexity and cost. The general verification methodology, as an advanced verification method, aims to provide a unified framework and best practices to improve the efficiency, reusability, and scalability of hardware verification. This will be described in detail through one or more of the following embodiments.

[0070] The joint verification method for USART and DMA provided in this disclosure is applicable to scenarios where USART and DMA are used for system-level verification. This method can be executed by a joint verification device for USART and DMA, which can be implemented in software and / or hardware and integrated into an electronic device. The electronic device can include, but is not limited to, mobile terminals such as smartphones, laptops, digital radio receivers, personal digital assistants (PDAs), tablet PCs, PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable devices, etc., as well as fixed terminals such as digital televisions, desktop computers, smart home devices, etc.

[0071] Figure 2 This is a flowchart illustrating a joint verification method using USART and DMA provided in an embodiment of the present disclosure. The method is applied to a verification platform that includes verification environment components and a design under test, wherein the design under test includes a memory, multiple DMAs, and multiple USARTs.

[0072] For example, see Figure 3 , Figure 3 This disclosure provides a schematic diagram of the structure of a verification platform, as shown in the embodiments below. Figure 3 As shown, the verification platform includes environment components and the design under test (hereinafter referred to as the design under test). The environment components include proxy components, a reference model, and a scoreboard component. These environment components also refer to the verification platform components. The proxy components include monitoring components, driver components, and interface components. The design under test includes memory, multiple DMAs, and multiple USARTs. The memory can be static random access memory, such as... Figure 3As shown, multiple DMAs include DMA0 to DMA3, where 0-3 refer to numbers. Multiple USARTs include USART0 to USART7, where 0-7 also refer to numbers. Each DMA includes multiple channels. DMAs can establish transmission connections with any USART and memory through multiple channels. For example, DMA0 establishes a transmission connection with USART0 through channels 0 and 1, and establishes a transmission connection with USART1 through channels 2 and 3.

[0073] Specifically, the joint verification method of USART and DMA includes the following steps:

[0074] S201. Read the first data to be sent from the memory through the first DMA of the multiple DMAs, and transmit the first data to the first USART of the multiple USARTs based on the first channel pre-configured for data transmission in the first DMA.

[0075] Understandably, based on the verification requirements, a first DMA to be verified is determined from multiple DMAs, and a first USART to be verified is determined from multiple USARTs. Subsequently, the first data to be transmitted is read from memory via the first DMA. This first data is stimulus data written to the corresponding address in memory using a preset language. The stimulus data related to the verification requirements can be written to the corresponding address in memory before joint verification, so that the DMA can directly read the data to be transmitted; this data is the first data. After reading the first data, the first data is transmitted to the first USART based on a pre-configured first channel in the first DMA for data transmission with the first USART. Each DMA includes multiple channels, each channel can transmit data with at least one USART, and only one channel of the DMA can transmit data with either memory or the USART at a time. Figure 3 As shown, the first DMA is DMA0, the first channel is channel 0, and the first USART is USART0. One transmission path is that DMA0 will transmit the first data read from the memory to USART0 through channel 0.

[0076] Optionally, before reading the first data to be transmitted from memory via the first DMA of a plurality of DMAs, the method further includes:

[0077] The registers of multiple DMAs are configured such that at least one of the DMAs includes multiple channels for data transmission that are connected to at least one of the multiple USARTs; wherein the register configuration includes at least one setting of channel selection, transmission direction, transmission mode and data width; and the memory is configured to be read and written so that the memory can be written to and read from the memory in a preset language.

[0078] Understandably, before joint verification, register configuration is performed on multiple DMAs to establish transmission connections between multiple channels and multiple USARTs within the DMAs. For example, the first channel in the first DMA is configured to establish a transmission connection with the first USART, and the second channel in the second DMA is configured to establish a transmission connection with the second USART. Register configuration includes at least one of channel selection, transmission direction, transmission mode, and data width. Channel selection refers to selecting a specific channel to establish a transmission connection with the USART, and transmission direction refers to whether the data is sent or received by the DMA. Read / write configuration can also be performed on the memory. This configuration allows reading data from and writing data to memory using a preset language, such as C. For example, stimulus data can be written to the corresponding address of the static random access memory (SRAM) in the design under test (DUT) using C. The stimulus data will then be transferred to the USART via the DMA and transmitted based on the transmit path. Similarly, data received by the USART will be transferred to the corresponding address of the SRAM in the DUT via the DMA via the receive path, and then read using C.

[0079] Understandably, one possible transmission path is: DMA acquires the data written to memory by C language, transmits it to USART through the channel, and then sends it out through USART; another possible reception path is: after receiving the waveform, USART stores it in its receive data register, and stores the data of the waveform reconstruction into memory through the DMA channel, which can then be read through C language.

[0080] S202. Establish a transmission connection between the first USART and the second USART among multiple USARTs using the verification environment component, so as to transmit the second data to the second USART.

[0081] The second data is obtained based on the first data.

[0082] Understandably, based on the above S201, a transmission connection is established between the first USART and the second USART using the verification environment component, so that the first USART can transmit the second data to the second USART. Here, the first USART refers to a USART that receives the first data from the first DMA, and the second USART refers to a USART that receives the second data from the first USART. Specifically, the second USART can be determined from multiple USARTs according to the verification requirements. The second data can be understood as the waveform of the first data. The first USART transmits the waveform of the first data to the second USART. Subsequently, the second USART will restore the waveform to data according to the timing and transmit it to the second DMA. The timing between the first USART and the second USART can be synchronized by the verification component. Furthermore, the first USART and the second USART can be the same USART or different USARTs. For example, the verification requirement is to verify the transmission function between two USARTs. Alternatively, the first USART and the second USART can be the same USART, for example, the verification requirement is to verify the transmission function between a certain USART and the DMA.

[0083] The verification environment component includes an interface component and a driver component. The interface component predefines multiple interfaces, which are connected to multiple corresponding ports. The multiple ports refer to the ports of multiple USARTs. The multiple interfaces include a transmit interface and a receive interface. The driver component is used to connect the transmit interface and the receive interface.

[0084] Understandably, the verification environment components include interface components and driver components. The interface component contains the interface signal definitions for all USARTs. These interface signals are used to connect the port signals of at least one USART in the design under test. Specifically, the interface component predefines multiple interfaces. Each USART has ports, and multiple USARTs have multiple ports. These ports are connected one-to-one with their corresponding interfaces; that is, the interface component defines the interface signals and the port signals for one-to-one connection. The multiple interfaces include transmit and receive interfaces, and the multiple ports include transmit and receive ports. The transmit port of a USART is connected to the transmit interface defined for that USART in the interface component. Simultaneously, the transmit interface is connected to the receive interface defined for another USART or the USART itself in the interface component, thus establishing a transmission connection between that USART and another USART or between the USART itself. Figure 3As shown, the USART0 transmit port (0 is the USART number; in the case of multiple USARTs, a numeric suffix is ​​used for its number) and the USART0 transmit interface defined in the interface component are connected through interface signals and port signals. The USART0 transmit interface is connected through the driver component and the USART1 receive port defined in the interface component.

[0085] Understandably, driver components do not need to be like... Figure 1 The host driver module in the traditional structure shown focuses on specific data transmission timing (data transmission timing is used to convert data into waveforms and to restore waveforms back to data). Its main function is to connect the sending interface and receiving port defined in the interface component. For example... Figure 1 As shown, the transmit interface signal of USART1 is connected to the receive interface signal of USART0.

[0086] Optionally, the establishment of a transmission connection between the first USART and the second USART among multiple USARTs in S202 above using the verification environment component can be achieved through the following steps:

[0087] A transmission connection between a first transmitting interface and a first receiving interface is established using a driver component; wherein, the first transmitting interface corresponds to the first transmitting port of a first USART, and the first receiving interface corresponds to the first receiving port of a second USART among multiple USARTs, and the multiple interfaces include the first transmitting interface and the first receiving interface.

[0088] Understandably, the interface component defines a first transmit interface for a first USART, which is connected to the first transmit port of the first USART. The interface component also defines a first receive interface for a second USART, which is connected to the first receive port of the second USART. Based on this definition, the driver component connects the first transmit interface and the first receive interface. The aforementioned multiple interfaces include the first transmit interface and the first receive interface, and the aforementioned multiple ports include the first transmit port and the first receive port. Furthermore, if the first USART and the second USART are the same USART, then the first transmit interface and the first receive interface are both interfaces of the same USART defined in the interface component; similarly, the first transmit port and the first receive port are two ports of the same USART. Other possible interfaces and the USART to which the ports belong are not limited.

[0089] Optionally, the above-mentioned establishment of a transmission connection between the first transmitting interface and the first receiving interface using the driver component can be achieved through the following steps:

[0090] The system acquires the verification requirements that reflect the verification function and / or the verification timing; determines the target time for establishing a transmission connection between the first transmitting interface and the first receiving interface based on the verification requirements; and uses the driver component to establish a transmission connection between the first transmitting interface and the first receiving interface at the target time.

[0091] Understandably, the verification requirements are obtained, reflecting the verification function and / or verification timing. For example, the verification function refers to verifying the transmission function between two USARTs, and the verification timing refers to when the driver component connects the transmit and receive interfaces. For instance, the driver component might connect the transmit and receive interfaces after one minute, meaning an appropriate delay can be added. Subsequently, based on the verification timing, the connection timing for the first transmit and first receive interfaces is selected, determining the specific connection time, which is the target time. Then, at the target time, the driver component establishes the transmission connection between the first transmit and first receive interfaces; that is, the connection timing can be selected or an appropriate delay can be added based on the verification requirements.

[0092] Optionally, when multiple DMAs need to read data from memory and / or write data to memory, the method further includes:

[0093] Obtain the first priority preset for each of the multiple DMAs.

[0094] Understandably, there is a pre-defined first priority among multiple DMAs, which characterizes the order in which each DMA reads data from and writes data to memory. For example... Figure 3 As shown, DMA0 has a higher priority than DMA1. At any given time, if both DMA0 and DMA1 need to write data to the memory, then the write order of DMA0 must be before that of DMA1.

[0095] Optionally, the first data to be sent can be read from the memory through the first DMA of multiple DMAs, which can be achieved through the following steps:

[0096] First data is read from memory using the first DMA with the first priority.

[0097] Understandably, if the first DMA has a higher priority than the other DMAs, and all DMAs need to read data from memory, the first DMA will prioritize reading the first data from memory. Scenarios where multiple DMAs need to write data to memory will not be discussed further here.

[0098] Optionally, the first DMA includes multiple pre-configured transmission channels for data transmission. When the first DMA transmits data to at least two USARTs through the multiple transmission channels, the first data is transmitted to the first USART among the multiple USARTs based on the first channel pre-configured for data transmission in the first DMA. This can be achieved through the following steps:

[0099] Obtain the second priority preset for each of the multiple transmission channels; transmit the first data to the first USART based on the first channel according to the second priority; wherein the multiple transmission channels include the first channel, and at least two USARTs include the first USART.

[0100] Understandably, in the first DMA, multiple transmission channels for data transmission are pre-configured via registers, such as... Figure 3 The DMA0 shown is configured with channels 0 and 2 for transmission. When the first DMA transmits data to at least two USARTs through multiple transmit channels, and the first DMA can only use one channel to transmit data to the USART at a time, a pre-set priority is determined for each transmit channel. The channel with the highest priority is prioritized for transmitting data to the USART. If the priority of the first channel is higher than the other transmit channels, the first data is transmitted to the first USART primarily based on the first channel. Figure 3 As shown, DMA0 needs to send data to USART0 using channel 0, and at the same time, it also needs to send data to USART1 using channel 2. In this case, the priorities of channel 0 and channel 2 are compared, and the channel with higher priority sends data to its corresponding USART first.

[0101] S203. The second data in the second USART is transmitted to the second DMA of the multiple DMAs based on the second channel, so that the second DMA writes the second data into the memory.

[0102] The second channel is a pre-configured channel in the second DMA for data reception.

[0103] Understandably, based on the above S202, according to the verification requirements, the second DMA corresponding to the second USART is determined from multiple DMAs as the second DMA is selected. The second DMA and the first DMA can be the same DMA or different DMAs. After determining the second DMA, the second data in the second USART is transmitted to the second DMA based on the pre-configured second channel for data reception within the second DMA. If the first USART and the second USART are different, the second channel will... Figure 3 Channel 3 in DMA0 is shown. Subsequently, the second DMA writes the second data into memory, as shown... Figure 3As shown, DMA0 writes the second data (received data) into the static random access memory.

[0104] Optionally, the second DMA writes the second data into memory, which can be achieved through the following steps:

[0105] The second DMA writes the second data into the memory according to the first priority.

[0106] Understandably, when multiple DMAs need to write their received data to memory, the write order of the multiple DMAs is determined according to the priority of each DMA. For the second DMA, the second data is written to the memory based on the write order determined by the first priority of the second DMA.

[0107] Optionally, the second DMA includes multiple receive channels. When at least two USARTs need to transmit data to the second DMA through multiple receive channels, the second data in the second USART is transmitted to the second DMA among the multiple DMAs based on the second channel. This can be achieved through the following steps:

[0108] Obtain the third priority preset for each of the multiple receiving channels; according to the third priority, transmit the second data belonging to the second USART to the second DMA based on the second channel; wherein the multiple receiving channels include the second channel, and at least two USARTs include the second USART.

[0109] Understandably, the second DMA includes multiple receive channels, each with a pre-set third priority. When at least two USARTs need to transmit data through multiple receive channels, the transmission order is set according to the third priority of each receive channel, and based on this transmission order, the second data is transmitted to the second DMA using the second channel among the multiple receive channels. For example... Figure 3 As shown, the second DMA is DMA0. Channel 1 needs to transmit data from USART0, while channel 3 needs to transmit data from USART1. In this case, the priority of channel 1 and channel 3 is determined, and the channel with the higher priority transmits data first. Additionally, when at least two USARTs need to transmit data through the same receive channel, the transmission order is set according to the priority of each USART. Other possible methods for setting the transmission order based on priority are not limited and can be configured according to user needs.

[0110] Optionally, before reading the first data to be transmitted from memory via the first DMA of a plurality of DMAs, the method further includes:

[0111] Verification combinations are set up between multiple DMAs and multiple USARTs according to verification requirements to perform joint verification of USARTs and DMAs under the verification combination. The verification combinations include the first combination, the second combination, the third combination, and the fourth combination. The first combination means that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are different USARTs. The second combination means that the first DMA and the second DMA are the same DMA, and the first USART and the second USART are the same USART. The third combination means that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are different USARTs. The fourth combination means that the first DMA and the second DMA are different DMAs, and the first USART and the second USART are the same USART.

[0112] Understandably, based on verification requirements, the specific USART and DMA used for verification can be determined from multiple USARTs and multiple DMAs. There are various verification combinations between specific DMAs and specific USARTs. These verification combinations include the first, second, third, and fourth combinations. The first combination refers to a situation where the first DMA and the second DMA are the same DMA, and the first USART and the second USART are different USARTs; that is, a combination of one DMA and multiple USARTs, such as... Figure 3 The transmission path shown is as follows: the first DMA and the second DMA are DMA0, the first USART is USART0, and the second USART is USART1. Data transfer between USART0 and USART1 is implemented based on DMA0. The second combination refers to the first DMA and the second DMA being the same DMA, and the first USART and the second USART also being the same USART, i.e., a combination of one DMA and one USART, such as implementing data transfer between DMA1 and USART2. This combination is used for self-loopback testing. The third combination refers to the first DMA and the second DMA being different DMAs, and the first USART and the second USART also being different USARTs, i.e., a combination of multiple DMAs and multiple USARTs, such as implementing data transfer between DMA2, DMA3, USART4, and USART6. The fourth combination refers to the first DMA and the second DMA being different DMAs, and the first USART and the second USART being the same USART, i.e., a combination of multiple DMAs and one USART, such as implementing data transfer between DMA2, USART4, and USART6. Other combinations are not limited. In practice, this is also the process of determining the first DMA and the second DMA among multiple DMAs and the first USART and the second USART among multiple USARTs according to the verification requirements.

[0113] S204. The first data and the second data are compared by the verification environment component to generate the verification result.

[0114] Understandably, based on the above S203, the verification environment component compares the first data read from the memory and the second data written to the memory to determine the correctness and stability of the design under test and generate verification results.

[0115] Optionally, the aforementioned verification environment components include a monitoring component, a reference model, and a scoreboard component. The verification environment components compare the first data and the second data to generate verification results, which can be achieved through the following steps:

[0116] The monitoring component receives second data read from memory using a preset language and transmits it to the scoring board component as actual data; the reference model reads the contents of the configuration file and transmits the read contents to the scoring board component as expected data; the contents of the configuration file are generated by extracting stimulus data from the preset language, and the contents of the configuration file include register configuration and first data obtained by writing the stimulus data into memory; the scoring board component compares the actual data and the expected data to generate a verification result.

[0117] Understandably, the verification environment components include a monitoring component, a reference model, and a scoring board component. Unlike traditional slave monitoring components that collect data waveforms based on transmission timing, the monitoring component can retrieve data from memory using a predefined language. In other words, data collection can be achieved by reading the received data (secondary data) from memory and transmitting it to the monitoring component using C language. Additionally, the verification environment components include a proxy component, which encompasses the interface component, driver component, and monitoring component. The main function of the reference model is to read the contents of the configuration file and transmit it to the scoring board component as expected data. The configuration file content is generated by extracting stimulus data, including register configuration and primary data. The scoring board component compares the expected data from the reference model with the actual data from the monitoring component to determine the correctness and stability of the design under test and generate verification results.

[0118] One such Figure 3In the illustrated embodiment, after the design under test (DUT) is configured, stimulus data is written to the transmit address of the static random access memory (SRAM) using C language. The data is then transmitted through channel 0 of DMA0 to USART0, and then through the transmit port of USART0 to the receive port of USART1. The transmit and receive ports are connected via a driver component. After receiving the data, USART1 transfers it to the receive address of the SRAM via channel 3 of DMA0. Finally, the received data is read from the SRAM using C language and transmitted to the monitoring component of the verification platform. The monitoring component then transmits this data to the scoring board as actual data. Simultaneously, a configuration file extracted from C language is provided to the reference model as expected data. The scoring board component compares the actual data with the expected data to complete the verification of a complete transmit-receive path. The overall verification of multiple transmit-receive paths involving multiple USARTs and multiple DMAs follows the same process and will not be elaborated upon here.

[0119] The joint verification method for USART and DMA provided in this application interconnects multiple USARTs, making them master / slave to each other. This solves the problem of the large and complex verification structure caused by setting up multiple master / slave components in traditional architectures, simplifying the verification structure. It also eliminates the need for corresponding master driver components and slave monitoring components for verifying a single USART in traditional architectures, and the need to pay attention to the timing information of these components. This method allows each USART to transmit data without excessive attention to transmission timing issues, enabling synchronization among multiple USARTs. This simplifies data flow control and subsequent debugging, including the maintenance and updates of the verification environment, thus improving verification efficiency. Furthermore, joint verification can cover various scenarios, such as multiple master / slave or one master / slave USARTs. This means that not only are there various verification combinations between multiple USARTs and multiple DMAs, but there are also various connection relationships between multiple USARTs; only the connection relationships in the driver components need to be modified.

[0120] Based on the above embodiments, see Figure 4 , Figure 4 This is a schematic diagram of a joint verification apparatus for USART and DMA provided in an embodiment of this disclosure. The joint verification apparatus for USART and DMA provided in this embodiment can execute the processing flow provided in the embodiments of the joint verification method for USART and DMA, and is applied to a verification platform including verification environment components and a design under test. The design under test includes memory, multiple DMAs, and multiple USARTs, such as... Figure 4 As shown, the joint verification device 400 for USART and DMA includes a first transmission unit 401, a connection establishment unit 402, a second transmission unit 403, and a verification unit 404, wherein:

[0121] The first transmission unit 401 is used to read the first data to be transmitted from the memory through the first DMA among multiple DMAs, and transmit the first data to the first USART among multiple USARTs based on the first channel pre-configured for data transmission in the first DMA.

[0122] The connection establishment unit 402 is used to establish a transmission connection between the first USART and a second USART among a plurality of USARTs using the verification environment component, so as to transmit the second data to the second USART; wherein the second data is obtained based on the first data;

[0123] The second transmission unit 403 is used to transmit the second data in the second USART to the second DMA among multiple DMAs based on the second channel, so that the second DMA writes the second data into the memory; wherein, the second channel is a pre-configured channel for data reception in the second DMA.

[0124] The verification unit 404 is used to compare the first data and the second data through the verification environment component and generate a verification result.

[0125] The verification environment component includes an interface component and a driver component. The interface component predefines multiple interfaces, which are connected to multiple corresponding ports. The multiple ports refer to the ports of multiple USARTs. The multiple interfaces include a transmit interface and a receive interface. The driver component is used to connect the transmit interface and the receive interface.

[0126] Optionally, the connection establishment unit 402 is used for:

[0127] A transmission connection between a first transmitting interface and a first receiving interface is established using a driver component; wherein, the first transmitting interface corresponds to the first transmitting port of a first USART, and the first receiving interface corresponds to the first receiving port of a second USART among multiple USARTs, and the multiple interfaces include the first transmitting interface and the first receiving interface.

[0128] Optionally, the connection establishment unit 402 is used for:

[0129] The verification requirements reflect the verification functionality and / or the timing of verification.

[0130] The target time for establishing a transmission connection between the first transmitting interface and the first receiving interface is determined based on the verification requirements.

[0131] The driver component is used to establish a transmission connection between the first transmitting interface and the first receiving interface at the target time.

[0132] Optionally, before reading the first data to be transmitted from memory via the first DMA of the multiple DMAs, the joint verification device 400 of USART and DMA is also used for:

[0133] Register configuration is performed on multiple DMAs such that multiple channels for data transmission included in at least one of the multiple DMAs are connected to at least one of the multiple USARTs for transmission; wherein the register configuration includes at least one setting of channel selection, transmission direction, transmission mode and data width;

[0134] Configure the memory for read / write operations so that data can be written to and read from the memory in a preset language.

[0135] The validation environment components include monitoring components, a reference model, and a scoreboard component.

[0136] Optionally, verification unit 404 is used for:

[0137] The monitoring component receives second data read from memory using a preset language and transmits it to the scoreboard component as actual data.

[0138] The configuration file is read from the reference model and transmitted to the scoreboard component as expected data. The configuration file is generated by extracting stimulus data in a preset language. The configuration file includes register configuration and first data obtained by writing the stimulus data into memory.

[0139] The scoreboard component compares the actual data with the expected data to generate verification results.

[0140] Optionally, before reading the first data to be transmitted from memory via the first DMA of the multiple DMAs, the joint verification device 400 of USART and DMA is also used for:

[0141] Verification combinations are configured between multiple DMAs and multiple USARTs according to verification requirements to perform joint verification of USARTs and DMAs under the verification combinations; wherein, the verification combinations include the first combination, the second combination, the third combination, and the fourth combination, wherein:

[0142] The first combination refers to the first DMA and the second DMA being the same DMA, and the first USART and the second USART being different USARTs;

[0143] The second combination refers to the first DMA and the second DMA being the same DMA, and the first USART and the second USART being the same USART;

[0144] The third combination refers to the first DMA and the second DMA being different DMAs, and the first USART and the second USART being different USARTs;

[0145] The fourth combination refers to the first DMA and the second DMA being different DMAs, and the first USART and the second USART being the same USART.

[0146] Optionally, when multiple DMAs need to read data from and / or write data to memory, the joint verification device 400 for USART and DMA is also used for:

[0147] Obtain the pre-defined first priority of each DMA among multiple DMAs;

[0148] Optionally, the first transmission unit 401 is used for:

[0149] First data is read from memory according to a first priority via the first DMA;

[0150] The second DMA writes the second data into memory, including:

[0151] The second DMA writes the second data into the memory according to the first priority.

[0152] The first DMA includes multiple pre-configured transmission channels for data transmission.

[0153] Optionally, in the case where the first DMA transmits data to at least two USARTs through multiple transmit channels, the first transmission unit 401 is used for:

[0154] Obtain the pre-set second priority of each of the multiple transmission channels;

[0155] According to the second priority, the first data is transmitted to the first USART based on the first channel; wherein, multiple transmission channels include the first channel, and at least two USARTs include the first USART.

[0156] The second DMA includes multiple receiving channels. When at least two USARTs need to transmit data to the second DMA through multiple receiving channels, the second transmission unit 403 is used for:

[0157] Obtain the pre-set third priority of each of the multiple receiving channels;

[0158] According to the third priority, the second data belonging to the second USART is transmitted to the second DMA based on the second channel; wherein, multiple receive channels include the second channel, and at least two USARTs include the second USART.

[0159] Figure 4 The USART and DMA joint verification device shown in the embodiment can be used to execute the technical solution of the above method embodiment. Its implementation principle and technical effect are similar, and will not be repeated here.

[0160] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. See below for details. Figure 5 The diagram illustrates a structural schematic suitable for implementing the electronic device 500 in the embodiments of this disclosure. The electronic device 500 in the embodiments of this disclosure may include, but is not limited to, mobile terminals such as mobile phones, laptops, digital broadcast receivers, PDAs (personal digital assistants), PADs (tablet computers), PMPs (portable multimedia players), in-vehicle terminals (e.g., in-vehicle navigation terminals), wearable electronic devices, etc., as well as fixed terminals such as digital TVs, desktop computers, smart home devices, etc. Figure 5 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments disclosed herein.

[0161] like Figure 5 As shown, the electronic device 500 may include a processing unit 501 (e.g., a central processing unit, a graphics processing unit, etc.), which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 502 or a program loaded from a storage device 508 into a random access memory (RAM) 503 to implement the joint verification method of USART and DMA as described in the embodiments of this disclosure. Various programs and data required for the operation of the electronic device 500 are also stored in the RAM 503. The processing unit 501, ROM 502, and RAM 503 are interconnected via a bus 504. An input / output (I / O) interface 505 is also connected to the bus 504.

[0162] Typically, the following devices can be connected to I / O interface 505: input devices 506 including, for example, touchscreens, touchpads, keyboards, mice, cameras, microphones, accelerometers, gyroscopes, etc.; output devices 507 including, for example, liquid crystal displays (LCDs), speakers, vibrators, etc.; storage devices 508 including, for example, magnetic tapes, hard disks, etc.; and communication devices 509. Communication device 509 allows electronic device 500 to communicate wirelessly or wiredly with other devices to exchange data. Although Figure 5 An electronic device 500 with various devices is shown; however, it should be understood that it is not required to implement or possess all of the devices shown. More or fewer devices may be implemented or possessed alternatively.

[0163] In particular, according to embodiments of this disclosure, the processes described above with reference to the flowcharts can be implemented as computer software programs. For example, embodiments of this disclosure include a computer program product comprising a computer program carried on a non-transitory computer-readable medium, the computer program containing program code for performing the methods shown in the flowcharts, thereby implementing the joint verification method of USART and DMA as described above. In such embodiments, the computer program can be downloaded and installed from a network via communication device 509, or installed from storage device 508, or installed from ROM 502. When the computer program is executed by processing device 501, it performs the functions defined in the methods of embodiments of this disclosure.

[0164] It should be noted that the computer-readable medium described in this disclosure can be a computer-readable signal medium or a computer-readable storage medium, or any combination thereof. A computer-readable storage medium can be, for example,—but not limited to—an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this disclosure, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in connection with an instruction execution system, apparatus, or device. In this disclosure, a computer-readable signal medium can include a data signal propagated in baseband or as part of a carrier wave, carrying computer-readable program code. Such propagated data signals can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination thereof. A computer-readable signal medium can be any computer-readable medium other than a computer-readable storage medium, which can send, propagate, or transmit a program for use by or in connection with an instruction execution system, apparatus, or device. The program code contained on the computer-readable medium can be transmitted using any suitable medium, including but not limited to: wires, optical fibers, RF (radio frequency), etc., or any suitable combination thereof.

[0165] In some implementations, clients and servers can communicate using any currently known or future-developed network protocol such as HTTP (Hypertext Transfer Protocol) and can interconnect with digital data communication (e.g., communication networks) of any form or medium. Examples of communication networks include local area networks (“LANs”), wide area networks (“WANs”), the Internet (e.g., the Internet of Things), and peer-to-peer networks (e.g., ad hoc peer-to-peer networks), as well as any currently known or future-developed networks.

[0166] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0167] Optionally, when one or more of the above-described procedures are executed by the electronic device, the electronic device may also perform other steps described in the above embodiments.

[0168] Computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof, including but not limited to object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0169] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0170] The units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the units are not, in some cases, intended to limit the specific unit.

[0171] The functions described above in this document can be performed, at least in part, by one or more hardware logic components. For example, exemplary types of hardware logic components that can be used, without limitation, include: Field Programmable Gate Arrays (FPGAs), Application-Specific Integrated Circuits (ASICs), Application Standard Products (ASSPs), System-on-Chip (SoCs), Complex Programmable Logic Devices (CPLDs), and so on.

[0172] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0173] It should be noted that, in this document, relational terms such as "first" and "second" are used merely to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or gateway that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or gateway. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or gateway that includes said element.

[0174] The above description is merely a specific embodiment of this disclosure, enabling those skilled in the art to understand or implement it. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this disclosure. Therefore, this disclosure is not to be limited to the embodiments described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A joint verification method using USART and DMA, characterized in that, The method, applied to a verification platform including verification environment components and a design under test, wherein the design under test includes memory, multiple DMAs, and multiple USARTs, comprises: The first data to be sent is read from the memory through the first DMA of the plurality of DMAs, and the first data is transmitted to the first USART of the plurality of USARTs based on the first channel pre-configured for data transmission in the first DMA. The verification environment component is used to establish a transmission connection between the first USART and the second USART among the plurality of USARTs, so as to transmit the second data to the second USART; wherein the second data is obtained based on the first data; The second data in the second USART is transmitted to the second DMA among the plurality of DMAs via the second channel, so that the second DMA writes the second data into the memory; wherein, the second channel is a pre-configured channel for data reception in the second DMA; The verification environment component compares the first data and the second data to generate a verification result.

2. The method according to claim 1, characterized in that, The verification environment component includes an interface component and a driver component. The interface component predefines multiple interfaces, which are connected to multiple corresponding ports. The multiple ports refer to the ports of the multiple USARTs. The multiple interfaces include a transmitting interface and a receiving interface. The driver component is used to connect the transmitting interface and the receiving interface. The step of establishing a transmission connection between the first USART and the second USART among the plurality of USARTs using the verification environment component includes: The first transmitting interface and the first receiving interface are established using the driving component; wherein, the first transmitting interface corresponds to the first transmitting port of the first USART, the first receiving interface corresponds to the first receiving port of the second USART among the plurality of USARTs, and the plurality of interfaces include the first transmitting interface and the first receiving interface.

3. The method according to claim 2, characterized in that, The step of establishing a transmission connection between the first transmitting interface and the first receiving interface using the driving component includes: The verification requirements reflect the verification functionality and / or the timing of verification. The target time for establishing a transmission connection between the first sending interface and the first receiving interface is determined according to the verification requirements. The driving component is used to establish a transmission connection between the first transmitting interface and the first receiving interface at the target time.

4. The method according to claim 1, characterized in that, Before reading the first data to be sent from the memory via the first DMA of the plurality of DMAs, the method further includes: The registers of the plurality of DMAs are configured such that at least one of the DMAs includes multiple channels for data transmission that are connected to at least one of the USARTs; wherein the register configuration includes at least one setting of channel selection, transmission direction, transmission mode and data width; The memory is configured to be read and write so that data can be written to and read from the memory in a preset language.

5. The method according to claim 4, characterized in that, The verification environment component includes a monitoring component, a reference model, and a scoreboard component. The step of comparing the first data and the second data through the verification environment component to generate verification results includes: The monitoring component receives the second data read from the memory using the preset language and transmits it to the scoreboard component as actual data. The reference model reads the contents of the configuration file and transmits the read contents to the scoreboard component as expected data; wherein, the contents of the configuration file are generated by extracting the stimulus data of the preset language, and the contents of the configuration file include the register configuration and the first data obtained by writing the stimulus data into the memory; The scoreboard component compares the actual data with the expected data to generate a verification result.

6. The method according to claim 1, characterized in that, Before reading the first data to be sent from the memory via the first DMA of the plurality of DMAs, the method further includes: Verification combinations are set between the multiple DMAs and the multiple USARTs according to verification requirements, so as to perform joint verification of USART and DMA under the verification combinations; wherein, the verification combinations include a first combination, a second combination, a third combination, and a fourth combination, wherein: The first combination refers to the first DMA and the second DMA being the same DMA, and the first USART and the second USART being different USARTs; The second combination refers to the first DMA and the second DMA being the same DMA, and the first USART and the second USART being the same USART; The third combination refers to the first DMA and the second DMA being different DMAs, and the first USART and the second USART being different USARTs; The fourth combination refers to the first DMA and the second DMA being different DMAs, and the first USART and the second USART being the same USART.

7. The method according to claim 1, characterized in that, When all of the multiple DMAs need to read data from the memory and / or write data to the memory, the method further includes: Obtain the first priority preset for each of the multiple DMAs; The step of reading the first data to be sent from the memory through the first DMA of the plurality of DMAs includes: First data is read from the memory according to the first priority via the first DMA; The second DMA writes the second data into the memory, including: The second DMA writes the second data into the memory according to the first priority.

8. The method according to claim 1, characterized in that, The first DMA includes multiple pre-configured transmission channels for data transmission. When the first DMA transmits data to at least two USARTs through these multiple transmission channels, transmitting the first data to the first USART among the multiple USARTs based on the pre-configured first channel for data transmission in the first DMA includes: Obtain the second priority preset for each of the plurality of transmission channels; According to the second priority, the first data is transmitted to the first USART based on the first channel; wherein, the plurality of transmission channels include the first channel, and the at least two USARTs include the first USART.

9. The method according to claim 1, characterized in that, The second DMA includes multiple receive channels. When at least two USARTs need to transmit data to the second DMA through the multiple receive channels, the step of transmitting the second data from the second USART to the second DMA among the multiple DMAs based on the second channel includes: Obtain the third priority preset for each of the plurality of receiving channels; According to the third priority, the second data belonging to the second USART is transmitted to the second DMA based on the second channel; wherein, the plurality of receiving channels include the second channel, and the at least two USARTs include the second USART.

10. A joint verification device for USART and DMA, characterized in that, An apparatus applicable to a verification platform comprising verification environment components and a design under test, wherein the design under test includes memory, multiple DMAs, and multiple USARTs, the apparatus comprising: The first transmission unit is configured to read the first data to be transmitted from the memory through the first DMA among the plurality of DMAs, and transmit the first data to the first USART among the plurality of USARTs based on the first channel pre-configured for data transmission in the first DMA. A connection establishment unit is used to establish a transmission connection between the first USART and the second USART among the plurality of USARTs using the verification environment component, so as to transmit the second data to the second USART; wherein the second data is obtained based on the first data; The second transmission unit is used to transmit the second data in the second USART to the second DMA among the plurality of DMAs based on the second channel, so that the second DMA writes the second data into the memory; wherein, the second channel is a pre-configured channel for data reception in the second DMA; The verification unit is used to compare the first data and the second data through the verification environment component and generate a verification result.

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