Display panel, driving method thereof and display device

Abstract

The invention provides a display panel, a driving method thereof and a display device, and relates to the technical field of display, the display panel comprises a gate driving circuit and a plurality of pixel driving circuits, the gate driving circuit comprises N stages of shifting registers which are cascaded with each other, and N is greater than or equal to 2; one shift register comprises a level transmission module and at least two gating modules connected with the level transmission module, and the gating modules comprise a first gating module and a second gating module; the level transmission module is used for outputting a level transmission signal; the first gating module and the second gating module are configured to at least receive frequency control signals and output scanning signals through the output ends of the first gating module and the second gating module; wherein in at least part of the shift registers, the output end of the first gating module and the output end of the second gating module are respectively connected with the pixel driving circuits in different rows. Therefore, the display accuracy of the display product is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a display panel and a driving method thereof, and a display device. Background Art

[0002] With the continuous development of science and technology, more and more display products, such as mobile phones, tablets, laptops and smart wearable devices, are widely used in people's daily life and work, bringing great convenience to people's daily life and work, and becoming an indispensable tool for people today.

[0003] The normal display of display products is usually controlled by multiple signals. When special display is required, for example, different areas of the display product in a display frame need to be displayed at different refresh rates, display abnormalities are likely to occur. Therefore, how to improve the display accuracy of display products has become one of the technical issues that need to be solved urgently at this stage. Summary of the invention

[0004] In order to solve the above technical problems, the present disclosure provides a display panel and a driving method thereof, and a display device, aiming to improve the display accuracy of display products.

[0005] In a first aspect, the present disclosure provides a display panel, including a gate driving circuit and a plurality of pixel driving circuits, wherein the gate driving circuit includes N-stage shift registers cascaded to each other, where N≥2;

[0006] A shift register includes a level transmission module and at least two gating modules connected to the level transmission module, the gating module includes a first gating module and a second gating module;

[0007] The level transmission module is used to output the level transmission signal, the level transmission signal of the i-th level shift register is the input signal of the j-th level shift register, 1≤i≤N, 1≤j≤N, i≠j;

[0008] The first gating module and the second gating module are configured to at least receive a frequency control signal and output a scanning signal through the output ends of the first gating module and the second gating module; wherein, in at least part of the shift register, the output end of the first gating module and the output end of the second gating module are respectively connected to pixel driving circuits of different rows.

[0009] In a second aspect, based on the same inventive concept, the present disclosure provides a method for driving a display panel, for driving the display panel provided in the first aspect, wherein the first gating module receives a first frequency control signal, the second gating module receives a second frequency control signal, and the driving method includes:

[0010] Controlling the first frequency control signal and the second frequency control signal to maintain the same potential in at least one display frame;

[0011] The first frequency control signal and the second frequency control signal are controlled to undergo a potential jump in at least one display frame, the display frame comprising a first stage and a second stage, in the first stage, the first frequency control signal and the second frequency control signal maintain the same potential; in the second stage, the first frequency control signal and the second frequency control signal undergo a potential jump, and the potential jump time of the first frequency control signal is earlier than the potential jump time of the second frequency control signal.

[0012] In a third aspect, based on the same inventive concept, the present disclosure provides a display device, comprising the display panel provided in the first aspect of the present disclosure.

[0013] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0014] In the display panel and its driving method and display device provided by the embodiments of the present disclosure, the same shift register can output two scanning signals through the first gating module and the second gating module respectively. Among them, in at least some shift registers, the output end of the first gating module and the output end of the second gating module are respectively connected to the pixel driving circuits of different rows. Assuming that in the same shift register, the first gating module is connected to the pixel driving circuit of the a-th row, and the second gating module is connected to the pixel driving circuit of the b-th row, when the refresh requirements for different display areas are different, for example, when the pixel driving circuit of the a-th row needs to be refreshed, and the pixel driving circuit of the b-th row does not need to be refreshed, the first gating module can output the effective level signal of the scanning signal to the pixel driving circuit of the a-th row to refresh the pixel driving circuit of the a-th row, and the second gating module can output the invalid level signal of the scanning signal to the pixel driving circuit of the b-th row, without refreshing the pixel driving circuit of the b-th row, so that the pixel driving circuits with different refresh requirements can all receive the correct scanning signal, which is conducive to improving the display accuracy during the partition refresh. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0016] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.

[0017] Figure 1 Shown is a schematic structural diagram of a display panel provided by an embodiment of the present disclosure;

[0018] Figure 2 FIG. 1 is a schematic diagram showing a structure of a gate driving circuit in a display panel provided in an embodiment of the present disclosure;

[0019] Figure 3 The figure shows a connection diagram of a shift register and a pixel driving circuit in a gate driving circuit;

[0020] Figure 4 Shown is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure;

[0021] Figure 5 Shown with Figure 4 A schematic diagram of a connection between a shift register and a pixel driving circuit in a corresponding gate driving circuit;

[0022] Figure 6 FIG. 1 is a circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0023] Figure 7 FIG. 2 is another circuit schematic diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0024] Figure 8 Shown Figure 6 A timing diagram of a pixel driving circuit;

[0025] Fig. 9 The figure shows a connection diagram of a gate driving circuit and a pixel driving circuit in the related art;

[0026] Fig.10 Another connection diagram of the shift register and the pixel driving circuit in the gate driving circuit is shown;

[0027] Fig.11 Another connection diagram of the shift register and the pixel driving circuit in the gate driving circuit is shown;

[0028] Fig.12 FIG. 1 is a schematic diagram of a structure of a gate driving circuit provided in an embodiment of the present disclosure;

[0029] Fig.13 FIG. 2 is another schematic diagram of the structure of the gate driving circuit provided by the embodiment of the present disclosure;

[0030] Fig.14 Shown Fig.13 A driving timing diagram of the stage transfer module of the shift register;

[0031] Fig.15The figure shows a structural schematic diagram of a first gating module and a second gating module provided in an embodiment of the present disclosure;

[0032] Fig.16 Shown Fig.15 A working timing diagram of the middle strobe module;

[0033] Fig.17 Shown Fig.15 Another working timing diagram of the middle strobe module;

[0034] Fig.18 The figure shows a driving timing diagram of a pixel driving circuit by a gate driving circuit provided by an embodiment of the present disclosure;

[0035] Fig.19 FIG. 2 is another schematic diagram of the structure of the gate driving circuit provided by the embodiment of the present disclosure;

[0036] Fig. 20 Shown with Fig.19 A structural schematic diagram of a gating module corresponding to the embodiment;

[0037] Fig.21 FIG. 1 is a flow chart of a method for driving a display panel provided in an embodiment of the present disclosure;

[0038] Fig. 22 Shown is a schematic structural diagram of a display device provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0039] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.

[0040] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.

[0041] Figure 1 FIG. 1 is a schematic diagram of a structure of a display panel 100 provided in an embodiment of the present disclosure. Figure 2 FIG. 1 is a schematic diagram of a structure of a gate driving circuit 00 in a display panel 100 provided in an embodiment of the present disclosure. Figure 3 FIG. 1 is a schematic diagram showing a connection between the shift register 01 in the gate driving circuit 00 and the pixel driving circuit P0 .

[0042] Please refer to Figures 1 to 3The embodiment of the present disclosure provides a display panel 100, including a gate driving circuit 00 and a plurality of pixel driving circuits P0, the gate driving circuit 00 includes N-stage shift registers 01 cascaded with each other, N≥2; one shift register 01 includes a stage transmission module 10 and at least two gating modules 20 connected to the stage transmission module 10, the gating module 20 includes a first gating module 21 and a second gating module 22; the stage transmission module 10 is used to output a stage transmission signal NEXT, the stage transmission signal of the i-th stage shift register is the input signal of the j-th stage shift register, 1≤i≤N, 1≤j≤N, i≠j; the first gating module 21 and the second gating module 22 are configured to at least receive a frequency control signal Ctrl, and output a scanning signal S1N_OUT / S2N_OUT through the output ends of the first gating module 21 and the second gating module 22; wherein, in at least some of the shift registers 01, the output end of the first gating module 21 and the output end of the second gating module 22 are respectively connected to the pixel driving circuits P0 of different rows.

[0043] It should be noted that Figure 1 Only a rectangular display panel is used as an example for illustration, and the actual shape of the display panel is not limited. In some other embodiments of the present disclosure, the display panel can also be embodied in any other feasible shape such as a circle, a rounded rectangle, etc. Optionally, the display panel provided in this embodiment can be an organic light-emitting display panel, and the corresponding light-emitting element is an organic light-emitting element. Of course, in some other embodiments of the present disclosure, the display panel can also use a display panel using inorganic light-emitting diode display technology, such as a Micro LED display panel, or a Mini LED display panel, etc., and the present disclosure does not limit this.

[0044] To clearly illustrate the relative position relationship between the gate driving circuit and the pixel driving circuit, Figure 1 Other structures of the display panel such as the light emitting element are not shown, and the pixel driving circuit is only illustrated in a rectangular structure, without limiting the number and arrangement of the pixel driving circuit. Figure 1 The position of the gate driving circuit in the display area is only for illustration, and only one set of gate driving circuits 00 is introduced into the display panel, and the gate driving circuit 00 is arranged in the non-display area on one side of the display area. However, the present disclosure is not limited to this. In some other embodiments of the present disclosure, two sets of gate driving circuits may be arranged in the display panel. For example, please refer to Figure 4 and Figure 5 , Figure 4 FIG. 1 is another schematic diagram of a planar structure of a display panel provided by an embodiment of the present disclosure. Figure 5 Shown with Figure 4A connection diagram of the shift register and the pixel driving circuit in the corresponding gate driving circuit. This embodiment is explained by taking the introduction of two groups of gate driving circuits 00 in the display panel and the two groups of gate driving circuits 00 being respectively arranged in the left and right border areas of the display panel as an example. The method of driving the pixel driving circuit P0 by two groups of gate driving circuits 00 is beneficial to improving the transmission efficiency and transmission reliability of the scanning signal.

[0045] Alternatively, refer to 1 to Figure 5 The gate driving circuit 00 includes a plurality of cascaded shift registers 01, the output end of the shift register 01 is connected to the scan line S, the scan line S is further electrically connected to the pixel driving circuit P0, and the shift register 01 provides a scan signal to the pixel driving circuit P0 through the scan line S. The scan signal includes, for example, a reset control signal, a data writing control signal, a light emitting control signal, etc., to control the operation of the pixel driving circuit P0. Optionally, at least two different control signals correspond to different gate driving circuits, for example, the gate driving circuit that sends the reset control signal and the gate driving circuit that sends the light emitting control signal are two independent gate driving circuits. Figure 6 FIG. 1 is a circuit diagram of a pixel driving circuit provided by an embodiment of the present disclosure. Figure 6For example, the pixel driving circuit P0 includes a first transistor M1, a second transistor M2, a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a seventh transistor M7, an eighth transistor M8 and a capacitor C, wherein the third transistor M3 is a driving transistor, which is used to provide a driving current for the light-emitting element D0, and the gate, the first electrode and the second electrode of the driving transistor are respectively connected to the first subnode N01, the third subnode N03 and the second subnode N02. The first electrode and the second electrode of the fifth transistor M5 are respectively connected to the first reset signal terminal Vref1 and the first subnode N01, the gate is connected to the first control signal terminal S1N, and is used to receive the reset control signal, and the fifth transistor M5 is used to provide the first reset signal Vref1 to the first subnode N01. The first electrode and the second electrode of the second transistor M2 are respectively connected to the data voltage signal terminal Vdata and the second subnode N02, the gate receives the control signal SP, and the second transistor M2 is used to transmit the data voltage signal Vdata to the second subnode N02. It should be noted that the signal terminal and the signal transmitted by the signal terminal in the embodiment of the present disclosure are represented by the same reference numerals. The first and second electrodes of the fourth transistor M4 are connected to the third subnode N03 and the first subnode N01 respectively, and the gate is connected to the second control signal terminal S2N for receiving the control signal S2N. The fourth transistor M4 is used to perform threshold compensation on the third transistor M3. The first and second electrodes of the seventh transistor M7 are connected to the second reset signal terminal Vref2 and the first electrode of the light-emitting element D0 respectively, and the gate is connected to the control signal terminal SPX. The seventh transistor M7 is used to reset the first electrode of the light-emitting element D0. The first and second electrodes of the eighth transistor M8 are connected to the bias adjustment signal terminal DVH and the second subnode N02 respectively, and the gate is connected to the control signal terminal SPX. The first and second electrodes of the first transistor M1 are connected to the first power signal terminal PVDD and the second subnode N02 respectively, and the gate is connected to the light control signal terminal Emit. The first and second electrodes of the sixth transistor M6 are connected to the third subnode N03 and the first electrode of the light-emitting element D0 respectively, and the gate is connected to the light control signal terminal Emit for transmitting the driving current to the light-emitting element D0. The second electrode of the light-emitting element D0 is connected to the second power signal PVEE. It should be noted that the embodiment of the present disclosure is only described by taking the example that the gates of the seventh transistor M7 and the eighth transistor M8 are both connected to the control signal terminal SPX, but the present disclosure is not limited to this. It should also be noted that, Figure 6 The pixel driving circuit in the figure is only for illustration, and the present disclosure does not limit the specific structure of the pixel driving circuit. Figure 6In the embodiment, the fourth transistor M4 and the fifth transistor M5 connected to the first subnode N01 are N-type transistors, which may be oxide transistors. The signal controlling the conduction of the fourth transistor M4 and the fifth transistor M5 is a high-level signal, and the other transistors are P-type transistors. In the present embodiment, the fourth transistor M4 and the fifth transistor M5 are N-type transistors, which may be oxide transistors, which may help reduce the leakage of the fourth transistor M4 and the fifth transistor M5 to the first subnode N01, thereby helping to maintain the stability of the potential of the gate of the driving transistor connected to the first subnode N01. In some other embodiments, the pixel driving circuit may also be embodied in other structures, for example, please refer to Figure 7 , Figure 7 FIG. 1 is another circuit diagram of the pixel driving circuit provided in the embodiment of the present disclosure, and the connection relationship and working principle are similar to those of FIG. Figure 6 Same as Figure 6 The only difference is that the fourth transistor M4 and the fifth transistor M5 are P-type transistors, and the P-type transistors are turned on under the control of a low-level signal. Figure 7 When all transistors in the illustrated embodiment are P-type transistors, it is beneficial to simplify the manufacturing process of the pixel driving circuit.

[0046] Figure 6 and Figure 7 In the pixel driving circuit shown, the first control signal terminal S1N, the second control signal terminal S2N, the light emitting control signal terminal Emit, and the control signal terminals SP and SPX are all connected to the gate driving circuit, the first control signal terminal S1N and the second control signal terminal S2N may correspond to the same group of gate driving circuits, and the light emitting control signal terminal Emit, the control signal terminals SP and SPX may correspond to other different gate driving circuits. It should be noted that in the embodiment of the present disclosure, only the structure of the gate driving circuit corresponding to the first control signal terminal S1N and the second control signal terminal S2N is described, and the structure of other gate driving circuits in the display panel is not limited.

[0047] The following will be combined Figure 8 right Figure 6 The working principle of Figure 7 The working principle of the pixel driving circuit may refer to this embodiment. Figure 8 Shown Figure 6 A timing diagram of the pixel driving circuit in Figure 6 and Figure 8 The specific working process of the pixel driving circuit P0 includes an initialization phase t1, a data writing and threshold compensation phase t2, a bias phase t3 and a light emitting phase t4.

[0048] In the initialization stage t1, the high level signal of the first control signal S1N controls the fifth transistor M5 to be turned on, and transmits the first reset signal Vref1 to the control end of the third transistor M3 for initialization, so as to eliminate the residual charge of the previous frame to improve the display effect of the display panel. In the present disclosure, in a part of the time period of the initialization stage t1, the effective levels of the first control signal S1N and the second control signal S2N have an overlap time, which is conducive to improving the hysteresis problem of the driving transistor during the initialization stage.

[0049] In the data writing and threshold compensation stage t2, the fifth transistor M5 is turned off, the control signal SP controls the second transistor M2 to be turned on, the second control signal S2N controls the fourth transistor M4 to be turned on, and the data voltage signal Vdata is written into the third transistor M3 through the second transistor M2. The fourth transistor M4 is connected between the gate and the first electrode of the third transistor M3, and the threshold voltage of the third transistor M3 can be captured to the gate of the third transistor M3, thereby realizing the compensation of the threshold voltage and self-compensating the deviation of the threshold voltage of the driving transistor.

[0050] In the bias stage t3, the control signal SPX controls the eighth transistor M8 to be turned on, and the bias adjustment signal DVH is transmitted to the second electrode (i.e., the second subnode N02) of the driving transistor through the eighth transistor M8 to adjust the bias state of the driving transistor. At the same time, the control signal SPX controls the seventh transistor M7 to be turned on, and the second reset signal Vref2 is transmitted to the anode of the light emitting element D0 through the seventh transistor M7 to reset the light emitting element D0.

[0051] In the light emitting stage t4, the second transistor M2, the fourth transistor M4, the fifth transistor M5 and the seventh transistor M7 are all turned off, the first transistor M1, the third transistor M3 and the sixth transistor M6 are all turned on, and the driving current is transmitted to the first electrode of the light emitting element D0, and the light emitting element D0 emits light. It should be noted that Figure 8 The timing diagram is for illustration only and is not intended to be limiting. In some other embodiments of the present disclosure, pixel driving circuits with different structures may correspond to different timings.

[0052] Fig. 9 FIG. 1 is a schematic diagram showing a connection between a gate driving circuit 00′ and a pixel driving circuit in the related art. To simplify the panel design, the shift register for transmitting the reset control signal S1N is usually multiplexed with the shift register for transmitting the control signal S2N, that is, the same shift register is used to transmit the reset control signal S1N and the control signal S2N. Fig. 9In the gate driving circuit, the output of the shift register 01' at this stage can provide a control signal S2N for the pixel driving circuit of the nth row, and can also provide a reset control signal S1N for the pixel driving circuit of the mth row, so that the fourth transistor M4 in the pixel driving circuit of the nth row is turned on to achieve threshold compensation, and the fifth transistor of the mth row is controlled to be turned on to achieve resetting of the gate of the driving transistor, m>n. For a display panel using such a gate drive circuit, the reset control signal S1N and the control signal S2N corresponding to the two rows of pixel drive circuits are multiplexed. When the display panel needs to implement partition refresh, for example, in two adjacent display areas, the pixel drive circuit in one display area needs to be refreshed (the first control signal terminal S1N and the second control signal terminal S2N both need to receive the valid level signal in the scanning signal), while the pixel drive circuit in the other display area does not need to be refreshed (the first control signal terminal S1N and the second control signal terminal S2N both need to receive the invalid level signal in the scanning signal). Assuming that the pixel drive circuit in the first row needs to be refreshed and the pixel drive circuit in the second row does not need to be refreshed, considering that the second-stage shift register 01 is simultaneously connected to the first pixel drive circuit in the first row, the pixel drive circuit in the second row does not need to be refreshed. The second control signal terminal S2N and the first control signal terminal S1N in the second row pixel driving circuit, in order to ensure the normal refresh of the first row pixel driving circuit, the second-stage shift register needs to output the valid level signal of the control signal S2N, but in order to ensure that the second row pixel driving circuit is not refreshed, the corresponding shift register needs to output the invalid level signal of the reset control signal S1N. It can be seen that the signals required by the pixel driving circuits of the first row and the second row are different, but because the pixel driving circuits of the first row and the second row are connected to the output terminal of the same shift register, the corresponding two control signals are multiplexed, and the output signals are consistent, so they cannot meet the different refresh requirements of the two rows of pixel driving circuits, resulting in display abnormalities when the display panel has a partition refresh requirement.

[0053] To solve the above problems, the present disclosure improves the structure of the shift register. Figures 2 to 5In the N-stage shift register included in the gate driving circuit, each shift register includes a stage transmission module 10 and a first gating module 21 and a second gating module 22 connected to the stage transmission module 10, wherein the stage transmission module 10 is used to transmit the stage transmission signal, and the stage transmission signal of the i-th stage shift register is used as the input signal of the j-th stage shift register. The first gating module 21 and the second gating module 22 output the scanning signal at least according to the received frequency control signal Ctrl, that is, the same shift register 01 can output two scanning signals through the first gating module 21 and the second gating module 22 respectively. Among them, in at least part of the shift register, the output end of the first selection module 21 and the output end of the second selection module 22 are respectively connected to the pixel driving circuits of different rows. Assuming that in the same shift register, the first selection module 21 is connected to the pixel driving circuit of the a-th row, and the second selection module 22 is connected to the pixel driving circuit of the b-th row, when the refresh requirements of different display areas are different, for example, when the pixel driving circuit of the a-th row needs to be refreshed, but the pixel driving circuit of the b-th row does not need to be refreshed, the first selection module 21 can output a valid level signal of the scanning signal to the pixel driving circuit of the a-th row to refresh the pixel driving circuit of the a-th row, and the second selection module 22 can output an invalid level signal of the scanning signal to the pixel driving circuit of the b-th row, without refreshing the pixel driving circuit of the b-th row, so that the pixel driving circuits with different refresh requirements can all receive the correct scanning signal, which is beneficial to improving the display accuracy of the display panel during partition refresh.

[0054] Please refer to the appropriate Figures 2 to 5 In an optional embodiment of the present disclosure, in at least one display frame, the first gating module 21 and the second gating module 22 in at least one shift register are configured to receive different frequency control signals respectively. The frequency control signal mentioned in the embodiment of the present disclosure can be regarded as one of the control signals for controlling whether the gating module outputs a valid level signal. For example, when the frequency control signal is a certain level signal, the scanning signal output by the corresponding gating module may include a valid level signal, which can realize the normal refresh of the corresponding row pixel driving circuit; and when the frequency control signal is another level signal, the scanning signal output by the corresponding gating module may only include an invalid level signal, and the pixel driving circuit of the corresponding row is not refreshed. Therefore, in at least one display frame, if the first gating module 21 and the second gating module 22 in the shift register receive different frequency control signals, different refresh requirements of the pixel driving circuits of different rows connected to the first gating module 21 and the second gating module 22 of the shift register can be realized to meet the partition refresh requirements of the display panel, and it is beneficial to ensure that the pixel driving circuits with different refresh requirements can receive the correct scanning signal, which is beneficial to improve the display accuracy during partition refresh. The following embodiments will further illustrate the differences in frequency control signals in conjunction with timing.

[0055] Please refer to the appropriate Figure 2 and Figure 3 In an optional embodiment of the present disclosure, the first gating module 21 and the second gating module 22 are configured to receive different frequency control signals respectively, which can be specifically embodied as follows: in at least one display frame and in at least one shift register, one of the frequency control signal received by the first gating module 21 and the frequency control signal received by the second gating module 22 is a high level signal and the other is a low level signal. For example, the first gating module 21 receives the first frequency signal Ctrl_1, and the second gating module 21 receives the second frequency signal Ctrl_2. Corresponding to a certain shift register, the potentials of the first frequency signal Ctrl_1 and the second frequency signal Ctrl_2 are opposite. Optionally, when the frequency control signal received by the gating module is a low level signal, the scanning signal output by the gating module may include an effective level signal to achieve refreshing of the pixel driving circuit; when the frequency control signal received by the gating module is a high level signal, the scanning signal output by the gating module does not include an effective level signal, and the pixel driving circuit is not refreshed. Of course, in some other embodiments of the present disclosure, when the frequency control signal received by the gating module is high, the scanning signal output by the gating module can be controlled not to include a valid level signal, and vice versa, when the received frequency control signal is low, the scanning signal output by the gating module can be controlled to include a valid level signal, and the present disclosure is not limited thereto. By controlling the output of the gating module by setting the frequency control signal high or low, and thus achieving different refresh requirements in different areas, it is beneficial to simplify the signal control of the panel.

[0056] Please continue to refer to Figure 2 and Figure 3In an optional embodiment of the present disclosure, in at least one display frame, in at least one shift register, the scanning signal transmitted by the first selection module 21 to the corresponding pixel driving circuit includes a valid level signal. At this time, the pixel driving circuit connected to the first selection module 21 can be refreshed normally, and the scanning signal output by the second selection module 22 to the corresponding pixel driving circuit does not include a valid level signal. At this time, the pixel driving circuit connected to the first selection module 21 does not need to be refreshed. The above embodiment is only described by taking the example that the pixel driving circuit connected to the first selection module 21 is refreshed normally and the pixel driving circuit connected to the second selection module 22 does not need to be refreshed. In some other implementations of the present disclosure, the output signals of the first selection module 21 and the second selection module 22 can be controlled to achieve that the pixel driving circuit connected to the first selection module 21 is not refreshed, and the pixel driving circuit connected to the second selection module 22 is refreshed normally. For example, if the scanning signal transmitted by the first selection module 21 to the corresponding pixel driving circuit does not include a valid level signal, the pixel driving circuit connected to the first selection module 21 is not refreshed, and the scanning signal output by the second selection module 22 to the corresponding pixel driving circuit includes a valid level signal, then the normal refresh of the pixel driving circuit corresponding to the second selection module 22 is achieved.

[0057] In this way, by controlling the output signals of the first selection module 21 and the second selection module 22 in the shift register, the different refresh requirements of different pixel driving circuits connected to the same shift register are met, and there is no need to introduce different shift registers for pixel driving circuits with different refresh requirements, which is beneficial to reducing the number of shift registers actually included in the gate driving circuit, simplifying the panel structure, and realizing a narrow border design.

[0058] In an optional embodiment of the present disclosure, in at least one display frame, the two gating modules in the shift register are configured to receive the same frequency control signal. For example, the frequency control signals received by the first gating module 21 and the second gating module 22 are both high-level signals, or both are low-level signals. Assuming that the received frequency control signal is a low-level signal, the scanning signal output by the corresponding gating module includes a valid level signal, and the corresponding pixel driving circuit can be refreshed normally; when the received frequency control signal is a high-level signal, the scanning signal output by the corresponding gating module only includes an invalid level signal, and the corresponding pixel driving circuit is not refreshed. Therefore, when both gating modules receive low-level signals, the pixel driving circuits corresponding to the two gating modules can be refreshed normally, and when both gating modules receive high-level signals, the pixel driving circuits corresponding to the two gating modules do not need to be refreshed. The pixel driving circuit connected to the two selection modules in the same shift register corresponding to this embodiment does not need to be refreshed differentially. Therefore, the scheme of introducing at least two selection modules in the same shift register in the disclosed embodiment can meet the differentiated refresh requirements of different display areas, and can also meet the same refresh requirements of different display areas, which is beneficial to meet the different display requirements of the display panel.

[0059] In an optional embodiment of the present disclosure, in at least one display frame, in at least one shift register, the scanning signals transmitted by the first gating module 21 and the second gating module 22 to the corresponding pixel driving circuit all include valid level signals, or do not include valid level signals. When the scanning signals transmitted by the first gating module 21 and the second gating module 22 to the corresponding pixel driving circuit all include valid signals, the pixel driving circuits corresponding to the first gating module 21 and the second gating modules can be refreshed normally; when the scanning signals transmitted by the first gating module 21 and the second gating module 22 to the corresponding pixel driving circuit do not include valid level signals, that is, when they are both invalid level signals, the pixel driving circuits corresponding to the first gating module 21 and the second gating module 22 do not need to be refreshed. In other words, the pixel driving circuits corresponding to the first gating module 21 and the second gating module 22 can also be refreshed using the same refresh requirements. The method of simultaneously introducing the first gating module 21 and the second gating module 22 in the same shift register can meet the differentiated refresh requirements of different display areas, and can also meet the same refresh requirements of different display areas, thereby meeting the different display requirements of the display panel.

[0060] Please refer to Figure 6 , Figure 3 and Figure 5In an optional embodiment of the present disclosure, the pixel driving circuit P0 includes a first control signal terminal S1N and a second control signal terminal S2N, and the first control signal terminal S1N and the second control signal terminal S2N are configured to receive scanning signals output by different shift registers 01; it should be noted that, in order to simplify the description, the signal terminal and the signal transmitted by the signal terminal are represented by the same reference numerals in the embodiment of the present disclosure. The first control signal terminal S1N in the pixel driving circuit P0 can be regarded as a signal terminal connected to the gate of the fifth transistor M5, and the signal of the first control signal terminal S1N is used to control the conduction state of the fifth transistor M5. When the fifth transistor M5 is turned on, the gate of the driving transistor can be reset. The second control signal terminal S2N can be regarded as a signal terminal connected to the gate of the fourth transistor M4 in the pixel driving circuit, and the signal of the second control signal terminal S2N is used to control the conduction state of the fourth transistor M4. When the signal of the second control signal terminal S2N controls the fourth transistor M4 to be turned on and the signal of the control signal terminal SP controls the second transistor M2 to be turned on, data writing and threshold compensation of the driving transistor can be realized. When the pixel driving circuit is working, when the pixel driving circuit is refreshed normally, the fifth transistor M5 will be turned on earlier than the fourth transistor M4, that is, the time when the gate of the fifth transistor M5 receives the effective level signal is earlier than the time when the gate of the fourth transistor M4 receives the effective level signal, and the gate of the driving transistor is reset first, and then the data writing and threshold compensation stage is performed. Therefore, in the same pixel driving circuit, the gate of the first transistor M5 (corresponding to the first control signal terminal S1N) and the gate of the fourth transistor M4 (corresponding to the second control signal terminal S2N) are respectively connected to different shift registers, and the scanning signals are provided by different shift registers.

[0061] In the same shift register 01, the first gating module 21 and the second gating module 22 are respectively used to connect different control signal terminals in the pixel driving circuit. For example, the first gating module 21 is used to connect to the first control signal terminal S1N to control whether to reset the gate of the driving transistor of the pixel driving circuit, and the second gating module 22 is used to connect to the second control signal terminal S2N to control the conduction state of the fourth transistor M4. In the embodiment of the present disclosure, when the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit are configured to receive the scanning signals output by different shift registers 01, the output of the corresponding gating module can be controlled by the frequency control signal, so that the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit can both receive the valid level signal in the scanning signal to achieve refresh, or both receive the invalid level signal in the scanning signal to not refresh.

[0062] The foregoing Figure 3 and Figure 5The embodiment shows a mode in which one gating module in the shift register is electrically connected to only one row of pixel driving circuits, that is, one gating module drives one row of pixel driving circuits. In this mode, the load of the gating module is small, which is conducive to improving the driving capability. Figure 3 and Figure 5 When one gating module drives a row of pixel driving circuits, the shift register of the n+1th stage can be set on one side or both sides of the pixel driving circuit of the nth row, the first control signal terminal S1N corresponding to the pixel driving circuit of the nth row is connected to the output terminal of the first gating module 21 in the nth stage shift register, and the second control signal terminal S2N of the pixel driving circuit of the nth row is connected to the output terminal of the second gating module 22 in the n+1th stage shift register.

[0063] In some other embodiments of the present disclosure, a gating module in the shift register may also be connected to at least two rows of pixel driving circuits. Fig.10 , Fig.10 Another connection diagram of the shift register and the pixel driving circuit in the gate driving circuit is shown. In the pixel driving circuits of the sth and pth rows, the second control signal terminal S2N is connected to the output terminal of the second gating module 22 in the mth stage shift register, and the first control signal terminal S1N is connected to the output terminal of the first gating module 21 in the nth stage shift register, s≥1, p≥1, s≠p, m>n≥1. For example Fig.10 In the embodiment, the first control signal terminal S1N of the first row pixel driving circuit and the second row pixel driving circuit are both connected to the output terminal of the first selection module 21 in the first stage shift register, and the second control signal terminal S2N of the first row pixel driving circuit and the second row pixel driving circuit are both connected to the output terminal of the second selection module 22 in the second stage shift register.

[0064] In this embodiment, the pixel driving circuits in the sth row and the pth row may be any two rows of pixel driving circuits in the display panel, and the two rows of pixel driving circuits may be adjacent or not adjacent. Fig.10 Only the two adjacent ones are used as an example for explanation, but the invention is not limited thereto. The second control signal terminal S2N in the two rows of pixel driving circuits is connected to the same shift register, and the first control signal terminal S1N in the two rows of pixel driving circuits is connected to another shift register, so that the gate resetting process of the driving transistors in the two rows of pixel driving circuits is carried out simultaneously, and the threshold compensation and data writing process are also carried out simultaneously. The same shift register is used to drive the two rows of pixel driving circuits, and there is no need to introduce different shift registers for the pixel driving circuits of different rows, which is conducive to simplifying the number of shift registers actually included in the gate driving circuit, reducing the space actually occupied by the gate driving circuit in the display panel, and thus is conducive to realizing the narrow frame design of the display panel.

[0065] It should be noted that, in the pixel driving circuits of the s-th row and the p-th row, the shift registers connected to the first control signal terminals S1N are different from the shift registers connected to the second control signal terminals S2N. The first control signal terminal S1N is connected to the output terminal of the first selection module 21 in the n-th stage shift register, and the second control signal terminal S2N is connected to the output terminal of the second selection module 22 in the m-th stage shift register, and n<m, that is, the n-th stage shift register outputs the scanning signal first, and the m-th stage shift register outputs the scanning signal later. In this way, during actual refreshing, it is possible to first send the valid level signal in the scanning signal to the first control signal terminal S1N, complete the gate resetting of the driving transistors of the two rows of pixel driving circuits, and then send the valid level in the scanning signal to the second control signal terminal S2N to complete the threshold voltage compensation. Of course, when refreshing is not required, the shift register of the nth stage first sends the invalid level signal in the scanning signal to the first control signal terminal S1N, and the shift register of the mth stage then sends the invalid level signal in the scanning signal to the second control signal terminal S2N. It should be noted that in an actual display panel, the pixel driving circuits of the sth row and the pth row have the same refresh requirements, for example, both need to be refreshed, or both do not need to be refreshed.

[0066] Optionally, in the above embodiment, p=s+1, mn=1. That is to say, when the same shift register is used to drive two rows of pixel driving circuits, the two rows of pixel driving circuits can be, for example, two adjacent rows. In an actual panel, for example, the pixel driving circuits of the 1st and 2nd rows are taken as a whole, the pixel driving circuits of the 3rd and 4th rows are taken as a whole, and so on. This is conducive to simplifying the connection between the pixel driving circuits of different rows and the shift registers. When mn=1, the shift register representing the nth level and the shift register representing the mth level are adjacent, that is, the two-stage shift registers that respectively provide scanning signals to the first control signal terminal S1N and the second control signal terminal S2N of the pixel driving circuits of the adjacent two rows are shift registers of adjacent levels. This is conducive to reducing the interval from the gate reset stage of the driving transistor to the data writing and threshold compensation stage in the pixel driving circuit, and is conducive to improving the working efficiency of the pixel driving circuit.

[0067] Please continue to refer to Fig.10The above embodiment illustrates the connection relationship between the pixel driving circuits of the adjacent sth and pth rows and the shift registers. For the connection relationship of the pixel driving circuits after the pth row, reference may be made to the connection relationship between the pixel driving circuits of the sth and pth rows. For example, in an optional embodiment of the present disclosure, in the pixel driving circuits of the p+1th and p+2th rows (the pixel driving circuits of the 3rd and 4th rows may be taken as examples), the second control signal terminal S2N is connected to the output terminal of the second gating module 22 in the shift register of the m+1th stage, and the first control signal terminal S1N is connected to the output terminal of the first gating module 21 in the shift register of the mth stage. That is to say, the pixel driving circuits of the p+1th and p+2th rows are taken as a whole, and each first control signal terminal S1N receives the scanning signal output by the first gating module 21 in the shift register of the mth stage to determine whether to reset the gate of the driving transistor, and each second control signal terminal S2N receives the scanning signal output by the second gating module 22 in the shift register of the m+1th stage to determine whether to turn on the transistor. Figure 6 or Figure 7 The fourth transistor M4 in the pixel driving circuit is shown.

[0068] When the pixel driving circuits of the sth and pth rows are taken as a whole, and the pixel driving circuits of the p+1th and p+2th rows are taken as another whole, it is possible to achieve that the pixel driving circuits of the sth and pth rows are refreshed normally, and the pixel driving circuits of the p+1th and p+2th rows are not refreshed, or that the pixel driving circuits of the sth and pth rows are not refreshed, and the pixel driving circuits of the p+1th and p+2th rows are refreshed normally. Taking the pixel driving circuits of the sth and pth rows being refreshed normally, and the pixel driving circuits of the p+1th and p+2th rows being not refreshed as an example, the scanning signal outputted by the first gating module 21 in the nth stage shift register to the first control signal terminal S1N of the pixel driving circuits of the sth and pth rows includes an effective level signal, so as to achieve the resetting of the gate of the driving transistor, and the scanning signal outputted by the second gating module 22 in the mth stage shift register to the second control signal terminal S2N of the pixel driving circuits of the sth and pth rows includes an effective level signal, so as to achieve the compensation of the threshold voltage, thereby achieving the refreshing of the pixel driving circuits of the sth and pth rows. The scanning signal outputted by the first selection module 21 in the first shift register of the mth stage to the pixel driving circuits of the p+1th row and the p+2th row does not include an effective level signal, and the scanning signal outputted by the second selection module 22 of the shift register of the m+1th stage to the pixel driving circuits of the p+1th row and the p+2th row does not include an effective level signal, thereby realizing that the pixel driving circuits of the p+1th row and the p+2th row are not refreshed. When the pixel driving circuits of the sth row and the pth row are refreshed and the pixel driving circuits of the p+1th row and the p+2th row are not refreshed, the first control signal terminal S1N and the second control signal terminal S2N of the corresponding pixel driving circuit can both receive the correct scanning signal, thereby avoiding the problem of abnormal display of the display panel in the partition refresh stage.

[0069] Please refer to the appropriate Fig.10 In an optional embodiment of the present disclosure, in at least one display frame, the scanning signals received by the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit of the same row both include valid level signals, that is, when a certain row of pixel driving circuits needs to be refreshed normally, the first control signal terminal S1N and the second control signal terminal S2N of the pixel driving circuit of the row can receive the signal that normally controls it to refresh, and the problem that one of the first control signal terminal S1N and the second control signal terminal S2N in the related art receives an incorrect refresh signal will not occur. Similarly, when a certain row of pixel driving circuits does not need to be refreshed, the scanning signals received by the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit of the same row both do not include valid level signals, and the problem that one of the first control signal terminal S1N and the second control signal terminal S2N in the related art receives a valid level signal and causes a display error will not occur.

[0070] Please refer to Figure 3 and Fig.10 The display panel includes C circuit groups Z0, C≥1, the circuit group Z0 includes multiple pixel driving circuits, and one circuit group Z0 includes at least one row of pixel driving circuits. Figure 3 In the embodiment shown, a circuit group Z0 includes a row of pixel driving circuits, Fig.10 In the illustrated embodiment, a circuit group Z0 includes two adjacent rows of pixel driving circuits. The pixel driving circuit includes a first control signal terminal S1N and a second control signal terminal S2N, and the first control signal terminal S1N and the second control signal terminal S2N are configured to receive scanning signals output by different shift registers; in a circuit group Z0, the first control signal terminal S1N of the pixel driving circuit is connected to the output terminal of the first gating module 21 in a shift register 01, and the second control signal terminal S2N of the pixel driving circuit is connected to the output terminal of the second gating module 22 in another shift register 01. The number of shift registers included in a group of gate driving circuits N≥C+1. That is, when the number of circuit groups in the display panel is C, the number of shift registers N included in a group of gate driving circuits is at least C+1. The present disclosure takes N=C+1 as an example for explanation, but is not limited thereto. In some other embodiments of the present disclosure, the number of shift registers N included in a group of gate driving circuits may also be greater than C+1. It can be understood that a shift register needs to provide corresponding scanning signals to pixel circuits of different rows through the first gating module 21 and the second gating module 22. At the same time, the first control signal terminal S1N and the second control signal terminal S2N of the pixel driving circuit in a circuit group are also provided with scanning signals by different shift registers. In this way, it may happen that the first signal control terminal S1N or the second signal control terminal S2N in some circuit groups do not have a corresponding shift register to provide scanning signals. In the embodiment of the present application, setting the number of shift registers to be greater than the number of circuit groups can ensure that the first control signal terminal S1N and the second control signal terminal S2N of each pixel driving circuit are provided with corresponding scanning signals, so as to ensure that the display panel can display normally.

[0071] When the number of shift registers included in a group of gate drive circuits is set to be at least 1 more than the number of circuit groups, the extra shift register can act as a buffer to ensure that the signal has enough time to stabilize during transmission and avoid data errors caused by timing deviations. In addition, in high-speed refresh operations, the extra shift register can provide an additional clock cycle to compensate for signal delays, so that the scan signals output by shift registers of different levels can be generated and processed in the same way, reducing circuit complexity.

[0072] by Fig.10For example, when N=C+1, the first control signal terminal S1N of the pixel driving circuit of the first row and the second row is connected to the output terminal of the first gating module 21 of the first-stage shift register, and the second control signal terminal S2N of the pixel driving circuit of the first row and the second row is connected to the output terminal of the second gating module 22 of the second-stage shift register. At this time, the output terminal of the second gating module 22 of the first-stage shift register is not connected to the pixel driving circuit. Optionally, in the gate driving circuit, the output terminal of the second gating module 22 in at least the first-stage shift register is floated or connected to the first signal line X1, and the first signal line X1 is not connected to the pixel driving circuit. That is to say, the output end of the second selection module 22 in the first-stage shift register may not be connected to any other signal, or a first signal line X1 may be introduced in the display panel to be connected to the output end of the second selection module 22. The first signal line X1 may be regarded as a virtual signal line that is not connected to the pixel driving circuit. The first signal line X1 may receive a fixed-level signal in the display panel, such as a high-level signal or a low-level signal, or other fixed potential signals in the display panel. This is helpful in preventing static electricity from affecting the normal operation of the shift register through the output end of the second selection module 22.

[0073] For the shift register located at the last stage, the output end of the second gating module 22 is electrically connected to the second control signal end S2N of the last two rows of pixel driving circuits in the display panel, and the output end of the first gating module 21 in the last stage shift register is not connected to the pixel driving circuit. At this time, at least the output end of the first gating module 21 in the shift register located at the last stage is floating or connected to the second signal line X2, and the second signal line X2 is not connected to the pixel driving circuit. When the first gating module 21 is floating, the output end of the first gating module 21 may not be connected to any other signal. When the output end of the first gating module 21 is connected to the second signal line X2, the second signal line X2 can be regarded as a virtual signal line that is not connected to the pixel driving circuit. The second signal line X2 can receive a fixed level signal in the display panel, such as a high level signal or a low level signal, which is conducive to preventing static electricity from affecting the normal operation of the shift register through the output end of the above-mentioned first gating module 21. Optionally, the first signal line X1 and the second signal line X2 may be the same signal line, for example, both are high-level signal lines that receive high-level signals, or both are low-level signal lines that receive low-level signals. Optionally, the first signal line X1 and the second signal line X2 may be different signal lines, for example, one is a high-level signal line that receives high-level signals, and the other is a low-level signal line that receives low-level signals. Here, the high-level signal may be a high-level signal VGH described later, and the low-level signal may be a low-level signal VGL described later.

[0074] It should be noted that when the output end of the second gating module 22 of the first-stage shift register is floating, the output end of the first gating module 21 in the last-stage shift register may be floating, or connected to the second signal line X2 receiving a fixed potential signal. When the output end of the second gating module 22 of the first-stage shift register is connected to the first signal line X1 receiving a fixed potential signal, the output end of the first gating module 21 in the last-stage shift register may be floating, or connected to the second signal line X2 receiving a fixed potential signal, which is not specifically limited in the present disclosure.

[0075] The embodiment of the present disclosure introduces a first gating module 21 and a second gating module 22 for different shift registers, respectively, which are used to be electrically connected to the first control signal terminal S1N and the second control signal terminal S2N of the pixel driving circuit of different rows, and output scanning signals to the corresponding first control signal terminal S1N and the second control signal terminal S2N respectively. In an optional embodiment of the present disclosure, in the shift register, the first gating module 21 and the second gating module 22 have the same circuit structure. The same circuit structure mentioned here, for example, can be that the number of transistors included in the first gating module 21 and the second gating module 22 is the same, and the connection relationship between the transistors is the same. Considering that the first gating module 21 and the second gating module 22 have the same function and only the connected signal terminals are different, when the first gating module 21 and the second gating module 22 are formed by the same circuit structure, there is no need to introduce different circuits for the first gating module 21 and the second gating module 22, respectively, which is conducive to simplifying the overall circuit structure of the shift register. It should be noted that in the actual circuit layout, the circuit layout of the first enable module 21 and the second enable module 22 can be selected to be the same, or can be selected to be different according to actual needs. The present disclosure does not make specific limitations on this. In subsequent embodiments, the feasible circuit structures of the stage transmission module 10, the first enable module 21, and the second enable module 22 will be illustrated by examples.

[0076] Fig.10 The embodiment shown shows a scheme in which a group of gate driving circuits provide scanning signals to the first control signal terminal S1N and the second control signal terminal S2N in the same row of pixel driving circuits. In some other embodiments of the present disclosure, the first control signal terminal S1N and the second control signal terminal S2N in the same row of pixel driving circuits can also be driven by two groups of gate driving circuits respectively. For example, please refer to Fig.11 , Fig.11The figure shows another connection diagram of the shift register and the pixel driving circuit in the gate driving circuit. In an optional embodiment of the present disclosure, the display panel includes two groups of gate driving circuits 00, and the pixel driving circuit includes a first control signal terminal S1N and a second control signal terminal S2N; the first control signal terminal S1N of the pixel driving circuit in the same row is electrically connected to the shift registers 01 at the same level in the two groups of gate driving circuits 00, and the second control signal terminal S2N of the pixel driving circuit in the same row is electrically connected to the shift registers 01 at the same level in the two groups of gate driving circuits 00; the two shift registers 01 connected to the pixel driving circuit in the same row are respectively located on both sides of the pixel driving circuit in the row.

[0077] This embodiment shows a scheme in which two groups of gate driving circuits 00 are introduced on both sides of an array formed by pixel driving circuits, and the two groups of gate driving circuits jointly drive the pixel driving circuits. Taking the first row of pixel driving circuits as an example, each first control signal terminal S1N is respectively connected to the first selection module 21 in the first-stage shift register 01 in the two groups of gate driving circuits 00, and the two first selection modules 21 jointly provide scanning signals to each first control signal terminal S1N in the first row of pixel driving circuits, which is conducive to improving the overall driving capability of the panel, and improving the scanning efficiency and scanning effect of the pixel driving circuit. In particular, for the scheme in which a single shift register drives two rows of pixel driving circuits, since the number of pixel driving circuits loaded by a single shift register 01 is large, there may be a problem of weak driving capability. At this time, when two groups of gate driving circuits 00 are introduced to drive the pixel driving circuit, it is conducive to improving the overall driving capability of the gate driving circuit to the pixel driving circuit, and meeting the driving requirements of the display panel.

[0078] Please combine Figure 6 and Fig.11 In an optional embodiment of the present disclosure, the pixel driving circuit includes a driving transistor (the third transistor M3 is used as an example in the figure), a reset module 71 (the fifth transistor M5 is used as an example in the figure) and a threshold compensation module 72 (the fourth transistor M4 is used as an example in the figure), the reset module 71 is connected between the reset signal terminal Vref1 and the gate of the driving transistor M3, and the threshold compensation module 72 is connected between the gate of the driving transistor M3 and the first electrode of the driving transistor M3; the control end of the reset module 71 is connected to the first control signal terminal S1N, and the control end of the threshold compensation module 72 is connected to the second control signal terminal S2N; in a pixel driving circuit, the first control signal terminal S1N receives a scanning signal output by a first selection module 21 of a shift register, and the second control signal terminal S2N receives a scanning signal output by a second selection module 22 of another shift register.

[0079] In the embodiment of the present disclosure, the shift register introduced into the stage transmission module 10, the first selection module 21 and the second selection module 22 refers to a shift register that outputs a scanning signal to the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit, and the gate driving circuit mentioned in the embodiment of the present disclosure refers to a gate driving circuit that outputs a scanning signal to the first control signal terminal S1N and the second control signal terminal S2N in the pixel driving circuit.

[0080] Fig.12 FIG. 1 is a schematic diagram of a structure of a gate drive circuit provided in an embodiment of the present disclosure. Please refer to FIG. Fig.12 The level transmission module 10 includes a control unit 80 and a first output unit 91 and a second output unit 92 electrically connected to the control unit 80, the first output unit 91 and the control unit 80 are connected to a first node N1, and the second output unit 92 and the control unit 80 are connected to a second node N2; the first output unit 91 and the second output unit 92 output the level transmission signal NEXT according to the signal of the first node N1 and the signal of the second node N2; in this embodiment, the gating module 20 is configured to output a scanning signal according to the frequency control signal Ctrl, the signal of the first node N1, the signal of the second node N2, and the level transmission signal NEXT. In this embodiment, the gating module 20 also receives the level transmission signal NEXT.

[0081] Fig.13 FIG. 1 is another schematic diagram of the structure of the gate drive circuit provided by the embodiment of the present disclosure. Fig.12 and Fig.13 In this embodiment, the structure of the level transmission module 10 is refined. Optionally, the control unit 80 in the level transmission module 10 includes a first control module 81 and a second control module 81. The first control module 81 is used to receive the input signal IN, and control the signals of the third node N3 and the fourth node N4 in response to the first clock signal CK. The signal of the third node N3 is connected to the second node N2. The second control module 82 is used to receive the voltage signal VGH and the voltage signal VGL, and control the signal of the first node N1 in response to the signal of the third node N3, the signal of the fourth node N4, the first clock signal CK and the second clock signal XCK.

[0082] Exemplarily, the first control module 81 includes a transistor T13 and a transistor T14, the first electrode of transistor 13 is connected to the input signal terminal IN, the second electrode is connected to the fourth node N4, and the gate is connected to the first clock signal CK; the first electrode of transistor T14 is connected to the input signal terminal IN, the second electrode is connected to the third node N3, and the gate is connected to the first clock signal CK.

[0083] Exemplarily, the second control module 82 includes transistors T15 to T25, capacitor C4 and capacitor C5. The first electrode of transistor T15 receives a low-level signal VGL, the gate receives a first clock signal CK, and the second electrode is connected to node N0; the gate of transistor T16 is connected to the third node N3, the first electrode receives the first clock signal CK, and the second electrode is connected to node N0; the first electrode of transistor T17 is connected to node N0, the gate receives a low-level signal VGL, the second electrode is connected to the first plate of capacitor C4, and the second plate of capacitor C4 is connected to the first electrode of transistor T19; the first electrode of transistor T18 receives a second clock signal XCK, the gate is connected to the first plate of capacitor C4, and the second electrode is connected to the first electrode of transistor T19; the second electrode of transistor T19 is connected to the first node N1, and the gate receives the second clock signal XCK; the first electrode of transistor T20 receives a high-level signal VGH, and the second electrode is connected to The first electrode of the transistor T21 is connected to the third node N12, the second electrode is connected to the second node N2, and the gate receives the low level signal VGL; the first electrode of the transistor T22 is connected to the fourth node N4, the second electrode is connected to the first electrode of the transistor T23, and the gate receives the low level signal VGL; the first electrode and the gate of the transistor T23 are connected to the second electrode of the transistor T22, and the second electrode of the transistor T23 is connected to the second node N2; the first electrode plate of the capacitor C5 is connected to the gate of the transistor T23, and the second electrode plate is connected to the second electrodes of the transistors T24 and T25; the first electrode of the transistor T24 receives the low level signal VGL, and the gate is connected to the node N0; the first electrode of T25 receives the second clock signal XCK, and the gate is connected to the first electrode of the transistor M23.

[0084] Exemplarily, the first output unit 91 includes a transistor T11 and a capacitor C3, and the second output unit 92 includes a transistor T12, the gate of the transistor T11 is connected to the first node N1, the first electrode receives a high-level signal VGH, and the second electrode output stage transmits the signal NEXT; the first plate of the capacitor C3 receives the high-level signal VGH, and the second plate is connected to the gate of the transistor T11; the gate of the transistor T12 is connected to the second node N2, the first electrode receives a low-level signal VGL, and the second electrode output stage transmits the signal NEXT.

[0085] It should be noted that Fig.13 The circuit structure of the level transmission module shown is for illustration only and does not specifically limit the specific structure of the level transmission module. In some other embodiments of the present disclosure, the level transmission module may also adopt other feasible circuit structures.

[0086] Fig.14 Shown Fig.13 A driving timing diagram of the stage transmission module 10 of the shift register is shown below in combination with Fig.13 and Fig.14, the working principle and working process of the intermediate transmission module 10 are introduced:

[0087] In the Ta stage, the input signal IN is at a high level and the first clock signal CK is at a low level. At this time, the transistors T13, T14 and T15 are turned on, and the input signal IN is transmitted to the third node N3 and the fourth node N4 respectively through the transistors T13 and T14, so that the third node N3 and the fourth node N4 are both at a high level, and the transistors T16 and T20 are turned off; at the same time, the low-level signal VGL is transmitted to the node N0 through the transistor T15, the node N0 is at a low level, and the transistor T17 is normally open, then the node N5 is at a low level, the transistor T18 is turned on, the second clock signal XCK is at a high level, the node N6 remains at a high level, the transistor T19 is turned off, the first node N1 remains at a low level, the transistor T11 is turned on, and the high-level signal VGH is transmitted to the output end, so that the stage transfer signal NEXT is at a high level.

[0088] In the Tb stage, the input signal IN is at a high level, and the first clock signal CK is at a high level. At this time, the transistors T13, T14 and T15 are turned off, the third node N3 and the fourth node N4 remain at a high level, the transistors T16 and T20 are turned off, the node N0 remains at a low level, the transistor T18 is turned on, the second clock signal XCK is at a low level, and is transmitted to the node N6 through the transistor T18, so that the node N6 is at a low level, the transistor T19 is turned on, the signal of the node N6 is transmitted to the first node N1, the transistor T11 is turned on, and the high level signal VGH is transmitted to the output end, so that the stage transfer signal NEXT is at a high level.

[0089] In the Tc stage, the input signal IN is at a high level, and the first clock signal CK is at a low level. At this time, the transistors T13, T14 and T15 are turned on, and the input signal IN is transmitted to the third node N3 and the fourth node N4 respectively through the transistors T13 and T14, so that the third node N3 and the fourth node N4 are both at a high level, and the transistors T16 and T20 are turned off; at the same time, the low-level signal VGL is transmitted to the node N0 through the transistor T15, the node N0 is at a low level, and the transistor T17 is normally open, then the node N5 is at a low level, the transistor T18 is turned on, the second clock signal XCK is at a high level, the node N6 remains at a high level, the transistor T19 is turned off, the first node N1 remains at a low level, the transistor T11 is turned on, and the high-level signal VGH is transmitted to the output end, so that the stage transfer signal NEXT is at a high level.

[0090] In the Td stage, the input signal IN is at a low level, the first clock signal CK is at a high level, the transistors T13, T14 and T15 are all turned off, the third node N3 and the fourth node N4 are both kept at a high level, and the transistors T16 and T20 are both turned off; the node N0 is kept at a low level, and the transistor T17 is normally open, then the node N5 is at a low level, the transistor T18 is turned on, the second clock signal XCK is at a low level, and the second clock signal XCK is transmitted to the node N6 through the transistor T18, so that the node N6 is at a low level; at the same time, the transistor T19 is turned on, the signal of the node N6 is transmitted to the first node N1 at a low level, the transistor T11 is turned on, and the high level signal VGH is transmitted to the output end, so that the stage transfer signal NEXT is at a high level.

[0091] In the Te phase, the input signal IN is at a low level, the first clock signal CK is at a low level, the transistors T13, T14 and T15 are turned on, the input signal IN is transmitted to the third node N3 and the fourth node N4 respectively through the transistors T13 and T14, so that the third node N3 and the fourth node N4 are both at a low level, the transistors T16 and T20 are turned on; at the same time, the transistor T15 is turned on, the low level signal VGL is transmitted to the node N0 through the transistor T15, the node N0 is at a low level, and the transistor T17 is normally open, then the node N5 is low. level, transistor T18 is turned on, the second clock signal XCK is high, the node N6 maintains a high level, and the transistor T19 is turned off; the transistor T20 is turned on, and the high-level signal VGH is transmitted to the first node N1 through the transistor T20, so that the first node N1 is high level, and the transistor T11 is turned off; at the same time, the transistor T21 and the transistor T22 are normally open, and the signal of the third node N3 is transmitted to the second node N2, so that the second node N2 is low level, the transistor T12 is turned on, and the low-level signal VGL is transmitted to the output end, so that the stage transfer signal NEXT is low level.

[0092] It can be seen that in the Ta~Td stage, when the level transfer signal NEXT is output at a high level, one of the first node N1 and the second node N2 is at a low level and the other is at a high level. The embodiment of the present disclosure is explained by taking the level of the first node N1 as a low level and the level of the second node as a high level as an example.

[0093] Please continue to refer to Fig.12 and Fig.13In this embodiment, the first gating module 21 and the second gating module 22 are electrically connected to the first node N1 and the second node N2 in the level transmission module 10, respectively, and also receive the level transmission signal NEXT and the frequency control signal Ctrl_1 / Ctrl_2 respectively. The first gating module 21 and the second gating module 22 can output the scanning signal according to the frequency control signal Ctrl_1 / Ctrl_2, the signal of the first node N1, the signal of the second node N2, and the level transmission signal NEXT. The following will be described in conjunction with the specific structure of the gating module.

[0094] Please refer to Fig.15 , Fig.15 FIG. 2 is a schematic diagram of a structure of a first gating module 21 and a second gating module 22 provided in an embodiment of the present disclosure. Fig.13 and Fig.15 In an optional embodiment of the present disclosure, the gating module includes a first output unit 31, a second output unit 32, an isolation protection unit 33 and an output control unit 34, the control end of the isolation protection unit 33 receives the level transmission signal NEXT, the input end of the isolation protection unit 33 receives the frequency control signal Ctrl_1 / Ctrl_2, and the output end of the isolation protection unit 33 is connected to the control end of the output control unit 34; the input end of the output control unit 34 receives the signal of the first node N1, and the output end is connected to the control end of the first output unit 31; the input end of the first output unit 31 receives the first level signal VGH, and the output end is connected to the output end S1N_OUT / S2N_OUT of the gating module; the control end of the second output unit 32 receives the signal of the second node N2, the input end receives the second level signal VGL, and the output end is connected to the output end S1N_OUT / S2N_OUT of the gating module. Optionally, the gating module also includes a node control module 35, the control end of the node control module 35 receives the signal of the first node N1, the input end receives the first level signal VGH, and the output end is connected to the control end of the first output unit 31, for controlling the signal of the control end of the first output unit 31. Optionally, a capacitor may be introduced between the control terminal of the first output unit 31 and the first level signal terminal VGH, which may also play a role in maintaining the signal at the control terminal of the first output unit 31 .

[0095] Exemplarily, the isolation protection unit 33 includes a transistor T3 and a capacitor, the output control unit 34 includes a transistor T4, the first output unit 31 includes a transistor T1, and the second output unit 32 includes a transistor T2, wherein the gate of the transistor T3 receives a level transmission signal, the first electrode receives a frequency control signal Ctrl_1 / Ctrl_2, and the second electrode is connected to the gate of the transistor T4; the first electrode of the transistor T4 is connected to the first node N1 in the level transmission module 10, the second electrode is connected to the gate of the transistor T1, the first electrode of the transistor T1 receives a first level signal VGH, and the second electrode is connected to the output end of the gating module. The gate of the transistor T2 is connected to the first node in the level transmission module 10, the first electrode receives a second level signal VGL, and the second electrode is connected to the output end S1N_OUT / S2N_OUT of the gating module.

[0096] Fig.16 Shown Fig.15 A working timing diagram of the gate module in the middle, which reflects the working status of the gate module when the frequency control signal Ctrl_1 / Ctrl_2 is a low-level signal. Please refer to Fig.15 and Fig.16 , in the stage where the output of the level transmission signal is at a low level, the transistor T3 is turned on, the low level signal of the frequency control signal is transmitted to the gate of the transistor T4 through the transistor T3, and the transistor T4 is controlled to be turned on, the high level signal of the first node N1 is transmitted to the transistor T1 through the transistor T4, so that the transistor T1 is turned off, the low level signal of the second node N2 is transmitted to the transistor T2, the transistor T2 is turned on, the second level signal VGL is transmitted to the output end of the gating module through the transistor T2, and the output end of the gating module outputs a low level signal. In the stage where the output of the level transmission signal is at a high level, the second node N2 is at a high level, the first node N1 is at a low level, the transistor T2 is turned off, the transistor T3 is turned off, the transistor T4 remains turned on, the low level signal of the first node N1 is transmitted to the gate of the transistor T1, the transistor T1 is turned on, the first level signal VGH is transmitted to the output end of the gating module through the transistor T1, and the output end S1N_OUT / S2N_OUT of the gating module outputs a high level signal. Therefore, when the frequency control signal is at a low level, the output signal of the gating module will not be affected by the frequency control signal, and the gating module can output the scanning signal normally.

[0097] Fig.17 Shown Fig.15 Another working timing diagram of the gate module in the middle reflects the working condition of the gate module when the frequency control signal is a high-level signal. Please refer to Fig.15 and Fig.17, when the level transmission signal output is at a low level, transistor T3 is turned on, and the high level signal of the frequency control signal is transmitted to transistor T4, so that transistor T4 is turned off, and the signal of the first node N1 cannot be transmitted to the gate of transistor T1; at this time, the potential of the second node N2 is at a low level, and the control transistor T2 is turned on, and the second level signal VGL is transmitted to the output end of the gating module through transistor T2, and the output end of the gating module outputs a low level signal. When the level transmission signal jumps to a high level signal, transistor T3 is turned off, and transistor T4 remains in a cut-off state, and the signal of the first node N1 still cannot be transmitted to the gate of transistor T1, and transistor T1 remains cut off, and the high level of the second node N2 controls transistor T2 to be cut off, and the output end of the gating module remains at the low level of the previous stage. Therefore, when the frequency control signal is at a high level, the scanning signal output by the output end of the gating module only includes an invalid level signal.

[0098] Therefore, when the frequency control signal is at a low level, the gating module can output the scanning signal normally. When the frequency control signal changes from a low level signal to a high level signal, the gating module can only output an invalid level signal.

[0099] It should be noted that the function of the transistor T3 in the isolation protection unit 33 is to be cut off when the level transmission signal outputs a high level. If the frequency control signal jumps, the frequency control signal cannot be written into the gate of the transistor T4 until the level transmission signal jumps to a low level. The changed frequency control signal is then written into the gate of the transistor T4, thereby helping to avoid the problem of incomplete output signal of the selection module due to the change of the frequency control signal when the level transmission signal is halfway transmitted.

[0100] The following will be combined Fig.18 The working process of the display panel in the embodiment of the present disclosure when implementing partition refresh is described. Fig.18 FIG. 1 is a driving timing diagram of a pixel driving circuit by a gate driving circuit provided by an embodiment of the present disclosure. Fig.11Taking the architecture shown as an example, the first row pixel driving circuit and the second row pixel driving circuit are taken as a whole, each first control signal terminal S1N is connected to the output end of the first gating module 21 in the first stage shift register, and each second control signal terminal S2N is connected to the output end of the second gating module 22 in the second stage shift register. The third row pixel driving circuit and the fourth row pixel driving circuit are taken as a whole, each first control signal terminal S1N is connected to the output end of the first gating module 21 in the second stage shift register, and each second control signal terminal S2N is connected to the output end of the second gating module 22 in the third stage shift register. The fifth row pixel driving circuit and the sixth row pixel driving circuit are taken as a whole, each first control signal terminal S1N is connected to the output end of the first gating module 21 in the third stage shift register, and each second control signal terminal S2N is connected to the output end of the second gating module 22 in the fourth stage shift register.

[0101] Fig.18 In the above, NEXT(1) to NEXT(4) represent the level transmission signals outputted by the first to fourth shift registers, respectively; S1N_OUT(1) to S1N_OUT(4) represent the scanning signals outputted by the output ends of the first selection modules 21 in the first to fourth shift registers, respectively; S2N_OUT(1) to S2N_OUT(4) represent the scanning signals outputted by the output ends of the second selection modules 22 in the first to fourth shift registers, respectively. The first control signal terminal S1N of the pixel driving circuit of the second row receives the signal S1N_OUT(1), and the second control signal terminal S2N receives the signal S2N_OUT(2); the first control signal terminal S1N of the pixel driving circuit of the third and fourth rows receives the signal S1N_OUT(2), and the second control signal terminal S2N receives the signal S2N_OUT(3); the first control signal terminal S1N of the pixel driving circuit of the fifth and sixth rows receives the signal S1N_OUT(3), and the second control signal terminal S2N receives the signal S2N_OUT(4). Ctrl_1 represents the frequency control signal received by each first gating module 21 in each level of shift register; Ctrl_2 represents the frequency control signal received by each second gating module 22 in each level of shift register.

[0102] In the stage where the frequency control signals Ctrl_1 and Ctrl_2 are both at low levels, the pixel driving circuits in the 1st and 2nd rows and the pixel driving circuits in the 3rd and 4th rows all receive valid level signals in the scanning signal. When the third-stage shift register outputs the valid level signal in the stage transmission signal, the first frequency control signal Ctrl_1 has jumped from a low level signal to a high level signal, and the second frequency control signal Ctrl_2 is still a low level signal. Therefore, the second selection module 22 in the third-stage shift register can still output the scanning signal containing the valid level signal to the pixel driving circuits in the 3rd and 4th rows, while the first selection module 21 outputs the scanning signal containing only the invalid level signal to the pixel driving circuits in the 5th and 6th rows, and does not reset the gates of the driving transistors in the pixel driving circuits in the 5th and 6th rows. When the fourth-stage shift register outputs a valid level signal in the stage transmission signal, the second frequency control signal has jumped from a low level signal to a high level signal, and the first frequency control signal remains a high level signal, so the scanning signals output by the first gating module 21 and the second gating module 22 of the fourth-stage shift register only include invalid level signals, and starting from the 5th and 6th row pixel driving circuits, the subsequent pixel driving circuits are all reflected as not being refreshed. In this way, the partition refresh effect of refreshing the pixel driving circuits of the 1st to 4th rows normally and not refreshing the pixel driving circuits of the 5th row is achieved.

[0103] Since the first selection module 21 and the second selection module 22 are introduced into the shift register in the embodiment of the present disclosure, the first selection module 21 and the second selection module 22 in the same shift register can output different scanning signals, for example, one includes a valid level signal and the other does not include a valid level signal, so that the pixel driving circuits with different refresh requirements can receive the correct scanning signal, which is beneficial to improving the display accuracy during partition refresh.

[0104] Fig.19 FIG. 1 is another schematic diagram of the structure of the gate driving circuit provided by the embodiment of the present disclosure, Fig.12 In contrast, in this embodiment, in the same shift register 00, the first gating module 21 and the second gating module 22 are not connected to the level transmission signal NEXT output by the level transmission module 10. Fig.19 In an optional embodiment of the present disclosure, the level transmission module 10 includes a control unit 80 and a first output unit 91 and a second output unit 92 electrically connected to the control unit 80, the first output unit 91 and the control unit 80 are connected to a first node N1, and the second output unit 92 and the control unit 80 are connected to a second node N2; the first output unit 91 and the second output unit 92 output the level transmission signal NEXT according to the signal of the first node N1 and the signal of the second node N2; the selection module 20 is configured to output a scanning signal according to the frequency control signal Ctrl_1 / Ctr_2, the signal of the first node N1 and the signal of the second node N2.

[0105] It should be noted that the specific structure, circuit and working principle of the intermediate transmission module 10 in this embodiment can be referred to Fig.13 and Fig.14 The embodiments shown in the figure are not described in detail in this disclosure. Fig.13 and Fig.14 It can be seen from the illustrated embodiment that in the Ta~Td stage, when the level transfer signal NEXT is output at a high level, one of the first node N1 and the second node N2 is at a low level and the other is at a high level. The embodiment of the present disclosure is described by taking the first node N1 as having a low level and the second node N2 as having a high level as an example.

[0106] Fig. 20 Shown with Fig.19 A structural diagram of the gating module corresponding to the embodiment, please refer to Fig.19 and Fig. 20 In an optional embodiment of the present disclosure, the first gating module 21 and the second gating module 22 in the gating module 20 respectively include a first output unit s1 and a second output unit s2, the control end of the first output unit s1 receives the signal of the first node N1, the input end receives the frequency control signal Ctrl_1 / Ctrl_2, and the output end is connected to the output end S1N_OUT / S2N_OUT of the gating module; the control end of the second output unit s2 receives the signal of the second node N2, the input end receives the second level signal VGL, and the output end is connected to the output end S1N_OUT / S2N_OUT of the gating module. Optionally, the frequency control signal received by the first gating module 21 is the first frequency control signal Ctrl_1, and the frequency control signal received by the second gating module 22 is the second frequency control signal Ctrl_2.

[0107] In this embodiment, the first gating module 21 and the second gating module 22 are electrically connected to the first node N1 and the second node N2 in the stage transmission module 10, respectively, and also receive the frequency control signal Ctrl_1 / Ctrl_2, respectively. The first gating module 21 and the second gating module 22 can output scanning signals according to the frequency control signal Ctrl_1 / Ctrl_2, the signal of the first node N1, and the signal of the second node N2, respectively.

[0108] Please continue to refer to Fig. 20, exemplarily, the first output unit s1 in the first gating module 21 includes a transistor T26, the second output unit 32 includes a transistor T27, the first output unit s1 in the second gating module 22 includes a transistor T28, the second output unit 32 includes a transistor T29, when the signal of the first node N1 controls the transistor T26 to turn on, the first frequency control signal Ctrl_1 will be output from the output end S1N_OUT of the first gating module 21 as a scanning signal. Similarly, when the signal of the first node N1 controls the transistor T28 to turn on, the second frequency control signal Ctrl_2 will be output from the output end S2N_OUT of the second gating module 22 as a scanning signal. In this way, in the scanning stage, when the gating module needs to output a valid level signal of the scanning signal, the frequency control signal containing the valid level can be output as the scanning signal through the first output unit 31. When the gating module needs to output an invalid level signal of the scanning signal, the frequency control signal not containing the valid level is also output as the scanning signal through the first output unit 31. By adjusting the frequency control signal, different output requirements of the gating module can be met.

[0109] When the first gating module 21 and the second gating module 22 are respectively embodied as Fig. 20 In the structure shown, the first selection module 21 and the second selection module 22 respectively include two transistors, and the gates of the two transistors are respectively connected to the first node N1 and the second node N2 in the stage transmission module 10, and the conduction of the transistors is controlled by the potentials of the first node N1 and the second node N2. At this time, the selection module can output a scanning signal according to the frequency control signal, the signal of the first node and the signal of the second node. In addition, in the present disclosure, the first selection module 21 and the second selection module 22 are respectively composed of two transistors, and the structure is relatively simple, which is conducive to simplifying the overall structure of the gate drive circuit and reducing the space occupied by the gate drive circuit in the display panel, so it is conducive to realizing a narrow frame design of the display panel.

[0110] Based on the same inventive concept, the present disclosure also provides a method for driving a display panel. Fig.21 FIG. 1 is a flow chart of a method for driving a display panel provided in an embodiment of the present disclosure. The method is used to drive the display panel in the above-mentioned embodiment. Fig.21 , Fig.11 , Figures 16 to 18 , wherein the first gating module 21 receives the first frequency control signal Ctrl_1, and the second gating module 22 receives the second frequency control signal Ctrl_2, and the driving method includes:

[0111] S01 . Control the first frequency control signal and the second frequency control signal to maintain the same potential in at least one display frame.

[0112] S02, controlling the first frequency control signal and the second frequency control signal to perform a potential jump in at least one display frame, the display frame including a first stage T01 and a second stage T02, in the first stage T01, the first frequency control signal Ctrl_1 and the second frequency control signal Ctrl_2 maintain the same potential; in the second stage T02, the first frequency control signal Ctrl_1 and the second frequency control Ctrl_2 signals undergo a potential jump, and the potential jump time of the first frequency control signal is earlier than the potential jump time of the second frequency control signal.

[0113] It should be noted that there is no order of precedence for the two steps S02 and S03 mentioned in the method.

[0114] When the first frequency control signal and the second frequency control signal are controlled to maintain the same potential in the display frame, for example, the first frequency control signal and the second frequency control signal can both be reflected as low-level signals. Fig.16 At this time, each shift register can normally output the effective level signal in the scanning signal, and each row of pixel driving circuits can be refreshed. In a display frame, when the first frequency control signal and the second frequency control signal are both high-level signals, for example, please refer to Fig.17 , the scanning signals output by each shift register only include invalid level signals, and the pixel driving circuits of each row will not be refreshed.

[0115] When the potential jump of the first frequency control signal and the second frequency control signal occurs in a display frame, some pixel circuit rows can be controlled to be refreshed, while other pixel circuit rows can be controlled not to be refreshed. Fig.11 and Fig.18In the first stage T01, assuming that the first frequency control signal and the second frequency control signal are both low-level signals, the shift registers located at the first to third stages can output a scanning signal including a valid level signal to achieve the refresh of the pixel driving circuits of the 1st to 4th rows. In the second stage T02, when the shift register of the third stage outputs a valid level signal in the stage transmission signal, the first frequency control signal Ctrl_1 first jumps from a low level to a high level, and the second frequency control signal Ctrl_2 is still a low level signal, so the second gating module 22 in the third stage shift register can still output a scanning signal including a valid level signal to the pixel driving circuits of the 3rd and 4th rows, while the first gating module 21 outputs a scanning signal including only an invalid level signal to the pixel driving circuits of the 5th and 6th rows, and does not reset the gates of the driving transistors in the pixel driving circuits of the 5th and 6th rows. When the valid level signal in the output stage transmission signal of the fourth-stage shift register is transmitted, the second frequency control signal Ctrl_2 has jumped from a low level signal to a high level signal, and the first frequency control signal Ctrl_1 is maintained as a high level signal, so the scanning signals output by the first gating module 21 and the second gating module 22 of the fourth-stage shift register only include invalid level signals, and starting from the 5th and 6th row pixel driving circuits, the subsequent pixel driving circuits are all reflected as not being refreshed. In this way, the partition refresh effect of refreshing the pixel driving circuits of the 1st to 4th rows normally and not refreshing the pixel driving circuits of the 5th row is achieved.

[0116] Since the first selection module 21 and the second selection module 22 are introduced into the shift register in the embodiment of the present disclosure, the first selection module 21 and the second selection module 22 in the same shift register can output different scanning signals, for example, one includes a valid level signal and the other does not include a valid level signal, so that the pixel driving circuits with different refresh requirements can receive the correct scanning signal, which is beneficial to improving the display accuracy during partition refresh.

[0117] Based on the same inventive concept, the present disclosure also provides a display device, Fig. 22 FIG. 2 is a schematic diagram of a structure of a display device 200 provided in an embodiment of the present disclosure. Fig. 22 , the display device 200 includes the display panel 100 in any of the above embodiments. The display device 200 provided in the embodiment of the present disclosure may be any electronic device with a display function, such as a touch screen, a mobile phone, a tablet computer, a laptop computer, an e-book, or a television. The display device 200 provided in the embodiment of the present disclosure has the beneficial effects of the display panel provided in the embodiment of the present disclosure. For details, please refer to the specific description of the display panel in the above embodiments, which will not be repeated in this embodiment.

[0118] Understandably, Fig. 22Only a rounded rectangular structure is used as an example to illustrate one shape of the display device 200. In some other embodiments of the present disclosure, the display device 200 may also be circular, elliptical or any other feasible shape, and the present disclosure does not specifically limit this.

[0119] In summary, the technical solution provided by the embodiments of the present disclosure has the following advantages:

[0120] In the display panel and its driving method and display device provided by the embodiments of the present disclosure, the same shift register can output two scanning signals through the first gating module and the second gating module respectively. Among them, in at least some shift registers, the output end of the first gating module and the output end of the second gating module are respectively connected to the pixel driving circuits of different rows. Assuming that in the same shift register, the first gating module is connected to the pixel driving circuit of the a-th row, and the second gating module is connected to the pixel driving circuit of the b-th row, when the refresh requirements for different display areas are different, for example, when the pixel driving circuit of the a-th row needs to be refreshed, and the pixel driving circuit of the b-th row does not need to be refreshed, the first gating module can output the effective level signal of the scanning signal to the pixel driving circuit of the a-th row to refresh the pixel driving circuit of the a-th row, and the second gating module can output the invalid level signal of the scanning signal to the pixel driving circuit of the b-th row, without refreshing the pixel driving circuit of the b-th row, so that the pixel driving circuits with different refresh requirements can all receive the correct scanning signal, which is conducive to improving the display accuracy during the partition refresh.

[0121] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0122] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A display panel, characterized in that: It includes a gate driving circuit and a plurality of pixel driving circuits, wherein the gate driving circuit includes N-stage shift registers cascaded to each other, where N≥2; One of the shift registers includes a level transmission module and at least two gating modules connected to the level transmission module, and the gating module includes a first gating module and a second gating module; The level transmission module is used to output a level transmission signal, the level transmission signal of the i-th level shift register is the input signal of the j-th level shift register, 1≤i≤N, 1≤j≤N, i≠j; The first gating module and the second gating module are configured to at least receive a frequency control signal and output a scanning signal through the output ends of the first gating module and the second gating module; wherein, in at least part of the shift register, the output end of the first gating module and the output end of the second gating module are respectively connected to the pixel driving circuits of different rows.

2. The display panel according to claim 1, characterized in that: In at least one display frame, the first gating module and the second gating module in at least one shift register are configured to receive different frequency control signals, respectively.

3. The display panel according to claim 2, characterized in that: In the at least one display frame, in at least one of the shift registers, one of the frequency control signal received by the first gating module and the frequency control signal received by the second gating module is a high level signal and the other is a low level signal.

4. The display panel according to claim 2, characterized in that: In at least one display frame, in at least one shift register, the scanning signal transmitted by the first selection module to the corresponding pixel driving circuit includes a valid level signal, and the scanning signal output by the second selection module to the corresponding pixel driving circuit does not include a valid level signal; or, the scanning signal transmitted by the first selection module to the corresponding pixel driving circuit does not include a valid level signal, and the scanning signal output by the second selection module to the corresponding pixel driving circuit includes a valid level signal.

5. The display panel according to claim 1, characterized in that: In at least one display frame, the two gating modules in the shift register are configured to receive the same frequency control signal.

6. The display panel according to claim 5, characterized in that: In the at least one display frame and in at least one shift register, the scanning signals transmitted by the first gating module and the second gating module to the corresponding pixel driving circuit both include valid level signals or neither include valid level signals.

7. The display panel according to claim 1, characterized in that: The pixel driving circuit comprises a first control signal terminal and a second control signal terminal, wherein the first control signal terminal and the second control signal terminal are configured to receive different scanning signals output by the shift register; In the pixel driving circuits of the sth and pth rows, the second control signal terminal is connected to the output terminal of the second selection module in the mth level shift register, and the first control signal terminal is connected to the output terminal of the first selection module in the nth level shift register, s≥1, p≥1, s≠p, m>n≥1.

8. The display panel according to claim 7, characterized in that: In at least one display frame, the scanning signals received by the first control signal terminal and the second control signal terminal in the pixel driving circuit in the same row both include valid level signals; or, the scanning signals received by the first control signal terminal and the second control signal terminal in the pixel driving circuit in the same row do not include valid level signals.

9. The display panel according to claim 7, characterized in that: p=s+1,mn=1.

10. The display panel according to claim 9, characterized in that: In the pixel driving circuits of the p+1th row and the p+2th row, the second control signal terminal is connected to the output terminal of the second selection module in the m+1th level shift register, and the first control signal terminal is connected to the output terminal of the first selection module in the mth level shift register.

11. The display panel according to claim 1, characterized in that: The display panel includes C circuit groups, and one circuit group includes at least one row of pixel driving circuits; wherein C≥1, N≥C+1; The pixel driving circuit includes a first control signal terminal and a second control signal terminal, and the first control signal terminal and the second control signal terminal are configured to receive scanning signals output by different shift registers; in one circuit group, the first control signal terminal of the pixel driving circuit is connected to the output terminal of the first selection module in one shift register, and the second control signal terminal of the pixel driving circuit is connected to the output terminal of the second selection module in another shift register.

12. The display panel according to claim 11, characterized in that: In the gate driving circuit, at least the output end of the second gating module in the shift register of the first stage is floated or connected to a first signal line, and the first signal line is not connected to the pixel driving circuit; And / or, at least the output end of the first gating module in the shift register at the last stage is floated or connected to a second signal line, and the second signal line is not connected to the pixel driving circuit.

13. The display panel according to claim 1, characterized in that: In the shift register, the first gating module and the second gating module have the same circuit structure.

14. The display panel according to claim 1, characterized in that: The display panel includes two groups of gate driving circuits, and the pixel driving circuit includes a first control signal terminal and a second control signal terminal; the first control signal terminal of the pixel driving circuits in the same row is electrically connected to the shift registers at the same level in the two groups of gate driving circuits, and the second control signal terminal of the pixel driving circuits in the same row is electrically connected to the shift registers at the same level in the two groups of gate driving circuits; the two shift registers connected to the pixel driving circuits in the same row are respectively located on both sides of the pixel driving circuits in the row.

15. The display panel according to claim 1, characterized in that: The pixel driving circuit comprises a first control signal terminal and a second control signal terminal, wherein the first control signal terminal and the second control signal terminal are configured to receive different scanning signals output by the shift register; The pixel driving circuit comprises a driving transistor, a reset module and a threshold compensation module, wherein the reset module is connected between a reset signal terminal and a gate of the driving transistor, and the threshold compensation module is connected between the gate of the driving transistor and a first electrode of the driving transistor; a control terminal of the reset module is connected to the first control signal terminal, and a control terminal of the threshold compensation module is connected to the second control signal terminal; In one of the pixel driving circuits, the first control signal terminal receives a scanning signal output by the first selection module of one of the shift registers, and the second control signal terminal receives a scanning signal output by the second selection module of another of the shift registers.

16. The display panel according to claim 1, characterized in that: The level transmission module includes a control unit and a first output unit and a second output unit electrically connected to the control unit, wherein the first output unit and the control unit are connected to a first node, and the second output unit and the control unit are connected to a second node; the first output unit and the second output unit output the level transmission signal according to the signal of the first node and the signal of the second node; The gating module is configured to output the scanning signal according to at least the frequency control signal, the signal of the first node, and the signal of the second node.

17. The display panel according to claim 16, characterized in that: The gating module is configured to output the scanning signal further according to the level transfer signal.

18. The display panel according to claim 17, characterized in that: The gating module comprises a first output unit, a second output unit, an isolation protection unit and an output control unit, wherein the control end of the isolation protection unit receives the level transmission signal, the input end of the isolation protection unit receives the frequency control signal, and the output end of the isolation protection unit is connected to the control end of the output control unit; The input end of the output control unit receives the signal of the first node, and the output end is connected to the control end of the first output unit; The input end of the first output unit receives a first level signal, and the output end is connected to the output end of the gating module; The control end of the second output unit receives the signal of the second node, the input end receives the second level signal, and the output end is connected to the output end of the gating module.

19. The display panel according to claim 16, characterized in that: The gating module includes a first output unit and a second output unit, wherein the control end of the first output unit receives the signal of the first node, the input end receives the frequency control signal, and the output end is connected to the output end of the gating module; the control end of the second output unit receives the signal of the second node, the input end receives the second level signal, and the output end is connected to the output end of the gating module.

20. A method for driving a display panel, characterized in that: Used to drive the display panel according to any one of claims 1 to 19, wherein the first gating module receives a first frequency control signal, the second gating module receives a second frequency control signal, and the driving method comprises: Controlling the first frequency control signal and the second frequency control signal to maintain the same potential in at least one display frame; The first frequency control signal and the second frequency control signal are controlled to undergo a potential jump in at least one display frame, the display frame comprising a first stage and a second stage, in the first stage, the first frequency control signal and the second frequency control signal maintain the same potential; in the second stage, the first frequency control signal and the second frequency control signal undergo a potential jump, and the potential jump time of the first frequency control signal is earlier than the potential jump time of the second frequency control signal.

21. A display device, characterized in that: The display panel comprises any one of claims 1 to 19.

Images