Goa device, gate driving circuit and display panel

Abstract

The embodiment of the present application discloses a GOA device, comprising a plurality of GOA units connected in cascade, the Nth GOA unit comprising a pull-up control unit, a pull-up unit, a pull-down unit and a pull-down control unit; the pull-up control unit being connected with a gate signal point; the pull-down control unit being connected with the gate signal point and the pull-down unit, the pull-down unit being connected with the Nth horizontal scanning line; the pull-up unit being connected with the Nth horizontal scanning line; the Nth GOA unit comprising a first switch, the first switch being connected with a node voltage of the N+mth GOA unit and the pull-up unit, the working time of the first switch and the working time of the Nth GOA unit not being at the same time, wherein m is a positive integer and m>0. The embodiment of the present application enhances the driving ability of the thin film transistor of the GOA unit by adding a first switch controlled by the node voltage of the N+mth GOA unit, reduces the rising time and the falling time of the scanning signal, and thus the display error charging condition can be prevented.

Description

Technical Field

[0001] This invention relates to the field of liquid crystal display technology, and particularly to a GOA device, a gate driving circuit, and a display panel. Background Technology

[0002] With the development of LCD screens, more and more display panels are using GOA (Gate Driver on Array) circuits to drive horizontal scan lines, in order to reduce costs and obtain display panels with narrow bezels.

[0003] However, as the variety of displays on the market increases, consumers are increasingly focusing on image detail, leading to a growing demand for high-resolution and high-refresh-rate displays. High-resolution and high-refresh-rate displays, however, also increase the capacitor and resistor load on the circuitry. This can increase the fall time for each scan line, potentially causing incorrect charging to the next scan line and resulting in display abnormalities. Summary of the Invention

[0004] In view of at least some of the problems and deficiencies in the prior art, embodiments of the present invention disclose a GOA device, a gate driving circuit, and a display panel to solve the problem that existing GOA circuits may mischarge to the next scan line due to the increase in the fall time of the scan line.

[0005] On one hand, the GOA device provided in this embodiment of the invention includes multiple cascaded GOA units. The Nth-level GOA unit is used to output a gate drive signal to the Nth-level horizontal scan line. The Nth-level GOA unit is characterized by comprising: a pull-up control unit, a pull-up unit, a pull-down unit, and a pull-down control unit; wherein the pull-up control unit is connected to the gate signal point; the pull-down control unit is connected to the gate signal point and the pull-down unit, and the pull-down unit is connected to the Nth-level horizontal scan line; the pull-up unit is connected to the Nth-level horizontal scan line; wherein the Nth-level GOA unit further includes a first switch, the first switch is connected to the node voltage of the (N+m)th-level GOA unit, and the first switch is connected to the pull-up unit. The node voltage of the (N+m)th-level GOA unit is used to control the opening and closing of the first switch, wherein the operating time of the first switch is not at the same time as the operating time of the Nth-level GOA unit, where m is a positive integer and m>0.

[0006] The GOA device provided in this embodiment of the invention enhances the driving capability of the GOA unit's node voltage on the scan line controlled by the thin-film transistor by adding a first switch controlled by the node voltage of the N+m level GOA unit, and the working time of the first switch is not at the same time as the working time of the Nth level GOA unit. This reduces the rise time and fall time of the scan signal, thereby preventing display mischarging.

[0007] In one embodiment of the present invention, the pull-down control unit is connected to the (N+n)th level horizontal scan line, the pull-up control unit is connected to a start signal, and the pull-up unit is connected to a clock signal, the clock signal comprising M lines, where n is a positive integer, n = M / 2, 0 <m<n。

[0008] In one embodiment of the present invention, the first terminal of the first switch is connected to the gate signal point of the (N+m)th level GOA unit, the second terminal of the first switch is connected to the clock signal or a signal with the same frequency as the clock signal, the third terminal of the first switch is connected to the Nth level horizontal scan line, and the pull-up unit is connected to the Nth level horizontal scan line.

[0009] In one embodiment of the present invention, the first terminal of the first switch is connected to the transmission signal point of the N+m level GOA unit, the second terminal of the first switch is connected to the clock signal or a signal with the same frequency as the clock signal, the third terminal of the first switch is connected to the Nth level horizontal scan line, and the pull-up unit is connected to the Nth level horizontal scan line.

[0010] In one embodiment of the present invention, when the clock signal connected to the Nth level GOA unit switches from a low level H0 to a high level H1, the voltage of the gate signal point in the Nth level GOA unit is a second voltage H3; during the time period when the clock signal connected to the Nth level GOA unit is at a high level H1 and the clock signal connected to the N+m level GOA unit is at a low level H0, the first switch is in the open state, and the voltage of the gate signal point in the N+m level GOA unit connected to the first switch is coupled from a first voltage H2 to a first intermediate voltage H4 during the time period, wherein H2 <H4<H3。

[0011] In one embodiment of the present invention, when the clock signal accessed in the Nth level GOA unit switches from the high level H1 to the low level H0, the voltage of the gate signal point in the Nth level GOA unit is switched to the low level H0; during the time period when the clock signal accessed in the Nth level GOA unit is at a low level H0 and the clock signal accessed in the N+m level GOA unit is at a high level H1, the first switch is in the open state, and the voltage of the gate signal point of the N+m level GOA unit connected to the first switch is coupled from the second voltage H3 to the second intermediate voltage H5, wherein H0 <H4<H3。

[0012] In one embodiment of the present invention, during the time period when the clock signal connected to the Nth level GOA unit is low (H0) and the clock signal connected to the (N+m)th level GOA unit is high (H1), the first switch is in the open state, and the voltage of the intermediate signal transmission point in the Nth level GOA unit is coupled from the third voltage H6 to the third intermediate voltage H7 during the time period, wherein H0 <H7<H6,H6≤H1。

[0013] On the other hand, embodiments of the present invention provide a gate driving circuit, such as including the aforementioned GOA device.

[0014] In another aspect, embodiments of the present invention provide a display panel, including, for example, the aforementioned gate driving circuit.

[0015] As can be seen from the above, the technical features of the present invention can have one or more of the following beneficial effects: The GOA device provided by the embodiments of the present invention, by adding a first switch controlled by the node voltage of the N+m level GOA unit, and the working time of the first switch is not at the same time as the working time of the Nth level GOA unit, enhances the driving capability of the node voltage of the GOA unit for the thin film transistor controlled by the scan line, reduces the rise time and fall time of the scan signal, and thus can prevent the display from being incorrectly charged. Attached Figure Description

[0016] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0017] Figure 1 A circuit example diagram of a traditional GOA unit in related technologies.

[0018] Figure 2 for Figure 1Timing waveform diagram of a traditional GOA unit.

[0019] Figure 3 This invention provides an exemplary circuit module diagram of an Nth-level GOA device.

[0020] Figure 4 for Figure 3 Another exemplary circuit module diagram of the Nth level GOA device.

[0021] Figure 5 This is a schematic diagram of the timing waveform of the GOA unit provided in the first embodiment of the present invention.

[0022] Figure 6 The waveform diagrams for GN simulation comparison of the GOA unit provided in the first embodiment of the present invention are shown.

[0023] Figure 7 The QN simulation comparison waveform diagram of the GOA unit provided in the first embodiment of the present invention is shown.

[0024] Figure 8 The simulation comparison waveforms of the node voltage STN of the GOA unit provided in the second embodiment of the present invention are shown.

[0025] Figure 9 The waveform diagrams for GN simulation comparison of the GOA unit provided in the second embodiment of the present invention are shown. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this invention.

[0027] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such terms can be used interchangeably where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0028] The directional terms used in the embodiments of this invention, such as "up," "down," "front," "back," "left," "right," "inner," "outer," and "side," are merely for reference to the accompanying drawings. Therefore, the directional terms used are for illustration and understanding of the invention, and not for limiting the invention. For ease of understanding and description, the dimensions and thicknesses of each component shown in the drawings are arbitrarily shown, but the invention is not limited thereto. When a component, such as a layer, film, region, or substrate, is referred to as "on" another component, the component may be directly on the other component, or there may be an intermediate component. Furthermore, in the specification, "on" means located above or below the target component, and does not necessarily mean located on top based on gravity.

[0029] Furthermore, the division of multiple embodiments in this invention is merely for the convenience of description and should not constitute a special limitation. Features in various embodiments can be combined and referenced in each other without contradiction.

[0030] first, Figure 1 This is a circuit example diagram of a traditional GOA unit in related technologies. Figure 2 for Figure 1 Timing waveform diagram of a traditional GOA unit. In related technologies, a 4K screen with 12 clock signals CK is used as an example for illustration. Figure 2 Q13 / Q14 / GOUT_13 / GOUT_14 respectively correspond to Figure 1 The circuit node voltage QN and scanning voltage GN. See also... Figure 1 and Figure 2 In a traditional GOA cell, when the start signal STV changes from low level H0 to high level H1, the thin-film transistor T1 turns on, and the node voltage QN connected to the drain terminal of the thin-film transistor T1 changes from low level H0 to intermediate voltage H1. Based on the 12 clock signals CK, according to the cascading relationship of the GOA cell, Q14 is the first voltage H2 during the time period t2 to t5, and Q14 is the second voltage H5 during the time period t5 to t8. This node voltage QN is connected to the gate terminal of the thin-film transistor T2.

[0031] This invention provides a GOA device comprising multiple cascaded GOA units, wherein the Nth-level GOA unit outputs a gate drive signal to the Nth-level horizontal scan line G(N). See also Figure 3 , Figure 3For example, here is a schematic diagram of an exemplary circuit module for an Nth-level GOA device. The Nth-level GOA unit 10 includes: a pull-up control unit 100, a pull-up unit 200, a pull-down unit 300, a pull-down control unit 400, and a first switch T0. The pull-up control unit 100 is connected to the gate signal point Q(N); the pull-down control unit 400 is connected to the gate signal point Q(N) and the pull-down unit 300, and the pull-down unit 300 is also connected to the Nth-level horizontal scan line G(N); the pull-up unit is connected to the Nth-level horizontal scan line G(N). For example, the voltage at the gate signal point Q(N) is defined as the gate signal point voltage QN, and the voltage at the Nth-level horizontal scan line G(N) is defined as the scan voltage GN.

[0032] Furthermore, the first switch T0 is connected to the node voltage of the (N+m)th level GOA unit and is also connected to the pull-up unit 200. The node voltage of the (N+m)th level GOA unit is used to control the opening and closing of the first switch T0. The operating time of the first switch T0 is not the same as the operating time of the Nth level GOA unit, where m is a positive integer and m>0. For example, the node voltage of the (N+m)th level GOA unit is, for example, the gate signal point voltage QN+m of the (N+m)th level GOA unit, or the node voltage of the (N+m)th level GOA unit is, for example, the stage transmission signal point voltage STN+m of the (N+m)th level GOA unit. For example, the operating time of the Nth level GOA unit is, for example, the time period during which its output gate drive signal to the Nth level horizontal scan line is high. The operating time of the first switch T0 can be understood as the first switch T0 being in the open state, and the first switch T0 having a positive effect on the Nth level GOA unit 10.

[0033] For example, see Figure 5 The working time of the 13th level GOA unit is, for example, t4 to t7. Figure 5 During the period when GOUT_13 is at a high level, the first switch T0 in the 13th level GOA unit is in the open state from t2 to t8, but is only in the working state from t3 to t4 and t7 to t8. This is different from the working time of the 13th level GOA unit.

[0034] By adding a first switch controlled by the node voltage of the N+m level GOA unit, and the operating time of the first switch is not at the same time as the operating time of the Nth level GOA unit, the driving capability of the GOA unit node voltage on the scan line control thin film transistor is enhanced, the rise time and fall time of the scan signal are reduced, thereby preventing display mischarging.

[0035] For details, see Figure 4, the pull-up control unit 100 includes a second switch T1. The gate terminal and the source terminal of the second switch T1 are connected to the start signal STV, and the drain terminal of the second switch T1 is connected to the gate signal point Q(N). The pull-up unit 200 includes a third switch T2 and a fourth switch T5. The gate terminal of the third switch T2 is connected to the gate signal point Q(N), the source terminal of the third switch T2 is connected to the clock signal CK, and the drain terminal of the third switch T2 is connected to the Nth-level horizontal scan line G(N) to output a scan voltage GN. The gate terminal of the fourth switch T5 is connected to the gate signal point Q(N), the source terminal of the fourth switch T5 is connected to the clock signal CK, and the drain terminal of the fourth switch T5 outputs a transfer signal voltage STN to provide a gate voltage for the pull-up control unit in the subsequent stage circuit. The pull-down control unit 400 includes a fifth switch T3, and the pull-down unit 300 includes a sixth switch T4. The gate terminals of the fifth switch T3 and the sixth switch T4 are both connected to the (N + n)th-level horizontal scan line G(N + n), and the voltage at the (N + n)th-level horizontal scan line G(N + n) is the scan voltage GN + n, where n is a positive integer, n = M / 2, and 0 < m < n. The source terminal of the fifth switch T3 is connected to the gate signal point Q(N), the source terminal of the sixth switch T4 is connected to the Nth-level horizontal scan line G(N), and the drain terminals of the fifth switch T3 and the sixth switch T4 are both connected to a negative voltage (VSS). The Nth-level GOA unit 10 further includes a capacitor C1. One end of the capacitor C1 is connected to the gate signal point Q(N), and the other end is connected to the Nth-level horizontal scan line G(N). Wherein, when the scan voltage GN + n is at a high level H2, the fifth switch T3 and the sixth switch T4 are turned on, so as to pull down the scan voltage GN at both ends of the capacitor C1 and the gate signal point voltage QN to the negative voltage VSS.

[0036] In addition, a reset signal is provided in the circuit to cooperate with the adjustment of the clock signal CK. If there is no reset signal in the circuit, the voltage of the clock signal CK is set to a negative voltage during the non-display period.

[0037] The present invention provides a first embodiment. In the first embodiment, the gate terminal of the first switch T0 is connected to the gate signal point of the (N + m)th-level GOA unit, that is, the first switch accesses the voltage at the gate signal point in the (N + m)th-level GOA unit (gate signal point voltage QN + m). The source terminal of the first switch is connected to the clock signal or a signal with the same frequency as the clock signal, and the drain terminal of the first switch is connected to the Nth-level horizontal scan line.

[0038] The following example illustrates this specific implementation using a display panel containing 12 clock signals, where m=1. Based on the 12 clock signals in the display panel, it can be understood that the first-level GOA unit is connected to clock signal CK1, the second-level GOA unit is connected to clock signal CK2, and so on, with the 12th-level GOA unit connected to clock signal CK12, the 13th-level GOA unit connected to clock signal CK1, and the 14th-level GOA unit connected to clock signal CK2. When m=1, it can be understood that the first switch T0 in the 13th-level GOA unit is connected to the node voltage Q14 of the 14th-level GOA unit.

[0039] For details, see Figure 5 , Figure 5 This is a timing waveform diagram of the GOA unit provided in the first embodiment of the present invention. The gate signal voltage Q13 in the 13th-stage GOA unit is the first voltage H2 during the time period t1 to t3, and the gate signal voltage Q14 in the 14th-stage GOA unit is the first voltage H2 during the time period t2 to t4. When the clock signal CK1 connected to the 13th-stage GOA unit is switched to a high level H1 (corresponding to...) Figure 5 At time t4 of the 13th-level GOA unit, the gate signal voltage Q13 in the 13th-level GOA unit is the second voltage H3. During the time period when the clock signal connected to the 13th-level GOA unit is high level H1 and the clock signal connected to the 14th-level GOA unit is low level H0 (corresponding to...) Figure 5 During the time period t4 to t5, the first switch T0 in the 13th-level GOA unit is in the open state, increasing the parasitic capacitance between the gate and source of the first switch T0, thus enhancing the circuit's conduction capability. At this time, the voltage Q14 at the gate signal point of the 14th-level GOA unit connected to the first switch T0 in the 13th-level GOA unit is coupled from the first voltage H2 to the first intermediate voltage H4 during the time period t4 to t5. Where H2... <H4<H3。

[0040] During the time period t5 to t7, the clock signal CK connected to the 14th-level GOA unit remains high, and Q14 maintains the second voltage H3. During the time period when the clock signal connected to the 13th-level GOA unit is low (H0) and the clock signal connected to the 14th-level GOA unit is high (e.g., Figure 5During the time period t7 to t8), the first switch T0 in the 13th-stage GOA unit is in the open state, and the voltage Q14 of the gate signal point of the 14th-stage GOA unit connected to the first switch T0 in the 13th-stage GOA unit is coupled from the second voltage H3 to the second intermediate voltage H5, where H0 < H5 < H3. In addition, when the clock signal CK applied to the 14th-stage GOA unit changes from the high level H2 to the low level H0, the high potential in the subsequent-stage GOA unit cascaded with the 14th-stage GOA unit is input to the 14th-stage GOA unit as a pull-down potential, that is Figure 4 The scanning voltage GN+n at the gate terminals of the fifth switch T3 and the sixth switch T4 is at a high level (i.e., the voltage at the N+nth horizontal scanning line G(N+n)), the fifth switch T3 and the sixth switch T4 are turned on, both ends of the capacitor C1 are connected to the negative voltage VSS, Q14 and Gout14 are discharged, and the voltage is switched to the low level H0.

[0041] Specifically, refer to Figure 5 , the voltage Q14 of the gate signal point in the 14th-stage GOA unit is at the low level H0 during the time period t1 to t2. Since the number of timing signals CK is 12, it can be known from the stage transmission relationship that the signal provided by the 8th-stage GOA unit serves as the starting voltage STV of the 14th-stage GOA unit. From Figure 5 it can be seen that the CK signal CK8 applied to the 8th-stage GOA unit is at the high level H1 during t2 to t5. Therefore, based on the action of the signal provided by the 8th-stage GOA unit, the voltage Q14 of the gate signal point in the 14th-stage GOA unit is pulled up to the first voltage H 2，At this time, since the gate signal voltage Q14 in the 14th-level GOA unit is not H0, the first switch T0 of the 13th-level GOA unit is in the open state. Further, during the time interval t4 to t5, the first switch T0 of the 13th-level GOA unit is in the open state, and CK1 connected to the 13th-level GOA unit switches to a high level H1. Therefore, based on the action of the first switch T0 in the 13th-level GOA unit, the gate signal voltage Q14 in the connected 14th-level GOA unit is pulled up from the first voltage H2 to the first intermediate voltage H4, thus improving the circuit's conduction capability. Following the above, during the time interval t5 to t7, since the timing signal CK2 connected to the 14th-level GOA unit switches to a high level H1, the gate signal voltage Q14 in the 14th-level GOA unit is pulled up to the second voltage H3. Furthermore, during the time period t7 to t8, since the timing signal CK2 connected to the 14th-level GOA unit is still at a high level H1, the gate signal point voltage Q14 in the 14th-level GOA unit should still be the second voltage H3. However, since the first switch T0 of the 13th-level GOA unit is in the open state at this time, and CK1 connected to the 13th-level GOA unit is switched to a low level H0, the gate signal point voltage Q14 in the 14th-level GOA unit connected to it is pulled down from the second voltage H3 to the second intermediate voltage H5 based on the action of the first switch T0 in the 13th-level GOA unit.

[0042] For example, see: Figure 6 The GN simulation waveform comparison shows that the GOA device provided in the first embodiment of this invention reduces the fall time compared to traditional GOA devices. Furthermore, due to the addition of the first switch T0, during the time period t7-t8 corresponding to Q14, the CK corresponding to the 13th-level GOA unit switches from high level H2 to low level H0 at time t7. Also, due to the parasitic capacitance at the gate and source terminals of the first switch T0, the Q14 waveform in this patented solution will be lower than the second voltage H3 during this period, reducing the discharge time across capacitor C1 and thus reducing the GN fall time. For example, see, for instance... Figure 7 The QN simulation waveforms are shown in the diagram.

[0043] In summary, by adding a first switch controlled by the node voltage of the N+m level GOA unit, and ensuring that the operating time of the first switch is not at the same time as the operating time of the Nth level GOA unit, the driving capability of the thin-film transistor controlled by the node voltage of the GOA unit for the scan line is enhanced, and the rise and fall times of the scan signal are reduced, thereby preventing display mischarging.

[0044] Furthermore, the present invention provides a second embodiment. In the second embodiment, the gate terminal of the first switch T0 is connected to the stage transmission signal point of the (N+m)th level GOA unit, the source terminal of the first switch T0 is connected to the clock signal or a signal with the same frequency as the clock signal, and the drain terminal of the first switch is connected to the Nth level horizontal scan line. That is, the difference between the Nth level GOA unit provided in Embodiment 2 and the Nth level GOA unit provided in Embodiment 1 is only that in Embodiment 2, the gate terminal of the first switch T0 is connected to the stage transmission signal point of the (N+m)th level GOA unit, while in Embodiment 1, the gate terminal of the first switch T0 is connected to the gate signal point of the (N+m)th level GOA unit; all other connections and structures are the same.

[0045] Furthermore, the following example illustrates this specific implementation method using a display panel containing 12 clock signals, where m=1. Figure 8 This is the STN waveform of the node voltage of the GOA unit provided in the second embodiment of the present invention. During the time period when the clock signal connected to the 13th-level GOA unit is low (H0) and the clock signal connected to the 14th-level GOA unit is high (H1)... Figure 8 During the time interval t1~t2, the first switch is in the open state, and the voltage at the intermediate signal transmission point of the 13th level GOA unit is within the specified time period (t1~t2). Figure 8 (t1~t2) is coupled from the third voltage H6 to the third intermediate voltage H7, wherein H0 <H7<H6,H6≤H1。

[0046] Specifically, based on the addition of a first switch T0, since the gate terminal of the first switch T0 is connected to the subsequent STN voltage, the node voltage STN will be coupled due to the voltage abrupt change across T0. The node voltage STN waveform is as follows: Figure 8 The principle is the same as in Embodiment 1 above, and will not be repeated here; for example, please refer to Figure 9 The GN simulation waveforms show that the GOA device provided in the second embodiment of the present invention reduces the fall time compared to the traditional GOA device.

[0047] In summary, by adding a first switch controlled by the node voltage of the N+m level GOA unit, and ensuring that the operating time of the first switch is not at the same time as the operating time of the Nth level GOA unit, the driving capability of the thin-film transistor controlled by the node voltage of the GOA unit for the scan line is enhanced, and the rise and fall times of the scan signal are reduced, thereby preventing display mischarging.

[0048] In addition, the present invention also provides a gate drive circuit, including the aforementioned GOA device.

[0049] Furthermore, the present invention also provides a display panel including the aforementioned GOA device.

[0050] It is understood that the foregoing embodiments are merely illustrative examples of the present invention. Provided that the technical features do not conflict, the structure is not contradictory, and the purpose of the invention is not violated, the technical solutions of the various embodiments can be arbitrarily combined and used.

[0051] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A GOA device comprising a plurality of GOA units cascaded, an Nth stage GOA unit for outputting a gate driving signal to an Nth stage horizontal scan line, characterized in that, The Nth-stage GOA unit comprises a pull-up control unit, a pull-up unit, a pull-down unit and a pull-down control unit; The pull-up control unit is connected to a gate signal point; the pull-down control unit is connected to the gate signal point and the pull-down unit, and the pull-down unit is connected to the Nth-stage horizontal scanning line; and the pull-up unit is connected to the Nth-stage horizontal scanning line. The Nth-stage GOA unit further comprises a first switch, the first switch is connected to a node voltage of an N+mth-stage GOA unit and the pull-up unit, the node voltage of the N+mth-stage GOA unit is used to control the opening and closing of the first switch, the working time of the first switch is not at the same time as the working time of the Nth-stage GOA unit, m is a positive integer and m>0.

2. The GOA device according to claim 1, wherein, The pull-down control unit is connected to an N+nth-stage horizontal scanning line, the pull-up control unit is connected to a start signal, and the pull-up unit is connected to a clock signal, the clock signal comprises M lines, n is a positive integer, n=M / 2, and 0 3. The GOA device according to claim 2, wherein, The first end of the first switch is connected to a gate signal point of the N+mth-stage GOA unit, the second end of the first switch is connected to the clock signal or a signal with the same frequency as the clock signal, the third end of the first switch is connected to the Nth-stage horizontal scanning line, and the pull-up unit is connected to the Nth-stage horizontal scanning line.

4. The GOA device according to claim 2, wherein, The first end of the first switch is connected to a stage transmission signal point of the N+mth-stage GOA unit, the second end of the first switch is connected to the clock signal or a signal with the same frequency as the clock signal, the third end of the first switch is connected to the Nth-stage horizontal scanning line, and the pull-up unit is connected to the Nth-stage horizontal scanning line.

5. The GOA device according to claim 3, wherein, When the clock signal connected to the Nth-stage GOA unit is switched from a low level H0 to a high level H1, the voltage of the gate signal point in the Nth-stage GOA unit is a second voltage H3; In a time period when the clock signal connected to the Nth-stage GOA unit is at a high level H1 and the clock signal connected to the N+mth-stage GOA unit is at a low level H0, the first switch is in an open state, and the voltage of the gate signal point of the N+mth-stage GOA unit connected to the first switch is coupled from a first voltage H2 to a first intermediate voltage H4 in the time period, wherein H2 6. The GOA device according to claim 5, wherein, When the clock signal connected to the Nth-stage GOA unit is switched from the high level H1 to the low level H0, the voltage of the gate signal point in the Nth-stage GOA unit is switched to the low level H0; In a time period when the clock signal connected to the Nth-stage GOA unit is at a low level H0 and the clock signal connected to the N+mth-stage GOA unit is at a high level H1, the first switch is in the open state, and the voltage of the gate signal point of the N+mth-stage GOA unit connected to the first switch is coupled from a second voltage H3 to a second intermediate voltage H5, wherein H0 7. The GOA device according to claim 4, wherein, In a time period when the clock signal accessed by the Nth GOA unit is low H0 and the clock signal accessed by the N+mth GOA unit is high H1, the first switch is in an open state, and a voltage of a middle signal point in the Nth GOA unit is coupled from a third voltage H6 to a third intermediate voltage H7 in the time period, wherein H0 8. A gate drive circuit characterized by comprising: A GOA device as claimed in any one of claims 1 to 7.

9. A display panel, characterized by, A GOA device as claimed in any one of claims 1 to 7.

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