Semiconductor packaging structure and forming method thereof

Abstract

Various embodiments of the present disclosure are directed to a semiconductor package structure that includes a support structure having a first surface opposite a second surface. A first integrated circuit (IC) chip is on the first surface of the support structure. The cover structure is located on the second surface of the support structure. A vapor chamber is disposed in the support structure and over at least a portion of the first IC chip. The embodiment of the invention also provides a method for forming the semiconductor packaging structure.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to semiconductor package structures and methods of forming the same. Background Art

[0002] Integrated circuit (IC) chips with semiconductor devices are essential for many modern electronic devices. With the advancement of electronic technology, the size of semiconductor devices has become smaller and smaller, while the functions they have become more powerful and the number of integrated circuits has increased. Due to the miniaturized size of semiconductor devices, advanced semiconductor packaging is widely used to integrate multiple IC chips into a single multi-chip package. In addition, integrating multiple IC chips in a semiconductor package provides a higher density semiconductor device with a smaller form factor, thereby allowing for improved performance and reduced power consumption. Summary of the invention

[0003] Some embodiments of the present disclosure provide a semiconductor packaging structure, which includes: a support structure, including a first surface opposite to a second surface; a first integrated circuit (IC) chip, located on the first surface of the support structure; a cover structure, located on the second surface of the support structure; and a steam chamber, arranged in the support structure and located above at least a portion of the first IC chip.

[0004] Other embodiments of the present disclosure provide a semiconductor packaging structure, which includes: an interposer structure including a plurality of conductive interconnect structures; a plurality of integrated circuit (IC) chips located on the plurality of conductive interconnect structures and electrically coupled to the plurality of conductive interconnect structures; and a heat dissipation structure located on the plurality of IC chips, wherein the heat dissipation structure includes: a support structure located on the plurality of IC chips; a thermal interface structure located on the support structure; a heat sink structure located on the thermal interface structure; and one or more vapor chambers embedded in the support structure, wherein the one or more vapor chambers respectively include a bottom surface having a first width facing the plurality of IC chips and a top surface having a second width facing the heat sink structure, wherein the first width is smaller than the second width.

[0005] Another embodiment of the present disclosure provides a method for forming a semiconductor packaging structure, the method comprising: arranging a plurality of integrated circuit (IC) chips on an interposer structure; forming a vapor chamber within a supporting structure; bonding the supporting structure to the plurality of IC chips, wherein the vapor chamber is placed above at least a portion of a single IC chip among the plurality of IC chips; and bonding a cover structure to the supporting structure, wherein a thermal conductivity of the cover structure is greater than a thermal conductivity of the supporting structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, aspects of the present disclosure can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 Cross-sectional views of some embodiments of semiconductor package structures including a heat dissipation structure including a vapor chamber located above a plurality of integrated circuit (IC) chips are shown.

[0008] Figure 2 Cross-sectional views of some other embodiments of semiconductor package structures including a heat dissipation structure including a plurality of vapor chambers located above a plurality of IC chips are shown.

[0009] FIG. 3A to FIG. 3C Shown along Figure 2 The line A-A' intercepts Figure 2 Layout diagrams of various embodiments of a semiconductor package structure.

[0010] FIG. 4A to FIG. 4E Shows Figure 2 Cross-sectional views of some other embodiments of semiconductor package structures.

[0011] Figure 4F Shown along Figure 4A The line B-B' intercepts Figure 4A A top view of some embodiments of a portion of a heat spreading enhancement structure disposed within a vapor chamber of a semiconductor package structure.

[0012] Figure 4G and Figure 4H Various cross-sectional views of some embodiments of heat dispersion enhancement structures disposed in a vapor chamber are shown.

[0013] Figure 5A Cross-sectional views of some embodiments of semiconductor package structures including a vapor chamber that extends laterally from over a first IC chip continuously to over a second IC chip are shown.

[0014] Figure 5B Shows Figure 2 Cross-sectional views of some other embodiments of semiconductor package structures, wherein one or more vapor channels extend between adjacent vapor chambers.

[0015] Figure 6 Shown along Figure 5B The line A-A' intercepts Figure 5B Layout diagrams of some embodiments of semiconductor package structures.

[0016] Fig. 7A and Figure 7B Shows Figure 2 Cross-sectional views of some other embodiments of semiconductor package structures.

[0017] Figures 8 to 17 Cross-sectional views of some embodiments of methods of forming a semiconductor package structure having a heat dissipation structure including one or more vapor chambers located above a plurality of IC chips are shown.

[0018] Fig.18 A flow chart illustrating some embodiments of a method of forming a semiconductor package structure including a heat dissipation structure including one or more vapor chambers located above a plurality of IC chips. DETAILED DESCRIPTION

[0019] The following disclosure provides many different embodiments or examples for implementing the different components of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the individual embodiments and / or configurations discussed.

[0020] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," and "upper" may be used herein to describe the relationship of one element or component to another element or component as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0021] The semiconductor package structure may include a plurality of integrated circuit (IC) chips on a base structure. Each IC chip includes a plurality of semiconductor devices (e.g., transistors). The base structure may be or include an interposer that electrically couples the IC chips together and / or electrically couples the IC chips to other electronic devices through conductive interconnects such as wires, vias, bonding structures, and through substrate vias (TSVs). The semiconductor package structure also includes a support structure located above the plurality of IC chips that reduces mechanical stress on the IC chips and / or the base structure. During operation of the semiconductor package structure, semiconductor devices and / or conductive interconnects may generate heat (e.g., due to Joule heating). As devices are scaled down and more densely packed together, heat dissipation in ICs becomes increasingly important.

[0022] The semiconductor package structure may have local high temperature areas across the IC chip and / or the base structure. For example, the area of ​​the IC chip and / or the base structure running at relatively high power may generate high heat, thereby causing local high temperature areas in the semiconductor package structure. The support structure may be or include, for example, a silicon substrate, which is a poor conductor of heat and is placed directly above these local high temperature areas. The poor thermal conductivity of the support structure alleviates the heat dissipation at these local high temperature areas, which may lead to reduced reliability and / or poor circuit performance. For example, the local high temperature area may cause semiconductor devices to burn out and / or delamination around the conductive interconnect or in the layer of the conductive interconnect. In addition, the local high temperature area may cause a large temperature change across the entire semiconductor package structure, which may cause timing inaccuracy. This may significantly reduce the performance of semiconductor devices in high-performance computing applications (such as advanced servers and network applications) that require high data rates and reduced latency.

[0023] Various embodiments of the present disclosure are directed to a semiconductor package structure with a heat dissipation structure, which is located on multiple IC chips and is configured to enhance heat diffusion. In some embodiments, the semiconductor package structure includes multiple IC chips located on a base structure and a heat dissipation structure located on multiple IC chips. Each IC chip includes multiple semiconductor devices. The heat dissipation structure includes a support structure, a cover structure located on the support structure, and one or more steam chambers embedded in the support structure. One or more steam chambers are configured to enhance heat dissipation in a vertical direction away from multiple semiconductor devices of the IC chip and toward the capping structure. The cover structure has a relatively high thermal conductivity (e.g., greater than the thermal conductivity of the support structure) and is configured to effectively disperse heat from the IC chip to the external environment. One or more steam chambers that enhance heat dissipation in the vertical direction and the high thermal conductivity of the cover structure improve the heat dissipation performance of the semiconductor package structure and facilitate heat transfer from potential local high temperature areas. Thus, problems caused by high heat and / or large temperature changes across the entire IC chip (e.g., timing inaccuracies, burnout failures, etc.) are reduced, thereby improving the performance and reliability of the semiconductor package structure.

[0024] Figure 1 A cross-sectional view 100 of some embodiments of a semiconductor package structure including a heat dissipation structure 111 including a vapor chamber 110 positioned above a plurality of integrated circuit (IC) chips 104a - b is shown.

[0025] The semiconductor package structure includes a base structure 102, a plurality of IC chips 104a-b and a heat dissipation structure 111. In various embodiments, the plurality of IC chips 104a-b respectively include a plurality of semiconductor devices disposed on a semiconductor substrate and an interconnect structure (not shown) electrically coupled to the plurality of semiconductor devices. The semiconductor device may be or include one or more electronic devices, such as a diode, a transistor, a capacitor, a resistor, etc. In addition, the IC chip 104a-b may be or include one or more IC dies or a stack of IC dies. In various embodiments, the IC chip 104a-b may each be a system on chip (SoC), a system on an integrated circuit (SoIC), etc. In some embodiments, the base structure 102 is configured as an interposer and includes conductive interconnect wiring, substrate through-holes (TSVs), contact pads, etc. (not shown) configured to electrically couple the IC chips 104a-b to each other and / or electrically couple the IC chips 104a-b to another electronic device (not shown). The IC chip 104a-b is bonded to the base structure 102 via a plurality of conductive bonding elements 105. Conductive bonding elements 105 facilitate electrical coupling between IC chips 104a-b and base structure 102. Filling layer 106 is disposed above base structure 102 and around and between each IC chip 104a-b. Upper bonding structure 108 is disposed between heat dissipation structure 111 and multiple IC chips 104a-b.

[0026] The heat dissipation structure 111 is placed above the multiple IC chips 104a-b and is configured to enhance the heat dissipation in the semiconductor package structure. The heat dissipation structure 111 includes a support structure 112, a thermal interface structure 114, a cover structure 116 and one or more steam chambers 110. The support structure 112 is placed above the multiple IC chips 104a-b. In various embodiments, the support structure 112 includes one or more substrates (e.g., a silicon substrate), one or more dielectric layers (e.g., including silicon dioxide or some other suitable dielectrics), etc. (not shown). The steam chamber 110 is embedded or arranged in the support structure 112. In some embodiments, the steam chamber 110 is defined by at least one or more surfaces of the support structure 112 and is placed directly above at least the first region 101 of the first IC chip 104a. In various embodiments, the first region 101 of the first semiconductor chip 104a includes semiconductor devices (not shown) that are operated at high power and / or densely packaged together, so that the first region 101 may become a local high temperature region during the operation of the semiconductor package structure.

[0027] The thermal interface structure 114 is disposed between the support structure 112 and the lid structure 116. In some embodiments, the thermal interface structure 114 is configured to facilitate bonding the lid structure 116 to the support structure 112 and / or provide a thermal interface between the support structure 112 and the lid structure 116. The lid structure 116 has a relatively high thermal conductivity and is configured to effectively disperse heat from the plurality of IC chips 104a-b to the external environment. For example, the thermal conductivity of the lid structure 116 is greater than the thermal conductivity of one or more substrates and / or dielectric layers of the support structure 112.

[0028] Steam chamber 110 is configured to enhance heat dissipation in the vertical direction from multiple IC chips 104a-b towards cover structure 116. In certain embodiments, steam chamber 110 is sealed with evaporable working fluid and / or includes evaporable working fluid, which can undergo evaporation process to be converted into steam, and the steam can undergo condensation process to be converted back into fluid. In various embodiments, evaporable working fluid can be or include, for example, chlorofluorocarbon, hydrochlorofluorocarbon, water, alcohol, silicone oil, liquid nitrogen, fluorine-containing fluid, acetone, methanol, ethanol, heptane, ammonia, some other suitable cooling liquids or any combination thereof. Evaporable working fluid is arranged in steam chamber 110, and is configured to facilitate heat transmission in the vertical direction from IC chip 104a-b towards cover structure 116. For example, during the operation of semiconductor package structure, the heat generated by IC chip 104a-b and / or base structure 102 makes evaporable working fluid evaporate and be converted into steam. This evaporation effectively transfers heat in the vertical direction towards cover structure 116. When heat is transferred to the cover structure 116, the relatively high thermal conductivity of the cover structure 116 facilitates dissipation of the heat to the external environment and away from the IC chips 104a-b. The heat from the IC chips 104a-b is effectively dissipated through the vapor chamber 110 and the cover structure 116, reducing the problems caused by the high heat across the IC chips 104a-b (e.g., timing errors, burnout failures, etc.), thereby improving the performance and reliability of the semiconductor package structure.

[0029] Furthermore, in some embodiments, the steam chamber 110 is advantageously disposed directly above the first region 101 of the first semiconductor chip 104a. As described above, the first region 101 may become a local high temperature region. Disposing the steam chamber 110 directly above the first region 101 is conducive to effectively dissipating heat from the first region 101, thereby alleviating the formation of local high temperatures at and / or around high-power semiconductor devices and / or densely packaged semiconductor devices in the first region 101. Thus, the overall performance and reliability of the semiconductor packaging structure are improved.

[0030] Figure 2A cross-sectional view 200 of some other embodiments of semiconductor package structures including a heat dissipation structure 111 including a plurality of vapor chambers 110 located above a plurality of IC chips 104a - b is shown.

[0031] The semiconductor package structure includes multiple IC chips 104a-b, a base structure 102 and a heat dissipation structure 111. In some embodiments, the semiconductor package structure is a chip on wafer on substrate (COWOS) package structure, a SoIC package structure, a three-dimensional IC (3DIC) package structure or some other suitable package structure.

[0032] In some embodiments, the base structure 102 is configured as an interposer, which includes a lower substrate 208, a plurality of TSVs 210, a plurality of conductive interconnect structures 212, and a first plurality of conductive bonding structures 214. The lower substrate 208 can be or include, for example, silicon, germanium, silicon germanium, some other suitable substrate material, or any combination thereof. A lower dielectric layer 206 is disposed along the lower surface of the lower substrate 208, and a plurality of lower bonding pads 204 are disposed in the lower dielectric layer 206. The lower bonding pads 204 are aligned with and electrically coupled to at least one TSV in the plurality of TSVs 210. A plurality of solder bumps 202 are disposed on the lower bonding pads 204 and are configured to electrically couple and bond the base structure 102 to another device (e.g., a printed circuit board (PCB) or some other suitable device). A plurality of conductive interconnect structures 212 are disposed in a dielectric structure 218 on the upper surface of the lower substrate 208. In some embodiments, the plurality of conductive interconnect structures 212 include conductive contacts, conductive vias, and / or wires. A first plurality of conductive bonding structures 214 are disposed in the first dielectric structure 220. The first plurality of conductive bonding structures 214 include bonding vias, bonding pads, other suitable bonding structures, or any combination thereof. The conductive components of the base structure 102 are configured to electrically couple the plurality of IC chips 104a-b to each other and / or to electrically couple the plurality of IC chips 104a-b to another device (e.g., a PCB).

[0033] A plurality of IC chips 104a-b are placed above the base structure 102. The IC chips 104a-b include a second plurality of conductive bonding structures 216 disposed in a second dielectric structure 222. The second plurality of conductive bonding structures 216 include bonding vias, bonding pads, other suitable bonding structures, or any combination thereof. One or more bonding interfaces are disposed between the base structure 102 and the IC chips 104a-b. The first plurality of conductive bonding structures 214 meet the second plurality of conductive bonding structures 216 at one or more bonding interfaces. In various embodiments, the one or more bonding interfaces include conductor-to-conductor bonding and dielectric-to-dielectric bonding.

[0034] The IC chips 104a-b may each be a SoC, a SoIC, a semiconductor die, etc. In various embodiments, the IC chips 104a-b are configured as SoCs with a chiplet design, and the SoCs with a chiplet design each include one or more chiplets. For example, the IC chips 104a-b may be or include one or more switch chips, memory chips, application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), data processing units (DPUs), or some other suitable devices. The IC chips 104a-b each include one or more digital circuits, analog circuits, mixed signal circuits, etc. In some embodiments, the circuits of the IC chips 104a-b include a plurality of semiconductor devices (not shown), which may be or include transistors, memory devices, resistors, diodes, capacitors, some other electronic devices, or any combination of the above. For example, the circuits of the IC chips 104a-b include complementary metal oxide semiconductor (CMOS) transistors, planar CMOS transistors, fin field effect transistors (FinFETs), gate-all-around (GAA) transistors, nanosheet transistors, some other electronic devices, or any combination of the above.

[0035] In some embodiments, IC chip 104a-b includes one or more semiconductor substrate parts and one or more interconnect structures, respectively. The semiconductor part can be or include, for example, silicon, germanium, silicon germanium, epitaxial silicon, silicon on insulator (SOI) substrate, some other suitable substrate materials, or any combination of the above. Multiple semiconductor devices are formed in and / or on one or more semiconductor parts. One or more interconnect structures are arranged on a corresponding one of the one or more semiconductor parts. Each interconnect structure is arranged on a corresponding semiconductor part and is configured to provide electrical connection with multiple semiconductor devices. In various embodiments, the interconnect structure includes a plurality of conductive interconnect components, which are surrounded by one or more dielectric layers or arranged in one or more dielectric layers. The conductive interconnect components may include, for example, conductive contacts, wires, conductive vias, etc.

[0036] The filling layer 106 is placed above the base structure 102 and is arranged around and / or between the IC chips 104a-b. The filling layer 106 can be or include, for example, an oxide (e.g., silicon dioxide), a resin, or some other suitable material. The upper bonding structure 108 is placed above the multiple IC chips 104a-b. The upper bonding structure 108 includes a first dielectric bonding layer 108a located on the IC chips 104a-b and a second dielectric bonding layer 108b located on the heat dissipation structure 111. In various embodiments, the first dielectric bonding layer 108a and the second dielectric bonding layer 108b can be or include, for example, silicon dioxide or some other suitable dielectric material.

[0037] The heat dissipation structure 111 is placed above the multiple IC chips 104a-b and is configured to enhance the heat dissipation in the semiconductor package structure. The heat dissipation structure 111 includes a support structure 112, a thermal interface structure 114, a cover structure 116 and a plurality of steam chambers 110. The support structure 112 is placed above the multiple IC chips 104a-b, and the thermal interface structure 114 is arranged between the support structure 112 and the cover structure 116. In some embodiments, the support structure 112 includes a first substrate 224, a first dielectric layer 226, a second dielectric layer 228 and a second substrate 230. The first substrate 224 and the second substrate 230 can be or include, for example, silicon, epitaxial silicon, germanium, silicon germanium, some other suitable substrate materials, etc. The first dielectric layer 226 and the second dielectric layer 228 can be or include, for example, silicon dioxide or some other suitable materials. In various embodiments, the thickness of the first substrate 224 is less than the thickness of the second substrate 230.

[0038] A plurality of steam chambers 110 are embedded in the support structure 112, and each of the plurality of steam chambers 110 is defined by at least one or more surfaces of the free support structure 112. In some embodiments, the plurality of steam chambers 110 include a first portion 110p1 and a second portion 110p2. The second portion 110p2 is placed directly above the first portion 110p1 and is fluidly connected to the first portion 110p1. In some embodiments, each steam chamber 110 has a bottom surface facing a plurality of IC chips 104a-b and a top surface facing the cover structure 116, wherein the area of ​​the bottom surface of the steam chamber 110 is less than the area of ​​the top surface of the steam chamber 110. In various embodiments, the width or volume of the first portion 110p1 is less than the width or volume of the second portion 110p2. The width or volume of the first portion 110p1 is less than the width or volume of the second portion 110p2, which is conducive to effectively directing heat to the cover structure 116. For example, the shape of the steam chamber 110 facilitates directing the steam in the steam chamber from the smaller first portion 110 p 1 to the larger second portion 110 p 2 , thereby promoting the transfer of heat toward the cover structure 116 .

[0039] In some embodiments, thermal interface structure 114 includes first thermal dispersion layer 238, thermal interface layer 240, and second thermal dispersion layer 242. First thermal dispersion layer 238 and second thermal dispersion layer 242 may be or include, for example, a metal such as copper, aluminum, tungsten, silver, some other metal, or an alloy thereof. Thermal interface layer 240 may be or include, for example, lead, tin, silver, copper, indium, an alloy thereof (e.g., a solder alloy, an indium solder alloy, etc.), or some other suitable material. First thermal dispersion layer 238 and second thermal dispersion layer 242 are configured to facilitate dispersing heat from support structure 112 to cover structure 116, and / or directing heat from support structure 112 to cover structure 116. Thermal interface layer 240 is configured to bond cover structure 116 to support structure 112 and provide a thermal interface between cover structure 116 and support structure 112.

[0040] The cover structure 116 is placed above the support structure 112 and is configured to dissipate or disperse heat from the semiconductor package structure to the external environment. In some embodiments, the cover structure 116 is configured as or referred to as a heat sink structure. The cover structure 116 has a relatively high thermal conductivity, which is conducive to dispersing and / or dissipating heat to the external environment. The cover structure 116 can be or include, for example, a metal such as copper, aluminum, tungsten, silver, some other metals or their alloys, graphite, other suitable materials, or any combination of the above. In various embodiments, the thermal conductivity of the cover structure 116 is greater than the thermal conductivity of the first substrate 224 and the second substrate 230 and the first dielectric layer 226 and the second dielectric layer 228. In some embodiments, the thermal conductivity of the cover structure 116 is greater than, for example, about 100 watts / meter Kelvin (W / m*K), in the range of about 200 to 500W / m*K, about 400W / m*K, or some other suitable value. In further embodiments, the thermal conductivity of the first and second thermal dispersion layers 238 and 242 is greater than the thermal conductivity of the first and second substrates 224 and 230 and the first and second dielectric layers 226 and 228. In various embodiments, the area of ​​the lid structure 116 is equal to or substantially equal to the area of ​​the base structure 102 when viewed from a top view.

[0041] The vapor chamber 110 is configured to enhance heat dissipation in the vertical direction from the plurality of IC chips 104a-b toward the cover structure 116, thereby improving the overall heat dissipation performance of the semiconductor package structure. In some embodiments, the vapor chamber 110 includes and is sealed with a vaporizable working fluid (e.g., chlorofluorocarbons, hydrochlorofluorocarbons, water, alcohol, silicone oil, liquid nitrogen, fluorine-containing fluids, acetone, methanol, ethanol, heptane, ammonia, etc.). In various embodiments, the vaporizable working fluid is disposed in at least the first portion 110p1 of each vapor chamber 110. The vaporizable working fluid is configured to facilitate dispersing heat in the vertical direction from the first portion 110p1 of the vapor chamber 110 toward the second portion 110p2 of the vapor chamber. For example, during the operation of the semiconductor package structure, the current flowing through the structure (e.g., conductive interconnection and / or semiconductor device) of the IC chip 104a-b and / or the base structure 102 generates heat (e.g., due to Joule heating). The generated heat is directed to the vaporizable working fluid in the vapor chamber 110, which can induce the vaporizable working fluid to evaporate into steam. The vaporizable working fluid evaporates into vapor to effectively transfer heat in a vertical direction toward the cover structure 116. In addition, when the heat is transferred toward the cover structure 116, the vapor can undergo a condensation process in the second portion 110p2, wherein the condensation process cools the vapor and converts it back into liquid. Accordingly, the vaporizable working fluid is configured to undergo an evaporation process and a condensation process during operation of the semiconductor package structure, which is conducive to effectively dissipating heat from the plurality of IC chips 104a-b, thereby improving the performance and reliability of the semiconductor package structure.

[0042] The heat dispersion enhancement structure 231 is disposed in the vapor chamber 110. In some embodiments, the heat dispersion enhancement structure 231 is disposed on an upper surface of the second substrate 230 that defines the top surface of the vapor chamber 110. In various embodiments, the heat dispersion enhancement structure 231 includes a dielectric layer 236, a seed layer 234 disposed on the dielectric layer 236, and a heat dispersion enhancement layer 232 disposed on the seed layer 234. In various embodiments, the heat dispersion enhancement structure 231 is configured to improve the ability of the vapor chamber 110 to transfer heat toward the cover structure 116. For example, the seed layer 234 and the heat dispersion enhancement layer 232 have a thermal conductivity greater than the thermal conductivity of the first substrate 224 and the second substrate 230 and the first dielectric layer 226 and the second dielectric layer 228.

[0043] In further embodiments, when viewed from a top view (e.g., as Figure 4FAs shown), the heat dispersion enhancement layer 232 includes a plurality of holes and / or has a grid structure or a mesh structure. In some embodiments, the heat dispersion enhancement layer 232 is configured to assist the evaporation process and / or the condensation process, thereby improving the heat dissipation efficiency of the vapor chamber 110. For example, the vapor generated by the vaporizable working fluid can be dispersed on the surface of the heat dispersion enhancement layer 232, wherein the heat dispersion enhancement layer 232 absorbs the condensed liquid on the surface of the heat dispersion enhancement layer 232 by capillary action, thereby improving the ability to cool the vapor, thereby improving the condensation of the vapor. In yet further embodiments, the heat dispersion enhancement layer 232 can be disposed on one or more surfaces of the first portion 110p1 of the support structure 112 that defines the vapor chamber 110 (e.g., as Figure 4B 231 ), so that the mesh structure of the heat dispersion enhancement layer 232 transfers the evaporable working fluid by capillary action. As a result, the evaporable working fluid is dispersed on the surface of the heat dispersion enhancement layer 232, which can improve the evaporation of the evaporable working fluid. Accordingly, the heat dispersion enhancement structure 231 effectively improves the ability to dissipate heat from the IC chips 104a-b.

[0044] Dielectric layer 236 may be or include, for example, silicon dioxide or some other suitable dielectric material. Seed layer 234 may be or include, for example, titanium, tantalum, nitride (e.g., titanium nitride, tantalum nitride, etc.), copper, etc. Heat dispersion enhancement layer 232 may be or include, for example, copper, copper powder, or some other suitable material. In some embodiments, heat dispersion enhancement layer 232 is configured as and / or referred to as a wicking layer or wicking structure.

[0045] In addition, in some embodiments, the vapor chamber 110 is advantageously disposed directly above the corresponding first region 101 of the IC chip 104a-b, wherein the first portion 110p1 of each vapor chamber 110 is disposed directly above the corresponding first region 101. In various embodiments, the first region 101 of the IC chip 104a-b is a region that is likely to become a local high temperature region. For example, each IC chip 104a-b has a first region 101 and an adjacent second region 260, wherein during operation of the semiconductor package structure, the heat generated by the first region 101 is greater than that of the second region 260. In some embodiments, the first region 101 includes one or more of a CPU, a GPU, a high-voltage device, a high-density semiconductor device, a high-density conductive interconnect structure, etc., and the second region 260 includes one or more of a logic circuit, a memory containing a chip or circuit, a low-voltage device, a low-density semiconductor device, etc. Accordingly, due to the type or function of the device and / or the density of the device in the first region 101, high temperature is likely to accumulate in the first region 101. By arranging the vapor chamber 110 directly above the first region 101 of the IC chips 104a-b, heat can be effectively dissipated from the first region 101, thereby reducing the formation of local high temperatures at and / or around the semiconductor devices in the first region, which improves the overall performance and reliability of the semiconductor package structure to a certain extent.

[0046] In some embodiments, the height 244 of the first portion 110p1 of the vapor chamber 110 is less than the height 245 of the second portion 110p2 of the vapor chamber 110, so that the volume of the second portion 110p2 is greater than the volume of the first portion 110p1. Thus, the vapor in the vapor chamber 110 can be effectively directed to the cover structure 116, thereby improving heat dissipation in the semiconductor package structure.

[0047] In some embodiments, the height 246 of the support structure 112 is greater than the height 250 of the cover structure 116. In further embodiments, the ratio of the height 250 of the cover structure 116 to the height 246 of the support structure 112 is in the range of about 0.34 to 1 or some other suitable value. In various embodiments, a ratio of the height 250 to the height 246 being equal to or less than 1 facilitates the volume of the cover structure 116 to be large enough to effectively dissipate heat to the external environment while maintaining the structural integrity of the support structure 112. In further embodiments, a ratio of the height 250 to the height 246 being equal to or greater than 0.34 facilitates the volume of the cover structure 116 to be large enough to effectively dissipate heat to the external environment. In still further embodiments, a ratio of the height 250 to the height 246 being equal to or less than 1 improves the ability of the cover structure 116 to dissipate heat while reducing mechanical stress on the support structure 112 and underlying structures (e.g., the plurality of IC chips 104a-b). In various embodiments, the height 246 of the support structure 112 is equal to the height 250 of the cover structure 116. In yet further embodiments, the sum of the height 246 of the support structure 112, the height 248 of the thermal interface layer 240, and the height 250 of the lid structure 116 (e.g., height 246+height 248+height 250) is less than or equal to about 31 millimeters (mm) or some other suitable value. In such embodiments, the sum of the heights 246, 248, 250 being less than or equal to about 31 mm facilitates the heat dissipation structure 111 to effectively dissipate heat from the semiconductor package structure while reducing the overall height of the semiconductor package structure.

[0048] FIG. 3A to FIG. 3C Shown along Figure 2 The line A-A' intercepts Figure 2 Layout diagrams 300a-c of various embodiments of the package structure. For ease of description, FIG. 3A to FIG. 3C Shows Figure 2 The steam chamber 110 and IC chips 104a-b of the packaging structure are omitted. Figure 2 other structures.

[0049] like Figure 3A As shown in the layout diagram 300a of , the steam chambers 110 each have a circular shape. The width of the second portion 110p2 of each steam chamber 110 is greater than the width of the corresponding first portion 110p1. In various embodiments, the first portion 110p1 and the second portion 110p2 are concentric with each other. In various embodiments, when viewed from above, the first portion 110p1 and the second portion 110p2 can each have a circular shape, an elliptical shape, a rectangular shape or some other suitable shape.

[0050] like Figure 3BAs shown in the layout diagram 300b of FIG. 1 , the vapor chamber 110 is arranged in an array above each IC chip 104a-b, and the array includes multiple rows and multiple columns. It should be understood that although Figure 3B An array including two rows and three columns of vapor chambers 110 above each IC chip 104a-b is shown, but the number of rows and / or columns above the IC chips 104a-b is arbitrary.

[0051] like Figure 3C As shown in the layout diagram 300c of FIG. 1 , a plurality of IC chips 104a-b include a first device region 302 and a second device region 304, respectively. In some embodiments, the first device region 302 may include circuits and / or semiconductor devices that tend to generate local high temperatures in the corresponding IC chip. For example, the first device region 302 may include a CPU, a GPU, a high-voltage device, a high-density semiconductor device, etc. In addition, the second device region 304 may include, for example, a logic circuit, a low-voltage device, a low-density semiconductor device, etc. Accordingly, due to the type or function of the device in the first device region 302 and / or the density of the device, high temperature is likely to accumulate in the first device region 302 during the operation of the semiconductor package. Disposing the vapor chamber 110 above the first device region 302 of the IC chip 104a-b helps to effectively dissipate heat from the semiconductor device in the first device region 302. In a further embodiment, the vapor chamber 110 may be laterally offset from the second device region 304 of the IC chip 104a-b, thereby improving the support structure ( Figure 2 112) provides structural support for the semiconductor packaging structure.

[0052] Figure 4A Shows Figure 2 400a of some other embodiments of the semiconductor package structure, wherein the heat dispersion enhancement structure 231 extends along the opposite sidewalls and lateral surfaces of the second substrate 230, thereby defining the second portion 110p2 of each vapor chamber 110. This increases the ability of the heat dispersion enhancement structure 231 to assist / enhance the transfer of heat toward the cover structure 116. For example, by providing the heat dispersion enhancement structure 231 along the surface of the second portion 110p2 of the second substrate 230 that defines the vapor chamber 110, the surface area of ​​the heat dispersion enhancement layer 232 in the vapor chamber 110 is increased. Accordingly, the heat dispersion enhancement layer 232 can further assist / enhance the evaporation and / or condensation process in the vapor chamber 110 during operation of the semiconductor package structure. In various embodiments, when viewed in cross section, the dielectric layer 236, the seed layer 234, and the heat dispersion enhancement layer 232 each have a U-shape. In further embodiments, the dielectric layer 236 is part of the second dielectric layer 228.

[0053] Figure 4B Shows Figure 4A400b of some other embodiments of semiconductor package structures, wherein the second heat dispersion enhancement structure 402 is disposed along opposite sidewalls and lateral surfaces of the first portion 110p1 of the first substrate 224 defining each vapor chamber 110. In various embodiments, the second heat dispersion enhancement structure 402 is configured as Figure 2 In some embodiments, the heat dispersion enhancement structure 231 and the second heat dispersion enhancement structure 402 each include a dielectric layer 236 , a seed layer 234 , and a heat dispersion enhancement layer 232 .

[0054] The second heat dispersion enhancement structure 402 is disposed along the surface of the first portion 110p1 of the first substrate 224 defining the vapor chamber 110 to further improve the ability to transfer heat toward the cover structure 116. For example, the heat dispersion enhancement layer 232 of the second heat dispersion enhancement structure 402 assists / enhances the evaporation of the vaporizable working fluid in the vapor chamber 110 by dispersing the vaporizable working fluid onto the surface of the heat dispersion enhancement layer 232 by utilizing capillary action. In some embodiments, the relatively high thermal conductivity of the heat dispersion enhancement layer 232 can be beneficial for directing heat from the IC chips 104a-b to the vaporizable working fluid, thereby enhancing the evaporation of the vaporizable working fluid and improving the heat dissipation efficiency of the heat dissipation structure 111. In yet further embodiments, the heat dispersion enhancement layer 232 is disposed along a lateral surface 403 of the bottom of the second portion 110p2 of the first dielectric layer 226 defining each vapor chamber 110. Therefore, in some embodiments, the heat spreading enhancement layer 232 is disposed on all surfaces of the support structure 112 defining the vapor chamber 110 , thereby increasing the area of ​​the heat spreading enhancement layer 232 and the overall heat dissipation efficiency of the semiconductor package structure.

[0055] Figure 4C Shows Figure 4B 400c of some other embodiments of the semiconductor package structure, in which the dielectric layer ( Figure 4B In some embodiments, the seed layer 234 of the heat dispersion enhancement structure 231 directly contacts the surface of the second portion 110p2 of the second substrate 230 defining the vapor chamber 110, and the seed layer 234 of the second heat dispersion enhancement structure 402 directly contacts the surface of the first portion 110p1 of the first substrate 224 defining the vapor chamber 110.

[0056] Figure 4D Shows Figure 2400d of some other embodiments of the semiconductor package structure, wherein the opposite side walls of the second substrate 230 defining the second portion 110p2 of each vapor chamber 110 are inclined relative to a plane extending along the bottom surface of the second substrate 230. In various embodiments, the opposite side walls of the second substrate 230 are each inclined so that each side wall has an obtuse angle relative to the bottom surface of the second substrate 230, such as Figure 4D As shown. Accordingly, the second portion 110p2 of each steam chamber 110 may have, for example, a pyramid shape, a cone shape, a flat-topped pyramid shape, a flat-topped cone shape, a truncated cone shape, etc. Figure 4D As shown, by tilting the opposite sidewalls of the second substrate 230 defining the second portion 110p2 of each vapor chamber 110, the volume of each vapor chamber 110 can be increased, thereby improving the ability of the vapor chamber 110 to conduct heat to the cover structure 116 while maintaining the ability of the support structure 112 to provide structural support for the IC chips 104a-b. In various embodiments, the second portion 110p2 having a truncated cone shape facilitates guiding the vapor in the vapor chamber 110 in a vertical direction during operation of the semiconductor package structure.

[0057] Figure 4E Shows Figure 4D Some other embodiments of the semiconductor package structure are shown in cross-sectional view 400 e , in which the heat dispersion enhancement structure 231 extends along the inclined opposite sidewalls of the second substrate 230 defining the second portion 110 p 2 of each vapor chamber 110 .

[0058] Figure 4F Shown along Figure 4A The line B-B' intercepts Figure 4A FIG. 400f is a top view of some embodiments of a portion of a heat dispersion enhancement structure 231 in a semiconductor package structure. In various embodiments, Figure 4F A top view of a portion of the heat dispersion enhancement layer 232 is shown, wherein the heat dispersion enhancement layer 232 has a grid structure or mesh structure when viewed from above. In some embodiments, the heat dispersion enhancement layer 232 includes a plurality of opposing sidewalls defining a plurality of openings 410, wherein the heat dispersion enhancement layer 232 continuously surrounds each opening 410.

[0059] Figure 4G and Figure 4H Some embodiments of cross-sectional views 400g and 400h showing enlarged views of heat dispersion enhancement structures disposed in the vapor chamber 110 are shown.

[0060] Figure 4G Shows Figure 2FIG. 1 is an enlarged view of some embodiments of a separate vapor chamber 110 and a heat spreading enhancement structure 231 of a semiconductor package structure. In some embodiments, an outer sidewall of the heat spreading enhancement structure 231 directly contacts an opposite sidewall of the second substrate 230 .

[0061] Figure 4H Shows Figure 4B FIG. 1 is an enlarged view of some embodiments of a separate vapor chamber 110, a heat spreading enhancement structure 231, and a second heat spreading enhancement structure 402 of a semiconductor package structure. In some embodiments, a portion of the seed layer 234 and the heat spreading enhancement layer 232 of the second heat spreading enhancement structure 402 are disposed directly above the top surface of the first substrate 224.

[0062] Figure 5A Shows Figure 2 500a of some other embodiments of semiconductor package structures, wherein the heat dissipation structure 111 includes at least one vapor chamber 110, the at least one vapor chamber 110 having a second portion 110p2, the second portion 110p2 extending laterally from above the first IC chip 104a to above the second IC chip 104b continuously. In various embodiments, the vapor chamber 110 includes a second portion 110p2 and at least two first portions 110p1 located directly above both the first and second IC chips 104a-b. In some embodiments, at least two first portions 110p1 of the vapor chamber 110 are located directly above the corresponding regions 101 of the first and second IC chips 104a-b. In such embodiments, each region 101 of the first and second IC chips 104a-b is a potential local high temperature region of the corresponding IC chip, and may include high-power semiconductor devices, densely packaged semiconductor devices, and / or high computing components (e.g., CPU, GPU, etc.) of the IC chip. In various embodiments, the first portion 110p1 disposed above the corresponding region 101 of the IC chips 104a-b mitigates the formation of local high temperature regions in the IC chips 104a-b. Since the second portion 110p2 of the vapor chamber 110 is disposed above both the first and second IC chips 104a-b, the area of ​​the vapor chamber 110 is increased, thereby increasing the ability to effectively dissipate heat in a vertical direction toward the cover structure 116 and away from the IC chips 104a-b.

[0063] Figure 5B Shows Figure 2500 b of some other embodiments of the semiconductor package structure, wherein the semiconductor package structure further includes one or more steam channels 502 disposed in the support structure 112. The one or more steam channels 502 extend continuously between adjacent steam chambers in the plurality of steam chambers 110. In various embodiments, the one or more steam channels 502 are configured to fluidically connect the plurality of steam chambers 110 to each other. In some embodiments, the one or more steam channels 502 are formed by one or more surfaces of the second substrate 230 and / or one or more surfaces of the first substrate 224.

[0064] Figure 6 Shown along Figure 5B The line A-A' intercepts Figure 5B Layout diagram 600 of some embodiments of a semiconductor package structure. For ease of description, Figure 6 Shows Figure 5B The steam chamber 110, the steam channel 502 and the IC chips 104a-b of the semiconductor package structure are omitted. Figure 5B other structures.

[0065] like Figure 6 As shown, the steam channels 502 extend continuously laterally between adjacent steam chambers 110 and are configured to fluidly connect the steam chambers 110 to each other. In some embodiments, each steam channel 502 extends continuously between the second portions 110p2 of adjacent steam chambers 110. The first and second steam channels 502a-b extend continuously from the respective steam channels 502 to a point offset from the first and second IC chips 104a-b. In some embodiments, the first and second steam channels 502a-b extend to other steam chambers (not shown) located above other IC chips (not shown) in the semiconductor packaging structure. In further embodiments, the first and second steam channels 502a-b are fluidly connected to one or more vertical steam tubes (not shown) that are substantially parallel to the first and second steam chambers when viewed in cross section (e.g., when viewed in cross section). Figure 5B500b), the one or more vertical steam tubes extend in a vertical direction orthogonal to the top surfaces of the first and second IC chips 104a-b. In yet a further embodiment, one or more pipe plugs (not shown) are disposed in the vertical steam tubes and are configured to seal the steam chamber 110 at corresponding predetermined pressures and / or to seal the steam chamber 110 with a working fluid or working steam. In addition, the one or more vertical steam tubes are configured to facilitate the injection of working fluid or working steam into the multiple steam chambers. For example, the working fluid or working steam can flow into the multiple steam chambers 110 via the vertical steam tubes, and after the working fluid or working steam flows into the multiple steam chambers 110, the pipe plugs can be placed in the vertical steam tubes to seal the steam chambers 110. In various embodiments, the steam channels 502 facilitate the steam chambers 110 to have the same predetermined pressure and / or each have a substantially similar concentration or amount of working fluid or working steam. Thus, the steam chambers 110 can uniformly inject working fluid or working steam into the cover structure ( Figure 5B This enhances heat dissipation across the semiconductor package structure, thereby improving the overall performance and reliability of the semiconductor package structure.

[0066] Fig. 7A Shows Figure 2 700a of some other embodiments of semiconductor package structures, wherein the cover structure 116 is or includes a heat sink structure, which includes a plurality of heat sink fins 702 extending vertically upward from the base of the heat sink structure. The heat sink fins 702 are laterally spaced apart from each other so that air can flow between the heat sink fins 702 and dissipate the heat collected at the cover structure 116 to the external environment. In various embodiments, a fan (not shown) can be configured to guide the air between the heat sink fins 702 to take away the heat from the cover structure 116, thereby reducing the temperature of the cover structure 116. As a result, the ability of the heat dissipation structure 111 to effectively transfer heat away from the plurality of IC chips 104a-b is improved, thereby further improving the performance of the semiconductor package structure.

[0067] Figure 7B Shows Figure 2700 b of some other embodiments of the semiconductor package structure, wherein the cover structure 116 is or includes a liquid cooling structure, which includes a liquid cooling housing structure 704 and a liquid channel structure 706. The liquid channel structure 706 is disposed in the liquid cooling housing structure 704. In some embodiments, during operation of the semiconductor package structure, a liquid pump (not shown) is configured to circulate a liquid (e.g., water or another coolant) across the liquid channel structure 706. The liquid absorbs heat generated from the plurality of IC chips 104 a-b and is configured to be transported to an external cooler or heat exchanger (not shown) and / or is configured to be cooled by another structure (e.g., by a heat sink structure (not shown) disposed on the cover structure 116). This is conducive to further improving the heat dissipation performance of the semiconductor package structure, thereby further improving the performance of the semiconductor package structure.

[0068] Figures 8 to 17 Cross-sectional views 800-1700 of some embodiments of a method of forming a semiconductor package structure including a heat dissipation structure including one or more vapor chambers located above a plurality of integrated circuit (IC) chips are shown. Figures 8 to 17 The cross-sectional views 800-1700 shown in FIG. 8 are described with reference to the method, but it will be appreciated that Figures 8 to 17 The structure shown in is not limited to this method, but can exist independently of this method. Figures 8 to 17 Described as a series of actions, it is understood that these actions are not limited thereto, the order of the actions can be changed in other embodiments, and the disclosed method is also applicable to other structures. In other embodiments, some actions shown and / or described can be omitted in whole or in part.

[0069] like Figure 8 As shown in the cross-sectional view 800 of , a first dielectric layer 226 is formed on the first substrate 224. In some embodiments, the first dielectric layer 226 can be formed on the first substrate 224 by a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, a thermal oxidation process, or some other suitable deposition or growth process. The first substrate 224 can be or include, for example, silicon, epitaxial silicon, germanium, silicon germanium, or some other suitable substrate material. The first dielectric layer 226 can be or include, for example, an oxide (such as silicon dioxide) or some other suitable material.

[0070] like Fig. 9As shown in the cross-sectional view 900 of , a patterning process is performed on the first dielectric layer 226 and the first substrate 224 to form a plurality of first openings 904 in the first substrate 224. In some embodiments, the patterning process includes: forming a masking layer 902 on the first substrate 224; performing an etching process (e.g., a dry etching process) on the first substrate 224 and the first dielectric layer 226 according to the masking layer 902; and removing the masking layer 902 from above the first substrate 224 (not shown). In other embodiments, the process of forming the first openings 904 includes: patterning the first substrate 224 to form the first openings 904 in the first substrate 224; depositing (e.g., by CVD, PVD, ALD, thermal oxidation, etc.) the first dielectric layer 226 on the first substrate 224; and performing an etching process (e.g., a dry etching process, a wet etching process, etc.) to remove a portion of the first dielectric layer 226 from above the lower surface of the first substrate 224, the lower surface of the first substrate 224 defining the bottom of the first openings 904. In various embodiments, a heat dispersion enhancement structure (eg, Figure 4B and Figure 4C 402).

[0071] like Fig.10 As shown in the cross-sectional view 1000 of FIG. 1 , a patterning process is performed on the second substrate 230 to form a plurality of second openings 1004 in the second substrate 230. In some embodiments, the patterning process includes: forming a masking layer 1002 on the second substrate 230; performing an etching process (e.g., a dry etching process) on the second substrate 230; and removing the masking layer 1002 from above the second substrate 230 (not shown). The second substrate 230 may be or include, for example, silicon, epitaxial silicon, germanium, silicon germanium, or some other suitable substrate material.

[0072] like Fig.11As shown in the cross-sectional view 1100 of FIG. 1 , a second dielectric layer 228 is formed on the second substrate 230, and a heat dispersion enhancement structure 231 is formed on a lateral surface 1102 of the second substrate 230, the lateral surface 1102 defining at least a portion of each second opening 1004. In some embodiments, the second dielectric layer 228 may be formed on the second substrate 230 by a CVD process, a PVD process, an ALD process, a thermal oxidation process, or some other suitable deposition or growth process. In various embodiments, the heat dispersion enhancement structure 231 includes a dielectric layer 236, a seed layer 234 located on the dielectric layer 236, and a heat dispersion enhancement layer 232 located on the seed layer 234. The dielectric layer 236 may be formed on the lateral surface 1102 of the second substrate 230 by, for example, a CVD process, a PVD process, an ALD process, a thermal oxidation process, or some other suitable deposition or growth process. The seed layer 234 may be formed on the dielectric layer 236 by, for example, a CVD process, a PVD process, an ALD process, a thermal oxidation process, or some other suitable deposition or growth process. The heat spreading enhancement layer 232 may be formed on the seed layer 234 by, for example, a CVD process, a PVD process, an electroplating process, an electroless plating process, or some other suitable growth or deposition process. Figure 4F When viewed as shown and / or described above, the heat dispersion enhancement layer 232 has a grid structure or a mesh structure.

[0073] In yet a further embodiment, Fig.10 Before the patterning process, a second dielectric layer 228 may be formed on the second substrate 230. In such an embodiment, Fig.10 The second dielectric layer 228 is etched during the patterning process of the second dielectric layer 228. The second dielectric layer 228 can be or include, for example, silicon dioxide or some other suitable dielectric material. The seed layer 234 can be or include, for example, titanium, tantalum, nitride (e.g., titanium nitride, tantalum nitride, etc.), copper, etc. The heat dispersion enhancement layer 232 can be or include, for example, copper or some other suitable material.

[0074] like Fig.12 As shown in the cross-sectional view 1200 of , a steam chamber bonding process is performed to bond the first substrate 224 to the second substrate 230, and to form or define a plurality of steam chambers 110, thereby forming or defining a support structure 112. In some embodiments, the steam chambers 110 are defined by one or more surfaces of the support structure 112. The steam chambers 110 each include a first portion 110p1 and a second portion 110p2. In some embodiments, the width of the first portion 110p1 is less than the width of the second portion 110p2. In various embodiments, the steam chamber bonding process includes performing a steam chamber injection process to form a first and / or second opening ( Fig. 9 904 and / or Fig.111004) to form or deposit an evaporable working fluid or working vapor, and a bonding process to bond the first substrate 224 to the second substrate 230 and seal the vapor chamber 110. By performing a vapor chamber injection process before the bonding process, the plurality of vapor chambers 110 can be sealed with an evaporable working fluid or working vapor. In various embodiments, the process of forming the plurality of vapor chambers 110 includes Figures 8 to 12 The processing steps shown and / or described in .

[0075] In some embodiments, the vapor chamber injection process includes placing a vaporizable working fluid in the first and / or second openings ( Fig. 9 904 and / or Fig.11 1004). In various embodiments, the vaporizable working fluid may be or include, for example, chlorofluorocarbons, hydrochlorofluorocarbons, water, alcohol, silicone oil, liquid nitrogen, fluorinated fluids, acetone, methanol, ethanol, heptane, ammonia, some other suitable coolant, or any combination thereof. In some embodiments, the bonding process includes performing a melt bonding process or some other suitable bonding process. In various embodiments, the first opening (e.g., Fig. 9 904) (e.g. Fig. 9 ) corresponds to the first portion 110p1 of the vapor chamber 110, and a second opening (eg, Fig.11 1004) (e.g. Fig.10 ) shown and / or described corresponds to the second portion 110p2 of the steam chamber 110.

[0076] like Fig.13 As shown in the cross-sectional view 1300 of FIG. 1300 , a second dielectric bonding layer 108 b is formed on the support structure 112. In some embodiments, the second dielectric bonding layer 108 b is formed on the first substrate 224 of the support structure 112 by a CVD process, a PVD process, an ALD process, a thermal oxidation process, or some other suitable deposition or growth process. In various embodiments, before forming the second dielectric bonding layer 108 b, a planarization process (e.g., chemical mechanical polishing (CMP)) is performed on the first substrate 224 so that the upper surface of the first substrate 224 on which the second dielectric bonding layer 108 b is formed is substantially flat.

[0077] like Fig.14 As shown in the cross-sectional view 1400 of FIG. 1 , an IC structure 1402 is provided or otherwise formed, and the support structure 112 is bonded to the IC structure 1402. The IC structure 1402 includes a plurality of IC chips 104a-b located above the base structure 102. The plurality of IC chips 104a-b may be as shown in FIG. Figure 2In various embodiments, the base structure 102 is configured as an interposer, which includes a lower substrate 208, a plurality of TSVs 210, a plurality of conductive interconnect structures 212, and a first plurality of conductive bonding structures 214. In some embodiments, forming the IC structure 1402 includes: forming or otherwise providing the base structure 102 and a plurality of IC chips 104a-b; bonding the plurality of IC chips 104a-b to the base structure 102; and forming a fill layer 106 above the base structure 102 and around the IC chips 104a-b. In various embodiments, bonding the support structure 112 to the IC structure 1402 includes: forming (e.g., by CVD, PVD, ALD, etc.) a first dielectric bonding layer 108a on the plurality of IC chips 104a-b and the filling layer 106; performing an alignment process (e.g., an optical alignment process using one or more alignment marks) to precisely align the support structure 112 over the plurality of IC chips 104a-b; and performing a bonding process (e.g., a fusion bonding process) to bond the support structure 112 to the IC structure 1402. In further embodiments, before forming the first dielectric bonding layer 108a on the plurality of IC chips 104a-b, a planarization process (e.g., a CMP process) is performed on the plurality of IC chips 104a-b and the filling layer 106 so that upper surfaces of the IC chips 104a-b and the filling layer 106 are substantially planar and / or coplanar with each other.

[0078] In yet further embodiments, before the support structure 112 is bonded to the IC structure 1402, a first plurality of conductive structures (not shown) may be formed or disposed in the first dielectric bonding layer 108a, and a second plurality of conductive structures (not shown) may be formed or disposed in the second dielectric bonding layer 108b. The conductive structures may be or include, for example, copper or some other suitable material. In various embodiments, when the support structure is bonded to the IC structure 1402, the first plurality of conductive structures are aligned with the second plurality of conductive structures. In such embodiments, the support structure 112 meets the IC structure 1402 at a bonding interface that includes a dielectric-to-dielectric bond and a conductor-to-conductor bond. In various embodiments, one or more conductive structures are laterally aligned with each vapor chamber 110.

[0079] like Fig.15As shown in the cross-sectional view 1500 of FIG. 15 , a thermal interface structure 114 and a cover structure 116 are formed above the support structure 112, thereby defining or forming a heat dissipation structure 111 above the plurality of IC chips 104a-b. In some embodiments, the thermal interface structure 114 includes a first thermal dispersion layer 238, a thermal interface layer 240, and a second thermal dispersion layer 242. The first thermal dispersion layer 238 and the second thermal dispersion layer 242 can be or include, for example, a metal such as copper, aluminum, nickel, cobalt, some other metal, or an alloy thereof. The thermal interface layer 240 can be or include, for example, lead, tin, silver, copper, indium, an alloy thereof (e.g., a solder alloy), or other suitable materials. The cover structure 116 can be or include, for example, copper, aluminum, other suitable high thermal conductivity materials, etc.

[0080] In various embodiments, the process of forming the thermal interface structure 114 and the cover structure 116 includes: forming a first thermal dispersion layer 238 on the second substrate 230 (e.g., by CVD, PVD, electroplating, chemical plating, etc.); forming a second thermal dispersion layer 242 on the cover structure 116 (e.g., by CVD, PVD, electroplating, chemical plating, etc.); forming a thermal interface layer 240 on the first thermal dispersion layer 238 (e.g., by a screen printing process, a spraying process, a paste or grease application process, a dispensing process, a deposition process, etc.); and performing a bonding process (e.g., a reflow process) to bond the second thermal dispersion layer 242 and the cover structure 116 to the support structure 112 via the thermal interface layer 240. For example, the bonding process includes, after the cover structure 116 is disposed on the thermal interface layer 240, heating the thermal interface layer 240 to its melting point, and performing a cooling process to bond the cover structure 116 to the support structure 112.

[0081] like Fig.16 As shown in the cross-sectional view 1600 of FIG. 1 , a thinning process is performed on the lower substrate 208. In some embodiments, the thinning process reduces the thickness of the lower substrate 208 from the first thickness 1602 to the second thickness 1604 and exposes the bottom surface of the TSV 210. The thinning process may be or include, for example, a CMP process, a mechanical grinding process, or some other suitable process.

[0082] like Fig.17 As shown in the cross-sectional view 1700 of , a plurality of lower bonding pads 204 and a plurality of solder bumps 202 are formed along the lower surface of the lower substrate 208. In some embodiments, forming the plurality of lower bonding pads 204 includes: forming (e.g., by CVD, PVD, ALD, etc.) a lower dielectric layer 206 along the lower surface of the lower substrate 208; etching the lower dielectric layer 206 to form a plurality of openings in the lower dielectric layer 206; and forming the plurality of lower bonding pads 204 in the plurality of openings.

[0083] Fig.18A flow chart of some embodiments of a method 1800 for forming a semiconductor package structure is shown, and the semiconductor package structure includes a heat dissipation structure, and the heat dissipation structure includes one or more steam chambers located above multiple IC chips. Although method 1800 is shown and / or described as a series of actions or events, it is understood that the method is not limited to the order or actions shown. Therefore, in some embodiments, the actions can be implemented in an order different from that shown, and / or can be implemented simultaneously. In addition, in some embodiments, the actions or events shown can be subdivided into multiple actions or events, which can be implemented at different times or implemented simultaneously with other actions or sub-actions. In some embodiments, some of the actions or events shown can be omitted, and other actions or events not shown can be included.

[0084] At act 1802, a plurality of first openings are formed in a first substrate. Fig. 9 Cross-sectional view 900 corresponding to some embodiments of act 1802 is shown.

[0085] At act 1804, a plurality of second openings are formed in a second substrate. Fig.10 Cross-sectional view 1000 corresponding to some embodiments of act 1804 is shown.

[0086] At operation 1806, a heat spreading enhancement structure is formed in the plurality of second openings. Fig.11 Cross-sectional view 1100 corresponding to some embodiments of act 1806 is shown.

[0087] At action 1808, a vapor chamber bonding process is performed to bond the first substrate to the second substrate, thereby defining or forming a support structure and a plurality of vapor chambers. The vapor chamber bonding process includes performing a vapor chamber injection process to form a vaporizable working fluid in the plurality of vapor chambers, and performing a bonding process to bond the first substrate and the second substrate to each other and seal the vapor chambers. Fig.12 Cross-sectional view 1200 corresponding to some embodiments of act 1808 is shown.

[0088] At act 1810 , an IC structure including a plurality of IC chips on a base structure is provided or otherwise formed. Fig.14 Cross-sectional view 1400 corresponding to some embodiments of act 1810 is shown.

[0089] At act 1812, a lid structure is bonded to an IC structure, wherein a plurality of vapor chambers are positioned directly over one or more IC chips. Fig.14 Cross-sectional view 1400 corresponding to some embodiments of act 1812 is shown.

[0090] At act 1814 , a thermal interface structure and a lid structure are formed on the support structure, thereby defining or forming a heat sink structure over the plurality of IC chips. Fig.15 Cross-sectional view 1500 corresponding to some embodiments of act 1814 is shown.

[0091] At act 1816, a plurality of solder bumps are formed on the lower surface of the base structure. Fig.17 Cross-sectional view 1700 corresponding to some embodiments of act 1816 is shown.

[0092] Accordingly, in some embodiments, the present disclosure relates to a semiconductor package structure having a heat dissipation structure including one or more vapor chambers located above a plurality of IC chips, and a cover structure located above the one or more vapor chambers.

[0093] In some embodiments, the present application provides a semiconductor packaging structure. The semiconductor packaging structure includes: a support structure including a first surface opposite to a second surface; a first integrated circuit (IC) chip located on the first surface of the support structure; a cover structure located on the second surface of the support structure; and a vapor chamber disposed in the support structure and located at least partially above the first IC chip. In an embodiment, the vapor chamber includes a first chamber portion and a second chamber portion disposed above the first chamber portion, wherein the width of the first chamber portion is less than the width of the second chamber portion. In an embodiment, the width of the first chamber portion is constant, wherein the width of the second chamber portion decreases continuously from the bottom of the second chamber portion in a direction toward the cover structure. In an embodiment, the support structure includes a first substrate and a second substrate located above the first substrate, wherein the first chamber portion is defined by one or more surfaces of the first substrate, and the second chamber portion is defined by one or more surfaces of the second substrate. In an embodiment, the vapor chamber includes a vaporizable working fluid sealed in the vapor chamber. In an embodiment, the support structure includes one or more substrates and one or more dielectric layers, wherein the thermal conductivity of the cover structure is greater than the thermal conductivity of the one or more substrates and the one or more dielectric layers. In an embodiment, the height of the cover structure is less than the height of the support structure. In an embodiment, the semiconductor package structure further includes: a thermal interface structure disposed between the cover structure and the support structure, wherein the thermal interface structure includes a first thermal dispersion layer, a second thermal dispersion layer, and a thermal interface layer located between the first thermal dispersion layer and the second thermal dispersion layer, wherein the first thermal dispersion layer and the second thermal dispersion layer include a first material different from a second material of the thermal interface layer.

[0094] In some embodiments, the present application provides a semiconductor packaging structure. The semiconductor packaging structure includes: an interposer structure including a plurality of conductive interconnect structures; a plurality of integrated circuit (IC) chips located on the plurality of conductive interconnect structures and electrically coupled to the plurality of conductive interconnect structures; and a heat dissipation structure located on the plurality of IC chips, wherein the heat dissipation structure includes: a support structure located on the plurality of IC chips; a thermal interface structure located on the support structure; a heat sink structure located on the thermal interface structure; and one or more vapor chambers embedded in the support structure, wherein the one or more vapor chambers respectively include a bottom surface facing the plurality of IC chips having a first width and a top surface facing the heat sink structure having a second width, wherein the first width is less than the second width. In an embodiment, a heat dispersion enhancement structure is disposed in one or more vapor chambers, wherein the heat dispersion enhancement structure includes a heat dispersion enhancement layer, and the heat dispersion enhancement layer has a thermal conductivity greater than the thermal conductivity of the support structure. In an embodiment, when viewed from a top view, the heat dispersion enhancement layer has a mesh layout. In an embodiment, one or more vapor chambers include a vaporizable working fluid sealed therein, and wherein the heat dispersion enhancement layer is configured to assist in evaporating the vaporizable working fluid. In an embodiment, the heat spreading enhancement layer and the heat sink structure respectively comprise the same thermally conductive material. In an embodiment, the height of the heat sink structure is greater than the height of the one or more vapor chambers. In an embodiment, the ratio of the height of the heat sink structure to the height of the support structure is in the range of 0.34 to 1.

[0095] In some embodiments, the present application provides a method for forming a semiconductor package structure, the method comprising: arranging a plurality of integrated circuit (IC) chips on an interposer structure; forming a vapor chamber in a support structure; bonding the support structure to the plurality of IC chips, wherein the vapor chamber is placed above at least a portion of a single IC chip in the plurality of IC chips; and bonding a cover structure to the support structure, wherein the thermal conductivity of the cover structure is greater than the thermal conductivity of the support structure. In an embodiment, forming the vapor chamber comprises: etching a first substrate to define a first chamber portion in the first substrate; etching a second substrate to define a second chamber portion in the second substrate, wherein the width of the second chamber portion is greater than the width of the first chamber portion; and performing a bonding process to bond the first substrate to the second substrate, thereby sealing the vapor chamber, wherein the first chamber portion is laterally aligned with the second chamber portion. In an embodiment, forming the vapor chamber further comprises: before performing the bonding process, arranging at least one vaporizable working fluid in the first chamber portion and / or the second chamber portion, wherein the bonding process seals the at least one vaporizable working fluid in the vapor chamber. In an embodiment, the method further comprises: forming a heat dispersion enhancement structure along at least one of the one or more surfaces of the support structure defining the vapor chamber, wherein the heat dispersion enhancement structure comprises a wicking layer. In an embodiment, the support structure comprises a substrate, wherein the substrate comprises silicon and the cap structure comprises copper.

[0096] The features of several embodiments are summarized above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should understand that they can easily use the present disclosure as a basis to design or modify other processes and structures for implementing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and modifications herein without departing from the spirit and scope of the present disclosure.

Claims

1. A semiconductor packaging structure, comprising: a support structure comprising a first surface opposite a second surface; a first integrated circuit chip located on the first surface of the support structure; a cover structure located on the second surface of the support structure; as well as A vapor chamber is disposed in the support structure and is located over at least a portion of the first integrated circuit chip.

2. The semiconductor package structure according to claim 1, wherein: The steam chamber includes a first chamber portion and a second chamber portion disposed above the first chamber portion, wherein a width of the first chamber portion is smaller than a width of the second chamber portion.

3. The semiconductor package structure according to claim 2, wherein: The width of the first chamber portion is constant, wherein the width of the second chamber portion decreases continuously from a bottom of the second chamber portion in a direction towards the cover structure.

4. The semiconductor package structure according to claim 2, wherein: The support structure includes a first substrate and a second substrate located above the first substrate, wherein the first chamber portion is defined by one or more surfaces of the first substrate and the second chamber portion is defined by one or more surfaces of the second substrate.

5. The semiconductor package structure according to claim 1, wherein: The vapor chamber includes a vaporizable working fluid sealed within the vapor chamber.

6. The semiconductor package structure according to claim 1, wherein: The support structure includes one or more substrates and one or more dielectric layers, wherein the cover structure has a thermal conductivity greater than a thermal conductivity of the one or more substrates and the one or more dielectric layers.

7. The semiconductor package structure according to claim 6, wherein: The height of the cover structure is smaller than the height of the support structure.

8. The semiconductor package structure according to claim 1, further comprising: A thermal interface structure is disposed between the cover structure and the support structure, wherein the thermal interface structure includes a first thermal dispersion layer, a second thermal dispersion layer, and a thermal interface layer located between the first thermal dispersion layer and the second thermal dispersion layer, wherein the first thermal dispersion layer and the second thermal dispersion layer include a first material different from a second material of the thermal interface layer.

9. A semiconductor packaging structure, comprising: an interposer structure including a plurality of conductive interconnect structures; a plurality of integrated circuit chips located on and electrically coupled to the plurality of conductive interconnect structures; as well as A heat dissipation structure is located on the plurality of integrated circuit chips, wherein the heat dissipation structure comprises: a support structure located on the plurality of integrated circuit chips; a thermal interface structure, located on the support structure; a heat sink structure located on the thermal interface structure; and One or more vapor chambers are embedded in the support structure, wherein the one or more vapor chambers respectively include a bottom surface having a first width facing the multiple integrated circuit chips and a top surface having a second width facing the heat sink structure, wherein the first width is smaller than the second width.

10. A method for forming a semiconductor package structure, comprising: Disposing a plurality of integrated circuit chips on the interposer structure; forming a steam chamber within the support structure; bonding the support structure to the plurality of integrated circuit chips, wherein the vapor chamber is disposed over at least a portion of a single integrated circuit chip of the plurality of integrated circuit chips; and A cover structure is bonded to the support structure, wherein a thermal conductivity of the cover structure is greater than a thermal conductivity of the support structure.

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