LIN bus receiver circuit, chip and electronic equipment

Abstract

The embodiment of the invention provides an LIN bus receiver circuit, a chip and electronic equipment, and belongs to the field of circuit design. The circuit comprises an input stage circuit used for accessing and preprocessing a power supply voltage and an LIN bus voltage; the comparison circuit is used for comparing the preprocessed power supply voltage and the preprocessed LIN bus voltage by taking current as a parameter, outputting an overturning threshold value of the LIN bus according to a comparison result and realizing hysteresis of the overturning threshold value; and the output stage circuit is used for outputting a receiver output level signal according to the flip threshold. According to the embodiment of the invention, the hysteresis comparison circuit is designed, and the hysteresis amount is introduced for the overturning threshold value of the LIN receiver, so that the anti-electromagnetic interference capability and the overturning threshold value precision of the LIN bus are greatly improved.

Description

Technical Field

[0001] The present invention relates to the field of circuit design, in particular to the field of circuit design for chips or interfaces, and specifically to a LIN bus receiver circuit, chip and electronic equipment. Background Art

[0002] The Local Interconnect Network (LIN) bus is a single-wire, serial, low-speed, low-cost bus defined for distributed automotive electronic systems. It is mainly used in the control of car doors, steering wheels, seats, air conditioners, lighting, humidity / temperature / pressure sensors and brakes.

[0003] Figure 1 This is a schematic diagram of the definition of the LIN protocol receiving threshold. Figure 1 As shown, the LIN bus voltage V LIN At the power supply voltage V SUP The two dotted lines represent the receiver flip threshold V corresponding to the rising edge of the LIN bus. th(rec) The falling edge of the LIN bus corresponds to the receiver flip threshold V th(dom) , t bus(dom) and t bus(rec) are the bit widths of the corresponding dominant level and recessive level, respectively, RXD represents the receiver output level signal, where tp(rx)f and tp(rx)r represent the delay time of the receiver output signal relative to the corresponding flip threshold. Furthermore, the LIN bus protocol ISO17987 has strict requirements on the receiver flip threshold, including:

[0004] (1) LIN bus rising edge corresponds to the receiver flip threshold V th(rec) ≤0.6*V SUP ;

[0005] (2) LIN bus falling edge corresponds to the receiver flip threshold V th(dom) ≥0.4*V SUP ;

[0006] (3) Receiver center flip threshold V th(center) =(V th(rec) +V th(dom) ) / 2, and requires 0.475*V SUP ≤V th(center) ≤0.525*V SUP .

[0007] Based on these requirements, how to improve the accuracy of the LIN bus receiver flip threshold is a key technical difficulty in the design of LIN receiver circuits. In addition, the LIN bus receiver circuit belongs to the interface circuit, and for the interface circuit, EMI (Electromagnetic Interference) can easily introduce nonlinear effects at the input stage, resulting in DC offset and signal distortion. The automotive electronic environment (high temperature, high voltage, high EMI) is very harsh, so the electromagnetic compatibility (EMC) performance requirements of automotive electronic equipment and automotive-grade chips are extremely high. Therefore, how to improve the ability to resist electromagnetic interference is a key technical difficulty in improving the reliability of LIN bus receivers.

[0008] However, in order to meet the above-mentioned flip threshold requirements, the existing public technology often designs a rising edge flip threshold V th(rec) Equal to the falling edge flip threshold V th(dom) , so that V LIN =0.5*V SUP However, this ideal state does not conform to the actual situation. In fact, there is a lack of hysteresis design for the rising edge / falling edge, which cannot meet the Figure 1 The delay time requirement is shown. And, if the rising edge flips the threshold V th(rec) Equal to the falling edge flip threshold V th(dom) When the LIN bus voltage has a small disturbance near the flip threshold, a narrow pulse will appear in the final receiver output signal, which will cause receiver data errors, making it insufficient in flip threshold accuracy and anti-electromagnetic interference. Summary of the invention

[0009] The purpose of the embodiments of the present invention is to provide a LIN bus receiver circuit, chip and electronic device, which are used to at least partially solve the above technical problems.

[0010] In order to achieve the above-mentioned purpose, a first aspect of an embodiment of the present invention provides a LIN bus receiver circuit, comprising: an input stage circuit, used to connect a power supply voltage and a LIN bus voltage, and use an input resistor to preprocess the power supply voltage and the LIN bus voltage; a hysteresis comparison circuit, which is connected to the input stage circuit, and is used to compare the preprocessed power supply voltage and the LIN bus voltage with current as a parameter, and output a flip threshold of the LIN bus and implement the hysteresis of the flip threshold according to the comparison result; and an output stage circuit, which is connected to the hysteresis comparison circuit, and is used to output a receiver output level signal according to the flip threshold.

[0011] Optionally, the input stage circuit includes: a first resistor R1 and a first capacitor C1, one end of the first resistor R1 is connected to the power supply voltage, and the other end is grounded through the first capacitor C1; and a second resistor R2 and a second capacitor C2, one end of the second resistor R2 is connected to the LIN bus voltage, and the other end is grounded through the second capacitor C2.

[0012] Optionally, the hysteresis comparison circuit includes a current comparison circuit and a hysteresis setting circuit.

[0013] Wherein, the current comparison circuit includes: a first NMOS tube NM1, whose drain is connected to the gate and connected to the first node P1, and whose source is the second node P2, wherein the first node P1 is set between the first resistor R1 and the first capacitor C1; a second NMOS tube NM2, whose drain is connected to the gate and connected to the second node P2, and whose source is grounded; a third NMOS tube NM3, whose drain is connected to the fifth node P5, whose gate is connected to the gate of the second NMOS tube NM2, and whose source is grounded, wherein the fifth node P5 is set between the second resistor R2 and the second capacitor C2; a fourth NMOS tube NM4, whose gate is connected to the gate of the first NMOS tube NM1, whose drain is the third node P3, and whose source is connected to the drain of the fifth NMOS tube NM5; the fifth NMOS tube NM5, whose drain is connected to the gate of the fourth NMOS tube NM4; a sixth NMOS tube NM6, whose gate is connected to the fifth node P5, whose drain is connected to the fourth node P4, and whose source is grounded, wherein the fourth node P4 outputs the flip threshold, and the current injected into the fourth node P4 from the drain of the sixth NMOS tube NM6 is the discharge current for the hysteresis comparison circuit 200; and a first PMOS tube PM1 and a second PMOS tube PM2, whose sources are both connected to the working voltage and whose gates are connected, whose drain is connected to the third node P3, whose drain is connected to the fourth node P4, and whose current injected into the fourth node P4 from the drain of the second PMOS tube PM2 is the charge current for the hysteresis comparison circuit 200.

[0014] The hysteresis setting circuit is used to adjust the discharge current of the hysteresis comparison circuit or the input resistance of the input stage circuit 100 to achieve the hysteresis of the flip threshold.

[0015] Optionally, the hysteresis setting circuit includes: a seventh NMOS tube NM7, whose gate is connected to the receiver output level signal, whose drain is connected to the fourth node P4, and whose source is connected to the drain of the eighth NMOS tube NM8; and the eighth NMOS tube NM8, whose gate is connected to the fifth node P5, whose drain is connected to the source of the seventh NMOS tube NM7, and whose source is grounded.

[0016] Optionally, the first NMOS tube NM1, the second NMOS tube NM2, the third NMOS tube NM3, the fourth NMOS tube NM4, the fifth NMOS tube NM5 and the seventh NMOS tube NM7 have the same width-to-length ratio, and the ratio of the width-to-length ratios of the third NMOS tube NM3, the sixth NMOS tube NM6 and the eighth NMOS tube NM8 is 1:(1-k):2k, where k is any value greater than zero and less than 1.

[0017] Optionally, the hysteresis setting circuit includes: a third resistor R3, which is connected in series between the first resistor R1 and the first capacitor C1; a fourth resistor R4, which is connected in series between the second resistor R2 and the second capacitor C2; a seventh NMOS tube NM7, whose gate is connected to the level signal corresponding to the fourth node P4, the drain is connected to the end of the third resistor R3 connected to the first resistor R1, and the source is connected to the end of the third resistor R3 connected to the first capacitor C1; and an eighth NMOS tube NM8, whose gate is connected to the receiver output level signal, the drain is connected to the end of the fourth resistor R4 connected to the second resistor R2, and the source is connected to the end of the fourth resistor R4 connected to the second capacitor C2.

[0018] Optionally, the first NMOS tube NM1, the second NMOS tube NM2, the third NMOS tube NM3, the fourth NMOS tube NM4, the fifth NMOS tube NM5, the sixth NMOS tube NM6, the seventh NMOS tube NM7 and the eighth NMOS tube NM8 have the same width-to-length ratio.

[0019] Optionally, the output stage circuit includes: a Schmitt trigger, which is connected to the hysteresis comparison circuit and is used to de-glitch the output signal of the hysteresis comparison circuit; and an inverter, which is connected to the Schmitt trigger and is used to invert the signal after the de-glitch processing to output the receiver output level signal.

[0020] A second aspect of an embodiment of the present invention provides a chip, comprising any of the above-mentioned LIN bus receiver circuits.

[0021] A third aspect of an embodiment of the present invention provides an electronic device, comprising any of the above-mentioned LIN bus receiver circuits or chips.

[0022] Through the above technical scheme, the embodiment of the present invention designs a hysteresis comparison circuit. Compared with the LIN bus receiver design in the existing public technology that lacks a hysteresis link, a hysteresis amount is introduced for the flip threshold of the rising edge-falling edge of the receiver, thereby greatly improving the anti-electromagnetic interference capability and flip threshold accuracy of the LIN bus.

[0023] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0025] Figure 1 This is a schematic diagram of the definition of the LIN protocol receiving threshold;

[0026] Figure 2 is a schematic structural diagram of a LIN bus receiver circuit according to an embodiment of the present invention;

[0027] Figure 3 is a schematic diagram of a LIN bus receiver circuit of application example 1 of an embodiment of the present invention; and

[0028] Figure 4 Schematic diagram of a LIN bus receiver circuit of application example 2 of an embodiment of the present invention.

[0029] Description of Reference Numerals

[0030] 100, input stage circuit; 200, hysteresis comparison circuit; 300, output stage circuit;

[0031] 210. Current comparison circuit; 220. Hysteresis setting circuit. DETAILED DESCRIPTION

[0032] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0033] It should be noted that the “connection” and “access” involved in the embodiments of the present invention mainly refer to “electrical connection”, which is used to express the signal connection between two components, such as connection through a circuit, and the “connection” and “access” involved can be a direct electrical connection between the two components, or an indirect electrical connection through other components or circuits.

[0034] In addition, descriptions such as “first”, “second”, and “third” in the embodiments of the present invention are only used to distinguish between elements and should not be understood as indicating or implying the relative importance of the elements.

[0035] Figure 2 FIG. 1 is a schematic diagram of the structure of a LIN bus receiver circuit according to an embodiment of the present invention. Figure 2 As shown, the LIN bus receiver circuit includes: an input stage circuit 100, which is used to access the power supply voltage and the LIN bus voltage, and use the input resistor to process the power supply voltage and the LIN bus voltage; a hysteresis comparison circuit 200, which is connected to the input stage circuit 100, and is used to compare the pre-processed power supply voltage and the LIN bus voltage with the current as a parameter, and output the flip threshold of the LIN bus and realize the hysteresis of the flip threshold according to the comparison result; an output stage circuit 300, which is connected to the hysteresis comparison circuit 200, and is used to output the receiver output level signal according to the flip threshold.

[0036] The hysteresis comparison circuit 200 compares the power supply voltage and the LIN bus voltage using the current as a parameter, which is equivalent to implementing a current analog comparison circuit, so that the comparison between the power supply voltage and the LIN bus voltage is converted from voltage comparison to current comparison.

[0037] Thus, the embodiment of the present invention designs a hysteresis comparison circuit 200. Compared with the LIN bus receiver design lacking a hysteresis link in the prior art, a hysteresis amount is introduced for the flip threshold of the rising edge-falling edge of the receiver, so that it satisfies the following conditions: Figure 1 The definition of the LIN protocol receiving threshold greatly improves the LIN bus's anti-electromagnetic interference capability and flip threshold accuracy.

[0038] The circuit implementation and working principle of the LIN bus receiver circuit according to the embodiment of the present invention are specifically described below by way of examples.

[0039] Application Example 1

[0040] Figure 3 FIG. 1 is a schematic diagram of a LIN bus receiver circuit according to an application example 1 of an embodiment of the present invention. Figure 3 The input stage circuit 100, the hysteresis comparison circuit 200 and the output stage circuit 300 involved above will be described as follows.

[0041] 1. Input stage circuit 100.

[0042] In the first application example, the input stage circuit 100 includes a first resistor R1 and a first capacitor C1 and a second resistor R2 and a second capacitor C2.

[0043] One end of the first resistor R1 is connected to the power supply voltage V SUP The other end is connected to the ground through the first capacitor C1. One end of the second resistor R2 is connected to the LIN bus voltage V LIN , and the other end is grounded through the second capacitor C2.

[0044] Here, the first resistor R1 and the second resistor R2 serve as input resistors of the input stage circuit 100 and can be set to a larger value to reduce the current flowing through the corresponding circuit, thereby realizing circuit protection and voltage-to-current conversion functions. In the example, the ratio of the equivalent resistance values ​​of the first resistor R1 and the second resistor R2 is as follows: Figure 3 The 2:1 shown in the figure can be flexibly adjusted according to actual needs and specific scenarios to assist the hysteresis comparison circuit 200 in subsequent comparisons using current as a parameter.

[0045] In other examples, the input stage circuit 100 may also include only the first resistor R1 and the second resistor R2. However, the first application example of the embodiment of the present invention forms a first-order low-pass filter with a pole of about tens of kHz by connecting the first capacitor C1 and the second capacitor C2 to the ground in series at the ends of the corresponding resistors, so as to directly suppress the high-frequency electromagnetic interference from the LIN bus or the bus power supply.

[0046] 2. Hysteresis comparison circuit 200.

[0047] In the first application example, the hysteresis comparison circuit 200 includes a current comparison circuit 210 and a hysteresis setting circuit 220 , and the current comparison circuit 210 includes the following NMOS transistors NM1 - NM6 and PMOS transistors PM1 - PM2 .

[0048] The drain of the first NMOS transistor NM1 is connected to the gate and connected to the first node P1, and the source is the second node P2, wherein the first node P1 is arranged between the first resistor R1 and the first capacitor C1.

[0049] The second NMOS transistor NM2 has a drain connected to a gate and connected to the second node P2, and a source connected to the ground.

[0050] The third NMOS transistor NM3 has a drain connected to a fifth node P5, a gate connected to the gate of the second NMOS transistor NM2, and a source grounded, wherein the fifth node P5 is arranged between the second resistor R2 and the second capacitor C2.

[0051] The fourth NMOS transistor NM4 has a gate connected to the gate of the first NMOS transistor NM1, a drain as the third node P3, and a source connected to the drain of the fifth NMOS transistor NM5.

[0052] The fifth NMOS transistor NM5 has a drain connected to the source of the fourth NMOS transistor NM4 , a gate connected to the gates of the second NMOS transistor NM2 and the third NMOS transistor NM3 , and a source grounded.

[0053] The sixth NMOS transistor NM6 has a gate connected to the fifth node P5, a drain connected to the fourth node P4, and a source grounded, wherein the fourth node P4 outputs the flip threshold, and the current injected into the fourth node P4 from the drain of the sixth NMOS transistor NM6 is the discharge current for the hysteresis comparison circuit 200.

[0054] The sources of the first PMOS tube PM1 and the second PMOS tube PM2 are both connected to the operating voltage VCC and the gates of the two are connected, the drain of the first PMOS tube PM1 is connected to the third node P3, the drain of the second PMOS tube PM2 is connected to the fourth node P4, and the current injected from the drain of the second PMOS tube PM2 into the fourth node P4 is the charging current for the hysteresis comparison circuit 200.

[0055] As mentioned above, the first node P1 and the fifth node P5 are respectively the two input terminals of the hysteresis comparator circuit 200, and are therefore referred to as input nodes hereinafter, while the fourth node P4 is the output terminal of the hysteresis comparator circuit 200, and is therefore referred to as an output node hereinafter, wherein the charging current and the discharging current are determined in association with whether the output node P4 is charged or discharged.

[0056] The comparison using current as a parameter implemented by the hysteresis comparison circuit 200 of the first application example is analyzed below based on each node.

[0057] For the lines corresponding to the input nodes P1 and P5, the following equation holds:

[0058] I DS_NM3 =(V LIN -V DS_NM3 ) / R2 (1)

[0059] I DS_NM2 =(V SUP -V GS_NM1 -V GS_NM2 ) / R1 (2)

[0060] Among them, the gate-source voltage, drain-source voltage and drain-source current of any MOS tube are defined as V GS_X 、V DS_X and I DS_X , where X represents the corresponding MOS tube number, and R1 and R2 are defined as the equivalent resistance values ​​of the first resistor R1 and the second resistor R2, respectively, V LIN is the LIN bus voltage, V SUPis the power supply voltage.

[0061] At the flip threshold point of the hysteresis comparison circuit 200, that is, the output node P4, without introducing the hysteresis setting circuit 220, the ideal state without considering electromagnetic interference is that the charging and discharging currents of the node P4 are equal. At this time, the voltage (V GS_NM6 ) and P2 node (V GS_NM5 ) are equal, so the following equation holds:

[0062] V DS_NM3 =V DS_NM2 =V GS_NM2 =V GS_NM3 (3)

[0063] At this time, the input current I DS_NM3 =I DS_NM2 , and then substitute it into formula (1) and formula (2), we can get:

[0064] V LIN =(R2 / R1)*V SUP +[V GS_NM3 -(R2 / R1)*(V GS_NM1 +V GS_NM2 )] (4)

[0065] When R1=2*R2 and the threshold voltages of NMOS tubes NM1, NM2, NM3, NM5 and NM6 are equal (i.e. V th_NM1 =V th_NM2 =V th_NM3 =V th_NM5 =V th_NM6 ), the following equation holds:

[0066] V LIN =0.5*V SUP (5)

[0067] Among them, V th_X represents the threshold voltage of the MOS tube when the body effect is considered, where X represents the corresponding MOS tube number. To ensure that the formula (5) is established, according to formulas (3) and (4) and whether the body effect of the MOS tube, the channel length modulation effect of the saturation region MOS tube, etc. are considered, it is necessary to ensure that the first NMOS tube NM1, the second NMOS tube NM2 and the third NMOS tube NM3 are completely consistent in threshold, leakage current and size, that is, their width-to-length ratio W / L is completely the same.

[0068] However, the above formula (5) belongs to the ideal situation. In fact, due to non-ideal factors such as device matching accuracy and MOS tube threshold body effect, VLIN will fluctuate around 0.5*VSUP, resulting in loss of threshold accuracy. In addition, the establishment of formula (5) also requires that the LIN bus rising edge flip threshold Vth(rec) Equal to the falling edge flip threshold V th(dom) However, in practice it is difficult to avoid small disturbances in the LIN bus voltage near the flip threshold.

[0069] In this regard, a hysteresis setting circuit 220 is further designed in the hysteresis comparison circuit 200 of the first application example, which adjusts the above-mentioned discharge current to achieve the hysteresis of the flip threshold.

[0070] refer to Figure 3 The hysteresis setting circuit 220 includes a seventh NMOS transistor NM7 and an eighth NMOS transistor NM8.

[0071] As for the seventh NMOS transistor NM7, its gate is connected to the receiver output level signal, its drain is connected to the fourth node P4, and its source is connected to the drain of the eighth NMOS transistor NM8.

[0072] As for the eighth NMOS transistor NM8 , its gate is connected to the fifth node P5 , its drain is connected to the source of the seventh NMOS transistor NM7 , and its source is grounded.

[0073] Furthermore, for Figure 3 The dimensions of each NMOS tube involved are designed to ensure the normal operation of the related current mirror structure and the hysteresis setting circuit. Specifically, the width-to-length ratio of the first NMOS tube NM1, the second NMOS tube NM2, the third NMOS tube NM3, the fourth NMOS tube NM4, the fifth NMOS tube NM5 and the seventh NMOS tube NM7 are the same, and the width-to-length ratio of the third NMOS tube NM3, the sixth NMOS tube NM6 and the eighth NMOS tube NM8 is 1:(1-k):2k, where k is any value greater than zero and less than 1, preferably k<<1.

[0074] Accordingly, combined with Figure 3 The principle of implementing hysteresis for the flip threshold in this application example is as follows:

[0075] At the output node P4, the charge current is generated by a 1:1 current mirror (the second NMOS tube NM2 and the fifth NMOS tube NM5) and another 1:1 current mirror (the first PMOS tube PM1 and the second PMOS tube PM2), so the ideal charge current is equal to the leakage current of the second NMOS tube NM2. The discharge current is generated by a 1:(1-k):2k current mirror (the third NMOS tube NM3, the sixth NMOS tube NM6 and the eighth NMOS tube NM8), k<<1, so the ideal discharge current is equal to (1-k) times or (1+k) times the leakage current of the third NMOS tube NM3. Reference Figure 1, before the rising edge flip threshold of the LIN bus arrives, RXD is at a low level, and the seventh NMOS tube NM7 is turned off. At this time, it is equivalent to not connecting the seventh NMOS tube NM7 and the eighth NMOS tube NM8. Then the discharge current of the output node P4 is (1-k) times the charging current, that is, the discharge current is less than the charging current. Therefore, the required rising edge flip threshold V th(rec) Higher; before the falling edge flip threshold arrives, RXD is high level, the seventh NMOS tube NM7 switch is turned on, at this time the eighth NMOS tube NM8 and the sixth NMOS tube NM6 jointly affect the discharge current of the output node P4, so that the discharge current of the output node P4 is (1+k) times the charging current, so the falling edge flip threshold V th(dom) Lower.

[0076] In this way, the seventh NMOS transistor NM7 is turned on dynamically by the level signal RXD, so that the discharge current can be adjusted, and a hysteresis is introduced into the rising edge-falling edge flip threshold of the LIN receiver, thereby greatly improving the anti-electromagnetic interference capability of the LIN bus.

[0077] Furthermore, in the first application example, all MOS tubes are connected by directly shorting the source and the body. This is because the first NMOS tube NM1 and the second NMOS tube NM2 are in a series structure, and the threshold body bias effect of the second NMOS tube NM2 must be eliminated. Connecting all MOS tubes by directly shorting the source and the body helps to achieve this goal.

[0078] 3. Output stage circuit 300.

[0079] In application example 1, the output stage circuit 300 includes: a Schmitt trigger SMT_TRG1, which is connected to the hysteresis comparison circuit 200 and is used to perform glitch processing on the output signal of the hysteresis comparison circuit (200); and an inverter INV1, which is connected to the Schmitt trigger and is used to perform signal inversion processing on the signal after the glitch processing to output the receiver output level signal. Figure 3 As shown, the Schmitt trigger SMT_TRG1 is connected to the output node P4, and the inverter INV1 outputs the final receiver output level signal RXD. In this way, when the output node P4 outputs a high level signal, the inverter INV1 outputs a low level signal, and vice versa when the output node P4 outputs a low level signal, the inverter INV1 outputs a high level signal.

[0080] In other examples, the output stage circuit 300 may also use only the inverter INV1.

[0081] But when the power supply voltage V SUP Or LIN bus voltage V LINWhen high-frequency electromagnetic disturbance occurs, nodes P1, P2 or P5 will suddenly fluctuate, and then nodes P3 or P4 will experience transient fluctuations, which will eventually cause abnormal conditions such as glitches in the level signal RXD. Therefore, in this application example 1, the output node P4 is connected to a Schmitt trigger SMT_TRG1 to de-glitch the flip threshold output by the hysteresis comparison circuit 200, further improving the output stability.

[0082] In summary, this application example 1 has the following advantages:

[0083] (1) The input stage circuit 100 reuses the input resistors, that is, in addition to using resistors to realize voltage-to-current conversion, it also suppresses bus and power supply electromagnetic interference by adding capacitors to form a first-order low-pass filter. Therefore, this resistor reuse combines the first-order low-pass filtering and voltage-to-current conversion functions, which helps to reduce the resistor area overhead.

[0084] (2) The hysteresis comparison circuit 200 increases the dynamic channel of the discharge current, introduces the threshold hysteresis, and suppresses the bus electromagnetic interference.

[0085] (3) A Schmitt trigger is added to the output processing of the hysteresis comparator circuit 200 to suppress output glitches.

[0086] (4) The current mirror stages of the core hysteresis comparison circuit 200 are at most two stages (the second NMOS transistor NM2 and the fifth NMOS transistor NM5, the first PMOS transistor PM1 and the second PMOS transistor PM2), and the number of MOS transistors used is 10 in total. Compared with the hysteresis design that relies on a large number of current mirrors and MOS transistors, the circuit structure is simplified. In addition, the reduction of current mirrors and MOS transistors can relatively reduce the impact of process fluctuations such as device process mismatch and current mirror matching error on the accuracy of the flip threshold.

[0087] Application Example 2

[0088] Figure 4 1 is a schematic diagram of a LIN bus receiver circuit of application example 2 of an embodiment of the present invention. Compared with application example 1, the biggest difference of application example 2 is that the implementation method of the hysteresis setting circuit 220 is different. Application example 1 adjusts the flip threshold by dynamically adjusting the discharge current of the hysteresis comparison circuit, while application example 2 adjusts the input resistance of the input stage circuit 100 to achieve the hysteresis of the flip threshold.

[0089] like Figure 4 As shown, the hysteresis setting circuit 220 of the second application example includes a third resistor R3, a fourth resistor R4, a seventh NMOS transistor NM7 and an eighth NMOS transistor NM8.

[0090] The third resistor R3 is connected in series between the first resistor R1 and the first capacitor C1.

[0091] The fourth resistor R4 is connected in series between the second resistor R2 and the second capacitor C2.

[0092] Among them, regarding the seventh NMOS transistor NM7, the gate is connected to the level signal corresponding to the fourth node P4, that is, connected Figure 4 The level signal RXD_b shown in the figure; the drain is connected to one end of the third resistor R3 connected to the first resistor R1; the source is connected to one end of the third resistor R3 connected to the first capacitor C1, that is, the third resistor R3 is connected between the source and the drain, and the source is also connected to the input node P1.

[0093] Among them, regarding the eighth NMOS tube NM8, its gate is connected to the receiver output level signal, that is, the level signal RXD; the drain is connected to one end of the fourth resistor R4 connected to the second resistor R2; the source is connected to one end of the fourth resistor R4 connected to the second capacitor C2, that is, the fourth resistor R4 is connected between the source and the drain, and the source is also connected to the input node P5.

[0094] It should be noted that the first capacitor C1 and the second capacitor C2 belong to the input stage circuit 100. Figure 4 For the purpose of clarity of the drawing lines, the first capacitor C1 and the second capacitor C2 are not included in the block diagram of the input stage circuit 100 , but this is understandable based on the description of the first application example.

[0095] The resistors R1-R4 jointly determine the input resistance of the input stage circuit 100, and the equivalent resistance values ​​of the third resistor R3 and the fourth resistor R4 are respectively denoted as R3 and R4. Figure 4 As shown, R1=2*R, R2=R, R3=2*k*R, R4=k*R are set, and k is greater than zero and much less than 1. In terms of MOS tube size design, the seventh NMOS tube NM7 and the eighth NMOS tube NM8 have the same width-to-length ratio, which is also the same as the width-to-length ratio of other NMOS tubes involved in the hysteresis comparison circuit 200. It can be seen that the second application example mainly generates the hysteresis amount related to the flip threshold by adjusting the ratio of the third resistor R3 and the fourth resistor R4.

[0096] The principle of the hysteresis comparison circuit 200 in the second application example to realize the hysteresis about the flip threshold is described as follows:

[0097] At the output node P4, the charging current is generated by a 1:1 current mirror (the second NMOS tube NM2 and the fifth NMOS tube NM5) and another 1:1 current mirror (the first PMOS tube PM1 and the second PMOS tube PM2), so the ideal charging current is equal to the leakage current of the second NMOS tube NM2. The discharge current is generated by a 1:1 current mirror (the third NMOS tube NM3 and the sixth NMOS tube NM6), so the ideal discharge current is equal to the leakage current of the third NMOS tube NM3.

[0098] At the threshold flip point, there is V GS_NM1 =V GS_NM2 =V GS_NM3 =V DS_NM3 =V GS , where V GS It is an intermediate symbol set to simplify subsequent calculations.

[0099] Before the rising edge flip threshold of the LIN bus arrives, RXD is at a low level and RXD_b is at a high level. At this time, the seventh NMOS tube NM7 switch is turned on and the eighth NMOS tube NM8 switch is turned off, so that for the output node P4:

[0100] Charging current = (V SUP -V GS_NM1 -V GS_NM2 ) / R1 (6)

[0101] Discharge current = (V LIN -V DS_NM3 ) / (R2+R4) (7)At this time, V LIN The rising edge flip threshold is calculated as:

[0102] V th(rec) =0.5*V SUP +0.5*k*(V SUP- V GS ) (8)

[0103] Since k<<1 and V SUP >>V GS ,thereby:

[0104] V th(rec) ≈0.5*V SUP +0.5*k*V SUP (9)

[0105] Before the falling edge flip threshold of the LIN bus arrives, that is, RXD is high and RXD_b is low, the seventh NMOS tube NM7 switch is turned off and the eighth NMOS tube NM8 switch is turned on, so:

[0106] Charging current = (V SUP -VGS_NM1 -V GS_NM2 ) / (R1+R3) (10)

[0107] Discharge current = (V LIN -V DS_NM3 ) / R2 (11) At this time, the LIN bus voltage V LIN The falling edge flip threshold is expressed as:

[0108] V th(dom) =0.5*V SUP -k / (2+2k)*V SUP +k / (1+k)*V GS (12)

[0109] Since k<<1 and V SUP >>V GS ,but:

[0110] V th(dom) ≈0.5*V SUP -0.5*k*V SUP (13)

[0111] Accordingly, as shown in equation (9) and equation (3), the second application example dynamically adjusts the input resistance through the level signal RXD, introduces a hysteresis into the rising edge-falling edge flip threshold of the hysteresis comparison circuit 200, and greatly improves the anti-electromagnetic interference capability of the LIN bus.

[0112] The structures and corresponding principles of other circuit modules of the second application example can be referred to the first application example, and will not be described in detail here.

[0113] Another embodiment of the present invention further provides a chip, comprising any of the above-mentioned LIN bus receiver circuits.

[0114] Another embodiment of the present invention further provides an electronic device, comprising any of the above-mentioned LIN bus receiver circuits or chips.

[0115] For example, the LIN bus receiver circuit of the embodiment of the present invention serves as an interface circuit corresponding to an automotive-grade chip or automotive electronic equipment, and has the advantages of a wide comparison range, precise flip threshold, low power consumption, strong anti-electromagnetic interference capability, simple circuit structure, and high reliability. It can avoid DC offset and signal distortion caused by nonlinear effects introduced by EMI (Electromagnetic Interference) at the input stage, and meet the EMC (Electro Magnetic Compatibility) performance requirements of automotive electronic equipment and automotive-grade chips.

[0116] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0117] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A LIN bus receiver circuit, characterized in that: include: An input stage circuit (100) is used for receiving a power supply voltage and a LIN bus voltage, and pre-processing the power supply voltage and the LIN bus voltage using an input resistor; A hysteresis comparison circuit (200) connected to the input stage circuit (100) and used for comparing the pre-processed power supply voltage and the LIN bus voltage with the current as a parameter, and outputting a flip threshold of the LIN bus and realizing the hysteresis of the flip threshold according to the comparison result; as well as An output stage circuit (300) is connected to the hysteresis comparison circuit (200) and is used to output a receiver output level signal according to the flip threshold.

2. The LIN bus receiver circuit according to claim 1, characterized in that: The input stage circuit (100) comprises: a first resistor (R1) and a first capacitor (C1), wherein one end of the first resistor (R1) is connected to the power supply voltage, and the other end is grounded through the first capacitor (C1); and A second resistor (R2) and a second capacitor (C2), one end of the second resistor (R2) is connected to the LIN bus voltage, and the other end is grounded through the second capacitor (C2).

3. The LIN bus receiver circuit according to claim 2, characterized in that: The hysteresis comparison circuit (200) comprises a current comparison circuit (210) and a hysteresis setting circuit (220): The current comparison circuit (210) comprises: A first NMOS transistor (NM1), whose drain is connected to the gate and connected to the first node (P1), and whose source is the second node (P2), wherein the first node (P1) is arranged between the first resistor (R1) and the first capacitor (C1); a second NMOS transistor (NM2), wherein the drain is connected to the gate and connected to the second node (P2), and the source is grounded; a third NMOS transistor (NM3), whose drain is connected to a fifth node (P5), whose gate is connected to the gate of the second NMOS transistor (NM2), and whose source is grounded, wherein the fifth node (P5) is arranged between the second resistor (R2) and the second capacitor (C2); a fourth NMOS transistor (NM4), whose gate is connected to the gate of the first NMOS transistor (NM1), whose drain is the third node (P3), and whose source is connected to the drain of the fifth NMOS transistor (NM5); The fifth NMOS tube (NM5) has a drain connected to the source of the fourth NMOS tube (NM4), a gate connected to the gates of the second NMOS tube (NM2) and the third NMOS tube (NM3), and a source grounded; a sixth NMOS transistor (NM6), whose gate is connected to the fifth node (P5), whose drain is connected to the fourth node (P4), and whose source is grounded, wherein the fourth node (P4) outputs the flip threshold, and the current injected from the drain of the sixth NMOS transistor (NM6) into the fourth node (P4) is the discharge current for the hysteresis comparison circuit (200); and A first PMOS tube (PM1) and a second PMOS tube (PM2), both of which have their sources connected to an operating voltage and their gates connected, a drain of the first PMOS tube (PM1) connected to the third node (P3), a drain of the second PMOS tube (PM2) connected to the fourth node (P4), and a current injected from the drain of the second PMOS tube (PM2) into the fourth node (P4) as a charging current for the hysteresis comparison circuit (200); and The hysteresis setting circuit (220) is used to adjust the discharge current of the hysteresis comparison circuit (200) or the input resistance of the input stage circuit (100) to achieve the hysteresis of the flip threshold.

4. The LIN bus receiver circuit according to claim 3, characterized in that: The hysteresis setting circuit (220) comprises: a seventh NMOS transistor (NM7), whose gate is connected to the receiver output level signal, whose drain is connected to the fourth node (P4), and whose source is connected to the drain of the eighth NMOS transistor (NM8); and The eighth NMOS transistor (NM8) has a gate connected to the fifth node (P5), a drain connected to the source of the seventh NMOS transistor (NM7), and a source grounded.

5. The LIN bus receiver circuit according to claim 4, characterized in that: The first NMOS tube (NM1), the second NMOS tube (NM2), the third NMOS tube (NM3), the fourth NMOS tube (NM4), the fifth NMOS tube (NM5) and the seventh NMOS tube (NM7) have the same width-to-length ratio, while the ratio of the width-to-length ratios of the third NMOS tube (NM3), the sixth NMOS tube (NM6) and the eighth NMOS tube (NM8) is 1:(1-k):2k, where k is any value greater than zero and less than 1.

6. The LIN bus receiver circuit according to claim 3, characterized in that: The hysteresis setting circuit (220) comprises: a third resistor (R3) connected in series between the first resistor (R1) and the first capacitor (C1); a fourth resistor (R4) connected in series between the second resistor (R2) and the second capacitor (C2); a seventh NMOS transistor (NM7), whose gate is connected to the level signal corresponding to the fourth node (P4), whose drain is connected to one end of the third resistor (R3) connected to the first resistor (R1), and whose source is connected to one end of the third resistor (R3) connected to the first capacitor (C1); and An eighth NMOS transistor (NM8), whose gate is connected to the receiver output level signal, whose drain is connected to one end of the fourth resistor (R4) connected to the second resistor (R2), and whose source is connected to one end of the fourth resistor (R4) connected to the second capacitor (C2).

7. The LIN bus receiver circuit according to claim 6, characterized in that: The first NMOS tube (NM1), the second NMOS tube (NM2), the third NMOS tube (NM3), the fourth NMOS tube (NM4), the fifth NMOS tube (NM5), the sixth NMOS tube (NM6), the seventh NMOS tube (NM7) and the eighth NMOS tube (NM8) have the same width-to-length ratio.

8. The LIN bus receiver circuit according to claim 1, characterized in that: The output stage circuit (300) comprises: a Schmitt trigger connected to the hysteresis comparison circuit (200) and used for performing a deburring process on an output signal of the hysteresis comparison circuit (200); and An inverter is connected to the Schmitt trigger and is used to perform signal inversion processing on the signal after the deburring processing to output the receiver output level signal.

9. A chip, characterized in that: A LIN bus receiver circuit comprising any one of claims 1 to 8.

10. An electronic device, characterized in that: The invention comprises the LIN bus receiver circuit as described in any one of claims 1 to 8 or the chip as described in claim 9.

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