Nonlinear equalization circuit

Abstract

The invention provides a nonlinear equalization circuit which can be applied to the technical field of high-speed optical communication, the circuit comprises N basic units, N is a positive integer, each basic unit comprises an adjustable delay circuit, a pulse current generation circuit and an equalization strength adjustable circuit, the adjustable time delay circuit comprises a first adjustable time delay circuit and a second adjustable time delay circuit, and the first adjustable time delay circuit and the second adjustable time delay circuit are used for delaying input differential data to generate a first time delay signal and a second time delay signal; the equalization intensity adjustable circuit is used for adjusting the amplitude of the pulse current generated by the pulse current generation circuit so as to adjust the equalization intensity; and the pulse current generating circuit is used for logically combining the first delay signal and the second delay signal to generate pulse current for compensating the dynamic nonlinearity of the laser. And various requirements on nonlinear compensation are met, and meanwhile, a main signal is not weakened.

Description

Technical Field

[0001] The present invention relates to the technical field of high-speed optical communication, and in particular to a nonlinear equalization circuit. Background Art

[0002] With the rapid development of technologies such as the Internet, cloud computing, and big data, data traffic has shown an exponential growth trend. However, due to the increasing losses of traditional electrical interconnection methods, it is difficult to meet the needs of high-density and high-speed data transmission. In this context, optical interconnection technology has gradually emerged and become the mainstream solution in the field of data transmission.

[0003] Optical interconnection technology is mainly divided into two categories: direct modulation and indirect modulation. Among them, direct modulation has been widely used in medium and short distance interconnection due to its significant advantages of low cost and low power consumption. The lasers used for direct modulation mainly include distributed feedback (DFB) lasers and vertical-cavity surface-emitting lasers (VCSEL). However, both lasers have dynamic nonlinear characteristics, that is, their electro-optical frequency response curves change with changes in bias current. In the time domain, this characteristic is manifested as: when the current of the laser changes from low to high, overshoot and ringing will occur; when the current changes from high to low, the decline process appears to be relatively slow, and the bandwidth is obviously insufficient.

[0004] For the Non-Return to Zero (NRZ) modulation method, this dynamic nonlinear characteristic of the laser may not be a fatal problem. However, as the transmission rate continues to increase, when the four-level pulse amplitude modulation (4-Level Pulse Amplitude Modulation, PAM4) modulation method is adopted, the overshoot phenomenon will seriously affect the size of the adjacent sub-eyes of the eye diagram, causing each sub-eye to tilt, which in turn brings great pressure to the sampling work of the receiving end.

[0005] Therefore, in order to eliminate the ringing of the rising edge and the slowness of the falling edge and solve the signal integrity problem of the directly modulated laser under the PAM4 modulation format, we urgently need a circuit that can compensate for the dynamic nonlinearity of the laser. Summary of the invention

[0006] 1. Technical issues to be resolved

[0007] In order to solve the technical problem of signal integrity of directly modulated lasers under the four-level pulse amplitude modulation (PAM4) modulation format in the prior art, an embodiment of the present invention provides a nonlinear equalization circuit. The number of pulses generated by the nonlinear equalization circuit is adjustable, the direction is adjustable, the start time, the duration and the amplitude are independently adjustable, and various requirements for nonlinear compensation are supported. At the same time, the main signal will not be weakened. When there is no equalization signal, the output current is 0, and the amplitude of the main signal will not be weakened.

[0008] (II) Technical solution

[0009] In view of the above technical problem, an embodiment of the present invention provides a nonlinear equalization circuit.

[0010] According to a first aspect of the present invention, a nonlinear equalization circuit is provided, comprising N basic units, wherein N is a positive integer, and the basic units include: an adjustable delay circuit, a pulse current generating circuit, and an equalization strength adjustable circuit, wherein the adjustable delay circuit comprises a first adjustable delay circuit and a second adjustable delay circuit, the first adjustable delay circuit and the second adjustable delay circuit being used to delay input differential data to generate a first delay signal and a second delay signal; an equalization strength adjustable circuit being used to adjust the amplitude of a pulse current generated by a pulse current generating circuit to adjust the equalization strength; and a pulse current generating circuit being used to logically combine the first delay signal with the second delay signal to generate a pulse current for compensating for the dynamic nonlinearity of a laser.

[0011] In some exemplary embodiments, the delay times of the first adjustable delay circuit and the second adjustable delay circuit are independent of each other and can be adjusted; the delay time of the first adjustable delay circuit is greater than or equal to 0; and the delay time of the second adjustable delay circuit is greater than or equal to 0.

[0012] In some exemplary embodiments, the adjustable delay circuit is composed of an inverter chain with multiple stages of adjustable load capacitance. By adjusting the capacitance, the rise and fall time of the input signal can be changed to obtain different delay signals.

[0013] In some exemplary embodiments, the last stage inverter can restore the rise and fall time of the signal to the input signal bandwidth to ensure signal quality.

[0014] In some exemplary embodiments, the adjustable delay circuit is implemented by an on-chip transmission line; or the adjustable delay circuit is implemented by a cascaded controllable delay buffer; or when the delay time is 0, the adjustable delay circuit is directly connected to the input end of the pulse current generating circuit.

[0015] In some exemplary embodiments, the circuit with adjustable equalization strength uses a transistor as a control switch, and controls the conduction or short circuit of a resistor connected in parallel with the transistor to control the output impedance, thereby adjusting the amplitude of the pulse current.

[0016] In some exemplary embodiments, the circuit with adjustable equalization strength includes a logic unit, and the amplitude of the pulse current is adjusted by combining a plurality of logic units and controlling each logic unit to be turned on and off.

[0017] In some exemplary embodiments, the pulse current generating circuit is composed of a current mode combinational logic composed of transistors, which is used to generate a corresponding pulse current for an input delayed signal; wherein the pulse current can respond to the rising edge or the falling edge of the signal; and the start time of the pulse current generation, the pulse current width and the amplitude can be adjusted.

[0018] In some exemplary embodiments, the pulse current is directly output to the laser; or the pulse current is superimposed on one end of the differential input pair and finally superimposed on the laser.

[0019] In some exemplary embodiments, each of the N basic units can be configured as a nonlinear compensation circuit with different transition edges, different pulse generation and duration, and different equalization strengths by adjusting delay, strength, and combinational logic.

[0020] (III) Beneficial effects

[0021] It can be seen from the above technical solutions that the nonlinear equalization circuit provided by the embodiment of the present invention has at least the following beneficial effects:

[0022] (1) The structure is simple and does not require a detector for detecting the rising edge or falling edge, saving power consumption.

[0023] (2) The pulse current is configurable. The number of pulse signals is adjustable, the direction is adjustable, the start time, duration and amplitude are independently adjustable, and various requirements for nonlinear compensation are supported.

[0024] (3) It will not weaken the main signal. When there is no balanced signal, the output current is 0 and the amplitude of the main signal will not be weakened. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The above contents and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0026] Figure 1 A schematic diagram of the principle architecture of a nonlinear equalization circuit according to an embodiment of the present invention is schematically shown;

[0027] Figure 2A schematic diagram of the structure of an adjustable delay circuit according to an embodiment of the present invention is shown;

[0028] Figure 3 A schematic diagram of the structure of a circuit with adjustable equalization strength according to an embodiment of the present invention is shown;

[0029] Figure 4 A schematic diagram schematically shows the structure of a pulse current generating circuit according to an embodiment of the present invention; and

[0030] Figure 5 The schematic diagram shows a timing diagram of pulse current being superimposed on a laser according to an embodiment of the present invention. DETAILED DESCRIPTION

[0031] In order to make the purpose, technical scheme and advantages of the present invention more clearly understood, the present invention is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0032] Figure 1 The schematic diagram shows a principle structure of a nonlinear equalization circuit according to an embodiment of the present invention.

[0033] like Figure 1 As shown, a nonlinear equalization circuit according to an embodiment of the present invention includes N basic units, wherein N is a positive integer, and the basic units include: an adjustable delay circuit, a pulse current generating circuit, and an equalization strength adjustable circuit, wherein the adjustable delay circuit includes a first adjustable delay circuit and a second adjustable delay circuit, the first adjustable delay circuit and the second adjustable delay circuit are used to delay the input differential data to generate a first delay signal and a second delay signal; the equalization strength adjustable circuit is used to adjust the amplitude of the pulse current generated by the pulse current generating circuit to adjust the equalization strength; and the pulse current generating circuit is used to logically combine the first delay signal and the second delay signal to generate a pulse current for compensating for the dynamic nonlinearity of the laser.

[0034] In the embodiment of the present invention, each of the N basic units can be configured as a nonlinear compensation circuit with different transition edges, different pulse generation and duration, and different equalization strengths by adjusting delay, strength, and combinational logic.

[0035] In the embodiment of the present invention, the delay time of the first adjustable delay circuit and the second adjustable delay circuit are independent of each other and can be adjusted; the delay time of the first adjustable delay circuit is greater than or equal to 0; and the delay time of the second adjustable delay circuit is greater than or equal to 0. When the delay time is 0, it means that the input data is directly connected to the input end of the pulse generating circuit.

[0036] Figure 2 The schematic diagram shows the structure of an adjustable delay circuit according to an embodiment of the present invention.

[0037] like Figure 2 As shown, the adjustable delay circuit according to an embodiment of the present invention is composed of an inverter chain with multiple stages of adjustable load capacitance. By adjusting the capacitance, the rise and fall time of the input signal can be changed to obtain different delay signals. The last stage of the inverter can restore the rise and fall time of the signal to the input signal bandwidth to ensure signal quality.

[0038] In an embodiment of the present invention, the adjustable delay circuit is implemented by an on-chip transmission line; or the adjustable delay circuit is implemented by a cascaded controllable delay buffer; or when the delay time is 0, the adjustable delay circuit is directly connected to the input end of the pulse current generating circuit.

[0039] Figure 3 The schematic diagram shows the structure of the equalization strength adjustable circuit according to the embodiment of the present invention.

[0040] like Figure 3 As shown, the equalization strength adjustable circuit according to the embodiment of the present invention uses a transistor as a control switch, and controls the conduction or short circuit of the resistor connected in parallel with the transistor to control the output impedance, thereby adjusting the amplitude of the pulse current. By changing the amplitude of the pulse current, the equalization strength can be adjusted. Optionally, in addition to changing the size of the tail equivalent resistance to control the size of the pulse current, merging multiple logic units (slices) and controlling the opening and closing of each slice also falls within the protection scope of the present invention.

[0041] Figure 4 A schematic diagram schematically shows the structure of a pulse current generating circuit according to an embodiment of the present invention; and Figure 5 The schematic diagram shows a timing diagram of pulse current being superimposed on a laser according to an embodiment of the present invention.

[0042] like Figure 4 and Figure 5As shown, the pulse current generating circuit according to the embodiment of the present invention is composed of transistors forming a current mode combination logic, which is used to generate a corresponding pulse current for the input delay signal; wherein the pulse current can respond to the rising edge or falling edge of the signal; the pulse current generation start time, pulse current width and amplitude can be adjusted. The pulse current is directly output to the laser; or the pulse current is superimposed on one end of the differential input pair, and finally superimposed on the laser.

[0043] For example, two N-type metal oxide semiconductor (NMOS) transistors are connected in series to form AND logic. Figure 5 (a), (c), (e) and (g) are the pulse currents generated by the falling edge of the laser. The input differential signal passes through an adjustable delay circuit, where the adjustable delay circuit is configured so that the delay time of the positive input terminal is Δt1 (Δt1≠0), and the delay of the negative input terminal is 0, that is, it is directly connected to the input terminal of the pulse current generating circuit. When the signal reaches the pulse current generating circuit, due to the different delays of the two signals, both signals will be at a high level at the same time. For the pulse current generating circuit, the combinational logic of AND is implemented, that is, the input signals will only be turned on to generate current when they are 1 at the same time, and they are all in the off state in other cases. Therefore Figure 5 In the signal timing diagrams (a), (c), (e) and (g), within the Δt1 time after the input voltage (VIN) signal changes from low level to high level, the delay signal of the input differential signal (VIP) is 1 at the same time as VIN, so that the series NMOS is turned on, generating a pulse current with a duration of Δt1. This current is superimposed on the current of the laser, thereby generating an additional current signal within the Δt1 time after the output current of the laser changes from high level to low level, accelerating the downward jump of the signal. Figure 5 (b), (d), (f) and (h) are pulse currents generated for the rising edge of the laser. The input differential signal passes through an adjustable delay circuit. The adjustable delay circuit is configured such that the delay time of the positive input end is 0, that is, it is directly connected to the input end of the pulse current generating circuit, and the delay time of the negative input end is Δt4. When the signal reaches the pulse current generating circuit, due to the different delays of the two signals, the situation of being high level at the same time will also occur, such as Figure 5 In the signal timing diagrams shown in (b), (d), (f) and (h), within the Δt4 time after the VIP signal changes from low level to high level, the delay signal of VIN and VIP are both 1, so that the series NMOS is turned on, generating a pulse current with a duration of Δt4. This current is reversely superimposed on the current of the laser, so that the output current of the laser does not immediately rise to the maximum current value within the Δt4 time after it changes from high level to low level, slowing down the ringing of the rising edge.

[0044] It should be noted that, although the embodiment of the present application only describes the number of basic units N=2, and configures the equalization at the rising and falling edges respectively, in fact N can take any value and perform different configurations. For example, N=3, and only the rising edge is equalized. In this way, three current pulses are generated after the rising edge jump. The occurrence time of the current pulses is independent of each other, and the duration and amplitude may also be different, but they all fall within the protection scope of the embodiment of the application.

[0045] Furthermore, it should be understood that although the specific implementation is based on a laser, such as a DFB or a VCSEL, nonlinear equalization technology applied to other purposes is also within the protection scope of the embodiment of the application.

[0046] In summary, the present invention provides an equalization circuit for dynamic nonlinearity of lasers, including an adjustable delay circuit, an equalization intensity adjustment circuit, and a pulse circuit generation circuit, thereby realizing a nonlinear equalization circuit with low power consumption and wide adaptability.

[0047] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present invention in detail. It should be understood that the above are only specific embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A nonlinear equalization circuit, characterized in that: The circuit includes N basic units, wherein N is a positive integer, and the basic units include: an adjustable delay circuit, a pulse current generating circuit, and an adjustable equalization strength circuit. Wherein, the adjustable delay circuit includes a first adjustable delay circuit and a second adjustable delay circuit, and the first adjustable delay circuit and the second adjustable delay circuit are used to delay the input differential data to generate a first delay signal and a second delay signal; The equalization strength adjustable circuit is used to adjust the amplitude of the pulse current generated by the pulse current generating circuit to adjust the equalization strength; and The pulse current generating circuit is used for logically combining the first delay signal and the second delay signal to generate a pulse current for compensating for the dynamic nonlinearity of the laser.

2. The nonlinear equalizer circuit according to claim 1, characterized in that: The delay times of the first adjustable delay circuit and the second adjustable delay circuit are independent of each other and can be adjusted; The delay time of the first adjustable delay circuit is greater than or equal to 0; and The delay time of the second adjustable delay circuit is greater than or equal to 0.

3. The nonlinear equalizer circuit according to claim 1, characterized in that: The adjustable delay circuit is composed of an inverter chain with multiple stages of adjustable load capacitance. By adjusting the capacitance, the rise and fall time of the input signal can be changed to obtain different delay signals.

4. The nonlinear equalizer circuit according to claim 3, characterized in that: The last stage inverter can restore the rise and fall time of the signal to the input signal bandwidth to ensure signal quality.

5. The nonlinear equalizer circuit according to claim 1, characterized in that: The adjustable delay circuit is implemented by an on-chip transmission line; or The adjustable delay circuit is implemented by a cascade of controllable delay buffers; or When the delay time is 0, the adjustable delay circuit is directly connected to the input end of the pulse current generating circuit.

6. The nonlinear equalizer circuit according to claim 1, characterized in that: The equalization strength adjustable circuit uses a transistor as a control switch, and controls the conduction or short circuit of a resistor connected in parallel with the transistor, thereby controlling the output impedance and further adjusting the amplitude of the pulse current.

7. The nonlinear equalizer circuit according to claim 6, characterized in that: The equalization strength adjustable circuit includes a logic unit, and the amplitude of the pulse current is adjusted by combining multiple logic units and controlling each logic unit to be turned on and off.

8. The nonlinear equalizer circuit according to claim 1, characterized in that: The pulse current generating circuit is composed of transistors forming a current mode combination logic, and is used to generate a corresponding pulse current for the input delay signal; Wherein, the pulse current can respond to the rising edge or falling edge of the signal; The starting time of the pulse current generation, the pulse current width and the amplitude can be adjusted.

9. The nonlinear equalizer circuit according to claim 1, characterized in that: The pulse current is directly output to the laser; or The pulse current is superimposed on one end of the differential input pair and finally superimposed on the laser.

10. The nonlinear equalizer circuit according to claim 1, characterized in that: Each of the N basic units can be configured as a nonlinear compensation circuit with different jump edges, different pulse generation and duration, and different equalization strengths by adjusting delay, strength, and combinational logic.

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