Audio transmission method and device and electronic equipment

Abstract

The invention discloses an audio transmission method and apparatus, and an electronic device. The audio transmission method comprises the following steps: acquiring data parameters of TDM data to be transmitted; generating clock signal parameters required by transmission according to the data parameters; generating a clock signal through a clock module according to the clock signal parameter, and providing the clock signal to an I2S module and a TDM module; and transmitting the TDM data to be transmitted between the I2S module and the TDM module according to the clock signal. According to the invention, only the sending opportunity of the data needs to be limited, that is, the sending window and the receiving window are aligned, and clock conversion by additionally arranging an FPGA is not needed, so that the TDM mode can utilize the clock signal in the I2S mode, and the protocol of the TDM mode does not need to be additionally agreed.

Description

Technical Field

[0001] The present invention relates to the field of audio transmission, and in particular to an audio transmission method and device, and electronic equipment. Background Art

[0002] In audio transmission input and output applications, the I2S / PCM (transmission protocol for audio data) controller is a key component responsible for data transmission. However, the IP design (designed chip core) of some SoCs (system-on-chip) only supports standard I2S / PCM controllers, which means they can only process two-channel data. When the application scenario requires multi-channel audio transmission, this design limitation becomes a bottleneck.

[0003] Figure 1 : is a structural diagram of a device for realizing multi-channel audio transmission in the related art. In the related art, in order to overcome the problem that the standard I2S / PCM controller can only process data of two channels, an FPGA (field programmable gate array) module is introduced to process audio data of multiple channels, and to overcome the problem that the I2S / PCM controller of these SoCs does not support TDM (time division multiplexing) mode in IP design and cannot directly process data of more than two channels. The FPGA will first integrate and process the audio data of multiple channels, and then communicate with the SoC using the two-channel data protocol of the I2S / PCM controller to realize the exchange of multi-channel data. However, although the introduction of the FPGA module can realize multi-channel audio transmission, it increases the hardware cost and involves more complex circuit design and higher power consumption. Therefore, for applications that require a large number of audio channels, this solution may bring challenges in cost and performance. Summary of the invention

[0004] The present invention provides an audio transmission method and device, and electronic equipment, which realize multi-channel audio transmission through a standard I2S / PCM controller.

[0005] In one aspect of the present invention, an audio transmission method is provided. The method comprises: obtaining data parameters of TDM data to be transmitted; generating clock signal parameters required for transmission according to the data parameters; generating a clock signal according to the clock signal parameters by a clock module, and providing the clock signal to an I2S module and a TDM module; and transmitting the TDM data to be transmitted between the I2S module and the TDM module according to the clock signal.

[0006] In another aspect of the present invention, an audio transmission device is provided. The device includes a control module, a clock module, an I2S module and a TDM module; the output end of the clock module is electrically connected to the clock port of the I2S module and the clock port of the TDM module respectively, and the data port of the I2S module is electrically connected to the data port of the TDM module; the control module is configured to control the clock module to generate a clock signal parameter required for transmission according to the data parameter of the TDM data to be transmitted, and to generate a clock signal according to the clock signal parameter; the control module is configured to control the transmission of the TDM data to be transmitted between the I2S module and the TDM module according to the clock signal.

[0007] In another aspect of the present invention, an electronic device is provided, which includes a memory configured to store information associated with audio data, and at least one processor electrically coupled to the memory and configured to execute the above-mentioned audio transmission method.

[0008] According to the technical solution of the present invention, data parameters are extracted according to the TDM data to be transmitted, and clock signal parameters are calculated according to the data parameters; the clock module generates a corresponding clock signal through the clock signal parameters and sends it to the I2S module and the TDM module, so that the I2S with a standard format is directly used to provide a clock standard for the TDM interface, so that the I2S module and the TDM module can perform data interaction under the same source and same phase clock signal, so that only the timing of data transmission needs to be limited, that is, the transmission window and the receiving window need to be aligned, and there is no need to perform clock conversion by additionally setting up FPGA. Because the standard of I2S is dual-channel, it is equivalent to realizing the transmission of multi-channel data by limiting the same bit clock signal to transmit the same amount of data in the time interval of transmitting a group of dual-channels through clock alignment, so that the SOC of the I2S module can transmit signals through the I2S protocol with the TDM peripheral connection, and there are many peripherals that support TDM transmission. The compatibility of the I2S module and the TDM module improves the data transmission capacity of the I2S interface, so that the SOC with only the I2S interface has the ability to process TDM multi-channel audio without increasing hardware costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 A structural diagram of a device for realizing multi-channel audio transmission in the related art; Figure 2 is a flow chart of an audio transmission method according to an embodiment of the present invention; Figure 3 The present invention is a flowchart of an audio transmission method for a specific scenario according to an embodiment of the present invention.

[0010] Figure 4FIG. 4 is a schematic diagram of a data transmission timing of an I2S module according to an embodiment of the present invention.

[0011] Figure 5 FIG. 4 is a schematic diagram of an audio transmission device according to an embodiment of the present invention.

[0012] Figure 6 is a block diagram of an electronic device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] In order to explain the technical content, achieved objectives and effects of the present invention in detail, the following is an explanation in combination with the implementation modes and the accompanying drawings.

[0014] In the existing technology, directly using SoC built by other companies for development is also a common chip development method (IP design). However, some SoCs only support standard I2S / PCM controllers, that is, there is no TDM mode protocol agreement, and thus cannot support multi-channel audio data transmission.

[0015] In existing SoCs, the TDM mode of the I2S / PCM controller was not designed to handle audio data on multiple data lines at the same time, resulting in the controller only supporting the transmission of a single data line in some SoCs. This design limitation significantly limits the transmission capacity of audio data, especially in application scenarios that require high-channel audio processing, where the support of a single data line is insufficient to meet the needs, thus affecting the overall performance and scalability of the system.

[0016] The TDM mode design of existing SoCs limits the support for audio channels and can only process data for up to 8 channels. The I2S / PCM controller has the ability to process multiple data lines in parallel in I2S mode, and each data line can handle two channels. For example, when 8-channel audio input is required, 8-channel input can be formed by using 4 data lines at the same time, and each line is responsible for data transmission of two channels. In the face of audio transmission application scenarios that require a higher number of channels, such as 32 channels, 64 channels or more channels, the existing TDM mode cannot meet these expansion requirements.

[0017] In order to solve at least the above technical problems, the present disclosure provides an audio transmission channel construction method. According to the present disclosure, a clock module is introduced to provide a clock signal of the same source and phase for the I2S module and the TDM module, and a clock signal is calculated according to the TDM data to be transmitted, and the clock signal is used to guide the I2S module and the TDM module to transmit the TDM data to be transmitted. In this way, according to the embodiment of the present disclosure, the data transmission window can be synchronized through the clock synchronization of the I2S module and the TDM module under the I2S protocol, thereby completing the transmission of multiple channel data within the dual-channel data transmission time period of the I2S.

[0018] According to the disclosed embodiment, multi-channel data is transmitted using I2S and TDM protocols to achieve a more direct and efficient audio data transmission method. This method avoids the need to use third-party hardware circuits for traditional data forwarding, thereby significantly reducing the hardware cost of the system. At the same time, due to the reduction of additional hardware components, the debugging cost of the system is also reduced. This direct data transmission method simplifies system design and improves overall reliability and stability.

[0019] In addition, direct data transmission between I2S and TDM protocols greatly improves the performance of SoCs that do not originally support TDM functions in multi-channel audio transmission. This means that even if the SoC itself does not have a TDM interface, it can still achieve multi-channel audio data transmission through software-level adaptation and protocol conversion. This approach expands the application range of SoCs, enabling them to easily handle complex audio processing tasks such as multi-channel recording and playback, surround sound processing, etc.

[0020] In the I2S module, each data line (SDI / SDO) has the ability to send and receive TDM channel data, which means that in an I2S controller with multiple data lines, the multi-channel transmission capability of the SoC has been significantly multiplied. Specifically, if one data line can transmit 8 channels of audio data, then a controller with two data lines can transmit 16 channels simultaneously, three data lines can transmit 24 channels, and so on. This doubling of capabilities not only improves the throughput of audio data, but also increases the flexibility and scalability of the system. In addition, this design allows the SoC to use its internal resources more efficiently when processing multi-channel audio data, optimize data flow, reduce latency, and improve overall audio quality.

[0021] Hereinafter, the technical solution according to the present disclosure will be described with reference to specific embodiments and in conjunction with the accompanying drawings.

[0022] Figure 2 1 is a flow chart showing an audio transmission method 100 according to an embodiment of the present disclosure. Figure 2 The method 100 includes the following steps 102 to 108.

[0023] In step 102, data parameters of TDM data to be transmitted are obtained.

[0024] In some embodiments, the sampling rate, number of sampling channels and sampling width of the TDM data to be transmitted are obtained. In this way, the most critical parameters required in the process of audio data generation and transmission are obtained, thereby providing basic data support for the subsequent normal transmission of the TDM data to be transmitted between the I2S interface and the TDM interface.

[0025] In step 104, clock signal parameters required for transmission are generated according to the data parameters.

[0026] In some embodiments, the bit clock signal is calculated according to the sampling rate, the number of sampling channels, and the sampling width; the first frame clock signal required for the I2S mode is calculated according to the bit clock signal, and the sampling rate is used as the second frame clock signal. In this way, the bit clock signal, i.e., the total amount of data to be transmitted, is calculated by the basic data of the TDM data to be transmitted, so that the total amount of transmission within a window of the I2S interface and the TDM interface can be kept consistent, thereby avoiding data omission; that is, when sending the TDM data to be transmitted, the data of multiple channels are sent within the window of a single channel agreed to be sent in the I2S protocol under the premise that the total data sent is the same; thereby realizing the data transmission of multiple channels using the I2S module.

[0027] In some embodiments, calculating the bit clock signal according to the sampling rate, the number of sampling channels, and the sampling width includes obtaining the bit clock signal using the following formula: bit clock signal = sampling rate × number of sampling channels × sampling width. In this way, the bit clock signal is obtained according to the relevant data parameters of the TDM data to be transmitted, ensuring that the transmission parameters match the parameters of the collected TDM data, so that the TDM data can be completely transmitted; at the same time, the bit clock signal can unify the total amount of data transmitted by the I2S interface and the TDM interface within a fixed time, thereby ensuring that the data sending and receiving windows can be properly aligned.

[0028] In some embodiments, calculating the first frame clock signal required for the I2S mode according to the bit clock signal includes: obtaining the protocol sampling width and the number of protocol sampling channels in the I2S mode; obtaining the first frame clock signal using the following formula: first frame clock signal = bit clock signal ÷ protocol sampling width ÷ number of protocol sampling channels. In this way, under the premise that the bit clock signal has been determined, the frame clock signal under the I2S protocol is determined according to the I2S protocol, providing the necessary clock signal support for the data transmission process, ensuring that the data can be transmitted normally.

[0029] In step 106, a clock signal is generated by a clock module according to clock signal parameters, and the clock signal is provided to the I2S module and the TDM module.

[0030] In some embodiments, providing a clock signal to the I2S interface and the TDM interface includes: providing a bit clock signal to the I2S module and the TDM module as an I2S bit clock signal and a TDM bit clock signal, respectively; providing a first frame clock signal to the I2S module as an I2S frame clock signal; providing a second frame clock signal to the I2S module as an I2S frame synchronization signal, and providing the second frame clock signal to the TDM module as a TDM frame clock signal. In this way, the bit clock signal is simultaneously provided to the I2S interface and the TDM interface as the bit clock signal, ensuring that the total amount of data transmitted by the two within a time period is the same, thereby avoiding data omission; the first frame clock signal is provided to the I2S interface as the I2S frame clock signal, indicating the transmission of a frame of data on the I2S interface; and the sampling rate of the TDM data to be transmitted is provided as the second frame clock signal to the I2S interface as a frame synchronization signal and to the TDM as a frame clock signal. It can be seen that if the I2S standard protocol is followed, only dual-channel data can be transmitted. The present application transmits multi-channel data by time synchronization in the data transmission window of the I2S dual-channel. However, the window for transmitting the data of each channel in the TDM mode is smaller than the window for transmitting the data of each channel in the I2S mode. Therefore, the frame clock signal of the TDM interface is simultaneously used as the frame synchronization signal of the I2S interface to realize the reception of each frame of data of the TDM interface.

[0031] In step 108, the TDM data to be transmitted is transmitted between the I2S module and the TDM module according to the clock signal.

[0032] In some embodiments, transmitting the TDM data to be transmitted may include the following steps 108a and 108b.

[0033] In step 108a, the I2S frame synchronization signal and the I2S frame clock signal of the I2S module are read cyclically.

[0034] In some embodiments, when starting to read the I2S frame synchronization signal and the I2S frame clock signal of the I2S interface, the system interrupt is turned off. In this way, when the read signal changes, the system is prevented from being interrupted by other events, thereby affecting the reading result, and the interrupt service routine is prevented from occupying system resources during the reading process.

[0035] In step 108b, after the I2S frame synchronization signal changes from low level to high level, the I2S frame clock signal also changes from low level to high level, and the transmission of the TDM data to be transmitted between the I2S module and the TDM module begins. In this way, it is ensured that data transmission can be started on the same edge in the same cycle to avoid data sequence disorder.

[0036] In some embodiments, starting the transmission of the TDM data to be transmitted between the I2S module and the TDM module includes: restoring the system interruption. In this way, the system interruption is restored after the formal data transmission starts in the confirmation cycle, so that the application layer can normally participate in the data transmission process, and the application layer can use the TDM data to be transmitted.

[0037] In some embodiments, starting the transmission of the TDM data to be transmitted between the I2S module and the TDM interface includes steps 1082a to 1086a. In some embodiments, these steps can be considered as a process in which the I2S module receives data sent by the TDM module.

[0038] In step 1082a, the TDM data to be transmitted transmitted by the TDM module is received through the I2S module and buffered in a first-in-first-out queue.

[0039] In step 1084a, after receiving the data acquisition signal sent by the application, the TDM data to be transmitted in the first-in-first-out queue is transmitted to the memory through direct memory access, so that the application obtains the TDM data from the memory.

[0040] In step 1086a, after receiving the stop transmission signal sent by the application, continue to complete the data transmission within the current I2S frame clock signal, and stop receiving the TDM data to be transmitted.

[0041] In this way, the I2S interface receives the TDM data to be transmitted by the TDM peripheral. During the reception process, the FIFO (First-In-First-Out) buffer ensures that when the speed of the application reading and receiving data is inconsistent, no data is missed, and the data can be output in the order of the received data. When the application needs to obtain the signal, the data in the FIFO queue is transferred to the memory through direct memory access (DMA), and the application can directly access the memory to obtain the data, reducing the delay when the application obtains the data. After the data is sent, the last frame of data usually carries an end mark. After the application reads the end mark, it sends a stop transmission signal, and then continues to complete the data transmission within the current I2S frame clock signal and stops receiving the TDM data to be transmitted, which can avoid data omissions.

[0042] In some embodiments, starting the transmission of the TDM data to be transmitted between the I2S interface and the TDM interface includes steps 1082b to 1088b. In some embodiments, these steps can be considered as a process of the I2S module sending data to the TDM module.

[0043] In step 1082b, the TDM data to be transmitted sent by the application is received and buffered in the memory.

[0044] In step 1084b, the TDM data to be transmitted in the memory is read into a first-in-first-out queue through direct memory access.

[0045] In step 1086b, the TDM data to be transmitted is sent to the TDM module via the I2S module.

[0046] In step 1088b, when the data in the FIFO queue is empty, stop sending data to the TDM module at the start of the next I2S frame clock signal.

[0047] In this way, data is sent to TDM peripherals through the I2S interface. The TDM data to be transmitted generated by the application is first cached in the memory, then read into the first-in-first-out queue, and finally sent to the TDM interface by the I2S interface. The first-in-first-out queue also uses the characteristics of outputting in time sequence, and uses the first-in-first-out queue as a buffer during data transmission. At the same time, when the first-in-first-out queue is empty, it means that no new data to be transmitted is generated during the data transmission process, and the transmission process ends. Then, the data will continue to be sent within the current I2S frame clock signal to prevent data omission. When the next I2S frame clock signal starts, the data will stop being sent, and the process of sending the TDM data to be transmitted ends.

[0048] Hereinafter, application scenarios of the audio channel construction method and the audio transmission method according to the embodiments of the present invention will be described by way of examples.

[0049] In existing SoCs (system-on-chips), the TDM (time division multiplexing) mode of the I2S / PCM (pulse code modulation) controller was not designed to handle audio data on multiple data lines at the same time, resulting in the controller only supporting the transmission of a single data line in some SoCs. This design limitation significantly limits the transmission capacity of audio data, especially in application scenarios that require high-channel audio processing, where the support of this single data line is insufficient to meet the needs, thus affecting the overall performance and scalability of the system. In addition, the current SoC's TDM (time division multiplexing) mode design limits the support for audio channels and can only process data for up to 8 channels. In the face of audio transmission application scenarios that require a higher number of channels, such as 32 channels, 64 channels or more channels, the existing TDM mode cannot meet these expansion requirements. In addition, if the existing I2S / PCM controller wants to achieve multi-channel data input, it is necessary to increase the number of data lines, with each line responsible for data transmission of two channels, which also requires hardware modification.

[0050] In addition, the existing audio transmission solution requires the use of additional modules for data transfer due to the limitations of the I2S / PCM controller of the SoC. In the existing solution, in order to process multi-channel audio data and transmit it to the SoC, other modules (such as FPGA) must be used for transfer. Although this approach can achieve the function, it inevitably increases the hardware cost. The FPGA module is responsible for integrating multi-channel audio data and converting it into a format that the SoC can handle. The converted audio data is then transmitted to the SoC through the I2S / PCM interface.

[0051] Figure 3 FIG. 1 is a flowchart showing an implementation of an audio transmission method in a specific scenario according to an embodiment of the present invention. Figure 3 As shown, the method includes the following steps 301 to 308.

[0052] In step 301, data parameters of the TDM data to be transmitted are obtained, including a sampling rate of 48 kHz (kilohertz), a sampling channel number of 8CH (Channel) and a sampling width of 32 bits (bits).

[0053] The data parameters here are only examples, and other sampling rate formats that can satisfy the corresponding calculation method can be used in this solution.

[0054] In TDM mode, the number of sampling channels indicates the number of audio channels transmitted simultaneously. If it is I2S mode, the standard number of channels is 2. The sampling width indicates the number of bits per sample per channel.

[0055] In step 302, a bit clock signal required for transmission, a first frame clock signal corresponding to the I2S frame clock signal, and a second frame clock signal corresponding to the TDM frame clock signal are generated according to the data parameters.

[0056] Bit clock signal = sampling rate × number of sampling channels × sampling width = 48K*8*32 = 12288kHz. By unifying the bit clock signals of the I2S interface and the TDM interface, the I2S interface and the TDM interface can synchronously send and receive each bit of digital audio data.

[0057] The key to solving the problem of high cost of transmitting and receiving audio data by existing hardware is to ensure the consistency of audio data. Since audio data is driven by the bit clock signal, as long as the bit clock signal of the I2S module of the SoC is the same as the bit clock signal of the multi-channel audio TDM device, the consistency of data volume can be ensured.

[0058] The first frame clock signal, i.e., the I2S frame clock signal provided to the I2S interface = bit clock signal ÷ protocol sampling width ÷ number of sampling channels = 12288 / 2 / 32 = 192kHz. That is, while ensuring that the bit clock and the number of sampling channels are the same, it can be ensured that the calculated first frame clock signal is a multiple of the second frame clock signal, i.e., avoiding the situation where the falling edge of the I2S frame clock signal is at the rising edge of the second frame clock signal, thereby ensuring that the TDM data to be transmitted can be completely transmitted. The first frame clock signal identifies the left channel and right channel data in each audio frame of the I2S signal, and transmits two samples of the left channel and the right channel in each first frame clock signal cycle. Since the present disclosure utilizes the I2S interface to transmit multi-channel data, the windows for sending or receiving the left channel and the right channel data are represented here, in which multiple TDM frames can be transmitted.

[0059] The second frame clock signal is the TDM frame clock signal provided to the TDM interface, and is also provided to the I2S interface as an I2S frame synchronization signal. Since the standard I2S protocol can only transmit data of two channels, and cannot transmit multi-channel data, in order to transmit the TDM data to be transmitted, the frame clock signal of the TDM data needs to be sent to the I2S interface, so that the two can synchronously receive and send data. Therefore, the second clock signal directly uses 48kHz, that is, the sampling interval. The I2S frame synchronization signal marks the beginning of an audio frame, that is, the beginning of channel sampling.

[0060] In order to maintain the correct order of multi-channel data, it is necessary to start data transmission when the I2S frame synchronization signal and the I2S frame clock signal of the SoC are aligned according to a specific edge. In this way, the transmission order of multi-channel data will not be confused, thus ensuring the synchronization and integrity of the audio data.

[0061] In step 303, a bit clock signal, a first frame clock signal and a second frame clock signal are generated by a clock module according to the calculated bit clock signal, the first frame clock signal and the second frame clock signal. In this way, the bit clock signal, the first frame clock signal and the second frame clock signal are generated by the same clock module, which can ensure that the clock signals are of the same source and in phase, so that the data transmission windows of the I2S interface and the TDM interface can overlap to complete the data transmission process. The same source and the same phase means that the clock signals come from the same clock source and have the same phase.

[0062] The clock module here can be an independent module in the SoC of the I2S device, or a module provided by other peripherals, as long as it can generate the same source and same phase clock signals.

[0063] In step 304, during the system startup phase, the clock module is initialized so that the clock module can continuously output the bit clock signal 12288kHz, the first frame clock signal 192kHz, and the second frame clock signal 48kHz. In this way, the I2S interface in the SoC system can use the same source and same phase clock signal as the TDM interface of the external device, thereby ensuring synchronous transmission of audio data and ensuring the correct transmission order.

[0064] In step 305, the I2S frame synchronization signal and the I2S frame clock signal of the I2S interface are read cyclically. When the I2S frame synchronization signal changes from a low level to a high level (rising edge), the data transmission is started after the I2S frame clock signal also changes from a low level to a high level (rising edge). For example, the high and low level changes of the pins connected to the I2S frame synchronization signal and the pins connected to the I2S frame clock signal are monitored through a while loop.

[0065] Figure 4 1 is a schematic diagram showing a data transmission timing of an I2S interface according to an embodiment of the present disclosure. Figure 4 , SDOx represents the output data line of the I2S interface in the SoC, corresponding to the SDI of the TDM device, SDIx is the input data line of the I2S interface in the SoC, corresponding to the SDO of the TDM device, LRCLK is the I2S frame clock signal, and FSYNC is the I2S frame synchronization signal. It can be seen that after the rising edge of the I2S frame synchronization signal, the data transmission is started again at the rising edge of the I2S frame clock signal. Since the I2S frame synchronization signal is consistent with the TDM frame clock signal, the frame clock signals of the I2S module and the TDM module of the peripheral are aligned, that is, within one I2S frame clock signal cycle, TDM just sends the eight-channel data of ch0-ch7, so that the I2S module and the TDM module start at the same edge of the same cycle, ensuring that the multi-channel data sequence of each transmission is correct. That is, it is ensured that the communication with the peripheral of the TDM interface is carried out according to the timing of I2S.

[0066] Furthermore, during the reading of high and low level changes, the system interrupt is turned off to prevent the interrupt service program from occupying system resources during the reading process, ensuring that data transmission can be started on the same edge in the same cycle to avoid data sequence disorder.

[0067] Next, in step 306, after the data transmission starts, the system interruption is recovered, and the application layer can start to intervene in the data transmission process.

[0068] In step 307a, the I2S interface receives the TDM data to be transmitted transmitted by the TDM peripheral device, including the following steps (1)-(3). If the TDM peripheral device is a recording device, this process is a recording process.

[0069] (1) Receive TDM data to be transmitted from the TDM device through the I2S interface and the TDM interface according to the I2S protocol.

[0070] (2) Store this data in a FIFO (first-in-first-out queue).

[0071] (3) Data is transferred from FIFO to DMA (direct memory access), so that the application can read data from DMA and obtain 48KHz sampling rate, 8 channels, 32 bits of TDM data to be transmitted.

[0072] In step 307b, data is sent to the TDM peripheral device via the I2S interface, including the following steps (1)-(2). If the TDM peripheral device is an audio device, this process is the playback process.

[0073] (1) Read the TDM data to be written in the DMA into the FIFO. The TDM data to be written is the TDM data to be transmitted with a sampling rate of 48 kHz, 8 channels, and 32 bits generated by the application and written into the DMA by the application.

[0074] (2) According to the I2S protocol, the data in the FIFO is output to the TDM device through the I2S interface and the TDM interface.

[0075] It can be seen that since the bit clock signal between the I2S interface and the TDM interface is from the same clock source, and the I2S frame synchronization signal and the TDM frame clock signal are also synchronized, the integrity and accuracy of the data transmission can be ensured and transmission errors can be avoided during the transmission process of the TDM data to be transmitted in steps 307a and 307b.

[0076] After step 307a, step 308a is further included.

[0077] In step 308a, a stop signal sent by the application is received, and the stop signal is generated when the application reads the last bit mark in the TDM data to be transmitted. After completing the data transmission in the current I2S frame clock signal cycle, stop receiving new data when the rising edge of the next I2S frame clock signal arrives, thereby ensuring that the data transmission can be correctly terminated at the frame boundary.

[0078] In this way, in the recording process, when the audio data acquisition is about to end, the rising edge of the I2S frame synchronization signal and the I2S frame clock signal is detected and preparations are made to end the current data transmission session, ensuring that after the rising edge of the last I2S frame clock signal, all remaining TDM data to be transmitted are correctly received and stored in the FIFO, and are transferred to the DMA for the application to read.

[0079] After step 307b, step 308b is also included.

[0080] In step 308b, when the data in the FIFO is cleared, after the data output of the current I2S frame clock signal is finished, the data output is stopped at the rising edge of the next I2S frame clock signal, thereby ending the data transmission at the frame boundary. Further, in order to improve the accuracy of the judgment, in order to avoid the situation that the data in the FIFO is cleared due to the inconsistent writing and taking-out rates of the FIFO data, while the actual TDM data to be transmitted has not been completely transmitted, the FIFO clearing state can be set to be maintained for a certain period of time before the operation of stopping the data output at the rising edge of the next I2S frame clock signal is performed; or the stop signal is agreed with the application, and the operation of stopping the data output at the rising edge of the next I2S frame synchronization signal and the I2S frame clock signal is performed after the stop signal sent by the application is received, that is, when the I2S frame synchronization signal and the I2S frame clock signal enter the rising edge at the same time, it marks the end of the previous frame of data and the start of the transmission of the new frame of data.

[0081] In this way, in the playback process, when the TDM data to be transmitted is about to end, the application will stop writing new data to the DMA; at this time, the data in the FIFO will continue to be output to the TDM device until the rising edge of the next I2S frame clock signal and the I2S frame synchronization signal is detected, marking the end of the current frame, ensuring that all data in the FIFO has been transmitted.

[0082] In some embodiments, steps 301 to 308 are directly implemented by a controller inside the SoC, for example, by an I2S / PCM controller.

[0083] According to another aspect of the present invention, Figure 5 4 is a schematic diagram showing an audio transmission device 400 according to an embodiment of the present invention. Figure 5 The audio transmission device 400 includes a control module (SOC), a clock module (CLK module), an I2S module and a TDM module (TDM DEVICE).

[0084] The output end of the clock module is electrically connected to the clock port of the I2S module and the clock port of the TDM module respectively, and the data port of the I2S module is electrically connected to the data port of the TDM module.

[0085] Reference Figure 5 , the data port SDI0 / 1 / 2 / 3 of the I2S interface is connected to the data port SDO0 / 1 / 2 / 3 of the TDM interface 406. In addition, the data port SDO0 / 1 / 2 / 3 of the I2S interface is connected to the data port SDI0 / 1 / 2 / 3 of the TDM interface 406.

[0086] The control module is configured to control the clock module to generate clock signal parameters required for transmission according to data parameters of the TDM data to be transmitted, and to generate a clock signal according to the clock signal parameters. In addition, the control module is configured to control the transmission of the TDM data to be transmitted between the I2S module and the TDM module according to the clock signal.

[0087] In some embodiments, the clock port of the I2S module includes an I2S frame synchronization port FSYNC_IO, an I2S bit clock port BCLK1 and an I2S frame clock port LRCLK1; the clock port of the TDM interface includes a TDM frame clock port LRCLK2 and a TDM bit clock port BCLK2; the output end of the clock module includes a bit clock output end CLK1, a first frame clock output end CLK2 and a second frame clock output end CLK3; the bit clock output end CLK1 is respectively connected to the I2S bit clock port BCLK1 and the TDM bit clock port BCLK2; the first frame clock output end CLK2 is connected to the I2S frame clock port LRCLK1; the second frame clock signal CLK3 is respectively connected to the I2S frame synchronization port FSYNC_IO and the TDM frame clock port LRCLK2.

[0088] In this way, the clock module generates a bit clock output end which is respectively provided to the I2S bit clock port of the I2S interface and the TDM bit clock port of the TDM interface, thereby realizing synchronous data transmission of each audio sampling bit. Specifically for channel transmission, the clock module generates a first frame clock output end which is connected to the I2S frame clock port to provide the frame clock required by the I2S interface. Since the standard I2S interface only transmits two channel data, the transmission of the TDM data to be transmitted in the transmission window of the two channel data requires synchronization of each channel signal during the transmission process. Therefore, the second frame clock signal is used to provide a frame synchronization clock for the I2S interface and a frame clock for the TDM interface, namely, the I2S interface can know the window in which the TDM interface sends data, thereby realizing data reception and completing the sending of the TDM data to be transmitted.

[0089] According to yet another aspect of the present invention, Figure 6 is a block diagram showing an electronic device 500 according to an embodiment of the present invention. Figure 6 , the electronic device 500 includes a memory 502 and at least one processor 504. The at least one processor 504 is electrically coupled to the memory 502. The memory 502 is configured to store information associated with the audio data. The at least one processor 504 is configured to perform the corresponding steps or actions in the audio transmission method described in the above embodiment, which will not be repeated here.

[0090] In summary, the audio transmission channel construction method, audio transmission method, device and electronic device provided by the present invention use a clock module to provide a bit clock signal of the same source to the I2S interface and the TDM interface, and provide a first frame clock signal as the I2S frame clock signal of the I2S interface, and provide a second frame clock signal as the I2S frame synchronization signal of the I2S interface and the TDM frame clock signal of the TDM interface. In this way, the I2S interface and the TDM interface ensure that the amount of data transmitted in one frame is the same through the same bit clock signal, and start transmitting data when the I2S frame clock signal and the I2S frame synchronization signal are both rising edges, so that the TDM interface can use the timing of I2S to realize data transmission, solve the problem that the use of the TDM interface requires additional agreed data transmission rules and the use of I2S for data transmission cannot transmit multi-channel data. And avoid the traditional need to use a third-party hardware circuit for data forwarding, thereby significantly reducing the hardware cost of the system. At the same time, due to the reduction of additional hardware components, the debugging cost of the system is also reduced. This direct data transmission method simplifies the system design and improves the overall reliability and stability.

[0091] Through direct data transmission between I2S and TDM protocols, we have greatly improved the performance of multi-channel audio transmission for SoCs that do not originally support TDM functions. This means that even if the SoC itself does not have a TDM interface, it can still achieve multi-channel audio data transmission through software-level adaptation and protocol conversion. This approach expands the application range of SoCs, enabling them to easily handle complex audio processing tasks such as multi-channel recording and playback, surround sound processing, etc.

[0092] In the I2S module, through the method disclosed in the present invention, each data line (SDI / SDO) can be enabled to have the ability to send and receive TDM channel data, which means that in an I2S controller with multiple data lines, the multi-channel transmission capability of the SoC is significantly multiplied. Specifically, if one data line can transmit 8 channels of audio data, a controller with two data lines can transmit 16 channels simultaneously, three data lines can transmit 24 channels, and so on. This doubling of capabilities not only improves the throughput of audio data, but also increases the flexibility and scalability of the system. For example, in professional audio equipment or advanced home theater systems, this doubled transmission capability can meet the needs of high-channel audio processing, thereby providing a richer and more immersive auditory experience. In addition, this design allows the SoC to more efficiently utilize its internal resources, optimize data flow, reduce latency, and improve overall audio quality when processing multi-channel audio data.

[0093] The above descriptions are merely embodiments of the present invention and are not intended to limit the patent scope of the present invention. Any equivalent transformations made using the contents of the present invention's specification and drawings, or directly or indirectly applied in related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An audio transmission method, characterized in that: include: Obtain data parameters of TDM data to be transmitted; Generating clock signal parameters required for transmission according to the data parameters; Generate a clock signal according to the clock signal parameter through a clock module, and provide the clock signal to an I2S module and a TDM module; as well as The TDM data to be transmitted is transmitted between the I2S module and the TDM module according to the clock signal.

2. The audio transmission method according to claim 1, characterized in that: Acquiring data parameters of the TDM data to be transmitted includes: acquiring the sampling rate, number of sampling channels and sampling width of the TDM data to be transmitted, Generating the clock signal parameters required for transmission according to the data parameters includes: calculating the bit clock signal according to the sampling rate, the number of sampling channels and the sampling width; and calculating the first frame clock signal required for the I2S mode according to the bit clock signal, and using the sampling rate as the second frame clock signal. Wherein providing the clock signal to the I2S module and the TDM module includes: providing the bit clock signal to the I2S module and the TDM module as an I2S bit clock signal and a TDM bit clock signal respectively; providing the first frame clock signal to the I2S module as an I2S frame clock signal; and providing the second frame clock signal to the I2S module as an I2S frame synchronization signal, and providing the second frame clock signal to the TDM module as a TDM frame clock signal.

3. The audio transmission method according to claim 2, characterized in that: Calculating the bit clock signal according to the sampling rate, the number of sampling channels, and the sampling width includes obtaining the bit clock signal using the following formula: Bit clock signal = sampling rate × number of sampling channels × sampling width, The step of calculating the first frame clock signal required for the I2S mode according to the bit clock signal comprises: Get the protocol sampling width and number of protocol sampling channels in I2S mode; and The first frame clock signal is obtained using the following formula: The first frame clock signal = bit clock signal ÷ protocol sampling width ÷ number of sampling channels.

4. The audio transmission method according to claim 1, characterized in that: Transmitting the TDM data to be transmitted between the I2S module and the TDM module according to the clock signal includes: Circularly reading an I2S frame synchronization signal and an I2S frame clock signal of the I2S module; and If the I2S frame clock signal also changes from a low level to a high level after the I2S frame synchronization signal changes from a low level to a high level, the transmission of the TDM data to be transmitted between the I2S module and the TDM module begins.

5. The audio transmission method according to claim 4, characterized in that: Cyclic reading of the I2S frame synchronization signal and the I2S frame clock signal of the I2S module includes: During the reading of the I2S frame synchronization signal and the I2S frame clock signal of the I2S module, the system interrupt is turned off.

6. The audio transmission method according to claim 5, characterized in that: Starting the transmission of the TDM data to be transmitted between the I2S module and the TDM module includes: Recover the system interruption.

7. The audio transmission method according to claim 4, characterized in that: Starting the transmission of the TDM data to be transmitted between the I2S module and the TDM module includes: Receiving the TDM data to be transmitted transmitted by the TDM module through the I2S module, and buffering the data in a first-in-first-out queue; After receiving a data acquisition signal sent by an application, the TDM data to be transmitted in the first-in-first-out queue is transmitted to a memory through direct memory access, so that the application acquires the TDM data from the memory; After receiving the stop transmission signal sent by the application, continue to complete the data transmission within the current I2S frame clock signal and stop receiving the TDM data to be transmitted.

8. The audio transmission method according to claim 4, characterized in that: Starting the transmission of the TDM data to be transmitted between the I2S module and the TDM module includes: Receive TDM data to be transmitted sent by the application and buffer it in the memory; Reading the TDM data to be transmitted in the memory into a first-in-first-out queue through direct memory access; Sending the TDM data to be transmitted to the TDM module through the I2S module; When the data in the FIFO queue is empty, the sending of data to the TDM module is stopped at the start of the next I2S frame clock signal.

9. An audio transmission device, characterized in that: Including control module, clock module, I2S module and TDM module; The output end of the clock module is electrically connected to the clock port of the I2S module and the clock port of the TDM module respectively, and the data port of the I2S module is electrically connected to the data port of the TDM module; The control module is configured to control the clock module to generate clock signal parameters required for transmission according to data parameters of the TDM data to be transmitted, and to generate a clock signal according to the clock signal parameters; The control module is configured to control the transmission of the TDM data to be transmitted between the I2S module and the TDM module according to the clock signal.

10. The audio transmission device according to claim 9, characterized in that: The clock port of the I2S module includes an I2S frame synchronization port, an I2S bit clock port and an I2S frame clock port; The clock port of the TDM module includes a TDM frame clock port and a TDM bit clock port; The output end of the clock module includes a bit clock output end, a first frame clock output end and a second frame clock output end; The bit clock output end is connected to the I2S bit clock port and the TDM bit clock port respectively; The first frame clock output end is connected to the I2S frame clock port; The second frame clock signal is connected to the I2S frame synchronization port and the TDM frame clock port respectively.

11. An electronic device, characterized in that: include: a memory configured to store information associated with the audio data; as well as At least one processor is electrically coupled to the memory and is configured to execute the audio transmission method according to any one of claims 1 to 8.

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