SerDes with robust parameter initialization

Abstract

Serializer / deserializer (SerDes) modules, equalizers, and equalization techniques with robust parameter initialization can significantly reduce convergence time. An illustrative equalizer includes a discrete time finite impulse response ("FIR") filter to convert a received signal to a filtered signal; a decision element for determining a channel symbol represented by the filtered signal; and a controller. The controller is configured to estimate, for each of a plurality of values within a search range, performance of the equalizer based on the channel symbols, and based on at least one of the filtered signal or an input signal of the decision element; the search unit is configured to search a centroid value based on the performance of each of a plurality of parameter values within a search range; and configured to derive an initial value of the parameter from the centroid value.

Description

Background Art

[0001] Digital communication occurs between a transmitting device and a receiving device through an intermediate communication medium or "channel" (e.g., a fiber optic cable or insulated copper wire). Each transmitting device typically transmits symbols at a fixed symbol rate, while each receiving device detects (possibly damaged) symbol sequences and attempts to reconstruct the transmitted data. A "symbol" is a state or important condition of a channel that lasts for a fixed period of time, which is called a "symbol interval." For example, a symbol can be a voltage or current level, an optical power level, a phase value, or a specific frequency or wavelength. The change from one channel state to another is called a symbol transition. Each symbol can represent (i.e., encode) one or more binary bits of data. Alternatively, data can be represented by a symbol transition, or by a sequence of two or more symbols.

[0002] Many digital communication links use only one bit per symbol; a binary "0" is represented by one symbol (e.g., a voltage or current signal within a first range), and a binary "1" is represented by another symbol (e.g., a voltage or current signal within a second range), but higher order signal constellations are known and frequently used. In 4-level pulse amplitude modulation ("PAM4"), each symbol interval can carry any of four symbols, typically labeled -3, -1, +1, and +3. Two binary bits can thus be represented by each symbol.

[0003] Channel imperfections create dispersion that can cause each symbol to interfere with its neighbors, a result known as "inter-symbol interference" ("ISI"). ISI can make it difficult for a receiving device to determine which symbols were sent in each interval, especially when such ISI is combined with added noise.

[0004] To combat noise and ISI, receiving devices can employ various equalization techniques. Linear equalizers typically must balance reducing ISI with avoiding noise amplification. Decision feedback equalizers ("DFEs") are typically preferred because they are able to combat ISI without inherently amplifying noise. As the name implies, a DFE employs a feedback path to remove the effects of ISI originating from previously decided symbols. Other equalizer designs are also known. As symbol rates continue to increase, whichever equalizer is used must adapt the channel to compensate for the increasing levels of ISI. To make the situation more challenging, the selected equalizer design must cope with potential changes in the performance of its components due to process variations, supply voltage variations, and temperature variations (collectively referred to as "PVT variations"), as well as drift due to component aging.

[0005] A popular technique for dealing with such changes is called adaptive equalization, in which the parameters of the equalizer are iteratively adjusted until the performance of the equalizer converges to an optimal value. A known challenge with adaptive equalization is the time that such convergence can take to occur. This convergence time can be reduced if the parameters of the equalizer are initialized to close to their ideal values. Summary of the invention

[0006] Therefore, disclosed herein are serializer / deserializer (SerDes) modules, equalizers, and equalization techniques with robust parameter initialization, which can significantly reduce convergence time. An illustrative equalizer includes: a discrete-time finite impulse response ("FIR") filter for converting a received signal into a filtered signal; a decision element for determining a channel symbol represented by the filtered signal; and a controller. The controller is configured to estimate the performance of the equalizer based on the channel symbol and based on at least one of the filtered signal or the input signal of the decision element for each of a plurality of values ​​within a search range; configured to find a centroid value based on the performance of each of a plurality of parameter values ​​within the search range; and configured to derive an initial value of the parameter from the centroid value.

[0007] An illustrative equalization method includes: converting a received signal into a filtered signal using a discrete-time finite impulse response ("FIR") filter; determining a channel symbol represented by the filtered signal using a decision element; estimating an equalization performance for each of a plurality of parameter values ​​within a search range; finding a centroid value based on the equalization performance for each of the plurality of parameter values ​​within the search range; and deriving an initial value of the parameter from the centroid value.

[0008] Each of the foregoing embodiments may be implemented individually or in combination, and may be implemented in any suitable combination with any one or more of the following features: 1. The search range is a reduced search range determined based on three extension values ​​from the entire search range. 2. The three extension values ​​are at 1 / 4, 2 / 4 and 3 / 4 of the search range. 3. The reduced search range spans half of the entire search range and is centered on the extension value that provides the best performance among the three extension values. 4. The parameter is a coefficient of the FIR filter. 5. The parameter is one of a plurality of parameters. 6. The error module is configured to repeat the estimation, search and derivation operations for each of the plurality of parameters. 7. The parameter is a decision threshold used by the decision element. 8. The equalizer includes a feedback filter for converting a channel codeword into a feedback signal; and an adder for combining the feedback signal with the filtered signal to provide an equalized signal to the decision element. 9. The parameter is a coefficient of the feedback filter. 10. The decision element includes a decision feedback pre-compensation unit, and the parameter is a pre-compensation value. 11. The equalizer of example 1, wherein the error module is configured to adjust the initial value based on the performance of the equalizer using the initial value of the parameter. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 An illustrative computer network is shown.

[0010] Figure 2 is a block diagram of an illustrative point-to-point communications link.

[0011] Figure 3 is a block diagram of an illustrative serializer-deserializer integrated circuit device.

[0012] Figure 4 is a block diagram of an illustrative decision feedback equalizer ("DFE").

[0013] Figure 5 is a block diagram of an illustrative discrete-time finite impulse response ("FIR") filter.

[0014] Figure 6 is a block diagram of an illustrative parallel DFE.

[0015] Figure 7 is a timing diagram of the clock signals used for the parallel DFE.

[0016] Fig. 8A is a graph of illustrative equalizer performance as a function of parameter values.

[0017] Figure 8B is a graph of the area defined by the performance / parameter value curves.

[0018] Figure 8C is a graph of the area defined by the performance / dispersion parameter value curves.

[0019] Figure 9A-9D It is a graph of different performance curve scenarios.

[0020] Fig.10 is a flow chart of an illustrative equalization method. DETAILED DESCRIPTION

[0021] Note that the specific embodiments given in the drawings and the following description do not limit the present disclosure. Instead, they provide a basis for those of ordinary skill in the art to identify alternatives, equivalents, and modifications that are within the scope of the claims.

[0022] The disclosed equalizer and equalization method are best understood in the context of the larger environment in which they operate. Figure 1 An illustrative communication network is shown that includes a mobile device 102 and computer systems 103-104 coupled via a packet-switched routing network 106. Routing network 106 may be or include, for example, the Internet, a wide area network, or a local area network. Figure 1 , routing network 106 includes a network of equipment items 108, such as hubs, switches, routers, bridges, etc. Equipment items 108 are connected to each other and to computer systems 103-104 via point-to-point communication links 110 that transmit data between the various network components.

[0023] Figure 2 It can be expressed Figure 1 1 is a diagram of an illustrative point-to-point communication link of link 110 in FIG. The illustrated embodiment includes a first node (“node A”) communicating with a second node (“node B”). Nodes A and B may each be, for example, any of mobile device 102, equipment item 108, computer systems 103-104, or other transmit / receive devices suitable for high rate digital data communication.

[0024] Node A includes a transceiver 202, which is coupled to the internal data bus 204 of node A via a host interface 206. Similarly, node B includes a transceiver 203, which is coupled to its internal bus 205 via a host interface 207. Data transmission within the node can occur via, for example, a parallel 64-bit or 128-bit bus. When a block of data needs to be transmitted to or from a remote destination, the host interface 206, 207 can convert between the internal data format and the network packet format, and can provide packet sorting and buffering for the transceiver. The transceivers 202, 203 serialize the packet payload to transmit via a high-bandwidth communication channel 208, and process the received signal to extract the transmitted data.

[0025] A communication channel 208 extends between transceivers 202, 203. Channel 208 may include, for example, transmission media such as fiber optic cables, twisted pairs, coaxial cables, backplane transmission lines, and wireless communication links. (It is also possible that the channel is formed by a magnetic or optical information storage medium, in which a write-read transducer is used as a transmitter and a receiver.) Separate unidirectional channels may be used to provide bidirectional communication between node A and node B, or in some cases, a single channel may be used that transmits signals in opposite directions without interference. The channel signal may be, for example, a voltage, current, optical power level, wavelength, frequency, phase value, or any suitable energy property that is transferred from the beginning of the channel to the end of the channel. The transceiver includes a receiver that processes the received channel signal to reconstruct the transmitted data.

[0026] Figure 3 An illustrative monolithic transceiver chip 302 is shown. The chip 302 includes: a SerDes module with contacts 320 for receiving and transmitting high-rate serial bit streams across eight lanes of the communication channel 208; an additional SerDes module with contacts 322 for transmitting the high-rate serial bit streams to the host interface 206; and core logic 324 for buffering the bit streams between the channel and the host interface while implementing the channel communication protocol. Various support modules and contacts 326, 328 are also included, such as power regulation and distribution, clock generation, digital input / output lines for control signals, and a JTAG module for built-in self-test.

[0027] The "deserializer" implements the receive function of chip 302, implements decision feedback equalization ("DFE") or any other suitable equalization technique, including those employing discrete-time finite impulse response ("FIR") filters with adjustable tap coefficients, e.g., linear equalization, partial response equalization. At the contemplated symbol rates (above 50 Gbd), the selected equalizer operates under strict timing constraints.

[0028] Figure 4An illustrative implementation of a DFE configured for receiving a PAM4 signal is shown. An optional continuous time linear equalization ("CTLE") filter 404 provides analog filtering to band limit the signal spectrum while optionally boosting high frequency components of the received signal RX_IN. A feed forward equalization ("FFE") filter 406 minimizes preamble inter-symbol interference ("ISI") while optionally reducing the length of the channel impulse response. An adder 408 subtracts the feedback signal provided by the feedback filter 410 from the filtered signal provided by the FFE filter 406 to produce an equalized signal in which the effects of post-ISI have been minimized. A decision element 412 (sometimes referred to as a "limiter") operates on the equalized signal to determine which symbol it represents in each symbol interval. The resulting symbol decision stream is represented as A. k , where k is the time index.

[0029] In the illustrated example, the symbols are assumed to be PAM4 (-3, -1, +1, +3), so the comparator employed by the decision element 412 uses decision thresholds of -2, 0, and +2, respectively. (For generality, the units used to express the symbols and thresholds are omitted, but volts can be assumed for the purpose of explanation.) The comparator outputs can be collectively a thermometer-coded digital representation of the output symbol decision, or a digitizer can be optionally used to convert the comparator outputs to a binary number representation, for example, 00 represents -3, 01 represents -1, 10 represents +1, and 11 represents +3. Alternatively, a Gray coded representation can be employed.

[0030] DFE uses a memory that stores recent output symbol decisions (A k-1 , A k-2 , …, A k-N , where N is the filter coefficient F iThe feedback signal is generated by a feedback filter 410 having a series of delay elements D (e.g., latches, flip-flops, or shift registers) having a plurality of delay elements D (e.g., a plurality of delay elements D ...

[0031] Additionally, we note here that a timing recovery unit is typically included in any practical DFE implementation, but such considerations are addressed in the literature and are well known to those skilled in the art. However, we note here that at least some contemplated embodiments include one or more additional comparators for comparing the combined signal to one or more of the extreme symbol values ​​(-3, +3), thereby providing an error polarity signal that can be used for timing recovery utilizing, for example, a "bang-bang" design.

[0032] The FFE filter 406 is an analog discrete time FIR filter, or if the FFE filter 406 is preceded by an analog-to-digital converter, the FFE filter 406 is a digital discrete time FIR filter. In either case, the FFE filter 406 has adjustable tap coefficients. The error module 418 measures the equalization error by subtracting the symbol decision of the given symbol interval from the value of the filtered signal of the symbol interval. Alternatively, the error module 418 measures the equalization error by subtracting the symbol decision from the equalized signal, which forms the input of the decision element 412 of the symbol interval (i.e., the output of the adder 408). The controller 420 can adjust the coefficients of the filters 404, 406, 410 based on the correlation between the equalization error and the symbol decision to minimize the residual error. Alternatively or additionally, the error module 418 and / or the controller 420 can estimate the equalization performance. The equalization performance can be measured in various ways (including residual noise power, signal-to-noise ratio, eye gap size (also known as decision margin), bit error rate, etc.). To make such performance measurements, the error module 418 may include a level detector, such as the level detector disclosed in U.S. Pat. No. 11,018,656 ("Multi-function level finder for Serdes"), which is incorporated herein by reference in its entirety. As another alternative, the error module 418 may collect equalization error histograms or other signals or error statistics from which a bit error rate or symbol error rate may be estimated.

[0033] The controller 420 may be a programmable processor or an application specific integrated circuit configured with firmware that is configured to systematically change one or more equalization parameters and determine which values ​​optimize the estimated equalization performance. These parameters may include, for example, filter coefficients and decision thresholds. Optimizing equalization performance may include minimizing the estimated bit error rate or maximizing the eye gap. After the initial optimization phase, the controller 420 may then employ adaptive equalization techniques to further improve the parameter values.

[0034] Figure 5 An illustrative implementation of an analog discrete-time FIR filter that can be used for FFE filter 406 is shown. An input signal is supplied to a sequence of sample and hold ("S&H") elements. The first of the S&H elements captures the input signal value once in each symbol interval, while outputting the captured value from the previous symbol interval. Each of the other S&H elements captures and holds a value from the previous element, repeating the operation to provide increasingly delayed input signal values. A collection of analog signal multipliers multiplies the input signal by corresponding coefficients F iEach of the input values ​​in the sequence is scaled, and the scaled value is provided to an adder, which outputs the sum of the scaled input values. This weighted sum may be referred to herein as a filtered signal.

[0035] Figure 5 The FFE filter needs to perform a large number of operations in each symbol interval, which becomes increasingly challenging as the symbol interval becomes smaller. Figure 6 A parallel version of the FFE filter (with parallel decision elements and feedback filters) is provided.

[0036] exist Figure 6 , CTLE filter 404 band limits the received signal before supplying it in parallel to the S&H element array. Each of the S&H elements is provided with a respective clock signal, each of which has a different phase, causing the elements in the array to take turns sampling the input signal. At any given time, only one of the S&H element outputs is switching. See Figure 7 Illustration of how clock signals can be phase-shifted relative to each other. Note that the duty cycles shown are merely illustrative; the main point to be conveyed in the figure is the sequential nature of the transitions in the different clock signals.

[0037] An array of FFE filters (FFE0 to FFE7) each forming a weighted sum of the S&H element outputs. The weighted sum employs filter coefficients that are cyclically shifted relative to one another. FFE0 operates on the hold signals from the 3 S&H elements operating before CLK0, the S&H elements responsive to CLK0, and the 3 S&H elements operating after CLK0, such that during the assertion of CLK4, the weighted sum produced by FFE0 corresponds to the FFE filter 406 ( Figure 4 and Figure 5 ) output. FFE1 operates on the hold signals from the 3 S&H elements operating before CLK1, the S&H elements responding to CLK1, and the 3 S&H elements operating after CLK1, so that during the assertion of CLK5, the weighted sum corresponds to the output of FFE filter 406. And the operation of the remaining FFE filters in the array follows the same pattern with associated phase shifts. In practice, the number of filter taps can be smaller, or the number of elements in the array can be larger, in order to provide a longer effective output window.

[0038] and Figure 4 Like an equalizer, the adder can combine the output of each FFE filter with the feedback signal to provide an equalized signal to the corresponding decision element. Figure 6An array of decision elements (limiter 0 to limiter 7) is shown, each operating on an equalized signal derived from a corresponding FFE filter output. Figure 4 Like the decision element 412 of FIG. 4 , the illustrated decision element employs a comparator to determine which symbol the equalized signal most likely represents. Decisions are made when the corresponding FFE filter output is valid (e.g., limiter 0 operates when CLK4 is asserted, limiter 1 operates when CLK5 is asserted, etc.). Symbol decisions can be provided in parallel on the output bus to enable lower clock rates to be used for subsequent on-chip operations.

[0039] An array of feedback filters (FBF0 to FBF7) operates on the previous symbol decision to provide feedback signals for the adder. As with the FFE filter, the input to the feedback filter is cyclically shifted and is only applied if the input corresponds to the feedback filter 410 ( Figure 4 ) content, consistent with the time window of the corresponding FFE filter. In practice, the number of feedback filter taps can be less than that shown, or the number of array elements can be larger to provide a longer valid output window.

[0040] and Figure 4 Like the decision element 412, Figure 6 The decision elements in can each adopt additional comparator to provide timing recovery information, coefficient training information and / or pre-compensation to expand one or more taps of feedback filter. After taking into account the cyclic shift, the same tap coefficient can be used for each in the FFE filter and each in the feedback filter. Optimization controller 620 can be a parallel version of controller 420, which collects parallel symbol decisions and combines them with FFE output or decision element input to calculate equalization error, estimate equalizer performance and set or adjust coefficient and / or decision threshold.

[0041] During initialization of the equalizer, the controller can systematically vary the values ​​of the parameters and estimate the performance of the equalizer for each value. Fig. 8A An illustrative curve 802 of performance versus parameter value is shown. The performance curve can be expected to be a smooth curve with peaks or valleys corresponding to optimal performance. However, the performance estimation process is subject to some uncertainty; for example, certain channel symbol patterns may produce unexpectedly good or unexpectedly poor estimated performance as parameter values ​​vary. Fig. 8A , point 803 is the best equalizer performance, but point 804 is an unexpectedly good estimated performance, which may cause the controller to mistakenly select suboptimal parameter values. Point 805 corresponds to the minimum estimated performance.

[0042] To minimize the effects of unexpectedly good or poor estimated performance, the optimization controller 620 can find the centroid of the estimated performance curve 802 and select parameter values ​​corresponding to the centroid. The centroid calculation process has been found to work best if the performance curve 802 is first normalized. For curves where the best values ​​correspond to peaks, normalization is performed by subtracting the minimum estimated performance 805 from each value. For curves where the best values ​​correspond to valleys, normalization can be performed by subtracting each value from the maximum estimated performance.

[0043] Figure 8B The area 810 enclosed between the normalized curve 802 and the horizontal axis is shown. The controller 620 may set the parameter value corresponding to the centroid 812 to The calculation is as follows: Where a, b are the minimum and maximum parameter values, and f(x) is the normalized performance curve. In practice, the calculation can be numerically approximated as: Where, for x i = 1...N i is the parameter value, and f(x i ) is the normalized performance curve value. Figure 8C A region 810 of numerical approximation of illustrative curve 802 and a corresponding centroid 812 are shown.

[0044] Parameter value corresponding to the centroid Usually the parameter value x is located on the performance curve i The controller can be configured to convert the calculated parameter value Round to the nearest argument value to set x i .

[0045] In order to reduce the search space and thus speed up the initialization process, the controller can be configured to detect performance trends using extended parameter values. For example, the controller can estimate the performance of the parameter value at the midpoint between the lower limit and the upper limit of the parameter value range. The controller can further estimate the performance of the parameter value at the middle between the midpoint and the lower limit of the range and the performance of the parameter value at the middle between the midpoint and the upper limit of the range. Therefore, the controller can estimate the performance of the parameter value at 1 / 4, 2 / 4 and 3 / 4 of the entire search range.

[0046] like Figure 9A-9D As shown, such spread measurements can reveal trends in performance curves. Fig.9Ashows a trend in which the midpoint of the performance curve exceeds the performance at the 1 / 4 point and the 3 / 4 point. In this case, the peak of the performance curve might be expected to fall between the 1 / 4 point and the 3 / 4 point, and the controller does not need to estimate performance for parameter values ​​outside this range, thereby reducing the search range by half. The controller may set the parameter value corresponding to the centroid of the reduced search range to Round to the nearest argument value to set x i .

[0047] Fig. 9B shows a decreasing trend in which the performance at the 1 / 4 point exceeds the midpoint performance, which in turn exceeds the 3 / 4 point performance. In this case, the peak of the performance curve may be expected to fall between the midpoint and the lower limit of the range, so the controller does not need to estimate the performance for parameter values ​​above the midpoint, thereby reducing the search range by half. As a further improvement, the controller may set the parameter value corresponding to the centroid of the reduced search range to Round to the next lowest argument value to set x i , as this may tend to be closer to the optimal value than simply rounding to the nearest parameter value setting.

[0048] Fig. 9C shows an upward trend in which the performance at the 3 / 4 point exceeds the midpoint performance, which in turn exceeds the 1 / 4 point performance. In this case, the peak of the performance curve may be expected to fall between the midpoint and the upper limit of the range, so the controller does not need to estimate the performance for parameter values ​​below the midpoint, thereby reducing the search range by half. As a further improvement, the controller may set the parameter value corresponding to the centroid of the reduced search range to Round to the next highest argument value to set x i , as this may tend to be closer to the optimal value than simply rounding to the nearest parameter value setting.

[0049] In each of these examples, the controller may accordingly narrow the search range and determine a centroid of the performance curve within the narrowed search range.

[0050] Fig.9D An example is shown where no trend is apparent, either because the midpoint performance is lower than the performance at the 1 / 4 and 3 / 4 points, or simply because the performance values ​​do not exhibit significant variation. In this example, the controller may be configured to estimate the performance of each parameter value within the entire search range and determine the centroid of the resulting performance curve. The controller may then assign the parameter value corresponding to the centroid of the reduced search range to the value corresponding to the centroid of the reduced search range. Rounds to the nearest parameter value setting.

[0051] Fig.10is a flow chart of an illustrative equalization method that may be implemented by controller 420 or 620. In block 1002, the controller initializes the equalizer parameters using default values. In block 1004, the controller selects a first parameter to be optimized. As an example, the controller may select the FFE coefficient F -1 As initial coefficients. In box 1006, the controller determines estimated equalizer performance for three extended parameter values ​​(e.g., at 1 / 4, 2 / 4, and 3 / 4 of the entire search range). Based on the observed trend, in box 1008, the controller selects a reduced search range, e.g., centered around the observed best performance. In box 1010, the controller determines estimated equalizer performance for each parameter value within the reduced search range. In box 1012, the controller normalizes the performance curve and finds the parameter value corresponding to the centroid of the performance curve within the reduced search range. Appropriate rounding is performed based on the observed trends. In block 1014, the controller determines whether there are other parameters to be optimized, and if so, selects the next parameter in block 1016 and then repeats blocks 1006 to 1014. In optional block 1018, the controller determines whether sufficient performance has been achieved, and if not, repeats blocks 1004-1018. Thereafter, in block 1020, the controller may adaptively improve the parameter value using known adaptive techniques.

[0052] Once the above disclosure is fully understood, numerous alternatives, equivalents, and modifications will become apparent to those skilled in the art. Although the foregoing description is illustrated using a DFE, these principles also apply to all equalizers including adjustable parameter values. The order of the operations described in the flow charts and shown in the formulas may be changed, with certain operations being reordered, pipelined, and / or performed in parallel. Where applicable, the claims are intended to be interpreted as including all such alternatives, equivalents, and modifications.

Claims

1. An equalizer, comprising: A discrete-time finite impulse response (FIR) filter for converting a received signal into a filtered signal; a decision element for determining a channel symbol represented by said filtered signal; as well as A controller, the controller: configured to estimate, for each of a plurality of values ​​within a search range, a performance of the equalizer based on the channel symbol and based on at least one of the filtered signal or an input signal of the decision element; configured to find a centroid value based on a performance of each of the plurality of values ​​within the search range; as well as and configured to derive initial values ​​of parameters from the centroid value.

2. The equalizer according to claim 1, wherein: The search range is a reduced search range determined based on three extension values ​​from the entire search range.

3. The equalizer according to claim 2, wherein: The three extension values ​​are at 1 / 4, 2 / 4 and 3 / 4 of the search range.

4. The equalizer according to claim 3, wherein: The reduced search range spans half of the entire search range and is centered around the extension value that provides the best performance among the three extension values.

5. The equalizer according to claim 1, wherein: The parameters are the coefficients of the FIR filter.

6. The equalizer according to claim 1, wherein: The parameter is one of a plurality of parameters, and wherein the controller is configured to repeat the estimating, finding, and deriving operations for each parameter of the plurality of parameters.

7. The equalizer according to claim 1, wherein: The parameter is a decision threshold used by the decision element.

8. The equalizer according to claim 1, further comprising: A feedback filter, used for converting the channel symbol into a feedback signal; as well as an adder for combining the feedback signal with the filtered signal to provide an equalized signal to the decision element, The parameters are coefficients of the feedback filter.

9. The equalizer according to claim 1, wherein: The decision element comprises a decision feedback pre-compensation unit, and wherein the parameter is a pre-compensation value.

10. The equalizer according to claim 1, wherein: The controller is configured to adjust the initial value based on the performance of the equalizer using the initial value of the parameter.

11. A balancing method, comprising: converting the received signal into a filtered signal using a discrete-time finite impulse response (FIR) filter; determining, using a decision element, a channel symbol represented by the filtered signal; estimating equalization performance for each of a plurality of parameter values ​​within a search range; finding a centroid value based on a balanced performance of each of the plurality of parameter values ​​within the search range; as well as Initial values ​​for the parameters are derived from the centroid value.

12. The equalization method according to claim 11, wherein: The search range is a reduced search range determined based on three extension values ​​from the entire search range.

13. The equalization method according to claim 12, wherein: The three extension values ​​are at 1 / 4, 2 / 4 and 3 / 4 of the search range.

14. The equalization method according to claim 13, wherein: The reduced search range spans half of the entire search range and is centered around the spread value that provides the best equalization performance among the three spread values.

15. The equalization method according to claim 11, wherein: The parameters are the coefficients of the FIR filter.

16. The equalization method according to claim 11, wherein: The parameter is one of a plurality of parameters, and wherein the controller is configured to repeat the estimating, finding, and deriving operations for each parameter of the plurality of parameters.

17. The equalization method according to claim 11, wherein: The parameter is a decision threshold used by the decision element.

18. The equalization method according to claim 11, further comprising: Converting the channel symbol into a feedback signal using a feedback filter; as well as combining the feedback signal with the filtered signal to provide an equalized signal to the decision element, The parameters are coefficients of the feedback filter.

19. The equalization method according to claim 11, wherein: The decision element comprises a decision feedback pre-compensation unit, and wherein the parameter is a pre-compensation value.

20. The equalization method according to claim 11, further comprising: The initial value is adjusted based on the equalization performance using the initial value of the parameter.

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