Low-speed bus coaxial power supply receiving end equalization circuit for suppressing baseline drift

Abstract

The invention relates to the field of digital communication, and discloses a low-speed bus coaxial power supply receiving end equalization circuit for suppressing baseline drift, comprising: a differential amplifier for receiving and amplifying differential signals of a POC channel; the hysteresis comparator is used for judging the amplified differential signal; the equalization circuit comprises a multi-path selection circuit, a series filter and a voltage and current conversion circuit, the series filter is formed by cascading a high-pass filter and a low-pass filter, and the voltage and current conversion circuit is realized by adopting an adjustable transconductance amplifier with a source electrode degradation resistor. According to the framework, through series configuration of the high-pass filter and the low-pass filter and design of an adjustable transconductance value, signal low-frequency components are effectively recovered while low-frequency jitter is suppressed, accurate compensation for baseline drift is realized, and the reliability of data transmission is improved.

Description

Technical Field

[0001] The present application relates to the field of digital communications, and in particular to a baseline drift compensation circuit for a low-speed bus coaxial power supply system. Background Art

[0002] With the development of low-speed bus technology, the use of coaxial power supply (POC) technology in low-speed bus systems has become an important trend. POC technology transmits data signals and power supply current simultaneously through the same coaxial cable, which not only simplifies system wiring and reduces costs, but also improves system integration. However, in order to avoid the interference of power supply current on data signals, POC systems must introduce DC blocking capacitors in the signal transmission path. Although this design solves the problem of power supply interference, it also brings new challenges to data transmission.

[0003] Due to the presence of DC blocking capacitors, the POC channel exhibits high-pass characteristics, causing the low-frequency components of the data signal to be severely attenuated during transmission. This frequency-selective attenuation can cause a phenomenon called baseline wander. Specifically, when continuous "0" or "1" appears in the transmitted data, the signal level will shift significantly, making it difficult for the receiving end comparator to make sampling decisions. In some extreme cases, baseline wander can even cause bit errors, seriously affecting the reliability of the system.

[0004] Commonly used baseline drift compensation solutions in the prior art mainly include two categories: one is based on analog equalization, which compensates for signal distortion by designing an equalizer complementary to the channel characteristics at the receiving end; the other is based on digital processing, which estimates and compensates for baseline drift through digital filtering and adaptive algorithms. However, these solutions have obvious limitations: analog equalization solutions are often sensitive to changes in the capacitance of the DC blocking capacitor in the channel, making it difficult to ensure the consistency of the equalization effect; while digital processing solutions require higher processing power and hardware resources, increasing the complexity and cost of the system.

[0005] In addition, in actual applications, the working environment and conditions of the POC system often vary greatly, which places higher requirements on the adaptability and robustness of the equalization circuit. Especially in low-speed bus application scenarios, due to the strict restrictions on cost and power consumption of the system, it is difficult for existing equalization solutions to achieve an ideal balance between performance, complexity and cost.

[0006] Therefore, a new baseline drift compensation scheme is urgently needed, which can effectively suppress the baseline drift phenomenon in the POC channel and ensure the reliability of data transmission while maintaining low circuit complexity and implementation cost. At the same time, the scheme should also have good self-adaptability and environmental adaptability to meet the needs of different application scenarios. Summary of the invention

[0007] The purpose of the present application is to provide a low-speed bus coaxial power supply receiving end equalization circuit for suppressing baseline drift, so as to solve the problems raised in the above background technology.

[0008] The present application discloses a low-speed bus coaxial power supply receiving end equalization circuit for suppressing baseline drift, comprising:

[0009] A differential amplifier, whose differential input terminal is used to receive a differential signal input by a POC channel having a high-pass characteristic, and whose differential output terminal generates an amplified differential signal;

[0010] A hysteresis comparator, whose input end is connected to the output end of the differential amplifier, is used to judge the amplified differential signal and output the judgment result;

[0011] An equalization circuit, for compensating for baseline drift caused by the POC channel, comprising:

[0012] a multiplexer circuit, wherein a first input terminal thereof is connected to a reference voltage, and a second input terminal thereof is connected to an output terminal of the hysteresis comparator via a delay circuit;

[0013] A series filter, whose input end is connected to the output end of the multi-way selection circuit, comprises a high-pass filter and a low-pass filter connected in series, wherein the cut-off frequency of the low-pass filter is higher than the cut-off frequency of the high-pass filter;

[0014] A voltage-to-current conversion circuit, whose input end is connected to the output end of the series filter and whose output end is connected to the load end of the differential amplifier, and is used for converting the output voltage of the series filter into a compensation current;

[0015] The multiplexer circuit selects the reference voltage when equalization is not started, and selects the decision result delayed by the delay circuit after equalization is started.

[0016] In a preferred example, it is characterized in that: the multi-way selection circuit is a multiplexer, having a selection control terminal, when the level of the selection control terminal is in a first state, the reference voltage is selected, and when the level of the selection control terminal is in a second state, the decision result delayed by the delay circuit is selected.

[0017] In a preferred example, it is characterized in that: the high-pass filter is used to suppress low-frequency jitter in the decision result to prevent saturation of the equalization loop, and the low-pass filter is used to restore the lost low-frequency component in the differential signal.

[0018] In a preferred example, it is characterized in that: the high-pass filter and the low-pass filter are both RC filters.

[0019] In a preferred example, it is characterized in that: the voltage-current conversion circuit is an adjustable transconductance amplifier, including a differential pair and a source degeneration resistor, and the source degeneration resistor is connected to the source of the differential pair and is used to adjust the transconductance value to control the equalization strength.

[0020] In a preferred example, it is characterized in that: the differential pair is a PMOS differential pair.

[0021] In a preferred example, it is characterized in that: the POC channel includes a twisted pair structure.

[0022] In a preferred example, it is characterized in that: the delay circuit includes a series structure of inverters.

[0023] In a preferred example, it is characterized in that: the reference voltage is a common mode voltage, which is generated by a resistor voltage divider circuit.

[0024] The low-speed bus coaxial power supply receiving end equalization circuit of the present application shows excellent technical effects in suppressing baseline drift and improving data transmission reliability, which is specifically reflected in the following aspects:

[0025] First, the present application adopts an equalization circuit topology based on the DFE1TAP structure, which has significant advantages in loop gain and equalization effect compared with traditional equalization technology. Due to the decision feedback mechanism inherent in the DFE1TAP structure, the equalization circuit of the present application can dynamically track changes in channel characteristics while restoring the low-frequency components of the signal, thereby achieving adaptive equalization. This adaptive capability not only enhances the robustness of the equalization circuit to channel changes, but also effectively reduces the system's sensitivity to deviations in the capacitance of the DC blocking capacitor, greatly broadening the scope of application of the equalization circuit.

[0026] Secondly, the present application introduces a multi-way selection circuit for controlling the startup and shutdown of the balancing circuit. Before the balancing is started, the multi-way selection circuit selects the reference voltage to establish a suitable initial working state for the voltage-current conversion circuit; once the balancing is started, the multi-way selection circuit will switch to the judgment result path. This mechanism not only ensures the normal startup of the balancing circuit, but also effectively avoids unstable factors that may occur during the startup process. At the same time, the multi-way selection circuit also cooperates with the delay unit to accurately match the signal timing relationship inside the balancing loop. Combining the above effects, the introduction of the multi-way selection circuit ensures the robust operation of the balancing loop from both the functional and timing levels.

[0027] Furthermore, the present application sets a composite filtering structure consisting of a high-pass filter and a low-pass filter in series in the equalization loop. In actual work, due to the use of a positive feedback topology, the low-frequency jitter in the decision result will continue to accumulate in the loop. When the jitter amplitude exceeds the tolerance of the hysteresis comparator, it will cause the transconductance amplifier output to saturate, causing the entire equalization circuit to collapse. In order to prevent this situation, the present application connects a high-pass filter in series before the low-pass filter to suppress the low-frequency jitter component in the decision result. At the same time, the cutoff frequencies of the high-pass filter and the low-pass filter have been carefully optimized to form a bandpass characteristic, which can restore the damaged low-frequency components of the signal to the maximum extent while suppressing the low-frequency jitter. It can be seen that the composite filtering structure achieves a perfect balance between the equalization effect and the loop stability.

[0028] Finally, in the voltage-current conversion link, this application uses an adjustable transconductance amplifier. By introducing an adjustable degeneration resistor at the source of the input stage differential pair of the transconductance amplifier, the transconductance value of the amplifier can be continuously adjusted. The transconductance value directly determines the amplitude of the compensation current after conversion, which in turn affects the equalization strength. This provides users with the possibility of post-tuning, so that the equalization circuit can adapt to different channel conditions and system requirements. Compared with fixed equalization strength, the introduction of adjustable transconductance circuits greatly improves the flexibility and adaptability of equalization circuits.

[0029] In summary, the equalization circuit of the present application combines the DFE1TAP structure, multi-way selection circuit, series composite filter and adjustable transconductance amplifier in an exquisite, coordinated and complementary manner to form a high-gain, adaptive, robust and adjustable baseline drift suppression scheme. Its outstanding equalization effect, good loop stability and excellent environmental adaptability enable it to maintain reliable data transmission under harsh channel conditions, better meet the technical requirements of low-speed bus coaxial power supply system, and have extremely high practical value and promotion potential.

[0030] A large number of technical features are recorded in the specification of this application, which are distributed in various technical solutions. If all possible combinations of technical features of this application (i.e., technical solutions) are to be listed, the specification will be too long. In order to avoid this problem, the various technical features disclosed in the above-mentioned invention content of this application, the various technical features disclosed in the various embodiments and examples below, and the various technical features disclosed in the accompanying drawings can be freely combined with each other to form various new technical solutions (these technical solutions are all deemed to have been recorded in this specification), unless the combination of such technical features is technically infeasible. For example, in one example, feature A+B+C is disclosed, and in another example, feature A+B+D+E is disclosed, and features C and D are equivalent technical means that play the same role. Technically, only one can be used, and it is impossible to use them at the same time. Feature E can be combined with feature C technically. Then, the solution of A+B+C+D should not be deemed to have been recorded because it is technically infeasible, and the solution of A+B+C+E should be deemed to have been recorded. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figure 1 It is a schematic diagram of the top-level architecture of the receiving end equalization circuit of an embodiment of the present application;

[0032] Figure 2 It is a schematic diagram of the POC structure of an embodiment of the present application;

[0033] Figure 3 It is a schematic diagram of a baseline wander equalization circuit based on DFE1TAP in an embodiment of the present application;

[0034] Figure 4 is a balanced input signal gating logic circuit diagram of an embodiment of the present application;

[0035] Figure 5 is a filter circuit diagram of an embodiment of the present application;

[0036] Figure 6 is a circuit diagram of a transconductance amplifier according to an embodiment of the present application. DETAILED DESCRIPTION

[0037] In the following description, many technical details are provided to help readers better understand the present application. However, those skilled in the art can understand that the technical solution claimed in the present application can be implemented even without these technical details and various changes and modifications based on the following embodiments.

[0038] Description of some concepts:

[0039] Baseline drift: In a communication system, when the digital signal after transmission coding is coupled by AC or transformer, the low-frequency component of the signal will be filtered out due to the presence of DC blocking capacitors, causing the DC level of the signal to shift, making it difficult for the receiving end to make an accurate judgment. This phenomenon is called baseline drift. When the digital signal after coding has a long period of continuous 0 or 1, the baseline drift is particularly serious.

[0040] Power Over Coaxial (POC): A technology that transmits data signals and DC power current simultaneously through a coaxial cable. POC technology simplifies system wiring, reduces costs, and improves integration, but requires the introduction of DC blocking capacitors in the signal transmission path to isolate the power current, which exacerbates the baseline drift problem.

[0041] Decision Feedback Equalizer (DFE): A commonly used adaptive equalizer structure that dynamically compensates for channel distortion by feeding back the decision result to the equalizer input. DFE has the advantages of simplicity, adaptability, and easy convergence. DFE1TAP means that only one tap (Tap) of decision feedback is used, which is the simplest DFE structure.

[0042] Transconductance: A parameter that characterizes the change in current caused by a change in voltage. It is usually expressed as gm, and its value is equal to the ratio of the change in current to the change in voltage. The unit is A / V or S (Siemens). A transconductance amplifier is an amplifier circuit that converts an input voltage signal into an output current signal.

[0043] Source Degeneration: A common amplifier linearization technique that introduces resistance or inductance at the source to increase the negative feedback of the input signal on the output current, thereby reducing distortion and improving linearity. The transconductance of the amplifier can be adjusted by adjusting the source degeneration resistor.

[0044] Hysteresis Comparator: A comparator circuit with hysteresis characteristics. When the input signal rises above the threshold, the output is high, and when the input signal drops below the threshold, the output is low, thereby avoiding frequent triggering near the threshold. Hysteresis comparators are often used to suppress noise and shape waveforms.

[0045] The following is a brief description of some of the innovative features of this application:

[0046] In general, the present application aims to propose an innovative receiving-end adaptive equalization circuit and its construction method to address a series of technical problems caused by the use of coaxial power supply technology in low-speed buses. In actual application scenarios, in order to achieve isolation between the power supply current and the data signal, the POC system often introduces DC blocking capacitors in the transmission path, which causes the channel to exhibit obvious high-pass characteristics. This characteristic causes the low-frequency components in the signal to suffer significant attenuation, especially when the source data appears to be continuously 0 or 1 for a long time, the DC component of the signal will show serious baseline drift. This phenomenon further causes the sampling moment of the sampling and decision circuit at the receiving end to deviate from the optimal sampling point, and in severe cases it may even cause bit errors, thereby seriously affecting the transmission quality and reliability of the system.

[0047] The equalization solutions in the existing technology, such as the compensation method based on analog equalizer and the adaptive equalization algorithm based on digital signal processing, have alleviated the baseline drift problem to a certain extent, but there are still many technical bottlenecks that need to be solved. The former is extremely sensitive to the change in the capacitance of the DC blocking capacitor in the system, and it is difficult to ensure the consistency and stability of the equalization effect in actual engineering applications; the latter requires huge computing resources and storage space, which greatly increases the complexity and cost of the system. In addition, the existing solutions generally lack special optimization for low-speed bus application scenarios, and few solutions can achieve a satisfactory balance between equalization performance, circuit complexity and implementation cost.

[0048] The core concept of this application is to adopt a receiving-end equalization circuit topology based on the DFE1TAP structure, and deeply couple it with key modules such as the multi-way selection circuit, the composite filter structure, and the adjustable transconductance amplifier, thereby forming a high-gain, adaptive, robust and flexibly adjustable baseline drift suppression scheme. Among them, the DFE1TAP structure uses the decision feedback mechanism to realize the adaptive adjustment of the equalization loop, which can not only dynamically track the changes in channel characteristics, but also significantly improve the loop gain and enhance the equalization effect. The coordinated cooperation of the multi-way selection circuit and the delay unit ensures the robust startup and smooth operation of the equalization loop from both the functional and timing levels. The series combination of high-pass and low-pass filters effectively suppresses the low-frequency jitter components in the decision results while maximally restoring the damaged low-frequency components of the signal, effectively balancing the contradiction between the equalization effect and the loop stability. In addition, the introduction of the adjustable transconductance amplifier gives the equalization circuit the flexibility of post-tuning, so that it can adapt to the changing channel conditions and system requirements.

[0049] In summary, this application integrates innovative technical means such as DFE1TAP structure, multi-channel selection circuit, composite filter and adjustable transconductance amplifier to form a highly coordinated, complementary and accurate baseline drift suppression solution. This solution has significant equalization effect, robust loop characteristics and excellent environmental adaptability, and can maintain high-quality, low-error data transmission under harsh channel conditions. At the same time, thanks to the streamlined circuit structure and flexible parameter adjustment capabilities, this solution can take into account multiple factors such as performance, complexity and cost, and provide a set of practical technical approaches for the engineering application of low-speed POC systems, demonstrating extremely high innovation value and broad promotion potential.

[0050] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below in conjunction with the accompanying drawings.

[0051] The first embodiment of the present application relates to a low-speed bus coaxial power supply receiving end equalization circuit for suppressing baseline drift, such as Figure 1 As shown, including:

[0052] A differential amplifier, whose differential input terminal is used to receive a differential signal input by a POC channel having a high-pass characteristic, and whose differential output terminal generates an amplified differential signal;

[0053] A hysteresis comparator, whose input end is connected to the output end of the differential amplifier, is used to judge the amplified differential signal and output the judgment result;

[0054] An equalization circuit, for compensating for baseline drift caused by the POC channel, comprising:

[0055] a multiplexer circuit, wherein a first input terminal thereof is connected to a reference voltage, and a second input terminal thereof is connected to an output terminal of the hysteresis comparator via a delay circuit;

[0056] A series filter, whose input end is connected to the output end of the multi-way selection circuit, comprises a high-pass filter and a low-pass filter connected in series, wherein the cut-off frequency of the low-pass filter is higher than the cut-off frequency of the high-pass filter;

[0057] A voltage-to-current conversion circuit, whose input end is connected to the output end of the series filter and whose output end is connected to the load end of the differential amplifier, and is used for converting the output voltage of the series filter into a compensation current;

[0058] The multiplexer circuit selects the reference voltage when equalization is not started, and selects the decision result delayed by the delay circuit after equalization is started.

[0059] Optionally, the multi-way selection circuit is a multiplexer having a selection control terminal. When the level of the selection control terminal is in a first state, the reference voltage is selected; when the level of the selection control terminal is in a second state, the decision result delayed by the delay circuit is selected.

[0060] Optionally, the high-pass filter is used to suppress low-frequency jitter in the decision result to prevent saturation of the equalization loop, and the low-pass filter is used to restore lost low-frequency components in the differential signal.

[0061] Optionally, both the high-pass filter and the low-pass filter are RC filters.

[0062] Optionally, the voltage-current conversion circuit is an adjustable transconductance amplifier, including a differential pair and a source degeneration resistor, wherein the source degeneration resistor is connected to the source of the differential pair and is used to adjust the transconductance value to control the equalization strength.

[0063] Optionally, the differential pair is a PMOS differential pair.

[0064] Optionally, the POC channel includes a twisted pair structure.

[0065] Optionally, the delay circuit includes a series structure of inverters.

[0066] Optionally, the reference voltage is a common mode voltage, which is generated by a resistor voltage divider circuit.

[0067] Specifically, this embodiment proposes a low-speed bus coaxial power supply receiving end equalization circuit for suppressing baseline drift, which is mainly composed of three parts: a differential amplifier, a hysteresis comparator and an equalization circuit.

[0068] The function of the differential amplifier is to receive and amplify the differential signal from the POC channel. Due to the presence of DC blocking capacitors in the POC system, the channel presents a high-pass characteristic, which causes the low-frequency signal component to attenuate and cause baseline drift. While the differential amplifier amplifies the signal, it also amplifies this distortion and provides input for subsequent equalization processing.

[0069] The hysteresis comparator is used to judge the amplified differential signal. It converts the analog differential signal into the corresponding digital level according to the set threshold and outputs the judgment result. The introduction of hysteresis characteristics can avoid frequent triggering near the threshold and improve the anti-noise ability. The judgment result is used as the feedback input of the equalization circuit to form an adaptive adjustment loop.

[0070] The equalization circuit is the core of this solution, which consists of a multi-channel selection circuit, a series filter and a voltage-current conversion circuit, and is used to dynamically compensate for the baseline drift caused by the POC channel. Its working principle is as follows:

[0071] The multi-way selection circuit selectively feeds back the reference voltage or the judgment result to the equalization circuit according to the equalization start signal. When the equalization is not started, the reference voltage is selected to provide a suitable initial working point for the equalization circuit; when the equalization is started, it switches to the judgment result to form an adaptive equalization loop. The multi-way selection circuit ensures the smooth startup and normal operation of the equalization circuit.

[0072] The decision result is input into the equalization circuit after passing through the delay circuit. The purpose of the delay is to match the delay of the feedback path and maintain loop stability. The delayed decision result enters the series filter, which is composed of a high-pass filter and a low-pass filter cascaded.

[0073] The high-pass filter is used to suppress the low-frequency jitter components in the decision results. Due to the positive feedback structure used in the loop, the decision errors will continue to accumulate and cause oscillations. The high-pass filter removes these low-frequency interferences to ensure loop stability.

[0074] The low-pass filter is used to restore the damaged low-frequency components of the signal. Its cutoff frequency is higher than that of the high-pass filter, forming a bandpass characteristic. The low-pass filter compensates the low-frequency loss caused by baseline drift back into the signal path to achieve equalization.

[0075] The output of the series filter is a voltage signal, which needs to be converted into a current form, superimposed on the load of the differential amplifier, and added to the original signal to complete the equalization compensation. This conversion is completed by a voltage-to-current conversion circuit, a common one being a transconductance amplifier. The transconductance amplifier can have an adjustable source degeneration resistor for flexible adjustment of the equalization strength.

[0076] In summary, the receiving end equalization circuit uses a differential amplifier to extract the signal to be equalized, the hysteresis comparator generates judgment result feedback, the multi-way selection circuit controls the equalization start, the series filter suppresses low-frequency interference and recovers the signal, and the transconductance amplifier performs equalization compensation. Multiple links work closely together to finally achieve adaptive and accurate baseline drift suppression. This equalization scheme fully considers the characteristics of the POC system and engineering application requirements, and solves the key technical problem of baseline drift without introducing too much complexity. It has significant technical advantages and application value.

[0077] More specifically, regarding the specific implementation of the multi-path selection circuit, this embodiment uses a multiplexer as the core structure. The multiplexer can selectively transmit different input signals to the output terminal by selecting the level state of the control terminal. Specifically, when the control terminal is in a first state (such as a low level), the reference voltage path is selected; when it is in a second state (such as a high level), the decision result path after delayed processing is selected. This design provides a flexible input source switching mechanism for the equalization process.

[0078] In the design of the series filter, the high-pass filter and the low-pass filter have different functions. The high-pass filter is mainly used to suppress the low-frequency jitter components in the decision result. This is extremely important because in the actual circuit, factors such as device noise and power supply ripple will introduce low-frequency jitter in the decision result. If not suppressed, these jitters will continue to accumulate in the positive feedback loop, eventually leading to saturation of the transconductance amplifier output and completely failing the equalization function. The low-pass filter is responsible for recovering the low-frequency component of the signal, and its cutoff frequency needs to be higher than that of the high-pass filter, so that effective low-frequency information can be retained while suppressing interference.

[0079] For the specific implementation of the filter, this embodiment uses an RC filter network. This choice is based on the following considerations: the RC filter has a simple structure, stable performance, easy integration, and low cost. The high-pass filter uses a resistor and capacitor series structure, while the low-pass filter uses a parallel structure. By carefully designing the RC value, an ideal frequency response characteristic can be achieved.

[0080] In the voltage-current conversion link, this embodiment adopts an adjustable transconductance amplifier solution. The amplifier includes a differential input stage and a current output stage, and its special feature is that an adjustable degeneration resistor is introduced into the source. This design allows the transconductance value to be changed by adjusting the source degeneration resistor value, thereby achieving flexible adjustment of the equalization strength, making the circuit more adaptable.

[0081] For the selection of differential pairs, PMOS tubes are preferred in this embodiment. This is because PMOS has low noise characteristics, especially its 1 / f noise is lower than that of NMOS, which is crucial for suppressing low-frequency interference in the balancing loop. At the same time, the common-mode input range of PMOS is closer to the power supply voltage, which is conducive to the interconnection with the previous circuit.

[0082] In the physical implementation of the POC channel, this embodiment adopts a twisted pair structure. The twisted pair has excellent electromagnetic interference suppression capability through the winding design of two wires. Its stable characteristic impedance helps impedance matching, reduces transmission line reflection, and improves signal integrity. In addition, the low cost and simple wiring characteristics of the twisted pair also facilitate system integration and deployment.

[0083] For the delay circuit, this embodiment uses an inverter chain structure. By adjusting the number of cascaded inverters, the delay time can be accurately controlled. This design is not only simple in structure, but also low in power consumption and easy to integrate, which is very suitable for the application requirements of this solution.

[0084] In terms of the generation of the reference voltage, this embodiment adopts a resistor voltage division scheme. By reasonably designing the voltage division ratio, a stable reference voltage can be generated. In order to obtain good noise performance, this embodiment makes special optimization in the resistor value, while ensuring accuracy, it also takes power consumption into consideration.

[0085] The selection of these technical features has been through in-depth analysis and weighing, taking into full account the application environment and technical requirements of the low-speed POC system. While ensuring performance, it also focuses on implementation complexity and cost control. In engineering practice, these features can be flexibly selected according to specific application scenarios to optimize the overall performance of the equalization circuit.

[0086] Working principle:

[0087] The low-speed bus coaxial power supply receiving end equalization circuit of this embodiment is mainly used to solve the baseline drift problem in the POC channel. The POC channel has a high-pass characteristic due to the presence of the DC blocking capacitor, which causes the low-frequency component of the channel transmission data to be attenuated. When the data appears "continuous 0" or "continuous 1", it will cause the signal level to shift. This phenomenon is called baseline drift. Baseline drift will cause the bit eye width of the comparator output to deviate, which may cause bit errors in severe cases.

[0088] This embodiment uses an equalization architecture based on DFE1TAP to compensate for baseline drift. First, the differential amplifier receives the differential input signal from the POC channel and amplifies it. The amplified differential signal is sent to the hysteresis comparator for judgment, and the judgment result is output. The equalization circuit achieves signal compensation through the cooperation of a multi-way selection circuit, a series filter and a voltage-current conversion circuit.

[0089] During the equalization startup process, the multiplexer first selects the reference voltage (common mode voltage) to establish the initial operating point of the voltage-current conversion circuit. Once the equalization is started, the multiplexer switches to select the decision result after the delay circuit. The delay circuit is necessary to match the timing relationship of signal transmission.

[0090] The decision result enters the series filter, which is composed of a high-pass filter and a low-pass filter in series. The high-pass filter is used to suppress the low-frequency jitter in the decision result to prevent the saturation of the equalization loop; the low-pass filter is responsible for recovering the low-frequency components lost in the channel, and its cut-off frequency needs to be higher than the cut-off frequency of the high-pass filter. The two together form a bandpass characteristic. Since the equalization circuit adopts a positive feedback structure, if the low-frequency jitter is not suppressed, when the jitter is large or the hysteresis voltage of the hysteresis comparator is large, the low-frequency jitter will continue to accumulate in the loop, eventually causing the output of the voltage-current conversion circuit to completely deviate to one side, making the comparator unable to work normally.

[0091] The voltage-to-current conversion circuit is implemented using an adjustable transconductance amplifier, which includes a PMOS input differential pair and a source degeneration resistor. By adjusting the size of the source degeneration resistor, the equivalent transconductance value of the transconductance amplifier can be controlled, thereby adjusting the equalization strength. The transconductance amplifier converts the filtered voltage signal into a compensation current, adds it to the load of the differential amplifier, and adds it to the original signal to complete the compensation of the baseline drift.

[0092] Through the collaborative work of the above structures, the equalization circuit of this embodiment can effectively compensate for the baseline drift caused by the POC channel and improve the reliability of data transmission. Compared with the traditional baseline drift equalization technology, this embodiment has a higher loop gain, a more flexible circuit design, a better equalization effect, and is not affected by the capacitance of the channel DC blocking capacitor.

[0093] In order to better understand the technical solution of the present application, a specific example is provided below for illustration. The details listed in the example are mainly for ease of understanding and are not intended to limit the scope of protection of the present application.

[0094] Figure 1 The example shows the receiving end and equalization architecture of the coaxial power supply for the low-speed bus. The system uses POC (Power Over Coaxial) to transmit data and power the next-level node. Figure 2 The specific structure diagram of POC is shown. As can be seen from the structure diagram, due to the presence of DC blocking capacitors, the POC channel has a high-pass characteristic. Therefore, the low-frequency component of the data transmitted by the channel will be attenuated, resulting in a more serious baseline wander phenomenon. That is, when the data appears "continuous 0" or "continuous 1", the signal level will shift. Baseline wander will cause the eye width of the output bit of the comparator circuit to deviate, and in severe cases, even direct bit errors will occur. In order to solve this problem, a special equalization circuit is required at the receiving end to compensate for the offset signal level. The equalization circuit is essentially a frequency domain compensation for the channel with high-pass characteristics in the low-frequency area.

[0095] More specifically, the POC system uses coaxial cable to transmit data signals and DC power supply current at the same time. Although this design simplifies the system wiring and reduces costs, it also brings some technical challenges. In the POC structure, in order to isolate the DC power supply current to prevent it from interfering with the data signal, it is necessary to introduce a DC blocking capacitor in the signal transmission path. However, the presence of the DC blocking capacitor makes the POC channel exhibit obvious high-pass characteristics. Specifically, the channel will show significant attenuation of low-frequency signals, especially those with very low frequencies, such as the DC component of the signal and low-frequency components close to DC. When there are long periods of continuous 0 or continuous 1 in the transmitted data, these low-frequency components are severely lost, causing the signal baseline level to drift, which is the baseline wander phenomenon.

[0096] Baseline wander has a great impact on the data recovery circuit at the receiving end, especially the comparator circuit used for signal sampling and judgment. The threshold level of the comparator is usually fixed at the midpoint of the signal amplitude. When baseline wander occurs, the average level of the signal will deviate from this threshold level. This causes the eye width of the digital bit output by the comparator to deviate from the optimal sampling point, which reduces the signal's anti-noise tolerance. When baseline wander is serious, the signal level may even completely deviate from one side of the comparator threshold, directly leading to bit errors, seriously affecting the transmission quality and reliability of the system.

[0097] In order to overcome the problems caused by baseline wander, the receiving end of the POC system must be equipped with a special equalization circuit to dynamically compensate for the offset of the signal level. The basic principle of the equalization circuit is to compensate the channel with high-pass characteristics in the low-frequency band in the frequency domain. Specifically, a low-frequency gain that is complementary to the high-pass characteristic of the channel is applied to the signal at the receiving end to restore and emphasize the signal component that is attenuated in the low-frequency band of the channel, thereby offsetting the low-frequency loss introduced by the channel, making the signal spectrum flat again, and eliminating the baseline drift phenomenon. This can be achieved by introducing a pole-zero pair filter in the time domain, where the pole provides low-frequency gain and the zero limits high-frequency gain, and the parameters are carefully designed to match the high-pass characteristics of the channel.

[0098] In short, baseline wander is a key technical challenge in the POC system. It originates from the high-pass characteristics of the channel caused by the DC blocking capacitor, which will seriously affect the judgment performance of the data recovery circuit and reduce the system reliability. The receiving-end equalization circuit introduces compensation gain in the low-frequency band to reconstruct the low-frequency component of the signal, which is an effective way to suppress baseline wander. A properly designed equalization circuit can not only improve the transmission quality of the POC system and enhance the anti-interference ability, but also help reduce the system's sensitivity to device parameter drift and improve the system's robustness and environmental adaptability. It can be foreseen that with the continuous development and application expansion of POC technology, the receiving-end equalization circuit will become a key design link to improve system performance and play an increasingly important role in related technical fields.

[0099] Figure 3 The circuit schematic diagram of the baseline wander equalization circuit is shown. The traditional baseline wander equalization technology is greatly affected by the capacitance of the DC blocking capacitor on the channel and is not flexible enough. Therefore, we propose a baseline wander equalization circuit based on DFE1TAP: the equalization circuit of this structure has high loop gain, flexible circuit design, and better equalization effect. The specific process of its operation is as follows: the result of the hysteresis comparator is directly sent to the filter in the equalization circuit. The filter is composed of a high-pass filter and a low-pass filter in series. The high-pass filter is responsible for filtering out the low-frequency offset in the comparison result to prevent the equalization loop from saturation; the low-pass filter is responsible for recovering the low-frequency component of the channel data loss. The output of the low-pass filter is connected to the input of a transconductance amplifier. Here, the transconductance amplifier is equivalent to converting the low-frequency component of the recovered channel data from a voltage signal to a current signal, and adding it to the load of the differential amplifier, thereby realizing the addition of the equalization signal and the original signal to complete the equalization process.

[0100] More specifically, this example uses an equalization circuit topology based on the DFE1TAP structure, and uses the decision feedback mechanism to achieve adaptive equalization. Compared with traditional analog equalization schemes, this structure has the advantages of high loop gain, fast convergence speed, and strong anti-interference ability, and is more suitable for the application scenario of low-speed POC systems.

[0101] In this equalization circuit, the output result of the hysteresis comparator is used as the feedback input of the equalization loop and is directly sent to the series filter for processing. The series filter consists of a high-pass filter and a low-pass filter, which plays a vital role. The main purpose of the high-pass filter is to filter out the low-frequency offset component in the judgment result. Since the comparator circuit itself has an offset voltage, coupled with the cumulative effect of the DC offset in the loop, if these low-frequency offsets are directly fed back to the equalization loop, the equalization strength will continue to increase, eventually causing the loop to saturate, making the equalization device completely biased and losing its adjustment ability. The high-pass filter removes the low-frequency offset, which is equivalent to an anti-saturation measure, ensuring the stable operation of the equalization loop.

[0102] In conjunction with the high-pass filter, the low-pass filter is responsible for restoring the low-frequency components of the signal. Due to the high-pass characteristics of the POC channel, the DC component and low-frequency components in the signal are severely attenuated, which is reflected as baseline drift. To compensate for this low-frequency loss, the low-pass filter extracts effective low-frequency information from the judgment result of the comparator, re-adds it to the received signal, and reconstructs the low-frequency part of the signal. The cutoff frequency of the low-pass filter needs to be higher than that of the high-pass filter, which must ensure the transparency of the low-frequency signal and avoid introducing too much high-frequency noise.

[0103] The signal processed by the series filter is in voltage form and needs to be converted into current and added to the input signal of the differential amplifier to complete the equalization compensation. This conversion process is realized by the transconductance amplifier. The transconductance amplifier converts the output voltage signal of the low-pass filter into an output current signal, which is then applied to the load of the differential amplifier. Since the load of the differential amplifier is connected to the original input signal and the equalization compensation signal at the output of the differential amplifier, the original signal and the equalization signal are naturally added together at the output of the differential amplifier, eliminating the influence of baseline drift.

[0104] It is worth mentioning that an adjustable resistor is introduced into the source of the transconductance amplifier to control the transconductance value of the amplifier. The magnitude of the transconductance value directly determines the equalization strength. By adjusting the source degeneration resistor, the compensation degree of the equalization loop can be flexibly adjusted to adapt to different channel conditions and equalization requirements. This adjustable design greatly improves the flexibility and adaptability of the equalization circuit and provides convenience for optimizing system performance.

[0105] In summary, this example uses the DFE1TAP structure to extract the decision result through the hysteresis comparator, the series filter eliminates the DC offset and restores the low-frequency signal, and the transconductance amplifier performs voltage-current conversion, finally achieving adaptive and accurate baseline drift equalization. This equalization circuit gives full play to the advantages of decision feedback, and has the characteristics of high loop gain, fast convergence speed, and strong anti-interference ability. At the same time, it takes into account the engineering implementation requirements of the system. Without introducing too much complexity, it effectively solves the key technical problems of the low-speed POC system, reflecting outstanding innovation and practical value.

[0106] Figure 4 The delay unit, MUX gate and common-mode voltage circuit diagram are shown. When the circuit is not equalized, the MUX gate selects the common-mode voltage to connect to the gate of the transconductance amplifier to complete the establishment of the initial common-mode voltage and ensure that the transconductance amplifier can work normally; after the circuit is equalized, the MUX gate selects the delayed decision data to enter the filter circuit.

[0107] This circuit design embodies the adaptive startup and steady-state working mechanism of the equalizer circuit. Through the gating control of the MUX gate, the smooth establishment and normal operation of the equalizer loop are achieved.

[0108] More specifically, in the initial state of the equalization circuit, that is, when the equalization function has not yet been turned on, the input of the transconductance amplifier requires a suitable bias level to ensure that it can work normally at the target operating point. This bias level is usually selected as the common mode voltage of the system, that is, the midpoint voltage of the differential signal. The establishment of the common mode voltage can be achieved through a resistor divider network, such as Figure 4 As shown in Figure 1, two resistors with equal resistance are connected in series between the power supply and the ground, and the middle node is the common-mode voltage output terminal.

[0109] In this initial state, the control terminal of the MUX gate is at the "0" level, so the MUX gate selects the common-mode voltage and connects it to the gate input of the transconductance amplifier. In this way, a stable common-mode voltage is established at the input of the transconductance amplifier, providing suitable initial working conditions for the subsequent balancing operation. The establishment of the common-mode voltage is crucial to ensure the performance of the transconductance amplifier and the stability of the balancing loop.

[0110] Once the receiver detects that the equalization function needs to be turned on, the control end of the MUX gate switches to the "1" level. At this time, the MUX gate changes state, disconnects the common mode voltage, and selects the output signal of the delay unit, connecting it to the filter part of the equalization circuit. The delay unit here plays the role of matching the timing of the decision data and the equalization compensation signal. Due to the feedback loop in the equalization circuit, when the decision data is fed back to the input end of the equalization circuit, it needs to maintain a certain delay with the original signal to avoid signal correlation causing loop instability. The delay unit introduces appropriate delay to ensure that the timing of the decision data and the original signal is correctly aligned to meet the loop stability condition.

[0111] It is worth noting that the design of the delay unit needs to comprehensively consider the delay requirements of the balancing loop and the complexity of the circuit implementation. A common delay unit design is to use a multi-stage inverter series structure, and use the transmission delay accumulation of the inverter to obtain the required delay. The more inverter levels there are, the greater the delay introduced, but at the same time, the power consumption and area overhead will also increase accordingly. Therefore, it is necessary to balance the delay accuracy and circuit overhead and select the appropriate number of inverter levels. In addition, attention should be paid to the input and output swing matching of the delay unit to avoid damage to the signal integrity.

[0112] In general, Figure 4 The delay unit, MUX gate, and common-mode voltage circuit diagram shown in the figure reflect the timing control mechanism for the startup and steady-state operation of the equalization circuit. The MUX gate establishes the common-mode voltage in the initial stage through gating control to ensure the normal operation of the transconductance amplifier; in the equalization stage, it switches to the delayed decision data to achieve the closure and adaptive adjustment of the equalization loop. The introduction of the delay unit matches the loop timing and ensures the stability of the equalization loop. This design fully considers the actual working requirements of the equalization circuit, reasonably arranges the startup timing and signal interaction of the circuit, helps to optimize the performance of the equalization circuit and improve the reliability, and reflects a high level of design.

[0113] Figure 5 The circuit diagram of the filter is shown. It mainly consists of C 1 and R 1 The high-pass filter and C 2 and R 2The low-pass filter composed of is connected in series. Since the feedback loop of the baseline wander equalization circuit is a positive feedback, the low-frequency jitter in the judgment data will accumulate in the loop. When the jitter is large or the hysteresis voltage of the hysteresis comparator is large, the low-frequency jitter will continue to accumulate, and eventually the differential output current of the transconductance amplifier will be completely biased to one side, causing the comparator to fail to work. Therefore, the high-pass filter will filter out the low-frequency jitter to protect the normal operation of the loop. The pole of the low-pass filter needs to be set higher than the high-pass filter, and the two form a bandpass filter. The low-pass filter is responsible for recovering the low-frequency signal lost by the channel signal and adding it to the gate of the transconductance amplifier, controlling the output current of the transconductance amplifier to the load of the differential amplifier.

[0114] More specifically, the high-pass filter is composed of a capacitor C1 and a resistor R1 in parallel, and its purpose is to filter out the low-frequency jitter component in the decision data. In actual circuits, due to the influence of factors such as device noise and power supply ripple, the decision data usually contains a certain amount of low-frequency jitter. If these low-frequency jitters are directly fed back to the balancing loop, errors will continue to accumulate, resulting in loop instability. In particular, since the balancing circuit adopts a positive feedback structure, the low-frequency jitter cannot be effectively attenuated, but will continue to amplify, eventually causing the transconductance amplifier to completely lose balance, and its differential output current is completely biased to one side, losing its linear regulation ability. In this out-of-control state, the balancing loop completely fails, and the comparator cannot work properly. The high-pass filter cuts off the path of error accumulation by filtering out the low-frequency jitter component, which is equivalent to introducing anti-saturation measures for the loop, thereby protecting the loop from out-of-control and maintaining stable operation.

[0115] In conjunction with the high-pass filter, the low-pass filter is composed of a resistor R2 and a capacitor C2 in series, which is used to recover the lost low-frequency components in the channel signal. Due to the high-pass characteristics of the channel, the low-frequency components of the signal are significantly attenuated after transmission, especially the loss of the DC component, which will cause the signal baseline to drift. In order to compensate for this low-frequency loss, it is an important task of the equalization circuit to reconstruct the low-frequency components from the channel output signal. The low-pass filter extracts the low-frequency information from the decision data by low-pass filtering, feeds it to the input of the transconductance amplifier, modulates the output current of the transconductance amplifier, and then superimposes it on the load of the differential amplifier to compensate for the low-frequency loss of the channel. Here, the pole frequency of the low-pass filter needs to be higher than the pole frequency of the high-pass filter to avoid filtering out the required low-frequency signal components.

[0116] The series connection of high-pass filter and low-pass filter constitutes a band-pass filter. This series structure can well balance the needs of suppressing low-frequency jitter and restoring low-frequency signals. The low-frequency cutoff point of the band-pass filter is determined by the pole of the high-pass filter, and its main purpose is to suppress low-frequency jitter; the high-frequency cutoff point of the band-pass filter is determined by the pole of the low-pass filter, and its purpose is to retain the required low-frequency compensation signal. By reasonably setting the pole frequency of the high-pass filter and the low-pass filter, a balance can be achieved between preventing loop loss of control and optimizing equalization performance, which not only eliminates low-frequency interference but also restores the low-frequency components of the signal to the maximum extent.

[0117] In summary, the reasonable design of the filter circuit is crucial to achieve high-performance baseline drift equalization. The series connection of the high-pass filter and the low-pass filter constitutes the key link in the equalization loop, which plays the role of suppressing low-frequency jitter and recovering low-frequency signals respectively. This filter structure is simple and easy to implement. The target bandwidth can be flexibly set by adjusting the resistance and capacitance parameters, and it is well adapted to the actual needs of the POC system. At the same time, careful optimization of the performance indicators of the filter is conducive to improving the stability and dynamic response of the equalization loop, which is of great significance to improving the system's anti-interference ability and transmission quality. It can be seen that the design of the filter circuit fully reflects the essence of equalization technology and is the key to achieving high-reliability and low bit error rate data transmission.

[0118] Figure 6 The circuit diagram of the transconductance amplifier is shown. The transconductance amplifier uses a PMOS input pair tube, and a source degeneration resistor is added to the source of the PMOS pair tube. Adjusting the size of the resistor can control the equivalent transconductance of the transconductance amplifier, thereby achieving a better balancing effect. After receiving the output from the filter, the transconductance amplifier starts to output current to the load of the differential amplifier, completing the addition of the compensation signal and the original signal.

[0119] More specifically, the transconductance amplifier uses a PMOS tube as the input stage to form a differential pair with a shared source. Compared with the NMOS tube, the PMOS tube has lower flicker noise and better matching characteristics, and is more suitable as the input device of the transconductance amplifier. An adjustable resistor, called the source degeneration resistor, is introduced at the source of the two PMOS tubes. The function of this resistor is to adjust the equivalent transconductance value of the transconductance amplifier, thereby controlling the compensation strength of the balancing loop.

[0120] The introduction of source degeneration resistance is based on the principle of negative feedback. By introducing series negative feedback at the input stage, the transconductance value of the transconductance amplifier can be reduced and its linearity can be improved. Specifically, the source degeneration resistance is equivalent to introducing a feedback resistor at the source of the PMOS tube. As the input signal changes, a voltage drop in the same direction as the input signal will be generated across the resistor, which will produce a negative feedback effect on the input signal, thereby suppressing the change of the transconductance value. The larger the source degeneration resistance, the stronger the negative feedback, the more obvious the reduction in transconductance value, and the weaker the equalization strength; conversely, the smaller the source degeneration resistance, the weaker the negative feedback, the closer the transconductance value is to the intrinsic transconductance of the PMOS tube, and the stronger the equalization strength.

[0121] By introducing an adjustable source degeneration resistor in the transconductance amplifier, the compensation strength of the equalization loop can be easily controlled to adapt it to different channel conditions and equalization requirements. In practical applications, the resistance value of the source degeneration resistor can be optimized and the equalization strength can be adjusted according to the specific indicators of the system, such as the degree of channel damage and the target bit error rate, to achieve the best equalization effect. This adjustable design provides an effective way to optimize the performance of the system and greatly improves the flexibility and adaptability of the equalization circuit.

[0122] The output stage of the transconductance amplifier adopts a current source structure, and the current signal obtained by transconductance transformation is directly fed to the load of the differential amplifier. Since the load of the differential amplifier is connected to both the original signal and the balanced compensation signal, the compensation signal and the original signal are naturally superimposed at the output of the differential amplifier, thereby compensating for the low-frequency damage introduced by the channel and suppressing the baseline drift phenomenon. This current domain superposition method is simple and efficient, eliminating the need for additional signal addition circuits and reducing system complexity.

[0123] In general, the reasonable design of the transconductance amplifier circuit is the key to achieving high-quality baseline drift equalization. The use of PMOS input stage, source degeneration structure, and the introduction of adjustable transconductance not only provide flexible equalization strength adjustment capabilities, but also take into account noise suppression and linearity improvement, which is well adapted to the actual needs of low-speed POC systems. At the same time, the current-type output stage realizes the seamless superposition of the compensation signal and the original signal, and the circuit is simple and efficient. It can be seen that the transconductance amplifier circuit fully embodies the essence of equalization technology and plays an indispensable role in optimizing system performance and improving transmission reliability. A well-designed transconductance amplifier can maximize the potential of the equalization algorithm and is an important guarantee for achieving robust and efficient channel equalization.

[0124] In practical applications, the parameter selection of each circuit module plays a key role in system performance. For series filters, the cutoff frequency of the high-pass filter is usually set at 10-100kHz, and the cutoff frequency of the low-pass filter is selected at 200-1000kHz to effectively suppress low-frequency jitter while retaining the necessary low-frequency signal components. In the filter, the typical values ​​of capacitors C1 and C2 are 0.5-4pF, and the range of resistors R1 and R2 is 10-500kΩ. The specific values ​​need to be optimized according to the channel characteristics.

[0125] The design parameters of the transconductance amplifier also need to accurately match the system requirements. In low-speed POC systems, the transconductance value is generally in the range of 0.1-0.3mS, and the typical value of the source degeneration resistance is 3-8kΩ to provide sufficient balance strength while maintaining good linearity.

[0126] The delay design of the delay unit needs to match the data rate of the low-speed bus. For a data transmission rate of 10-50Mbps, the delay time should be controlled between 4-10ns, which can be achieved by connecting 2-8 inverters in series, with the delay of each inverter being about 1-2ns.

[0127] The selection of the above parameters needs to be optimized according to the specific application scenario and system requirements, and the influence of factors such as process deviation and temperature change needs to be considered, so as to reserve appropriate margins for key indicators. In addition, there is a mutual constraint relationship between these parameters, and their rationality needs to be verified through simulation analysis to ensure that the overall performance of the system reaches the optimal level.

[0128] It should be noted that, in the application documents of the present application, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or equipment. In the absence of more restrictions, the elements defined by the sentence "include one" do not exclude the existence of other identical elements in the process, method, article or equipment including the elements. In the application documents of the present application, if it is mentioned that a certain action is performed according to a certain element, it means that at least the action is performed according to the element, which includes two situations: performing the action only according to the element and performing the action according to the element and other elements. Expressions such as multiple, multiple, multiple, etc. include 2, 2 times, 2 kinds and more than 2, more than 2 times, more than 2 kinds.

[0129] All documents mentioned in this application are considered to be included in the disclosure of this application as a whole, so that they can be used as the basis for modification when necessary. In addition, it should be understood that after reading the above disclosure of this application, those skilled in the art can make various changes or modifications to this application, and these equivalent forms also fall within the scope of protection claimed in this application.

Claims

1. A low-speed bus coaxial power supply receiving end equalization circuit for suppressing baseline drift, characterized in that: include: A differential amplifier, whose differential input terminal is used to receive a differential signal input by a POC channel having a high-pass characteristic, and whose differential output terminal generates an amplified differential signal; A hysteresis comparator, whose input end is connected to the output end of the differential amplifier, is used to judge the amplified differential signal and output the judgment result; An equalization circuit, for compensating for baseline drift caused by the POC channel, comprising: a multiplexer circuit, wherein a first input terminal thereof is connected to a reference voltage, and a second input terminal thereof is connected to an output terminal of the hysteresis comparator via a delay circuit; A series filter, whose input end is connected to the output end of the multi-way selection circuit, comprises a high-pass filter and a low-pass filter connected in series, wherein the cut-off frequency of the low-pass filter is higher than the cut-off frequency of the high-pass filter; A voltage-to-current conversion circuit, whose input end is connected to the output end of the series filter and whose output end is connected to the load end of the differential amplifier, and is used for converting the output voltage of the series filter into a compensation current; The multiplexer circuit selects the reference voltage when equalization is not started, and selects the decision result delayed by the delay circuit after equalization is started.

2. The equalization circuit according to claim 1, characterized in that: The multi-path selection circuit is a multiplexer having a gate control terminal. When the level of the gate control terminal is in a first state, the reference voltage is gated; when the level of the gate control terminal is in a second state, the decision result delayed by the delay circuit is gated.

3. The equalization circuit according to claim 1, characterized in that: The high-pass filter is used to suppress low-frequency jitter in the decision result to prevent saturation of the equalization loop, and the low-pass filter is used to restore the lost low-frequency component in the differential signal.

4. The equalizing circuit according to claim 3, characterized in that: The high-pass filter and the low-pass filter are both RC filters.

5. The equalizing circuit according to claim 1, characterized in that: The voltage-current conversion circuit is an adjustable transconductance amplifier, including a differential pair and a source degeneration resistor. The source degeneration resistor is connected to the source of the differential pair and is used to adjust the transconductance value to control the equalization strength.

6. The equalizing circuit according to claim 5, characterized in that: The differential pair is a PMOS differential pair.

7. The equalizing circuit according to claim 1, characterized in that: The POC channel includes a twisted pair structure.

8. The equalization circuit according to claim 1, characterized in that: The delay circuit includes a series structure of inverters.

9. The equalizing circuit according to claim 1, characterized in that: The reference voltage is a common mode voltage, which is generated by a resistor voltage divider circuit.

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