A 5G Synchronization Device Air Interface Synchronization Method and Apparatus

Abstract

The present invention relates to the field of communication technologies, and discloses a radio air interface synchronization method and device for a 5G synchronization device, including the following steps: S1, configure an analog-to-digital converter and load frequency point fast lock files of a plurality of synchronization signal blocks to support the capture of synchronization signal blocks; S2, configure synchronization parameters, including a synchronization mode and a duplex mode; S3, start a synchronization process and activate a synchronization algorithm module; S4, search for synchronization signal blocks and extract a first synchronization signal index and a second synchronization signal index; S5, decode a physical broadcast channel signal, extract frame synchronization information and verify the validity of the signal; S6, adjust the system time according to the frame synchronization information; S7, perform periodic synchronization; S8, when the synchronization error exceeds a preset threshold, quickly restart the initial synchronization process. Through the fast lock mode of the analog-to-digital converter and the dynamic frequency offset compensation mechanism, it is possible to quickly complete the search and capture of synchronization signals in a high-speed moving scenario and a multi-band complex environment.

Description

Technical Field

[0001] The present invention relates to the field of communication technologies, and particularly to an air interface synchronization method and device for a 5G synchronization device. Background Art

[0002] The 5G network is the fifth-generation mobile communication network. With the increasing number of 5G users year by year, it is urgent to develop synchronization devices suitable for the 5G standard to provide users with accurate time-frequency synchronization functions. Currently, 5G synchronization devices need to maintain high-precision time-frequency synchronization with base station transceivers. The mainstream synchronization methods include two technologies: GPS synchronization and air interface synchronization.

[0003] Although GPS synchronization has high precision, it cannot be used in indoor environments, and at the same time, the cost of GPS receivers is relatively high, which limits its application scenarios in portable synchronization devices. In contrast, air interface synchronization has the advantages of low cost and suitability for indoor and outdoor scenarios, so it has become the main synchronization technology for 5G synchronization devices. However, traditional air interface synchronization methods also have many deficiencies. Existing methods achieve time-frequency synchronization by a 5G synchronization device tracking the cell PCI (Physical Cell Identities) of a base station transceiver. This method performs well in areas with strong signal coverage and good field strength. However, when the device enters an area with poor field strength or signal coverage, it is prone to lose synchronization, resulting in the device being unable to maintain synchronization with the base station. In addition, to adapt to scenarios with insufficient signal coverage, 5G synchronization devices can also adopt the method of blind search of the full-frequency band GSCN (Global Synchronization Channel Number). However, due to the very large number of GSCNs, this method will lead to too long synchronization delay in cell search, making it difficult to meet the actual fast synchronization requirements.

[0004] In addition, traditional air interface synchronization methods usually rely on the peaks of the PSS and SSS signals in the SSB (Synchronization Signal / PBCH) signal to determine time-frequency information. However, this single peak search method has a high dependence on air interface signals and is easily affected by air interface signal interference or noise, resulting in frame header misjudgment problems, which in turn lead to synchronization failures and cannot meet the requirements of high-reliability synchronization in 5G networks. Summary of the Invention

[0005] Aiming at the deficiencies of the prior art, the present invention provides an air interface synchronization method and device for a 5G synchronization device, which solves the problems of out-of-step in areas with poor field strength, large synchronization delay caused by full-frequency band blind search, and poor frame synchronization reliability of existing 5G synchronization devices.

[0006] To achieve the above object, the present invention is realized through the following technical solutions: A radio interface synchronization method for a 5G synchronization device, comprising the following steps:

[0007] S1. Configure an analog-to-digital converter and load the frequency point fast lock files of several synchronization signal blocks to support the capture of synchronization signal blocks;

[0008] S2. Configure synchronization parameters, including synchronization mode and duplex mode;

[0009] S3. Start the synchronization process and activate the synchronization algorithm module;

[0010] S4. Search for synchronization signal blocks and extract the first synchronization signal index and the second synchronization signal index;

[0011] S5. Decode the physical broadcast channel signal, extract the frame synchronization information and verify the signal validity;

[0012] S6. Adjust the system time according to the frame synchronization information;

[0013] S7. Perform periodic synchronization;

[0014] S8. When the synchronization error exceeds the preset threshold, quickly restart the initial synchronization process.

[0015] Preferably, the synchronization signal blocks in step S4 include a first synchronization signal and a second synchronization signal, which are respectively used to determine the time offset and the physical cell identifier.

[0016] Preferably, in step S4, searching for synchronization signal blocks includes the following steps:

[0017] Receive the radio interface signal through the analog-to-digital converter, perform a correlation operation with the locally generated first synchronization signal code, and extract the first synchronization signal index;

[0018] Based on the time offset of the first synchronization signal, extract the index of the second synchronization signal;

[0019] Calculate the physical cell identifier according to the first synchronization signal index and the second synchronization signal index.

[0020] Preferably, the physical cell identifier is calculated and determined based on the following parameters:

[0021] The first synchronization signal index, whose value range is from 0 to 335;

[0022] The second synchronization signal index, whose value range is from 0 to 2;

[0023] The first synchronization signal index and the second synchronization signal index jointly determine a unique physical cell identifier.

[0024] Preferably, in step S5, decoding the physical broadcast channel signal includes the following steps:

[0025] Calculating a channel estimation value based on a demodulation reference symbol;

[0026] Using the channel estimation value to perform equalization processing on the received physical broadcast channel signal;

[0027] Demodulating the signal and performing descrambling, rate matching, and verification to extract the system frame number and half-frame indicator.

[0028] Preferably, the time adjustment in step S6 includes:

[0029] Adjusting the system time according to the frame synchronization information obtained by decoding the physical broadcast channel;

[0030] When the time adjustment deviation exceeds a threshold, quickly restart the synchronization process.

[0031] Preferably, the periodic synchronization in step S7 includes the following steps:

[0032] Periodically calculating the time-frequency error of the current system;

[0033] Based on the time-frequency error, adjusting the output frequency of the voltage-controlled crystal oscillator;

[0034] When the time-frequency error exceeds a preset threshold for multiple consecutive times, determine that the synchronization is lost and restart the synchronization process.

[0035] Preferably, the channel estimation value is calculated by the ratio of the received signal to the reference symbol, and the received signal is equalized based on the channel estimation value.

[0036] Preferably, in step S1, the analog-to-digital converter loads the frequency point configuration files of multiple synchronization signal blocks in fast lock mode to speed up the capture process of the synchronization signal blocks.

[0037] A radio air interface synchronization device for a 5G synchronization device, comprising:

[0038] An analog-to-digital converter, configured to receive a radio air interface signal and load the frequency points of multiple synchronization signal blocks in fast lock mode;

[0039] An FPGA, configured to implement the search for synchronization signal blocks, decoding of physical broadcast channels, and periodic synchronization;

[0040] A voltage-controlled crystal oscillator, configured to adjust the output frequency according to the synchronization signal;

[0041] A CPU, configured to configure the analog-to-digital converter, synchronization parameters, and control the synchronization process.

[0042] The present invention provides a method and device for air interface synchronization of 5G synchronization equipment. It has the following beneficial effects:

[0043] 1. Through the fast lock mode of the analog-to-digital converter and the dynamic frequency offset compensation mechanism, the equipment of the present invention can maintain efficient synchronization ability in high-speed moving scenarios. Fast signal capture and frequency point locking reduce the initial synchronization time. Even in a complex multi-band environment, it can quickly complete the search and capture of synchronization signals. The efficient correlation algorithm of the FPGA further shortens the signal processing time, ensuring that the equipment can quickly synchronize to the base station signal and adapt to the time-frequency change requirements in the high-speed moving scenario of the equipment.

[0044] 2. Through flexible synchronization parameter configuration and support for multiple synchronization modes, the adaptability of the equipment in different scenarios is enhanced. The combination of the PCI tracking mode and the SSB frequency point tracking mode enables the equipment to dynamically adjust the synchronization strategy according to the signal strength, ensuring the efficiency and flexibility of the synchronization process. The dynamic switching of the duplex mode further improves the compatibility of the equipment with different communication protocols and network environments.

[0045] 3. Through the frequency point fast lock mechanism, the parallel computing ability of the FPGA, and the frequency point priority strategy, the fast switching performance of the equipment is significantly improved. The frequency point fast lock mechanism can quickly respond to the change of the frequency point, ensuring the efficiency during the signal switching process; the high parallel processing ability of the FPGA guarantees the fast search and re-capture of the synchronization signal during the switching process.

[0046] 4. Through technical means such as multi-layer error detection and correction mechanism, CRC check, comprehensive error judgment, and multipath correction, the present invention ensures that the correctness of the equipment's frame header synchronization reaches 100%. Through the cross-verification of the synchronization signal by the FPGA, the decoding and verification of the PBCH signal, and the comprehensive evaluation of the dynamic synchronization error, the equipment can effectively avoid the impact of incorrect synchronization on the system performance. The mechanism of quickly restarting the initial synchronization process significantly improves the fault tolerance ability and ensures the long-term synchronization stability of the equipment in complex scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a schematic diagram of the method flow of the present invention;

[0048] Figure 2 It is a schematic diagram of the device architecture of the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0049] The technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0050] Please refer to the attached Figure 1 - attached Figure 2 , the embodiment of the present invention provides a method for air interface synchronization of a 5G synchronization device, including the following steps:

[0051] S1. Configure an analog-to-digital converter, and load the frequency point fast-lock files of several synchronization signal blocks to support the capture of synchronization signal blocks; the analog-to-digital converter loads the frequency point configuration files of multiple synchronization signal blocks through the fast-lock mode to speed up the capture process of synchronization signal blocks.

[0052] Specifically, in this embodiment, the configuration steps of the analog-to-digital converter include the following technical contents:

[0053] Generally, the analog-to-digital converter is configured in a zero intermediate frequency reception mode to receive air interface signals and digitize them. By loading the frequency point fast-lock files of several synchronization signal blocks, the analog-to-digital converter can significantly shorten the signal capture time and reduce the initial synchronization delay. The fast-lock file includes a pre-configured frequency point parameter table, which is set according to the specific frequency band allocation of the 5G network. As an option, the frequency point fast-lock file can cover the center frequencies of multiple candidate synchronization signal blocks to ensure that the synchronization device can quickly locate signals in different scenarios.

[0054] Specifically, the analog-to-digital converter first receives the analog signal from the air interface and converts it into a digital signal. In a possible implementation, these digital signals can be further processed by a filter to remove irrelevant interference signals. The signals received by the analog-to-digital converter are divided into multiple data blocks in the time domain, and each data block corresponds to a time window.

[0055] In the implementation of the present invention, the configuration steps of the analog-to-digital converter further include loading multiple groups of locally generated synchronization signal reference codes for it. The reference codes include 3 groups of candidate codes for the first synchronization signal (PSS) and 336 groups of candidate codes for the second synchronization signal (SSS). These reference codes are stored in the memory of the analog-to-digital converter for subsequent correlation calculation. As an option, these reference codes can be written into the storage module of the analog-to-digital converter in a pre-loaded manner, or dynamically loaded from a control module (such as a CPU).

[0056] In the extended implementation of the present invention, more parameter supports can be added to the configuration of the analog-to-digital converter:

[0057] As an option, the analog-to-digital converter can dynamically adjust the sampling rate according to specific scenarios to match the requirements of different signal bandwidths. Generally, the 5G signal bandwidth ranges from 20MHz to 100MHz, and the sampling rate of the analog-to-digital converter needs to be dynamically switched according to the bandwidth to ensure signal integrity.

[0058] In another possible implementation, the fast lock mode of the analog-to-digital converter can support multi-threaded operations, so as to load multiple sets of fast lock files for frequency points simultaneously to adapt to complex network environments.

[0059] S2. Configure synchronization parameters, including synchronization mode and duplex mode;

[0060] Specifically, after the analog-to-digital converter completes the capture of the synchronization signal block, it is necessary to configure the parameters of the synchronization device immediately to support the smooth progress of subsequent synchronization processes. The configuration of synchronization parameters involves the selection of the operating mode and synchronization method of the device, and this process plays a key role in the correct capture, tracking, and decoding of signals. The configured synchronization parameters not only include the basic duplex mode but also cover specific synchronization search modes. The purpose is to dynamically adjust the synchronization strategy according to the scenario where the device is located (such as indoor or outdoor, strong signal or weak signal environment) and the target requirements.

[0061] Specifically, the configuration of the synchronization mode includes the cell PCI tracking mode and the synchronization signal block (SSB) frequency point tracking mode. In the cell PCI tracking mode, the device achieves synchronization by capturing the physical cell identifier (PCI). This mode is suitable for scenarios with strong signal coverage and stable networks. In the synchronization signal block frequency point tracking mode, the device synchronizes by tracking the SSB frequency point, which is suitable for scenarios with weak or dynamically changing signal coverage.

[0062] In the technical implementation of the present invention, the synchronization signal block frequency point tracking mode depends on the signal eigenvalue captured by the ADC.

[0063] Specifically, the core of the frequency point tracking mode is to quickly lock the SSB frequency point. The selection of the frequency point can be determined by the following formula:

[0064] ;

[0065] Where: Target synchronization frequency point; Center frequency point in the frequency point fast lock file; Frequency offset value adjusted by the device according to the real-time signal.

[0066] Generally, is calculated based on the carrier offset of the received signal and is determined by the following formula:

[0067] ;

[0068] Wherein: Phase difference between adjacent sampling points; Sampling interval time.

[0069] Through the above frequency point calculation, the device can dynamically adjust the target synchronization frequency point, so as to adapt to the influence of frequency drift and Doppler effect.

[0070] S3. Start the synchronization process and activate the synchronization algorithm module;

[0071] Specifically, this step enables the system to enter the working state by activating the core synchronization algorithm module, and starts to execute the search for synchronization signals, correlation calculation, and extraction of synchronization identifiers. Starting the synchronization process is an organic combination of the signal capture result and parameter configuration, and its success or failure is directly related to the accuracy of subsequent decoding and timing adjustment.

[0072] To start the synchronization process, after completing the signal capture of the analog-to-digital converter and the initialization of synchronization parameters, the synchronization algorithm module is activated through a synchronization control signal. In one possible implementation, the CPU sends a start signal to the FPGA, and the synchronization algorithm module in the FPGA starts to parse and process the captured air interface signals.

[0073] Specifically, the first step in starting the synchronization process is to transfer the signal feature values stored in the analog-to-digital converter to the synchronization algorithm module. These signal feature values include the correlation result of the first synchronization signal (PSS), the frequency domain information of the second synchronization signal (SSS), and the center frequency point parameters defined in the frequency point fast lock file. In one implementation, these signal feature values are transferred to the FPGA in the form of a data stream through a high-speed bus.

[0074] When the synchronization process is started, the synchronization algorithm module in the FPGA will perform a maximum value search on the correlation result of the first synchronization signal to determine the index of the first synchronization signal. The specific formula for the maximum value search algorithm is as follows:

[0075] ;

[0076] Wherein: Index of the first synchronization signal; The Correlation result of the first synchronization signal in the

[0077] After completing the processing of the first synchronization signal, the next step in starting the synchronization process is to extract the index of the second synchronization signal using the frequency domain signal feature values. The FPGA performs a group-by-group correlation calculation on the FFT result of the synchronization signal block (SSB) and 336 groups of locally generated second synchronization signal codes to determine the index corresponding to the maximum correlation peak. The specific formula is as follows:

[0078] ;

[0079] Wherein: : Index of the second synchronization signal; : Frequency-domain sampling result of the synchronization signal block; : The th group of second synchronization signal codes generated locally.

[0080] As an option, the FPGA can store all correlation results in built-in registers for subsequent signal verification and comparison.

[0081] S4. Search for the synchronization signal block and extract the first synchronization signal index and the second synchronization signal index; the synchronization signal block in step S4 includes the first synchronization signal and the second synchronization signal, which are respectively used to determine the time offset and the physical cell identifier.

[0082] Searching for the synchronization signal block includes the following steps:

[0083] Receive the air interface signal through the analog-to-digital converter, perform correlation operation with the first synchronization signal code generated locally, and extract the first synchronization signal index;

[0084] Based on the time offset of the first synchronization signal, extract the index of the second synchronization signal;

[0085] Calculate the physical cell identifier according to the first synchronization signal index and the second synchronization signal index.

[0086] The physical cell identifier is calculated and determined based on the following parameters:

[0087] The first synchronization signal index, whose value range is from 0 to 335;

[0088] The second synchronization signal index, whose value range is from 0 to 2;

[0089] The first synchronization signal index and the second synchronization signal index jointly determine a unique physical cell identifier.

[0090] Specifically, after the start of the synchronization process is completed, the system needs to search for the synchronization signal block to extract the key synchronization signal characteristic values. The purpose of this step is to determine the physical cell identifier (PCI) and the time offset of the signal through the processing of the first synchronization signal (PSS) and the second synchronization signal (SSS), so as to provide accurate input for subsequent signal decoding and time adjustment.

[0091] Under normal circumstances, the search for synchronization signal blocks first processes the primary synchronization signal (PSS). The time-domain signal received by the analog-to-digital converter will be input into the synchronization algorithm module and subjected to a group-by-group correlation operation with the locally generated PSS code to determine the index of the primary synchronization signal. The core formula for the correlation operation is as follows:

[0092] ;

[0093] where: : The th time-domain signal sample received by the analog-to-digital converter; : The th group of locally generated PSS codes; : complex conjugate of; Total number of signal sampling points.

[0094] As an option, when the system detects multiple peaks in the correlation results of the three groups of PSS codes, a maximum peak selection strategy can be adopted, that is, the index of the primary synchronization signal is determined by the following formula:

[0095] ;

[0096] where: Index of the primary synchronization signal (PSS).

[0097] Specifically, the processing result of the primary synchronization signal directly affects the search for the secondary synchronization signal (SSS). In one possible implementation, after the PSS index extraction is completed, the system extracts the synchronization signal block (SSB) adjacent to the PSS from the data buffer of the analog-to-digital converter and performs a fast Fourier transform (FFT) on it.

[0098] The frequency-domain data of the SSB is then subjected to a group-by-group correlation operation with 336 groups of locally generated SSS codes. The core formula is as follows:

[0099] ;

[0100] where: : The th frequency-domain signal sampling point of the SSB; : The th group of locally generated SSS codes; : complex conjugate of; Number of frequency-domain sampling points.

[0101] Through the above formula, the system can calculate the correlation of 336 groups of SSS codes and select the index with the largest correlation result according to the following formula:

[0102] ;

[0103] Wherein: The index of the second synchronization signal (SSS).

[0104] ;

[0105] Here, and correspond to the index ranges of the second synchronization signal and the first synchronization signal respectively, ensuring the legality and correctness of the index values.

[0106] After completing the extraction of the indexes of the PSS and SSS, the system calculates the physical cell identifier (PCI) according to the following formula:

[0107] ;

[0108] Wherein: Physical cell identifier; The index of the second synchronization signal; The index of the first synchronization signal.

[0109] As an option, after the calculation of the PCl is completed, the system stores it in a dedicated register of the FPGA for subsequent signal verification modules to call.

[0110] S5. Decode the physical broadcast channel signal, extract the frame synchronization information and verify the signal validity; Decoding the physical broadcast channel signal includes the following steps:

[0111] Calculate the channel estimation value based on the demodulation reference symbol;

[0112] Use the channel estimation value to equalize the received physical broadcast channel signal;

[0113] Demodulate the signal and perform descrambling, rate matching and verification, and extract the system frame number and half-frame indicator. The channel estimation value is calculated by the ratio of the received signal to the reference symbol, and the received signal is equalized based on the channel estimation value.

[0114] Specifically, after completing the search for the synchronization signal block and the calculation of the physical cell identifier (PCI), the system needs to decode the physical broadcast channel (PBCH) signal. The main purpose of this step is to extract the system frame synchronization information by decoding the PBCH signal and verify the signal validity. The PBCH signal contains key information between the synchronization device and the base station, such as the system frame number (SFN) and half-frame indicator, etc.

[0115] Generally, the decoding of the PBCH signal is divided into three main steps, namely channel estimation, equalization processing, and frame synchronization and verification. Each step utilizes the synchronization signal eigenvalue extracted in the previous step.

[0116] Specifically, after receiving the physical broadcast channel signal, the device needs to first perform channel estimation.

[0117] After completing channel estimation, the device needs to perform equalization processing on the PBCH signal. After completing equalization processing, the device enters the frame synchronization and verification stage. In this stage, the equalized PBCH signal is descrambled and decoded to extract the system frame number (SFN) and the half-frame indicator. The descrambled signal will be rate-matched and decoded to extract the system frame number (SFN) and the half-frame indicator. After decoding is completed, the system performs cyclic redundancy check (CRC) on the check code of the PBCH signal to verify the validity of the decoding result.

[0118] S6. Adjust the system time according to the frame synchronization information; the time adjustment includes:

[0119] Adjust the system time according to the frame synchronization information obtained by decoding the physical broadcast channel;

[0120] When the time adjustment deviation exceeds the threshold, quickly restart the synchronization process.

[0121] Specifically, after completing the decoding of the physical broadcast channel (PBCH) signal and extracting the system frame synchronization information, it is necessary to adjust the system time of the device. The adjustment of the system time is based on the frame synchronization information and combines the time offset parameter to achieve complete alignment with the base station timing.

[0122] Generally, after the device extracts the frame synchronization information, it will correct the local system time according to this information. The frame synchronization information includes the system frame number (SFN) and the time offset, and these information are extracted by the PBCH decoding module and have high time accuracy. As an option, the implementation of time adjustment can include two stages: coarse synchronization adjustment and fine synchronization adjustment.

[0123] After completing the coarse synchronization adjustment, the system needs to further perform fine synchronization adjustment. After completing the time adjustment, the accuracy of the time correction can be detected through a cross-verification mechanism. For example, when the residual between the local time and the base station time exceeds the preset threshold, the system will trigger the frame synchronization process again.

[0124] S7. Perform periodic synchronization; the periodic synchronization includes the following steps:

[0125] Periodically calculate the time-frequency error of the current system;

[0126] Adjust the output frequency of the voltage-controlled crystal oscillator based on the time-frequency error;

[0127] When the time-frequency error exceeds the preset threshold continuously for multiple times, it is determined that the synchronization is lost and the synchronization process is restarted.

[0128] Specifically, after the initial adjustment of the system time, in order to ensure that the time-frequency reference of the device remains consistent with the base station in the long term, a periodic synchronization mechanism needs to be introduced. Periodic synchronization is a dynamic adjustment process, and its core lies in regularly detecting the time-frequency error of the device and real-time correcting the output frequency of the voltage-controlled crystal oscillator (VCXO), so as to ensure the synchronization stability of the device during long-term operation.

[0129] Generally, periodic synchronization requires continuous monitoring of the time error and frequency error between the device and the base station. The calculation of the time error is based on the system time of the device and combines the phase offset of the synchronization signal to obtain the time deviation parameter. . As an option, the time error can be calculated by the following formula:

[0130] ;

[0131] Where: The current time error; : The base station time extracted from the synchronization signal; The local system time of the device.

[0132] Specifically, the calculation of the frequency error is based on the phase change of the received signal. The device can calculate the frequency error using the following formula:

[0133] ;

[0134] Where: The frequency error; The phase difference between adjacent sampling points; The sampling time interval. The calculation results of the above time and frequency errors will be used as inputs for further adjusting the output frequency of the voltage-controlled crystal oscillator (VCXO).

[0135] In some embodiments, periodic synchronization needs to verify the results of time and frequency adjustments. If synchronization failure is detected, the system will re-trigger the initial synchronization process.

[0136] S8. When the synchronization error exceeds the preset threshold, quickly restart the initial synchronization process.

[0137] Specifically, after the dynamic adjustment of the periodic synchronization (step S7) is completed, the device can usually maintain time-frequency synchronization with the base station. However, in a complex wireless communication environment, such as in the presence of strong interference, multipath effects, or signal loss, synchronization errors may accumulate and exceed the allowable range. To ensure the reliable synchronization state of the system, when the detected synchronization error exceeds the preset threshold, the device needs to quickly restart the initial synchronization process and execute steps such as signal acquisition, synchronization signal search, and system time adjustment from the beginning.

[0138] In this embodiment, the specific content of quickly restarting the initial synchronization process includes the following technical steps:

[0139] Generally, the detection of synchronization errors is based on the time error and frequency error calculated in the periodic synchronization phase. The device will monitor these error values in real time and determine whether they exceed the preset threshold range. As an option, the comprehensive judgment of synchronization errors can be completed through the following formula:

[0140] ;

[0141] where: Comprehensive synchronization error; : Time error; Frequency error. When the system determines that the current synchronization state fails and triggers the synchronization restart process. Here, is the preset threshold of the comprehensive synchronization error, and the specific value can be configured according to different application scenarios.

[0142] In a possible implementation, after detecting the synchronization failure, the device will first deactivate the periodic synchronization mechanism and clear the temporary data related to synchronization. For example, the cached data in the analog-to-digital converter, the correlation calculation results in the FPGA, and the frequency offset value of the VCXO will all be reset.

[0143] Subsequently, the device will reload the frequency point fast lock file of the synchronization signal block and start the analog-to-digital converter for signal acquisition. This operation is equivalent to the execution process of step S1, and its purpose is to ensure that the device can synchronize the signal reception and processing from the beginning.

[0144] A radio air interface synchronization device for a 5G synchronization device, comprising:

[0145] An analog-to-digital converter for receiving radio air interface signals and loading the frequency points of multiple synchronization signal blocks through the fast lock mode;

[0146] An FPGA for implementing the search of synchronization signal blocks, physical broadcast channel decoding, and periodic synchronization;

[0147] A voltage-controlled crystal oscillator, which is used to adjust the output frequency according to a synchronization signal;

[0148] A CPU, which is used to configure an analog-to-digital converter, synchronization parameters and control the synchronization process.

[0149] Specifically, an analog-to-digital converter (ADC) is connected between the signal receiving module and the data processing module of the device. It is used to receive the analog air interface signal transmitted from the antenna and convert it into a digital signal that can be used by the digital processing module (FPGA). The analog-to-digital converter is connected to the CPU through a control bus, and the CPU is responsible for configuring its working mode, such as enabling the fast lock mode and loading the frequency points of the synchronization signal block. The analog-to-digital converter is also connected to the FPGA through a high-speed data bus and is responsible for transmitting the converted digital signal to the FPGA for subsequent processing. The working principle of the analog-to-digital converter is to use the internal sampling circuit to collect analog signals with high precision and convert them into digital signals through quantization and encoding. In the fast lock mode, the analog-to-digital converter can quickly switch and lock the preset frequency points to ensure the efficient capture of the synchronization signal block. This fast lock mode combines a preset frequency point table and a dynamic adjustment function, providing the device with the ability to adapt to complex signal environments.

[0150] As the core data processing module, the FPGA is directly connected to the analog-to-digital converter and is used to receive the digital signal output by it. At the same time, the FPGA is also connected to the CPU, and the CPU dynamically configures its working logic, including the search for the synchronization signal block, the decoding of the physical broadcast channel (PBCH) signal, and the initialization of the periodic synchronization function. The working principle of the FPGA is to implement complex signal processing tasks based on programmable logic units, including filtering, decoding, and correlation calculation of digital signals. In the search stage of the synchronization signal block, the FPGA quickly locates the primary synchronization signal (PSS) and the secondary synchronization signal (SSS) by matching the locally generated synchronization code with the received signal. In the PBCH decoding stage, the FPGA uses the demodulation reference signal for channel estimation and equalization processing to extract the frame synchronization information. In the periodic synchronization, the FPGA will calculate the frequency and time deviation in real time and transmit the adjustment instruction to the voltage-controlled crystal oscillator (VCXO) to ensure the long-term synchronization stability of the device.

[0151] The Voltage-Controlled Crystal Oscillator (VCXO) is closely connected to the FPGA, used to receive the frequency adjustment signal from the FPGA, and at the same time connected to the clock distribution module of the device to provide a stable clock output for the entire system. The working principle of the VCXO is to change its output frequency by adjusting the input control voltage to achieve dynamic frequency calibration. During the adjustment process of the synchronization signal, the FPGA generates a control signal based on the calculated frequency offset and transmits it to the VCXO through a dedicated interface. The VCXO responds to the change of the control signal and adjusts its oscillation frequency to ensure the complete consistency between the device clock and the base station clock. The VCXO also has the characteristics of high frequency stability and low phase noise, which can effectively reduce the synchronization error and enhance the reliability of the clock signal in a complex wireless environment.

[0152] The CPU, as the control center of the device, is connected to the analog-to-digital converter, FPGA, and VCXO through the control bus and data bus respectively, and is responsible for the initialization and dynamic control of the entire synchronization process. The working principle of the CPU is based on the preset synchronization logic and the signal status detected in real time, and configures the working parameters of each module in stages. For example, the CPU will first configure the fast lock mode of the analog-to-digital converter and load the frequency fast lock file of the synchronization signal block. Subsequently, the CPU initializes the synchronization algorithm module of the FPGA and activates the synchronization signal search and PBCH decoding functions. During the periodic synchronization stage, the CPU will monitor the time-frequency status of the system. When the detected synchronization error exceeds the preset threshold, it will quickly trigger the restart instruction of the initial synchronization process. Through close cooperation with each module, the CPU realizes the global control of the device synchronization function and ensures the efficient and stable operation of the synchronization system.

[0153] Although the embodiments of the present invention have been shown and described, it will be understood by those of ordinary skill in the art that various changes, modifications, substitutions, and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A method for air interface synchronization of a 5G synchronization device, characterized in that, It includes the following steps: S1. Configure an analog-to-digital converter and load the frequency point fast lock files of several synchronization signal blocks to support the capture of synchronization signal blocks; S2. Configure synchronization parameters, including synchronization mode and duplex mode; S3. Start the synchronization process and activate the synchronization algorithm module; S4. Search for synchronization signal blocks and extract the first synchronization signal index and the second synchronization signal index; The synchronization signal block includes a first synchronization signal and a second synchronization signal, which are respectively used to determine the time offset and the physical cell identifier; The search for the synchronization signal block first processes the first synchronization signal, and the core formula for the operation is as follows: Where: R ADC (n): The nth time-domain signal sample received by the analog-to-digital converter; PSS i (n): The PSS code generated locally in the ith group; PSS i (n) complex conjugate; N: The total number of signal sampling points; When the system detects multiple peaks in the correlation results of 3 groups of PSS codes, the index of the first synchronization signal is determined by the following formula: Wherein: Index of the first synchronization signal; The processing result of the first synchronization signal directly affects the search for the second synchronization signal. After the system completes the extraction of the PSS index, it extracts the synchronization signal block adjacent to the PSS from the data buffer of the analog-to-digital converter and performs a fast Fourier transform on it; Subsequently, the frequency domain data of the SSB is subjected to a group-by-group correlation operation with 336 groups of SSS codes generated locally, and the core formula is as follows: Where: FFT(R SSB )(k): The k-th frequency domain signal sampling point of the SSB; SSS j (k): The SSS code generated locally for the j-th group; SSS j (k) complex conjugate; K: The number of frequency domain sampling points; Calculate the correlation of 336 groups of SSS codes, and select the index with the largest correlation result according to the following formula: Wherein: Index of the second synchronization signal; and correspond to the index ranges of the second synchronization signal and the first synchronization signal, respectively; S5. Decode the physical broadcast channel signal, extract the frame synchronization information and verify the signal validity; S6. Adjust the system time according to the frame synchronization information; S7. Perform periodic synchronization, including the following steps: Periodically calculate the time-frequency error of the current system; Adjust the output frequency of the voltage-controlled crystal oscillator based on the time-frequency error; When the time-frequency error exceeds the preset threshold continuously for multiple times, determine that the synchronization is lost and restart the synchronization process; Periodic synchronization requires continuous monitoring of the time error and frequency error between the device and the base station. The calculation of the time error is based on the system time of the device and combines the phase offset of the synchronization signal to obtain the time error parameter T error , and the time error is calculated by the following formula: T errror = T sync - T local ; Where: T error : the current time error; T sync : the base station time extracted from the synchronization signal; T local : the local system time of the device; The calculation of the frequency error is based on the phase change of the received signal, and the frequency error is calculated using the following formula: where: f error : frequency error; Δφ: phase difference between adjacent sampling points; T period : sampling time interval; S8. When the synchronization error exceeds the preset threshold, quickly restart the initial synchronization process.

2. The air interface synchronization method of a 5G synchronization device according to claim 1, characterized in that, In the step S4, the search for the synchronization signal block includes the following steps: Receive the air interface signal through the analog-to-digital converter, perform a correlation operation with the first synchronization signal code generated locally, and extract the first synchronization signal index; Based on the time offset of the first synchronization signal, extract the index of the second synchronization signal; Calculate the physical cell identifier according to the first synchronization signal index and the second synchronization signal index.

3. A method for air interface synchronization of a 5G synchronization device according to claim 2, characterized in that The physical cell identifier is calculated and determined based on the following parameters: The first synchronization signal index, whose value range is from 0 to 335; The second synchronization signal index, whose value range is from 0 to 2; The first synchronization signal index and the second synchronization signal index jointly determine a unique physical cell identifier.

4. A method for air interface synchronization of a 5G synchronization device according to claim 1, characterized in that, In the step S5, the decoding of the physical broadcast channel signal includes the following steps: Calculate the channel estimation value based on the demodulation reference symbol; Use the channel estimation value to perform equalization processing on the received physical broadcast channel signal; Demodulate the signal and perform descrambling, rate matching and verification, and extract the system frame number and the half-frame indicator.

5. A method for air interface synchronization of a 5G synchronization device according to claim 1, characterized in that, The time adjustment in the step S6 includes: Adjust the system time according to the frame synchronization information obtained by decoding the physical broadcast channel; When the time adjustment deviation exceeds the threshold, quickly restart the synchronization process.

6. A method for air interface synchronization of a 5G synchronization device according to claim 1, characterized in that, The channel estimation value is calculated by the ratio of the received signal to the reference symbol, and the received signal is equalized based on the channel estimation value.

7. A method for air interface synchronization of a 5G synchronization device according to claim 1, characterized in that, In the step S1, the analog-to-digital converter loads the frequency point configuration files of multiple synchronization signal blocks through the fast lock mode to speed up the capture process of the synchronization signal blocks.

8. An air interface synchronization device for a 5G synchronization device, according to the air interface synchronization method for a 5G synchronization device described in any one of claims 1-7, characterized in that, Including: An analog-to-digital converter, configured to receive the air interface signal and load the frequency points of multiple synchronization signal blocks through the fast lock mode; An FPGA, configured to implement the search of the synchronization signal blocks, the decoding of the physical broadcast channel, and the periodic synchronization; A voltage-controlled crystal oscillator, configured to adjust the output frequency according to the synchronization signal; A CPU, configured to configure the analog-to-digital converter, the synchronization parameters, and control the synchronization process.

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