Memory device having COP structure and memory package including same

Abstract

A memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array. The memory cell array is connected to a plurality of word lines and a plurality of bit lines, and includes a plurality of normal memory cells storing normal data and a plurality of error correction code (ECC) memory cells storing ECC data. The second semiconductor layer is disposed in a vertical direction with respect to the first semiconductor layer, and includes a peripheral circuit. The peripheral circuit controls the memory cell array and includes a row decoder. At least a portion of a region in the first semiconductor layer in which the plurality of ECC memory cells are disposed overlaps at least a portion of a region in the second semiconductor layer in which the row decoder is disposed in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0152288 filed on November 7, 2023 in the Korean Intellectual Property Office (KIPO), the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates generally to semiconductor integrated circuits, and more particularly, to a memory device having a cell-on-periphery (COP) structure and a memory package including the memory device. Background Art

[0004] Semiconductor memory devices can be divided into two categories depending on whether they retain stored data when disconnected from power. These categories include volatile memory devices that lose stored data when disconnected from power, and non-volatile memory devices that retain stored data when disconnected from power. Although volatile memory devices can perform read and write operations at high speed, the content stored therein may be lost when power is off. Since non-volatile memory devices retain the content stored therein even when power is off, they can be used to store data that needs to be retained.

[0005] Various structures are being adopted to increase the integration of memory devices and reduce the size of memory devices. However, since the memory device should also include a peripheral circuit for driving a memory cell array and a wiring structure for electrically connecting the memory cell array to the peripheral circuit, the reduction in size of the memory device is limited. Recently, a method is used in which elements included in the memory device are manufactured on separate wafers and then bonded to each other, rather than being manufactured on a single wafer. Summary of the invention

[0006] At least one example embodiment of the present disclosure provides a memory device that is efficiently reduced in size.

[0007] At least one example embodiment of the present disclosure provides a memory package including a memory device.

[0008] According to an example embodiment, a memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array. The memory cell array is connected to a plurality of word lines and a plurality of bit lines, and includes a plurality of normal memory cells storing normal data and a plurality of ECC memory cells storing error correction code (ECC) data. A plurality of word lines extend in a first direction. A plurality of bit lines extend in a second direction intersecting the first direction. The second semiconductor layer is arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, and includes a peripheral circuit. The peripheral circuit controls the memory cell array and includes a row decoder. At least a portion of a region in which the plurality of ECC memory cells are arranged in the first semiconductor layer overlaps at least a portion of a region in which the row decoder is arranged in the second semiconductor layer in a plan view.

[0009] According to an example embodiment, a memory package includes a base substrate and a plurality of memory chips stacked on the base substrate. Each of the plurality of memory chips includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array. The memory cell array is connected to a plurality of word lines and a plurality of bit lines, and includes a plurality of normal memory cells storing normal data and a plurality of ECC memory cells storing error correction code (ECC) data. A plurality of word lines extend in a first direction. A plurality of bit lines extend in a second direction intersecting the first direction. The second semiconductor layer is arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, and includes a peripheral circuit. The peripheral circuit controls the memory cell array and includes a row decoder. At least a portion of a region in which the plurality of ECC memory cells are arranged in the first semiconductor layer overlaps at least a portion of a region in which the row decoder is arranged in the second semiconductor layer in a plan view.

[0010] According to an example embodiment, a memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array connected to a plurality of word lines and a plurality of bit lines, and a first bonding pad. The plurality of word lines extend in a first direction. The plurality of bit lines extend in a second direction intersecting the first direction. The second semiconductor layer is arranged in a third direction perpendicular to both the first direction and the second direction relative to the first semiconductor layer, and includes a peripheral circuit for controlling the memory cell array, and a second bonding pad connected to the first bonding pad. The memory cell array includes a plurality of normal memory cells and a plurality of error correction code (ECC) memory cells. The plurality of normal memory cells store normal data, and include a first normal memory cell and a second normal memory cell spaced apart from each other. The plurality of ECC memory cells store ECC data, and include a first ECC memory cell and a second ECC memory cell corresponding to the first normal memory cell and the second normal memory cell, respectively. The peripheral circuit includes a first row decoder, a first normal bit line sense amplifier and a second normal bit line sense amplifier, a first ECC bit line sense amplifier and a second ECC bit line sense amplifier, a first sub word line driver and a second sub word line driver. The first row decoder drives the first normal memory cell and the second normal memory cell and the first ECC memory cell and the second ECC memory cell. The first normal bit line sense amplifier and the second normal bit line sense amplifier drive the first normal memory cell and the second normal memory cell, respectively. The first ECC bit line sense amplifier and the second ECC bit line sense amplifier drive the first ECC memory cell and the second ECC memory cell, respectively. The first sub-word line driver drives the first normal memory cell and the first ECC memory cell. The second sub-word line driver drives the second normal memory cell and the second ECC memory cell. The first ECC memory cell and the second ECC memory cell are arranged in a first area between the first normal memory cell and the second normal memory cell in the first semiconductor layer. The first row decoder and the first ECC bit line sense amplifier and the second ECC bit line sense amplifier are arranged in a second area in the second semiconductor layer, and the second area overlaps with the first area in the first semiconductor layer in a plan view. The first normal bit line sense amplifier and the second normal bit line sense amplifier and the first sub-word line driver and the second sub-word line driver are arranged in a third area in the second semiconductor layer, and the third area is adjacent to the second area in the second semiconductor layer.

[0011] The memory device and the memory package according to the example embodiments may have or adopt a structure of stacking a peripheral circuit and a memory cell array, such as a COP structure in which a peripheral circuit is formed below and then a memory cell array is stacked above the peripheral circuit. Therefore, the memory device and the memory package may have a relatively small size.

[0012] In addition, in the memory device and the memory package according to the example embodiments, the ECC memory cell included in the memory cell array and the row decoder included in the peripheral circuit can be arranged to overlap each other vertically. Therefore, the area occupied by the ECC memory cell in the first semiconductor layer can be reduced, and / or the area occupied by the row decoder in the second semiconductor layer can be reduced. Therefore, the size of the memory device can be further reduced. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Illustrative, non-limiting example embodiments will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, wherein like reference numerals (when used) designate corresponding elements throughout the several views, and wherein:

[0014] Figure 1 is a perspective schematic diagram of a memory device according to an example embodiment;

[0015] Figure 2 is a schematic cross-sectional view of a memory device according to an example embodiment;

[0016] Figure 3 is a schematic block diagram illustrating an example of a memory device according to an example embodiment;

[0017] Figure 4 It is shown that the Figure 3 A schematic diagram of an example of a memory cell array in a memory device of FIG. 1 ;

[0018] Figure 5 yes Figure 1 A schematic perspective view of an example of a memory device;

[0019] Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Figure 8C and Fig. 9 Is used to describe Figure 5 A schematic diagram of a memory device;

[0020] Fig.10 yes Figure 1 A schematic perspective view of an example of a memory device;

[0021] Fig.11 Is used to describe Fig.10 A schematic diagram of a memory device;

[0022] Fig. 12A and Fig. 12B is a schematic perspective view of a memory device according to an example embodiment;

[0023] Fig.13A and Fig. 13B is a schematic cross-sectional view of a memory package according to an example embodiment; and

[0024] Fig.14 is a schematic block diagram illustrating a memory system according to example embodiments. DETAILED DESCRIPTION

[0025] Various example embodiments will be described more fully with reference to the accompanying drawings, in which embodiments are shown. However, the present disclosure may be implemented in many different forms and should not be construed as being limited to the embodiments set forth herein. Throughout this application, the same reference numerals refer to the same elements.

[0026] As used herein, expressions such as "at least one of..." when following a list of elements modify the entire list of elements rather than modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0027] It will be understood that when an element or layer is referred to as being “on,” “over,” “on,” “under,” “under,” “connected to,” or “coupled to,” it can be directly on, over, above, below, under, beneath, connected or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being “directly on,” “directly over,” “directly on,” “directly under,” “directly under,” “directly connected to,” or “directly coupled to,” there are no intervening elements or layers.

[0028] Figure 1 is a schematic perspective view of a memory device according to an example embodiment.

[0029] exist Figure 1In the figure, two directions that are each parallel to or substantially parallel to the first surface (e.g., top surface) of the substrate and intersect with each other are respectively referred to as the first direction D1 (e.g., X-axis direction) and the second direction D2 (e.g., Y-axis direction). In addition, the direction that is perpendicular to or substantially perpendicular to (i.e., perpendicular to) the first surface of the substrate is referred to as the third direction D3 (e.g., Z-axis direction) in this article. For example, the first direction D1 and the second direction D2 may be perpendicular or substantially perpendicular to each other. In addition, the third direction D3 may be perpendicular or substantially perpendicular to both the first direction D1 and the second direction D2. In addition, the direction indicated by the arrows in the figure and the opposite direction thereof are considered to be the same direction. The definitions of the first direction D1, the second direction D2, and the third direction D3 are the same in the subsequent figures.

[0030] refer to Figure 1 , the memory device 10 includes a first semiconductor layer L1 and a second semiconductor layer L2.

[0031] The first semiconductor layer L1 and the second semiconductor layer L2 are arranged or stacked in the third direction D3. For example, the first semiconductor layer L1 may be stacked above the second semiconductor layer L2 in the third direction D3, and the second semiconductor layer L2 may be arranged below (e.g., directly below or indirectly below) the first semiconductor layer L1 in the third direction D3. However, example embodiments are not limited thereto. For example, the memory device 10 may be flipped (i.e., vertically inverted) during the manufacturing process, and thus the second semiconductor layer L2 may be stacked above the first semiconductor layer L1 in the third direction D3. In some example embodiments, as will be referred to in Fig. 12A and Fig. 12B As described, three or more semiconductor layers may be stacked in the third direction D3.

[0032] The first semiconductor layer L1 includes a plurality of word lines WL, a plurality of bit lines BL, and a memory cell array MCA. Therefore, the first semiconductor layer L1 may be referred to as a memory cell region (MCR) or a unit cell.

[0033] For example, if you refer to Figure 2 As described, the first semiconductor layer L1 may include a first substrate. A plurality of word lines WL, a plurality of bit lines BL, and a memory cell array MCA may be arranged and / or formed on the first substrate. For example, each of the plurality of word lines WL may extend in a first direction D1, and the plurality of word lines WL may be arranged along a second direction D2 (i.e., separated from each other). For example, each of the plurality of bit lines BL may extend in a second direction D2, and the plurality of bit lines BL may be arranged along a first direction D1 (i.e., separated from each other). For example, the memory cell array MCA may be connected to the plurality of word lines WL and the plurality of bit lines BL.

[0034] The second semiconductor layer L2 may include a peripheral circuit PCKT controlling the memory cell array MCA. Therefore, the second semiconductor layer L2 may be referred to as a peripheral circuit region (PCR) or a peripheral wafer.

[0035] For example, if you refer to Figure 2 As described, the second semiconductor layer L2 may include a second substrate. The peripheral circuit PCKT may be disposed and / or formed on the second substrate. For example, the peripheral circuit PCKT may control the memory cell array MCA.

[0036] In some example embodiments, the first semiconductor layer L1 and the second semiconductor layer L2 may be manufactured separately, and then the first semiconductor layer L1 and the second semiconductor layer L2 may be connected to each other by a bonding scheme (or method). As may be used herein, the term "connected" (or "connected" or similar terms, such as "contacting" or "contacting") may refer to a physical and / or electrical connection between two or more elements, and may include other intermediate elements. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, as referenced Figure 2 As described, the first semiconductor layer L1 may include a first bonding pad, the second semiconductor layer L2 may include a second bonding pad, and the bonding scheme may refer to a method of electrically or physically connecting a bonding metal pattern (e.g., a first bonding pad) formed in the first semiconductor layer L1 to a bonding metal pattern (e.g., a second bonding pad) formed in the second semiconductor layer L2. For example, the bonding pad may be formed of copper (Cu), and the bonding scheme may be a Cu-Cu bonding scheme. Alternatively, the bonding pad may be formed of aluminum (Al) or tungsten (W).

[0037] The memory cell array MCA may include a plurality of normal memory cells NMC and a plurality of error correction code (ECC) memory cells EMC. The plurality of normal memory cells NMC may store normal data (e.g., user data), and the plurality of ECC memory cells EMC may store ECC data (e.g., parity data) associated or related to the normal data. The peripheral circuit PCKT may include a row decoder RDEC. The row decoder RDEC may control the plurality of normal memory cells NMC and the plurality of ECC memory cells EMC. The plurality of ECC memory cells EMC in the first semiconductor layer L1 and the row decoder RDEC in the second semiconductor layer L2 may be arranged to partially and / or completely overlap in a plan view or on a plane, which will be referred to as Figure 2 , Figure 5 and Fig.10As may be used herein, the term "overlap" (or "overlapping" or similar terms) may broadly refer to a first element that crosses at least a portion of a second element in a vertical direction (e.g., the third direction D3), but does not require that the first element and the second element be completely aligned with each other in a horizontal plane (e.g., in the first direction D1 and / or the second direction D2).

[0038] In computing, telecommunications, information theory, and coding theory, forward error correction (FEC) or channel coding is a technique used to control errors in data transmission over an unreliable or noisy communication channel. For example, the sender encodes the message in a redundant manner, most commonly by using an error correction code (ECC). The redundancy allows the receiver to not only detect errors that may occur anywhere in the message, but also to correct a limited number of errors frequently. Therefore, a reverse channel to request a retransmission may not be needed.

[0039] For example, when normal data is written into a plurality of normal memory cells NMC, an ECC encoder and an ECC may be used to generate ECC data associated with the normal data to be written. Normal data and ECC data may be stored in a plurality of normal memory cells NMC and a plurality of ECC memory cells EMC, respectively. For example, when normal data is read from a plurality of normal memory cells NMC, an ECC decoder and an ECC may be used to perform ECC decoding on the normal data based on the ECC data. When it is determined based on the result of ECC decoding that the normal data includes at least one error bit, in the case of a correctable error (CE), the ECC decoder may perform error correction and output the corrected normal data, and in the case of an uncorrectable error (UE), the ECC decoder may declare that ECC decoding is impossible. For example, the ECC may be a single error correction (SEC) code or a single error correction and double error detection (SECDED) code, but example embodiments are not limited thereto.

[0040] Figure 2 is a schematic cross-sectional view of a memory device according to example embodiments.

[0041] refer to Figure 1 and Figure 2 The first semiconductor layer L1 may include a first substrate SUB1, a memory cell array MCA, a first bonding pad PD_L1, a first contact CT_L1, and a first insulating layer IL1. The second semiconductor layer L2 may include a second substrate SUB2, a peripheral circuit PCKT, a second bonding pad PD_L2, a second contact CT_L2, and a second insulating layer IL2.

[0042] The first substrate SUB1 may be a supporting layer that supports components (or elements) of the first semiconductor layer L1, and the second substrate SUB2 may be a supporting layer that supports components of the second semiconductor layer L2. For example, each of the first substrate SUB1 and the second substrate SUB2 may be a silicon substrate and may be referred to as a base substrate; however, the first substrate SUB1 and the second substrate SUB2 do not need to be formed of the same material. The first insulating layer IL1 may cover the components of the first semiconductor layer L1, and the second insulating layer IL2 may cover the components of the second semiconductor layer L2. As may be used herein, the term "covering" (or "covering", "covering" or similar terms) may broadly refer to an element, structure or layer that is directly above or on another element, structure or layer, or an element, structure or layer that is above or on another element, structure or layer with one or more other intermediate elements, structures or layers therebetween.

[0043] The memory cell array MCA may include a plurality of normal memory cells NMC and a plurality of ECC memory cells EMC. The peripheral circuit PCKT may include a row decoder RDEC, a bit line sense amplifier BLSA, a sub-word line driver SWD, a column decoder CDEC, etc. Figure 1 As described above, the normal memory cell NMC and the ECC memory cell EMC can store normal data and ECC data, respectively. The row decoder RDEC, the bit line sense amplifier BLSA, the sub-word line driver SWD, and the column decoder CDEC can be used to drive the normal memory cell NMC and the ECC memory cell EMC. Figure 3 The detailed structure of the peripheral circuit PCKT is described.

[0044] The memory cell array MCA and the peripheral circuit PCKT may be electrically connected to each other through the first contact CT_L1 and the second contact CT_L2 and the first bonding pad PD_L1 and the second bonding pad PD_L2. For example, the memory cell array MCA may be electrically connected to the first contact CT_L1 and the first bonding pad PD_L1, the peripheral circuit PCKT may be electrically connected to the second contact CT_L2 and the second bonding pad PD_L2, and the memory cell array MCA and the peripheral circuit PCKT may be electrically connected to each other by electrically connecting the first bonding pad PD_L1 to the second bonding pad PD_L2. Although not shown in detail, at least one conductive line and / or contact may be further formed to connect the memory cell array MCA to the first bonding pad PD_L1, and at least one conductive line and / or contact may be further formed to connect the peripheral circuit PCKT to the second bonding pad PD_L2.

[0045] In some example embodiments, the first semiconductor layer L1 may be manufactured by forming a memory cell array MCA, a first bonding pad PD_L1, a first contact CT_L1, and a first insulating layer IL1 in and / or over a first substrate SUB1, the second semiconductor layer L2 may be manufactured by forming a peripheral circuit PCKT, a second bonding pad PD_L2, a second contact CT_L2, and a second insulating layer IL2 in and / or over a second substrate SUB2, the first semiconductor layer L1 may be flipped, and the bonding pads PD_L1 and PD_L2 may be connected using a bonding scheme. As a result, the first semiconductor layer L1 and the second semiconductor layer L2 may be electrically connected in a third direction D3.

[0046] although Figure 2 An example may be shown in which the semiconductor layers L1 and L2 include a pair of bonding pads PD_L1 and PD_L2 and a pair of contacts CT_L1 and CT_L2, but example embodiments are not limited thereto and the number of bonding pads and the number of contacts included in the semiconductor layers L1 and L2 may be determined in various ways according to example embodiments.

[0047] At least a portion of the region (or area) REG1 in which a plurality of ECC memory cells EMC are disposed in the first semiconductor layer L1 and at least a portion of the region REG2 in which a row decoder RDEC is disposed in the second semiconductor layer L2 may overlap in a plan view or on a plane. In other words, when the first semiconductor layer L1 and the second semiconductor layer L2 overlap and are viewed on the same plane, in the third direction D3, the region REG1 and the region REG2 may overlap, and / or a portion or all of the region REG1 may be included in the region REG2, or a portion or all of the region REG2 may be included in the region REG1.

[0048] In some example embodiments, as will be referred to Figure 5 As described, the region REG2 in the second semiconductor layer L2 where the row decoder RDEC is disposed can remain the same as the region REG2 of the existing memory device, and the region REG1 in the first semiconductor layer L1 where the plurality of ECC memory cells EMC are disposed can be moved to partially and / or completely overlap with the region REG2 in the third direction D3.

[0049] In some example embodiments, as will be referred to Fig.10 As described, the region REG1 in the first semiconductor layer L1 where the plurality of ECC memory cells EMC are disposed can remain the same as the region REG1 of the existing memory device, and the region REG2 in the second semiconductor layer L2 where the row decoder RDEC is disposed can be moved to partially and / or completely overlap with the region REG1 in the third direction D3.

[0050] The memory device 10 according to example embodiments may have or adopt a structure in which a peripheral circuit PCKT and a memory cell array MCA are stacked in a third direction D3, such as a cell-on-periphery (COP) structure in which the peripheral circuit PCKT is formed below and then the memory cell array MCA is stacked above the peripheral circuit PCKT. Therefore, the memory device 10 may have a relatively small size.

[0051] In addition, in the memory device 10 according to the example embodiment, the ECC memory cell EMC included in the memory cell array MCA and the row decoder RDEC included in the peripheral circuit PCKT may be arranged to overlap each other in the third direction D3. Therefore, the area occupied by the ECC memory cell EMC in the first semiconductor layer L1 may be reduced, and / or the area occupied by the row decoder RDEC in the second semiconductor layer L2 may be reduced. Therefore, the size of the memory device 10 may be further reduced. In other words, a size gain may be obtained.

[0052] However, example embodiments are not limited thereto, and the memory device 10 may have or employ a bonded vertical NAND (BVNAND) structure in which the memory cell array MCA includes vertical flash memory cells (e.g., vertical NAND cells) and the peripheral circuit PCKT and the memory cell array MCA are disposed or arranged in the third direction D3.

[0053] Figure 3 is a schematic block diagram illustrating an example of a memory device according to example embodiments.

[0054] Reference Figure 3 , the memory device 200 may include a peripheral circuit 201 and a memory cell array 300. The peripheral circuit 201 may include a control logic circuit 210, an address register 220, a bank control logic circuit 230, a row address multiplexer (RA MUX) 240, a refresh counter 245, a column address (CA) latch 250, a row decoder 260, a column decoder 270, a sense amplifier unit 285, an input / output (I / O) gating circuit 290, and a data I / O buffer 295. For example, the memory device 200 may be one of various volatile memory devices, such as a dynamic random access memory (DRAM).

[0055] The memory cell array 300 may include a first memory cell array 310 to an eighth memory cell array 380 (e.g., the first to eighth memory cell arrays 310, 320, 330, 340, 350, 360, 370 and 380, only the first and eighth memory cell arrays are explicitly shown). The row decoder 260 may include a first memory cell row decoder 260a to an eighth memory cell row decoder 260h (only the first memory cell row decoder and the eighth memory cell row decoder are explicitly shown) connected to the first memory cell array 310 to the eighth memory cell array 380, respectively. The column decoder 270 may include a first memory cell column decoder 270a to an eighth memory cell column decoder 270h (only the first memory cell column decoder and the eighth memory cell column decoder are explicitly shown) connected to the first memory cell array 310 to the eighth memory cell array 380, respectively. The sense amplifier unit 285 may include first to eighth bank sense amplifiers 285 a to 285 h (only the first and eighth bank sense amplifiers are explicitly shown) connected to the first to eighth bank arrays 310 to 380 , respectively.

[0056] The first to eighth bank arrays 310 to 380, the first to eighth bank row decoders 260a to 260h, the first to eighth bank column decoders 270a to 270h, and the first to eighth bank sense amplifiers 285a to 285h may form the first to eighth banks. Each of the first to eighth bank arrays 310 to 380 may include a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC located at intersections of the word lines WL and the bit lines BL.

[0057] although Figure 3 The memory device 200 is shown to include eight memory banks (and eight memory bank arrays, eight row decoders, etc.), but the memory device 200 may include any number of memory banks; for example, one, two, four, eight, sixteen, or thirty-two memory banks, or any number between one and thirty-two.

[0058] The address register 220 can be obtained from a memory controller (e.g., Fig.14 The memory controller 1200 in the embodiment receives the address ADDR supplied thereto, the address ADDR including the bank address BANK_ADDR, the row address ROW_ADDR and the column address COL_ADDR. The address register 220 may provide the received bank address BANK_ADDR to the bank control logic circuit 230, may provide the received row address ROW_ADDR to the row address multiplexer 240, and may provide the received column address COL_ADDR to the column address latch 250.

[0059] The bank control logic circuit 230 may generate a bank control signal in response to the bank address BANK_ADDR. In response to the bank control signal, one of the first bank row decoder 260a to the eighth bank row decoder 260h corresponding to the bank address BANK_ADDR may be activated, and in response to the bank control signal, one of the first bank column decoder 270a to the eighth bank column decoder 270h corresponding to the bank address BANK_ADDR may be activated.

[0060] The row address multiplexer 240 may receive the row address ROW_ADDR from the address register 220 and may receive the refresh row address REF_ADDR from the refresh counter 245. The row address multiplexer 240 may selectively output the row address ROW_ADDR or the refresh row address REF_ADDR as the row address RA. The row address RA output from the row address multiplexer 240 may be applied to the first to eighth bank row decoders 260a to 260h.

[0061] The activated one of the first to eighth bank row decoders 260a to 260h may decode the row address RA output from the row address multiplexer 240, and may activate the word line WL corresponding to the row address RA in the corresponding bank array. For example, the activated bank row decoder may generate a word line driving voltage, and may apply the word line driving voltage to the word line WL corresponding to the row address RA.

[0062] The column address latch 250 may receive the column address COL_ADDR from the address register 220 and may temporarily store the received column address COL_ADDR. In some example embodiments, in a burst mode, the column address latch 250 may generate a column address incremented from the received column address COL_ADDR. The column address latch 250 may apply the temporarily stored or generated column address to the first to eighth bank column decoders 270a to 270h.

[0063] An activated one of the first to eighth bank column decoders 270 a to 270 h may decode the column address COL_ADDR output from the column address latch 250 and may control the I / O gating circuit 290 to output data corresponding to the column address COL_ADDR.

[0064] The I / O gating circuit 290 may include a circuit configured to gate input / output data. The I / O gating circuit 290 may also include a read data latch configured to store data output from the first memory bank array 310 to the eighth memory bank array 380 (e.g., during a read operation), and may also include a write control device for writing data to the first memory bank array 310 to the eighth memory bank array 380 (e.g., during a write operation).

[0065] The data DAT read from one of the first memory bank array 310 to the eighth memory bank array 380 may be read by a corresponding one of the sense amplifiers in the sense amplifier unit 285 connected to the one memory bank array from which the data DAT is to be read, and may be stored in the read data latch. The data DAT stored in the read data latch may be provided to the memory controller via the data I / O buffer 295. The data DAT to be written into one of the first memory bank array 310 to the eighth memory bank array 380 may be provided from the memory controller to the I / O gating circuit 290 via the data I / O buffer 295, and the I / O gating circuit 290 may write the data DAT into the one memory bank array through the write driver.

[0066] The control logic circuit 210 may control the operation of the memory device 200. For example, the control logic circuit 210 may generate a control signal for the memory device 200 to perform a write operation and / or a read operation. The control logic circuit 210 may include a command decoder 211 that decodes a command CMD received from a memory controller and a mode register 212 that sets an operation mode of the memory device 200. In some example embodiments, the operations described herein as being performed by the control logic circuit 210 may be performed by a processing circuit. For example, the command decoder 211 may generate a control signal corresponding to the command CMD by decoding a write enable signal, a row address strobe signal, a column address strobe signal, a chip select signal, etc.

[0067] Figure 2 The row decoder RDEC in may correspond to the row decoder 260, and Figure 2 The column decoder CDEC in may correspond to the column decoder 270 . Figure 2 The bit line sense amplifier BLSA in the sense amplifier unit 285 may be included in the sense amplifier unit 285, and Figure 2 The sub word line driver SWD in may be disposed between the row decoder 260 and the memory cell array 300 and may control driving of the word line WL. In some example embodiments, one bank row decoder and / or one bank column decoder may be shared by two or more bank arrays.

[0068] Figure 4It is shown that it can be included in Figure 3 Schematic diagram of an example of a memory cell array in a memory device 200 .

[0069] refer to Figure 3 and Figure 4 , the first memory array 310 included in the memory cell array 300 may include a plurality of word lines WL1, WL2, ..., WLm-1, WLm (where m is a positive integer greater than or equal to 2), a plurality of bit lines BL1, BL2, ..., BLn-1, BLn (where n is a positive integer greater than or equal to 2, which may be the same as m or may be different from m), and a plurality of memory cells MC arranged at or near intersections between the word lines WL1 to WLm and the bit lines BL1 to BLn. For example, each of the plurality of memory cells MC may include a DRAM cell structure. The plurality of word lines WL1 to WLm connected to the plurality of memory cells MC may be referred to as rows of the first memory array 310, and the plurality of bit lines BL1 to BLn connected to the plurality of memory cells MC may be referred to as columns of the first memory array 310.

[0070] Figure 2 The normal memory cells NMC and the ECC memory cells EMC in the memory cell MC may correspond to a plurality of memory cells MC. For example, some of the memory cells MC may operate as normal memory cells NMC, and another one of the memory cells MC may operate as an ECC memory cell EMC.

[0071] Although the memory device according to the example embodiments is described based on DRAM, the memory device according to the example embodiments may be any volatile memory device and / or any nonvolatile memory device, such as static random access memory (SRAM), flash memory, phase change random access memory (PRAM), resistive random access memory (RRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), or the like.

[0072] Figure 5 yes Figure 1 A schematic perspective view of at least a portion of an example memory device.

[0073] refer to Figure 5 , the memory device 10a includes a first semiconductor layer L1a and a second semiconductor layer L2a. Figure 5 The first semiconductor layer L1a in may correspond to Figure 1 The first semiconductor layer L1 in the embodiment of the present invention is Figure 5 The second semiconductor layer L2a in may correspond to Figure 1 For the sake of simplicity, the second semiconductor layer L2 is omitted. Figure 1Descriptions of duplicate or overlapping descriptions.

[0074] The first semiconductor layer L1a may include a first memory array BA1a and a second memory array BA2a. The first memory array BA1a may include first normal memory cells NMC1 storing first normal data. The second memory array BA2a may include second normal memory cells NMC2 storing second normal data.

[0075] The first semiconductor layer L1a may include a first ECC memory cell EMC1 and a second ECC memory cell EMC2. The first ECC memory cell EMC1 may correspond to the first normal memory cell NMC1 and may store first ECC data associated with the first normal data. The second ECC memory cell EMC2 may correspond to the second normal memory cell NMC2 and may store second ECC data associated with the second normal data.

[0076] The first memory bank array BA1a and the second memory bank array BA2a may include Figure 1 and Figure 2 In the memory cell array MCA, each of the first memory bank array BA1a and the second memory bank array BA2a may correspond to Figure 3 The first normal memory cell NMC1 and the second normal memory cell NMC2 may include one of the first memory bank array 310 to the eighth memory bank array 380 in the embodiment of the present invention. Figure 1 and Figure 2 The first ECC memory unit EMC1 and the second ECC memory unit EMC2 may include Figure 1 and 2 In the multiple ECC memory cells EMC.

[0077] The first memory array BA1a may be disposed in a first memory array region R_BA1a in the first semiconductor layer L1a, and the second memory array BA2a may be disposed in a second memory array region R_BA2a in the first semiconductor layer L1a. The first memory array BA1a and the second memory array BA2a may be arranged to be spaced apart from each other in the first direction D1, and the first region R1a may exist between the first memory array BA1a and the second memory array BA2a.

[0078] The first ECC memory cell EMC1 may be disposed in a first ECC cell area R_EC1a in a first region R1a included in the first semiconductor layer L1a, and the second ECC memory cell EMC2 may be disposed in a second ECC cell area R_EC2a in the first region R1a included in the first semiconductor layer L1a. For example, the first ECC cell area R_EC1a may be formed in the first region R1a to be adjacent to the first memory cell array BA1a (e.g., adjacent to the first memory cell array area R_BA1a), and the second ECC cell area R_EC2a may be formed in the first region R1a to be adjacent to the second memory cell array BA2a (e.g., adjacent to the second memory cell array area R_BA2a).

[0079] The second semiconductor layer L2a may include a first bank row decoder BRDEC1. The first bank row decoder BRDEC1 may drive the first normal memory cell NMC1 and the second normal memory cell NMC2 (eg, the first bank array BA1a and the second bank array BA2a), and may drive the first ECC memory cell EMC1 and the second ECC memory cell EMC2. Figure 6 As described, the first bank row decoder BRDEC1 may drive a portion of the first normal memory cell NMC1 and the second normal memory cell NMC2.

[0080] The second semiconductor layer L2a may include a first normal bit line sense amplifier NBLSA1, a second normal bit line sense amplifier NBLSA2, a first ECC bit line sense amplifier EBLSA1, and a second ECC bit line sense amplifier EBLSA2. The first normal bit line sense amplifier NBLSA1 may drive the first normal memory cell NMC1, and the second normal bit line sense amplifier NBLSA2 may drive the second normal memory cell NMC2. The first ECC bit line sense amplifier EBLSA1 may drive the first ECC memory cell EMC1, and the second ECC bit line sense amplifier EBLSA2 may drive the second ECC memory cell EMC2. Fig. 8A Describe the power of each sense amplifier.

[0081] The second semiconductor layer L2a may include a first sub word line driver SWD1 and a second sub word line driver SWD2. The first sub word line driver SWD1 may drive the first normal memory cell NMC1 and the first ECC memory cell EMC1, and may be shared by the first normal memory cell NMC1 and the first ECC memory cell EMC1. The second sub word line driver SWD2 may drive the second normal memory cell NMC2 and the second ECC memory cell EMC2, and may be shared by the second normal memory cell NMC2 and the second ECC memory cell EMC2. Fig. 7A An example of each sub word line driver is described.

[0082] The second semiconductor layer L2a may include a first bank column decoder BCDEC1, a second bank column decoder BCDEC2, and a first intermediate circuit INTMID1. The first bank column decoder BCDEC1 may drive the first normal memory cell NMC1 and the first ECC memory cell EMC1, and the second bank column decoder BCDEC2 may drive the second normal memory cell NMC2 and the second ECC memory cell EMC2. The first intermediate circuit INTMID1 may be connected to the first bank row decoder BRDEC1, and may be used to drive the first normal memory cell NMC1 and the second normal memory cell NMC2 and the first ECC memory cell EMC1 and the second ECC memory cell EMC2.

[0083] The first bank row decoder BRDEC1 may include Figure 1 and Figure 2 The row decoder RDEC in the Figure 3 The first and second normal bit line sense amplifiers NBLSA1 and NBLSA2 and the first and second ECC bit line sense amplifiers EBLSA1 and EBLSA2 may be included in the memory cell row decoder 260a to the eighth memory cell row decoder 260h. Figure 2 The bit line sense amplifier BLSA and may be included in Figure 3 The first sub word line driver SWD1 and the second sub word line driver SWD2 may include Figure 2 The sub-word line driver SWD can be placed in Figure 3 between the row decoder 260 and the memory cell array 300, and can be used to drive Figure 3 The first bank column decoder BCDEC1 and the second bank column decoder BCDEC2 may include Figure 2In the column decoder CDEC, and each of the first bank column decoder BCDEC1 and the second bank column decoder BCDEC2 may correspond to Figure 3 The first intermediate circuit INTMID1 may correspond to one of the first memory column decoder 270a to the eighth memory column decoder 270h in FIG. Figure 3 At least a portion of the front end of the first memory bank row decoder 260a to the eighth memory bank row decoder 260h in the memory (for example, the control logic circuit 210, the address register 220, the memory bank control logic circuit 230, the row address multiplexer 240, etc.). For example, the first intermediate circuit INTMID1 may include a repeater, a control logic, etc.

[0084] The first memory row decoder BRDEC1 may be disposed in a second region R2a in the second semiconductor layer L2a, which overlaps the first region R1a in the first semiconductor layer L1a in the third direction D3. Therefore, the first memory row decoder BRDEC1 may be disposed below the first ECC memory cell EMC1 and the second ECC memory cell EMC2, and the first ECC memory cell EMC1 and the second ECC memory cell EMC2 and the first memory row decoder BRDEC1 may be arranged to overlap each other in the third direction D3. For example, when the first semiconductor layer L1a and the second semiconductor layer L2a overlap and are viewed on the same plane, the first region R1a and the second region R2a may coincide and may be substantially identical to each other. Although Figure 5 An example is shown in which the first region R1a and the second region R2a completely overlap, but example embodiments are not limited thereto, and the first region R1a and the second region R2a may partially overlap in the third direction D3.

[0085] The first ECC bit line sense amplifier EBLSA1 and the second ECC bit line sense amplifier EBLSA2 may be disposed in the second region R2a in the second semiconductor layer L2a. Therefore, the first ECC bit line sense amplifier EBLSA1 and the second ECC bit line sense amplifier EBLSA2 may be disposed under the first ECC memory cell EMC1 and the second ECC memory cell EMC2. For example, the first ECC bit line sense amplifier EBLSA1 and the second ECC bit line sense amplifier EBLSA2 may be disposed at or adjacent to at least one edge and / or at least one corner of the second region R2a in the second semiconductor layer L2a.

[0086] The first normal bit line sense amplifier NBLSA1 and the first sub word line driver SWD1 may be disposed in a region R31a in the second semiconductor layer L2a, the region R31a overlapping the first memory bank array region R_BA1a in the first semiconductor layer L1a in the third direction D3. Therefore, the first normal bit line sense amplifier NBLSA1 and the first sub word line driver SWD1 may be disposed under the first normal memory cell NMC1 (e.g., under the first memory bank array BA1a). For example, the region R31a may be formed adjacent to a first side of the second region R2a.

[0087] The second normal bit line sense amplifier NBLSA2 and the second sub word line driver SWD2 may be disposed in a region R32a in the second semiconductor layer L2a, and the region R32a overlaps the second memory cell array region R_BA2a in the first semiconductor layer L1a in the third direction D3. Therefore, the second normal bit line sense amplifier NBLSA2 and the second sub word line driver SWD2 may be disposed under the second normal memory cell NMC2 (e.g., under the second memory cell array BA2a). For example, the region R32a may be formed adjacent to a second side of the second region R2a opposite to the first side of the second region R2a.

[0088] Reference Figure 7B The sub-word line drivers SWD1 and SWD2, the memory cells NMC1, NMC2, EMC1 and EMC2, and the connection of the lines will be described and will be referred to Figure 8B and Figure 8C The bit line sense amplifiers NBLSA1, NBLSA2, EBLSA1, and EBLSA2, the memory cells NMC1, NMC2, EMC1, and EMC2, and the connections of the lines are described.

[0089] The first bank column decoder BCDEC1 may be disposed in a first bank column decoder region R41a in the second semiconductor layer L2a, and the second bank column decoder BCDEC2 may be disposed in a second bank column decoder region R42a in the second semiconductor layer L2a. For example, the first bank column decoder region R41a may be formed to be adjacent to the region R31a in the second direction D2, wherein the first normal bit line sense amplifier NBLSA1 and the first sub word line driver SWD1 are disposed in the region R31a, and the second bank column decoder region R42a may be formed to be adjacent to the region R32a in the second direction D2, wherein the second normal bit line sense amplifier NBLSA2 and the second sub word line driver SWD2 are disposed in the region R32a.

[0090] The first intermediate circuit INTMID1 may be disposed in a region R43a in the second semiconductor layer L2a. For example, the region R43a may be formed adjacent to the second region R2a in the second direction D2 and adjacent to the first memory column decoder region R41a and the second memory column decoder region R42a in the first direction D1. For example, the region R43a may be disposed at a position where the first memory column decoder region R41a and the second memory column decoder region R42a cross when they extend in the first direction D1 and the second region R2a extends in the second direction D2.

[0091] Conventionally, the first region R1a between the adjacent first memory array BA1a and the second memory array BA2a in the first semiconductor layer L1a is an empty space, the ECC memory cells are arranged in the first memory array BA1a and the second memory array BA2a, and the first memory row decoder BRDEC1 is arranged in the second semiconductor layer L2a in the second region R2a below the first region R1a. In the memory device 10a according to the example embodiment, the positioning (or location) of the first ECC memory cell EMC1 and the second ECC memory cell EMC2 can be moved to the first region R1a overlapping the second region R2a. In addition, the positioning of the ECC bit line sense amplifiers EBLSA1 and EBLSA2 for driving the first ECC memory cell EMC1 and the second ECC memory cell EMC2 can be moved to the second region R2a. Therefore, the size of the memory device 10a can be reduced.

[0092] although Figure 5 An example of the arrangement of two memory cell arrays BA1a and BA2a and related components is shown, but the example embodiments are not limited thereto. For example, a plurality of memory cell arrays may be arranged to be spaced apart along a first direction D1, ECC memory cells may be arranged between the memory cell arrays, and memory cell row decoders may be arranged under the ECC memory cells between the memory cell arrays. In addition, the above-mentioned memory cell arrays arranged along the first direction D1 may form a memory cell group, a plurality of memory cell groups may be arranged along a second direction D2, and the ECC memory cells and memory cell row decoders may be arranged similarly to those described above.

[0093] Figure 6 , Fig. 7A , Figure 7B , Fig. 8A , Figure 8B , Figure 8C and Fig. 9 Is used to describe Figure 5 Schematic diagram of an example memory device.

[0094] refer to Figure 6, shows an example in which the first memory bank row decoder BRDEC1 drives the first memory bank array BA1a and the second memory bank array BA2a.

[0095] The first memory array BA1a may include first normal memory cells NMC1L and NMC1R respectively disposed in the left and right halves of the first memory array BA1a, and the second memory array BA2a may include second normal memory cells NMC2L and NMC2R respectively disposed in the left and right halves of the second memory array BA2a.

[0096] More specifically, the first portion NMC1R of the first normal memory cells NMC1L and NMC1R may be placed in a partial area (e.g., the right half area) of the first memory array BA1a, and the second portion NMC1L of the first normal memory cells NMC1L and NMC1R may be placed in another partial area (e.g., the left half area) of the first memory array BA1a. Similarly, the first portion NMC2L of the second normal memory cells NMC2L and NCM2R may be placed in a partial area (e.g., the left half area) of the second memory array BA2a, and the second portion NMC2R of the second normal memory cells NMC2L and NCM2R may be placed in another partial area (e.g., the right half area) of the second memory array BA2a.

[0097] The first bank row decoder BRDEC1 may be connected to only the first portion NMC1R of the first normal memory cells NMC1L and NMC1R and the first portion NMC2L of the second normal memory cells NMC2L and NCM2R, and may drive only the first portion NMC1R of the first normal memory cells NMC1L and NMC1R and the first portion NMC2L of the second normal memory cells NMC2L and NCM2R. For example, the first portion NMC1R of the first normal memory cells NMC1L and NMC1R may be the first portion NMC1R of the first normal memory cells NMC1L and NMC1R that is connected to the first portion NMC1R of the second normal memory cells NMC2L and NCM2R. Figure 5 The right half normal memory cells adjacent to the first region R1a in the embodiment, and the first part NMC2L of the second normal memory cells NMC2L and NCM2R may be the ... Figure 5 The left half of the normal memory cells adjacent to the first region R1a in FIG. Figure 5 The first ECC memory cell EMC1 in the first region R1a in the embodiment may be an ECC memory cell corresponding to a first portion NMC1R of the first normal memory cells NMC1L and NMC1R, and Figure 5The second ECC memory cell EMC2 in the first region R1a in the EMBODIMENT may be an ECC memory cell corresponding to the second normal memory cell NMC2L and the first portion NMC2L of NCM2R.

[0098] Although not shown in detail, the ECC memory cell corresponding to the second portion NMC1L of the first normal memory cells NMC1L and NMC1R may be positioned adjacent to the left side of the first memory array BA1a, and a memory row decoder driving the second portion NMC1L of the first normal memory cells NMC1L and NMC1R and the corresponding ECC memory cell may be positioned below the corresponding ECC memory cell. Similarly, the ECC memory cell corresponding to the second portion NMC2R of the second normal memory cells NMC2L and NCM2R may be positioned adjacent to the right side of the second memory array BA2a, and a memory row decoder driving the second portion NMC2R of the second normal memory cells NMC2L and NCM2R and the corresponding ECC memory cell may be positioned below the corresponding ECC memory cell.

[0099] refer to Fig. 7A , shows an example of a schematic circuit structure of each of the sub-word line drivers SWD1 and SWD2 according to one or more embodiments.

[0100] The sub word line driver 410 may be connected to the word line WL and may have a circuit structure for driving the word line WL. For example, the sub word line driver 410 may include transistors PT11, NT11, and NT12 connected to the word line WL through a node ND11.

[0101] The transistor PT11 may be connected between the drive signal PXID and the node ND11, and may pull up the word line WL to the voltage level of the drive signal PXID in response to the word line enable signal NWEIB. The transistor NT11 may be connected between the node ND11 and the first negative voltage VBB1, and may pull down the word line WL to the voltage level of the first negative voltage VBB1 in response to the word line enable signal NWEIB. The transistor NT12 may be connected between the node ND11 and the second negative voltage VBB2, and may maintain the word line WL at the voltage level of the second negative voltage VBB2 when the word line WL is deactivated. For example, the transistor NT12 may switch between the source provided with the second negative voltage VBB2 and the drain connected to the word line WL in response to the drive signal PXIB complementary to the drive signal PXID. When the drive signal PXIB is at a logic high level, the transistor NT12 will be turned on, thereby maintaining the word line WL (and the node ND11) at the second negative voltage level VBB2. For example, the driving signals PXID and PXIB, the word line enable signal NWEIB, and the negative voltages VBB1 and VBB2 may be provided from an external voltage generator.

[0102] In some example embodiments, transistor PT11 may be a p-type metal oxide semiconductor (PMOS) transistor, and each of transistors NT11 and NT12 may be an n-type metal oxide semiconductor (NMOS) transistor. For example, transistors PT11, NT11, and NT12 may be referred to as a pull-up transistor, a pull-down transistor, and a holding transistor, respectively.

[0103] However, example embodiments are not limited thereto, and each sub word line driver is not limited to Fig. 7A The structure shown.

[0104] refer to Figure 7B , showing an example of connection between the first normal memory cell NMC1′ and the first sub word line driver SWD1′ and connection between the first ECC memory cell EMC1′ and the first sub word line driver SWD1″.

[0105] The first normal memory cell NMC1′ in the first bank array region R_BA1a in the first semiconductor layer L1a and the first sub word line driver SWD1′ in the region R31a in the second semiconductor layer L2a may be electrically connected to each other through a vertical line (or wire) VL_WN1 extending in the third direction D3 and a word line WL_N1 extending in the first direction D1.

[0106] The first ECC memory cell EMC1′ in the first ECC cell region R_EC1a in the first region R1a in the first semiconductor layer L1a and the first sub word line driver SWD1″ in the region R31a in the second semiconductor layer L2a may be electrically connected to each other through a vertical line (or wire) VL_WE1 extending in the third direction D3 and a word line WL_E1 extending in the first direction D1.

[0107] Relative to the vertical lines VL_WN1 and VL_WE1, the direction in which the word line WL_N1 connected to the first normal memory cell NMC1' extends and the direction in which the word line WL_E1 connected to the first ECC memory cell EMC1' extends may be opposite to each other. For example, the intersection of the vertical lines VL_WN1 and VL_WE1 and the word lines WL_N1 and WL_E1 may be arranged between the first memory array area R_BA1a and the first ECC cell area R_EC1a, and relative to the intersection, the word line WL_N1 may extend to the left, and the word line WL_E1 may extend to the right. In other words, the word lines WL_N1 and WL_E1 may be implemented in the form of extending two arms based on the intersection.

[0108] In some example embodiments, each of the vertical lines VL_WN1 and VL_WE1 may include Figure 2 The bonding pads PD_L1 and PD_L2 and the contacts CT_L1 and CT_L2 in FIG.

[0109] The first normal memory cell NMC1′, the first ECC memory cell EMC1′, and the first sub-word line drivers SWD1′ and SWD1″ may be respectively included in Figure 5 In the first normal memory cell NMC1, the first ECC memory cell EMC1 and the first sub word line driver SWD1. Figure 5 The connection between the first normal memory cell NMC1 and the first part of the first sub word line driver SWD1 in the embodiment may be substantially the same as the connection between the first normal memory cell NMC1′ and the first sub word line driver SWD1′, and Figure 5 The connection between the first ECC memory cell EMC1 and the second part of the first sub word line driver SWD1 in may be substantially the same as the connection between the first ECC memory cell EMC1 ′ and the first sub word line driver SWD1 ″.

[0110] Although not shown in detail, connections between the second normal memory cells NMC2 and the second ECC memory cells EMC2 and the second sub word line driver SWD2 may be substantially the same as the above-described connections between the first normal memory cells NMC1 and the first ECC memory cells EMC1 and the first sub word line driver SWD1 .

[0111] refer to Fig. 8A , shows an example of a schematic circuit structure of each of the bit line sense amplifiers NBLSA1, NBLSA2, EBLSA1, and EBLSA2 according to one or more embodiments.

[0112] The bit line sense amplifier 420 may be connected to the bit line BL and may have a circuit structure for driving the bit line BL. For example, the bit line sense amplifier 420 may include transistors PT21, PT22, NT21, and NT22, which are connected to the control line LA and the complementary control line LAB through nodes ND21 and ND22, respectively, and are connected to the bit line BL and the complementary bit line BLB through nodes ND23 and ND24, respectively.

[0113] The transistor PT21 may be connected between the node ND23 and the node ND21, and may have a gate electrode connected to the node ND24. The transistor PT22 may be connected between the node ND21 and the node ND24, and may have a gate electrode connected to the node ND23. The transistor NT21 may be connected between the node ND23 and the node ND22, and may have a gate electrode connected to the node ND24. The transistor NT22 may be connected between the node ND22 and the node ND24, and may have a gate electrode connected to the node ND23. Depending on the operation of turning on and / or off the transistors PT21, PT22, NT21, NT22 included in the bit line sense amplifier 420, various operations for the bit line BL, such as a precharge operation, an offset cancellation operation, a charge sharing operation, a developing and a read operation, etc., may be performed.

[0114] In addition, the bit line BL and the complementary bit line BLB can be connected to the global input / output (I / O) line GIO and the complementary global I / O line GIOB through transistors NT23 and NT24, respectively. The gate electrodes of transistors NT23 and NT24 can be connected to the column selection line CSL. When transistors NT23 and NT24 become conductive, read data can be output.

[0115] In some example embodiments, each of the transistors PT21 and PT22 may be a PMOS transistor, and each of the transistors NT21, NT22, NT23, and NT24 may be an NMOS transistor. However, example embodiments are not limited thereto, and each bit line sense amplifier is not limited to Fig. 8A The structure shown in .

[0116] refer to Figure 8B, shows an example of connection between the first normal memory cell NMC1′ and the first normal bit line sense amplifier NBLSA1′ and connection between the first ECC memory cell EMC1′ and the first ECC bit line sense amplifier EBLSA1′ according to one or more embodiments.

[0117] The first normal memory cell NMC1′ in the first bank array region R_BA1a in the first semiconductor layer L1a and the first normal bit line sense amplifier NBLSA1′ in the region R31a in the second semiconductor layer L2a may be electrically connected to each other through a vertical line (or wire) VL_BN1 extending in the third direction D3 and a bit line BL_N1 extending in the second direction D2.

[0118] The first ECC memory cell EMC1′ in the first ECC cell region R_EC1a in the first region R1a in the first semiconductor layer L1a and the first ECC bit line sense amplifier EBLSA1′ in the second region R2a in the second semiconductor layer L2a may be electrically connected to each other through a vertical line VL_BE1 extending in the third direction D3 and a bit line BL_E1 extending in the second direction D2.

[0119] In some example embodiments, each of the vertical lines VL_BN1 and VL_BE1 may include Figure 2 The bonding pads PD_L1 and PD_L2 and the contacts CT_L1 and CT_L2 in FIG.

[0120] The first normal memory cell NMC1 ′, the first ECC memory cell EMC1 ′, the first normal bit line sense amplifier NBLSA1 ′, and the first ECC bit line sense amplifier EBLSA1 ′ may be respectively included in Figure 5 The first normal memory cell NMC1, the first ECC memory cell EMC1, the first normal bit line sense amplifier NBLSA1 and the first ECC bit line sense amplifier EBLSA1 are included in the memory. Figure 5 The connection between the first normal memory cell NMC1 and the first normal bit line sense amplifier NBLSA1 in the embodiment may be substantially the same as the connection between the first normal memory cell NMC1′ and the first normal bit line sense amplifier NBLSA1′, and Figure 5 The connection between the first ECC memory cell EMC1 and the first ECC bit line sense amplifier EBLSA1 in EMBODIMENT 3 may be substantially the same as the connection between the first ECC memory cell EMC1 ′ and the first ECC bit line sense amplifier EBLSA1 ′.

[0121] Although not shown in detail, the connection between the second normal memory cell NMC2 and the second ECC memory cell EMC2 and the second normal bit line read amplifier NBLSA2 and the second ECC bit line read amplifier EBLSA2 can be basically the same as the connection between the above-mentioned first normal memory cell NMC1 and the first ECC memory cell EMC1 and the first normal bit line read amplifier NBLSA1 and the first ECC bit line read amplifier EBLSA1.

[0122] refer to Figure 8C , showing an example of connections between first and second ECC bit line sense amplifiers EBLSA1 and EBLSA2 and lines CSL1, GIO1, CSL2, and GIO2 according to one or more embodiments.

[0123] In the second semiconductor layer L2a, a first column selection line CSL1 and a first global I / O line GIO1 connected to the first ECC bit line sense amplifier EBLSA1 in the second region R2a and a second column selection line CSL2 and a second global I / O line GIO2 connected to the second ECC bit line sense amplifier EBLSA2 in the second region R2a may be formed in an empty space in the region R43a. For example, the first column selection line CSL1 and the first global I / O line GIO1 may be placed in an empty space to the left of the first middle circuit INTMID1 in the region R43a, and the second column selection line CSL2 and the second global I / O line GIO2 may be placed in an empty space to the right of the first middle circuit INTMID1 in the region R43a.

[0124] Although not described in detail, an I / O sense amplifier, a global I / O line driver, and / or an MDL that drives the first and second ECC memory cells EMC1 and EMC2 may be formed in an empty space in the region R43a.

[0125] refer to Fig. 9 , shows an example of connection between the first bank row decoder BRDEC1 and the line L_BRD1 according to one or more embodiments.

[0126] The line L_BRD1 connected to the first memory row decoder BRDEC1 in the second region R2a in the second semiconductor layer L2a may be disposed in a region other than the first ECC cell region R_EC1a and the second ECC cell region R_EC2a in the first region R1a in the first semiconductor layer L1a. For example, the line L_BRD1 connected to the first memory row decoder BRDEC1 may be disposed between the first ECC cell region R_EC1a and the second ECC cell region R_EC2a in the first region R1a in the first semiconductor layer L1a. In other words, the first ECC memory cell EMC1 and the second ECC memory cell EMC2 may be first disposed in a portion of the first region R1a, and then the remaining region in the first region R1a may be used as a bus region.

[0127] For example, the first bank row decoder BRDEC1 and the line L_BRD1 may be electrically connected via a vertical line VL_BRD1. For example, each of the vertical lines VL_BRD1 may include Figure 2 For example, the first bank row decoder BRDEC1 may be connected to other components of the memory device through line L_BRD1.

[0128] Fig.10 yes Figure 1 1 is a schematic perspective view of at least a portion of an example memory device 10.

[0129] refer to Fig.10 The memory device 10b includes a first semiconductor layer L1b and a second semiconductor layer L2b stacked in the third direction D3. Figure 1 and Figure 5 Descriptions of duplicate or overlapping descriptions.

[0130] The first semiconductor layer L1b may include a first memory bank array BA1b. The first memory bank array BA1b may include first normal memory cells NMC11 and NMC12 storing first normal data.

[0131] The first semiconductor layer L1b may include first ECC memory cells EMC11 and EMC12. The first ECC memory cells EMC11 and EMC12 may correspond to first normal memory cells NMC11 and NMC12, respectively, and may store first ECC data associated with first normal data.

[0132] The first memory bank array BA1b may include Figure 1 and Figure 2 The memory cell array MCA in the embodiment of the present invention may correspond to Figure 3The first normal memory cells NMC11 and NMC12 may include one of the first memory bank array 310 to the eighth memory bank array 380 in the embodiment of the present invention. Figure 1 and Figure 2 The first ECC memory cells EMC11 and EMC12 may include Figure 1 and Figure 2 In the multiple ECC memory cells EMC.

[0133] The first memory array BA1b may be disposed in the first memory array region R_BA1b in the first semiconductor layer L1b. The first normal memory cell NMC11 may be disposed in the first sub-region R_BA11b in the first memory array region R_BA1b, and the first normal memory cell NMC12 may be disposed in the second sub-region R_BA12b in the first memory array region R_BA1b. For example, the first sub-region R_BA11b and the second sub-region R_BA12b may be arranged to be spaced apart from each other in the first direction D1.

[0134] The first ECC memory cells EMC11 and EMC12 may be disposed in the first region R1b included in the first memory array region R_BA1b in the first semiconductor layer L1b. For example, the first region R1b may be formed at the center of the first memory array region R_BA1b between the first sub-region R_BA11b and the second sub-region R_BA12b or at the center of the first memory array region R_BA1b between the adjacent first sub-region R_BA11b and the second sub-region R_BA12b. For example, the first ECC memory cell EMC11 may be disposed in the first region R1b to correspond to and be adjacent to the first normal memory cell NMC11 (for example, adjacent to the first sub-region R_BA11b), and the first ECC memory cell EMC12 may be disposed in the first region R1b to correspond to and be adjacent to the first normal memory cell NMC12 (for example, adjacent to the second sub-region R_BA12b).

[0135] The second semiconductor layer L2b may include a first bank row decoder BRDEC11. The first bank row decoder BRDEC11 may drive the first normal memory cells NMC11 and NMC12 and the first ECC memory cells EMC11 and EMC12 (eg, may drive the first bank array BA1b). Fig.11 As described, the first bank row decoder BRDEC11 may drive a portion of the first normal memory cells NMC11 and NMC12.

[0136] The second semiconductor layer L2b may include first normal bit line sense amplifiers NBLSA11 and NBLSA12 and first ECC bit line sense amplifiers EBLSA11 and EBLSA12. The first normal bit line sense amplifiers NBLSA11 and NBLSA12 may drive first normal memory cells NMC11 and NMC12, respectively. The first ECC bit line sense amplifiers EBLSA11 and EBLSA12 may drive first ECC memory cells EMC11 and EMC12, respectively.

[0137] The second semiconductor layer L2b may include first sub word line drivers SWD11 and SWD12. The first sub word line drivers SWD11 and SWD12 may drive the first normal memory cells NMC11 and NMC12 and the first ECC memory cells EMC11 and EMC12 and may be shared by the first normal memory cells NMC11 and NMC12 and the first ECC memory cells EMC11 and EMC12.

[0138] The second semiconductor layer L2b may include first bank column decoders BCDEC11 and BCDEC12 and a first intermediate circuit INTMID11. The first bank column decoders BCDEC11 and BCDEC12 may drive the first normal memory cells NMC11 and NMC12 and the first ECC memory cells EMC11 and EMC12. The first intermediate circuit INTMID11 may be connected to the first bank row decoder BRDEC11 and may be used to drive the first normal memory cells NMC11 and NMC12 and the first ECC memory cells EMC11 and EMC12.

[0139] The first bank row decoder BRDEC11 may include Figure 1 and Figure 2 The row decoder RDEC in the Figure 3 The first normal bit line sense amplifiers NBLSA11 and NBLSA12 and the first ECC bit line sense amplifiers EBLSA11 and EBLSA12 may include one of the first memory bank row decoder 260a to the eighth memory bank row decoder 260h in the embodiment. Figure 2 The bit line sense amplifier BLSA and may be included in Figure 3 The first sub-word line drivers SWD11 and SWD12 may include Figure 2 The sub-word line driver SWD can be placed in Figure 3 between the row decoder 260 and the memory cell array 300, and can be used to drive Figure 3 The first bank column decoders BCDEC11 and BCDEC12 may include Figure 2 In the column decoder CDEC, and each of the first bank column decoders BCDEC11 and BCDEC12 may correspond to Figure 3 The first intermediate circuit INTMID11 may correspond to one of the first memory column decoder 270a to the eighth memory column decoder 270h. Figure 3 At least a portion of the front end of the first memory bank row decoder 260a to the eighth memory bank row decoder 260h.

[0140] In the second semiconductor layer L2b, the first bank row decoder BRDEC11, the first normal bit line sense amplifiers NBLSA11 and NBLSA12, the first ECC bit line sense amplifiers EBLSA11 and EBLSA12, the first sub word line drivers SWD11 and SWD12, the first bank column decoders BCDEC11 and BCDEC12, and the first intermediate circuit INTMID11 may be arranged similarly to the reference Figure 5 Those described.

[0141] For example, the first memory row decoder BRDEC11 may be disposed in a second region R2b in the second semiconductor layer L2b, the second region R2b overlapping the first region R1b in the first semiconductor layer L1b in the third direction D3. The first ECC bit line sense amplifiers EBLSA11 and EBLSA12 may be disposed in the second region R2b in the second semiconductor layer L2b. The first normal bit line sense amplifier NBLSA11 and the first sub-word line driver SWD11 may be disposed in a region R31b in the second semiconductor layer L2b, the region R31b overlapping the first sub-region R_BA11a in the first semiconductor layer L1b in the third direction D3. The first normal bit line sense amplifier NBLSA12 and the first sub-word line driver SWD12 may be disposed in a region R32b in the second semiconductor layer L2b, the region R32b overlapping the second sub-region R_BA12b in the first semiconductor layer L1b in the third direction D3. The first bank column decoders BCDEC11 and BCDEC12 may be disposed in first bank column decoder regions R41b and R42b in the second semiconductor layer L2b, respectively. The first intermediate circuit INTMID11 may be disposed in a region R43b in the second semiconductor layer L2b.

[0142] Conventionally, the ECC memory cells EMC11 and EMC12 are arranged in a memory array BA1b in the first semiconductor layer L1b, and the first memory row decoder is arranged so as not to overlap with the memory array region R_BA1b in the second semiconductor layer L2b. In the memory device 10b according to the example embodiment, the positioning of the first memory row decoder BRDEC11 can be moved to the second region R2b overlapping with the first region R1b where the ECC memory cells EMC11 and EMC12 are arranged. In addition, in order to obtain a space for arranging the first memory row decoder BRDEC11, the arrangement of other components (for example, the arrangement of the bit line sense amplifiers NBLSA11, NBLSA12, EBLSA11 and EBLSA12 and / or the sub word line drivers SWD11 and SWD12) can be partially changed. Therefore, the size of the memory device 10b can be reduced.

[0143] Fig.11 is used to describe according to one or more embodiments Fig.10 Schematic diagram of a memory device.

[0144] refer to Fig.11 , shows an example in which the first memory bank row decoder BRDEC11 drives the first memory bank array BA1b.

[0145] The first bank array BA1b may include first normal memory cells NMC11L, NMC11R, NMC12L, and NCM12R. The first bank row decoder BRDEC11 may be connected to only the first portion NMC11R and NMC12L of the first normal memory cells NMC11L, NMC11R, NMC12L, and NCM12R, and may drive only the first portion NMC11R and NMC12L of the first normal memory cells NMC11L, NMC11R, NMC12L, and NCM12R. For example, Fig.10 The first ECC memory cells EMC11 and EMC12 in the first region R1b in the EMBODIMENT may be ECC memory cells corresponding to the first parts NMC11R, NMC12L of the first normal memory cells NMC11L, NMC11R, NMC12L, and NMC12R.

[0146] In some example embodiments, Fig.10 The connections between the sub-word line drivers SWD11 and SWD12 and the memory cells NMC11, NMC12, EMC11 and EMC12 can be the same as those in the reference Figure 7B In some example embodiments, Fig.10The connections between the bit line sense amplifiers NBLSA11, NBLSA12, EBLSA11 and EBLSA12 and the memory cells NMC11, NMC12, EMC11, EMC12 and Fig.10 The connections between the bit line sense amplifiers NBLSA11, NBLSA12, EBLSA11 and EBLSA12 and the lines can be connected with the reference Figure 8B and Figure 8C In some example embodiments, the connections described are substantially the same. Fig.10 There may be no vacant space in the first region R1b of the first memory bank array region R_BA1b in FIG. Fig.10 The memory device 10b may omit the reference Fig. 9 The configuration described is that the lines connected to the first bank row decoder BRDEC11 are arranged in the first region R1b.

[0147] Fig. 12A and Fig. 12B is a schematic perspective view of a memory device according to an example embodiment. Figure 1 Descriptions of duplicate or overlapping descriptions.

[0148] refer to Fig. 12A , the memory device 12 includes a first semiconductor layer L1, a second semiconductor layer L2, and a third semiconductor layer L3. In addition to the memory device 12 also including the third semiconductor layer L3, Fig. 12A The example can be compared with Figure 1 The examples are basically the same.

[0149] The first semiconductor layer L1, the second semiconductor layer L2, and the third semiconductor layer L3 are arranged or stacked in the third direction D3. Fig. 12A An example is shown in which the first semiconductor layer L1 and the third semiconductor layer L3 are respectively arranged above and below the second semiconductor layer L2, but the example embodiments are not limited thereto. For example, both the first semiconductor layer L1 and the third semiconductor layer L3 can be arranged above or below the second semiconductor layer L2. It should be understood that although ordinal terms such as "first", "second", "third", etc. can be used to describe various elements in this article, these elements should not be limited by such terms. These terms are only used to distinguish one element from another element and are not used to convey any specific order of the corresponding elements. For example, without departing from the scope of the present disclosure, the first element can be referred to as the second element, and similarly, the second element can be referred to as the first element.

[0150] Like the first semiconductor layer L1, the third semiconductor layer L3 may include a memory cell array MCA and may be referred to as a memory cell region or a cell wafer. For example, the memory cell array MCA included in the first semiconductor layer L1 may be referred to as a first memory cell array, and the memory cell array MCA included in the third semiconductor layer L3 may be referred to as a second memory cell array.

[0151] Each of the memory cell arrays MCA of the first semiconductor layer L1 and the third semiconductor layer L3 may include a plurality of normal memory cells NMC and a plurality of ECC memory cells EMC, respectively. The plurality of ECC memory cells EMC in the first semiconductor layer L1 and the third semiconductor layer L3 and the row decoder RDEC in the second semiconductor layer L2 may be arranged to partially and / or completely overlap in a plan view or on a plane.

[0152] refer to Fig. 12B , the memory device 14 includes a first semiconductor layer L1, a second semiconductor layer L2, and a fourth semiconductor layer L4. In addition to the memory device 14 also including the fourth semiconductor layer L4, Fig. 12B The example can be compared with Figure 1 The examples are basically the same.

[0153] The first semiconductor layer L1, the second semiconductor layer L2, and the fourth semiconductor layer L4 are arranged or stacked in the third direction D3. Fig. 12B An example is shown in which the fourth semiconductor layer L4 and the second semiconductor layer L2 are disposed on and under the first semiconductor layer L1, respectively, but example embodiments are not limited thereto. For example, both the second semiconductor layer L2 and the fourth semiconductor layer L4 may be disposed on or under the first semiconductor layer L1.

[0154] Like the second semiconductor layer L2, the fourth semiconductor layer L4 may include a peripheral circuit PCKT and may be referred to as a peripheral circuit region or a peripheral wafer. For example, the peripheral circuit PCKT included in the second semiconductor layer L2 may be referred to as a first peripheral circuit, and the peripheral circuit PCKT included in the fourth semiconductor layer L4 may be referred to as a second peripheral circuit.

[0155] The peripheral circuits PCKT of the second and fourth semiconductor layers L2 and L4 may include row decoders RDEC, respectively. The plurality of ECC memory cells EMC in the first semiconductor layer L1 and the row decoders RDEC in the second and fourth semiconductor layers L2 and L4 may be arranged to partially and / or completely overlap in a plan view or on a plane.

[0156] Although not described in detail, a memory device according to example embodiments may include four or more semiconductor layers that are stacked.

[0157] Fig.13A and Fig. 13B is a schematic cross-sectional view of a memory package according to example embodiments.

[0158] refer to Fig.13A , the memory package 700 includes a base substrate 710 and a plurality of memory chips CHP1 , CHP2 , and CHP3 vertically stacked on the base substrate 710 .

[0159] Each of the memory chips CHP1 to CHP3 may include a memory cell layer CLY and a peripheral circuit layer PLY, and may further include a plurality of I / O pads IOPAD. The memory cell layer CLY and the peripheral circuit layer PLY may correspond to reference 4, 5, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54 Figure 1 The first semiconductor layer L1 and the second semiconductor layer L2 described herein may further include the elements described herein respectively included in the first semiconductor layer L1 and the second semiconductor layer L2 according to any example embodiment described herein. Each of the memory chips CHP1 to CHP3 may include a memory device according to example embodiments, and may be implemented such that the ECC memory cell EMC and the row decoder RDEC included in different semiconductor layers L1 and L2 are arranged to partially and / or completely overlap in a plan view or on a plane.

[0160] In some example embodiments, the memory chips CHP1 to CHP3 may be stacked on the substrate substrate 710 so that the surface on which a plurality of I / O pads IOPAD are formed faces upward. In some example embodiments, relative to each of the memory chips CHP1 to CHP3, a plurality of I / O pads IOPAD may be arranged near one side of the semiconductor substrate. In this way, the memory chips CHP1 to CHP3 may be stacked in proportion, that is, stacked in a stepped shape so that a plurality of I / O pads IOPAD of each memory chip may be exposed. In such a stacked state, the memory chips CHP1 to CHP3 may be electrically connected to the substrate substrate 710 by a plurality of bonding wires BW.

[0161] The stacked memory chips CHP1 to CHP3 and the plurality of bonding wires BW may be fixed by a sealing member (e.g., sealant) 740, and an adhesive member 730 may be disposed between the base substrate 710 and each of the adjacent memory chips CHP1 to CHP3. Conductive bumps 720 may be formed on the bottom surface of the base substrate 710 for providing electrical connection with an external device.

[0162] refer to Fig. 13B , the memory package 800 includes a substrate substrate 810 and a plurality of memory chips CHP1 to CHP3 stacked on the substrate substrate 810. For the sake of brevity, the memory package 800 is omitted. Fig.13ADescriptions of duplicate or overlapping descriptions.

[0163] Each of the memory chips CHP1 to CHP3 may include a vertically stacked memory cell layer CLY and a peripheral circuit layer PLY, and may further include a plurality of through silicon vias (TSVs) 830 .

[0164] In some example embodiments, with respect to each of the memory chips CHP1 to CHP3, a plurality of TSVs 830 may be arranged at the same position in each memory chip. In this way, the memory chips CHP1 to CHP3 may be stacked vertically (i.e., in the third direction D3), so that the plurality of TSVs 830 of each memory chip may be completely overlapped (e.g., the arrangement of the plurality of TSVs 830 may be perfectly matched (i.e., vertically aligned) in the memory chips CHP1 to CHP3). In such a stacked state, the memory chips CHP1 to CHP3 may be electrically connected to each other and to the substrate substrate 810 through the plurality of TSVs 830 and the conductive material 840 between the vertically adjacent TSVs 830.

[0165] The conductive bump 820 and the sealing member 850 may be respectively Fig.13A The conductive bumps 720 and the sealing member 740 in FIG. 7 are substantially the same.

[0166] Fig.14 is a block diagram illustrating a memory system according to example embodiments.

[0167] refer to Fig.14 , the memory system 1000 includes a memory controller 1200 and a memory device 1400. The memory system 1000 may further include a plurality of signal lines 1300 electrically connecting the memory controller 1200 and the memory device 1400.

[0168] The memory device 1400 may be controlled by the memory controller 1200. For example, based on a request from a host (not illustrated), the memory controller 1200 may store (e.g., write or program) data in the memory device 1400, or may retrieve (e.g., read or read out) data from the memory device 1400. The memory device 1400 may be a memory device according to example embodiments, and may be implemented such that the ECC memory cells EMC and the row decoders RDEC included in different semiconductor layers L1 and L2 are arranged to partially and / or completely overlap in a plan view or on a plane.

[0169] The plurality of signal lines 1300 may include a control line, a command line, an address line, a data input / output (I / O) line, and a power line. The memory controller 1200 may transmit a command CMD, an address ADDR, and a control signal CTRL to the memory device 1400 via the command line, the address line, and the control line, may exchange a data signal DS with the memory device 1400 via the data I / O line, and may transmit a power supply voltage PWR to the memory device 1400 via the power line. Although not shown in detail, the plurality of signal lines 1300 may further include a DQS line for transmitting a data strobe signal (DQS) signal.

[0170] Example embodiments may be applied to various electronic devices and systems including memory devices. For example, example embodiments may be applied to systems such as personal computers (PCs), server computers, data centers, workstations, mobile phones, smart phones, tablet computers, laptop computers, personal digital assistants (PDAs), portable multimedia players (PMPs), digital cameras, portable game consoles, music players, video cameras, video players, navigation devices, wearable devices, Internet of Things (IoT) devices, Internet of Everything (IoE) devices, e-book readers, virtual reality (VR) devices, augmented reality (AR) devices, robotic devices, drones, cars, etc.

[0171] The foregoing is an illustration of example embodiments and should not be construed as limiting thereof. Although some example embodiments have been described, those skilled in the art will readily appreciate that many modifications may be made in the example embodiments without substantially departing from the novel teachings and advantages of the example embodiments. Therefore, all such modifications are intended to be included within the scope of the example embodiments defined in the claims. Therefore, it should be understood that the foregoing is an illustration of various example embodiments and should not be construed as being limited to the specific example embodiments disclosed, and modifications to the disclosed example embodiments as well as other example embodiments are intended to be included within the scope of the appended claims.

Claims

1. A memory device, comprising: The first semiconductor layer comprises: a memory cell array connected to a plurality of word lines and a plurality of bit lines, the memory cell array including a plurality of normal memory cells configured to store normal data and a plurality of ECC memory cells configured to store error correction code ECC data, the plurality of word lines extending in a first direction, and the plurality of bit lines extending in a second direction intersecting the first direction; and a second semiconductor layer on the first semiconductor layer in a third direction perpendicular to both the first direction and the second direction, the second semiconductor layer comprising: A peripheral circuit configured to control the memory cell array, the peripheral circuit comprising a row decoder, and At least a portion of a region including the plurality of ECC memory cells in the first semiconductor layer at least partially overlaps with at least a portion of a region including the row decoder in the second semiconductor layer in a plan view.

2. The memory device according to claim 1, in, The plurality of normal memory cells include a first normal memory cell and a second normal memory cell, wherein the plurality of ECC memory cells include a first ECC memory cell and a second ECC memory cell corresponding to the first normal memory cell and the second normal memory cell, respectively; Wherein, the memory cell array further comprises: a first memory bank array and a second memory bank array spaced apart from each other, wherein the first memory bank array and the second memory bank array respectively include the first normal memory cells and the second normal memory cells, Wherein, the row decoder comprises: a first bank row decoder configured to drive the first normal memory cell and the second normal memory cell and the first ECC memory cell and the second ECC memory cell, wherein the first ECC memory cell and the second ECC memory cell are in a first region between the first memory bank array and the second memory bank array in the first semiconductor layer, and The first memory bank row decoder is in a second region in the second semiconductor layer, and the second region at least partially overlaps with the first region in the first semiconductor layer in a plan view.

3. The memory device according to claim 2, in, The peripheral circuit also includes: a first sub word line driver configured to drive the first normal memory cell and the first ECC memory cell, and The first sub-word line driver is in a third region in the second semiconductor layer, and the third region at least partially overlaps with a first memory array region including the first memory array in the first semiconductor layer in the plan view.

4. The memory device according to claim 3, in, The first normal memory cell and the first portion of the first sub word line driver are electrically connected to each other through a first vertical line extending in the third direction and a first word line among the plurality of word lines, wherein the first ECC memory unit and the second portion of the first sub-word line driver are electrically connected to each other through a second vertical line extending in the third direction and a second word line among the plurality of word lines, and Wherein, relative to the first vertical line and the second vertical line, a direction in which the first word line extends and a direction in which the second word line extends are opposite to each other.

5. The memory device according to claim 3, in, The peripheral circuit also includes: a first normal bit line sense amplifier configured to drive the first normal memory cell, and Wherein, the first normal bit line sense amplifier is in the third region in the second semiconductor layer.

6. The memory device according to claim 2, in, The peripheral circuit also includes: a first ECC bit line sense amplifier configured to drive the first ECC memory cell, and Wherein, the first ECC bit line sense amplifier is in the second region in the second semiconductor layer.

7. The memory device according to claim 6, in, The peripheral circuit also includes: a first bank column decoder in a first bank column decoder region in the second semiconductor layer and configured to drive the first normal memory cell and the first ECC memory cell, and Wherein, at least one line connected to the first ECC bit line sense amplifier is in a third region in the second semiconductor layer, the third region being adjacent to the second region in the second semiconductor layer and the first bank column decoder region.

8. The memory device according to claim 6, wherein: The first ECC bit line sense amplifier is adjacent to at least one side of the second region in the second semiconductor layer.

9. The memory device according to claim 2, in, The first ECC memory cell is in a first ECC cell area in the first area in the first semiconductor layer, wherein the second ECC memory cell is in a second ECC cell area in the first area in the first semiconductor layer, and The first ECC unit area is adjacent to the first memory bank array, and the second ECC unit area is adjacent to the second memory bank array.

10. The memory device of claim 9, wherein: At least one line electrically connected to the first bank row decoder is in a region other than the first ECC unit region and the second ECC unit region in the first region in the first semiconductor layer.

11. The memory device according to claim 10, wherein: The at least one line electrically connected to the first bank row decoder is between the first ECC cell area and the second ECC cell area in the first region in the first semiconductor layer.

12. The memory device of claim 2, wherein: The first bank row decoder is configured to drive a portion of the first normal memory cells and the second normal memory cells.

13. The memory device of claim 12, wherein: The first bank row decoder is configured to drive only the portion of the first normal memory cell and the second normal memory cell adjacent to the first region in the first semiconductor layer.

14. The memory device according to claim 1, in, The plurality of normal memory cells include a first normal memory cell, wherein the plurality of ECC memory cells include a first ECC memory cell corresponding to the first normal memory cell, Wherein, the memory cell array further comprises: a first memory array, in a first memory array region in the first semiconductor layer, the first memory array comprising the first normal memory cells, Wherein, the row decoder comprises: a first bank row decoder configured to drive the first normal memory cell and the first ECC memory cell, wherein the first ECC memory cell is in a first region of the first memory bank array region included in the first semiconductor layer, and The first memory bank row decoder is in a second region in the second semiconductor layer, and the second region at least partially overlaps with the first region in the first semiconductor layer in a plan view.

15. The memory device of claim 14, wherein: The first region in the first semiconductor layer is at a center of the first memory array region.

16. The memory device of claim 14, wherein: The first bank row decoder is configured to drive a portion of the first normal memory cells.

17. The memory device of claim 16, wherein: The first bank row decoder is configured to drive only the portion of the first normal memory cells adjacent to the first region in the first semiconductor layer.

18. The memory device according to claim 1, in, The first semiconductor layer further includes a first bonding pad, wherein the second semiconductor layer further comprises a second bonding pad electrically connected to the first bonding pad, and The first semiconductor layer and the second semiconductor layer are electrically connected in the third direction through the first bonding pad and the second bonding pad.

19. A memory package, comprising: substrate substrate; as well as A plurality of memory chips are provided on the substrate. Wherein, each of the plurality of memory chips comprises: The first semiconductor layer comprises: a memory cell array connected to a plurality of word lines and a plurality of bit lines, the memory cell array including a plurality of normal memory cells configured to store normal data and a plurality of ECC memory cells configured to store error correction code ECC data, the plurality of word lines extending in a first direction, and the plurality of bit lines extending in a second direction intersecting the first direction; and a second semiconductor layer on the first semiconductor layer in a third direction perpendicular to both the first direction and the second direction, the second semiconductor layer comprising: A peripheral circuit configured to control the memory cell array, the peripheral circuit comprising a row decoder, and Wherein, at least a portion of a region including the plurality of ECC memory cells in the first semiconductor layer at least partially overlaps with at least a portion of a region including the row decoder in the second semiconductor layer in a plan view.

20. A memory device comprising: The first semiconductor layer comprises: a memory cell array connected to a plurality of word lines extending in a first direction and a plurality of bit lines extending in a second direction intersecting the first direction; and a first bonding pad; and a second semiconductor layer on the first semiconductor layer in a third direction perpendicular to both the first direction and the second direction, the second semiconductor layer comprising: a peripheral circuit configured to control the memory cell array; and a second bonding pad connected to the first bonding pad, Wherein, the memory cell array comprises: a plurality of normal memory cells configured to store normal data, the plurality of normal memory cells including a first normal memory cell and a second normal memory cell spaced apart from each other; and a plurality of error correction code (ECC) memory cells configured to store ECC data, wherein the plurality of ECC memory cells include a first ECC memory cell and a second ECC memory cell corresponding to the first normal memory cell and the second normal memory cell, respectively; Wherein, the peripheral circuit includes: a first row decoder configured to drive the first normal memory cell and the second normal memory cell and the first ECC memory cell and the second ECC memory cell; A first normal bit line sense amplifier and a second normal bit line sense amplifier, configured to drive the first normal memory cell and the second normal memory cell, respectively; a first ECC bit line sense amplifier and a second ECC bit line sense amplifier configured to drive the first ECC memory cell and the second ECC memory cell, respectively; a first sub word line driver configured to drive the first normal memory cell and the first ECC memory cell; and a second sub word line driver configured to drive the second normal memory cell and the second ECC memory cell, wherein the first ECC memory cell and the second ECC memory cell are in a first region between the first normal memory cell and the second normal memory cell in the first semiconductor layer, wherein the first row decoder and the first and second ECC bit line sense amplifiers are in a second region in the second semiconductor layer, the second region at least partially overlapping the first region in the first semiconductor layer in a plan view, and The first normal bit line sense amplifier and the second normal bit line sense amplifier as well as the first sub word line driver and the second sub word line driver are in a third region in the second semiconductor layer, and the third region is adjacent to the second region in the second semiconductor layer.

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