Back-contact battery and its manufacturing method

Abstract

The present application provides a back-contact battery and a method for manufacturing the same, relating to the technical field of back-contact batteries. The back-contact battery includes a silicon wafer, a first semiconductor layer, a second semiconductor layer, crack ink, and a conductive film layer; the crack ink is disposed on the side edge of the second semiconductor opening region and is in direct contact with the second semiconductor layer, and both ends of the crack ink extend a preset distance along the horizontal direction of the silicon wafer; wherein, a plurality of cracks extending to its surface are formed in the crack ink, and the width of the cracks is ≤ 20 μm; the conductive film layer is continuously disposed on the outer surface of the second semiconductor layer, on the crack ink, and in the first semiconductor opening region, and the conductive film layer is disconnected at the cracks on the surface of the crack ink and forms an insulating channel together with the cracks. In the present invention, the deposited conductive film layer is isolated by the crack ink to form an insulating channel, and there is no need to specifically perform a process to form an insulating isolation groove after depositing the conductive film, thereby simplifying the process flow and improving the production yield of the battery.

Description

Technical Field

[0001] This application relates to the technical field of back contact batteries, and particularly to a back contact battery and a method for manufacturing the same. Background Art

[0002] The back contact heterojunction battery combined with the Topcon process for passivation generally uses a tunneling oxide layer as the first intrinsic semiconductor layer, a doped polycrystalline layer as the first conductive semiconductor layer, intrinsic amorphous silicon as the second intrinsic semiconductor layer, and doped amorphous / microcrystalline silicon as the second conductive semiconductor layer. An isolation groove is etched in the upper region corresponding to the mask layer for the conductive film layer.

[0003] However, at the side edge of the second semiconductor opening region, there is a phenomenon that there is only the second intrinsic semiconductor layer (the resistivity of the second intrinsic semiconductor layer is about 10 -1 -10 9 Ω·cm, about 10 -1 -10 3 Ω·cm when it is an N-type amorphous / microcrystalline silicon layer, about 10 4 -10 9 Ω·cm when it is a P-type amorphous / microcrystalline silicon layer) insulating the second conductive semiconductor layer (the resistivity of the second conductive semiconductor layer is about 10 -3 Ω·cm) and the first conductive semiconductor layer (the resistivity of the first conductive semiconductor layer is about 10 5 -10 10 Ω·cm). Although the resistivity of the second intrinsic semiconductor layer is relatively high, its thickness is very thin (about 10 nm). At the same time, because the conductivity of the first conductive semiconductor layer is very good, it is impossible to form good insulation between the first conductive semiconductor layer and the second conductive semiconductor layer. At the same time, the conductive film layer (the resistivity of the conductive film layer ≤ 10 -4 Ω·cm) on the surface of the second conductive semiconductor layer will span the side edge of the second semiconductor opening region in the horizontal direction, making it easy to have a relatively serious leakage phenomenon between the first semiconductor layer and the second semiconductor layer, thereby reducing the parallel resistance of the battery, and further reducing the battery conversion efficiency and the battery yield.

[0004] The Chinese patent with the patent number CN117174776B relates to a back-contact battery and a manufacturing method thereof, including a silicon wafer, a first semiconductor layer, a second semiconductor layer, and a conductive film layer, with isolation grooves formed on the conductive film layer; it further includes: an insulating ink layer, which is provided in several numbers and is arranged at intervals along the back X-axis direction between the second semiconductor layer and the conductive film layer, and the insulating ink layer is in direct contact with the second semiconductor layer, and in the X-axis direction, the insulating ink layer straddles the side edges of the second semiconductor opening area and extends at both ends; wherein, the insulating ink layer satisfies: the surface pencil hardness is not less than 2H, the resistivity is greater than 1e11 Ω·cm, and the mass content of volatile substances in the raw materials of the insulating ink layer is not greater than 5%.

[0005] However, there are still the following improvement points in this patent: After forming the conductive film layer on the insulating ink layer, it is necessary to use laser etching to form insulating grooves on the conductive film layer of the insulating ink layer at the junction of the first semiconductor and the second semiconductor. However, the process window is relatively narrow, and it is difficult to adopt the existing laser process.

[0006] On the other hand, even if only isolation grooves are etched on the conductive film layer of the insulating ink layer without specifying the specific position, it is still necessary to perform a special process to form insulating isolation grooves after depositing the conductive film. At the same time, if the operation is improper, laser etching is likely to damage the battery, thereby affecting the battery conversion efficiency and the battery yield.

[0007] Therefore, there is an urgent need to provide a back-contact battery to solve the above technical problems.

[0008] It should be noted that this part of the content of the present invention only provides the background technology related to the present invention, and does not necessarily constitute the prior art or the well-known technology. Summary of the Invention

[0009] In view of this, the purpose of this application is to provide a back-contact battery and a preparation method thereof, so as to at least solve the problems of complex existing technical processes and easy reduction of battery conversion efficiency and battery yield. The present invention forms crack ink in the area directly above the side of the second semiconductor opening, and then deposits the conductive film layer. The deposited conductive film layer is isolated by the crack ink to form an insulating channel, eliminating the need to perform a special process to form insulating isolation grooves after depositing the conductive film, thereby simplifying the process flow and improving the battery production yield.

[0010] In a first aspect, the present application provides a back-contact battery, comprising a silicon wafer, a first semiconductor layer, a second semiconductor layer, crack ink, and a conductive film layer; the silicon wafer has a front side and a back side; the first semiconductor layer is disposed on the back side of the silicon wafer, and second semiconductor opening regions are uniformly spaced apart on the first semiconductor layer; the second semiconductor layer is continuously disposed on the outer surface of the first semiconductor layer and within the second semiconductor opening regions, and first semiconductor opening regions are arranged at intervals with the second semiconductor opening regions on the second semiconductor layer; the crack ink is disposed on the side edges of the second semiconductor opening regions and is in direct contact with the second semiconductor layer, and both ends of the crack ink extend a preset distance along the horizontal direction of the silicon wafer; wherein, a plurality of cracks extending to its surface are formed within the crack ink, and the width of the cracks ≤ 20 μm; the conductive film layer is continuously disposed on the outer surface of the second semiconductor layer, on the crack ink, and within the first semiconductor opening regions, and the conductive film layer is disconnected at the cracks on the surface of the crack ink and jointly forms an insulating channel with the cracks.

[0011] In some embodiments, the width of both ends of the crack ink along the horizontal direction of the silicon wafer is 20 - 200 μm, the extending distance of one end of the crack ink along the direction of the first semiconductor layer ≥ 10 μm, and the extending distance of the other end of the crack ink along the direction of the second semiconductor opening region ≥ 10 μm.

[0012] In some embodiments, the maximum thickness of the crack ink along the vertical direction of the silicon wafer is 2 - 20 μm.

[0013] In some embodiments, the width of the first semiconductor opening region is 0.15 - 0.5 mm, and the width of the second semiconductor opening region is 0.3 - 0.6 mm.

[0014] In some embodiments, the crack ink is a UV-curable crack ink or a thermosetting crack ink.

[0015] In some embodiments, the UV-curable crack ink is composed of the following components by mass percentage: 70 - 85% resin, 2 - 10% additives, 0.5 - 5% solvent, 5 - 15% fillers, and 1 - 5% photoinitiator.

[0016] In some embodiments, the resin is one or a combination of acrylic resin, phenolic resin, and epoxy resin.

[0017] In some embodiments, the additives are one or a combination of benzophenone, tertiary amine acrylate, polyester solution, polyether compounds, silicone oil, and mineral oil.

[0018] In some embodiments, the solvent is one or a combination of propylene glycol, ethyl acetate, butyl ester, acetone, toluene, and ethanol.

[0019] In some embodiments, the filler is one or a combination of calcium carbonate, magnesium carbonate, barium sulfate, aluminum hydroxide, lithopone, and aluminum silicate.

[0020] In some embodiments, the first semiconductor layer includes a first intrinsic semiconductor film layer and a first conductive semiconductor film layer, and the second semiconductor layer includes a second intrinsic semiconductor film layer and a second conductive semiconductor film layer.

[0021] In some embodiments, the back contact cell further includes a metal electrode, which is disposed on the outer surface of the conductive film layer and within the first semiconductor opening region and the second semiconductor opening region.

[0022] In some embodiments, the back contact cell further includes a front film layer, which is disposed on the front side of the silicon wafer and includes a silicon dielectric passivation layer and a silicon dielectric antireflection layer.

[0023] In some embodiments, the front side of the silicon wafer is a textured surface, and the surface of the silicon wafer at the second semiconductor opening region is a textured surface or a polished surface.

[0024] In a second aspect, the present application further provides a method for manufacturing a back contact cell, and the manufacturing method includes the following steps:

[0025] S101. Form a first semiconductor layer having a second semiconductor opening region on the back side of the silicon wafer, dispose a second semiconductor layer on the outer surface of the first semiconductor layer and within the second semiconductor opening region, and a first semiconductor opening region spaced apart from the second semiconductor opening region is provided on the second semiconductor layer;

[0026] S102. Print and cure on the side edge of the second semiconductor opening region on the back side obtained in S101 to form crack ink;

[0027] Wherein, a plurality of cracks extending to its surface are formed in the crack ink, and the width of the cracks ≤ 20 μm;

[0028] S103. Deposit a conductive film layer on the back side obtained in S102;

[0029] Wherein, the conductive film layer is disconnected at the cracks on the surface of the crack ink and jointly forms an insulating channel with the cracks.

[0030] In some embodiments, in S102, when the crack ink is UV-curable crack ink, UV curing is used to form the crack ink after printing, and the UV curing energy is 500 - 10000 mj / cm 2 , and the UV curing temperature is 50 - 200 °C.

[0031] In some embodiments, in S102, when the crack ink is a thermosetting crack ink, the crack ink is formed by thermal curing after printing. The thermal curing temperature is 150 - 200 °C, and the thermal curing time is 5 - 30 min.

[0032] In some embodiments, before S101, it further includes forming a textured surface on the front side of the silicon wafer and forming a front side film layer.

[0033] In some embodiments, after S103, it further includes forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the regions where the first semiconductor opening region and the second semiconductor opening region are located, respectively.

[0034] In some embodiments, during the process of forming the metal electrodes, the number of cracks in the crack ink increases.

[0035] In some embodiments, during the process of forming the metal electrodes, the width of the cracks in the crack ink increases until it reaches 5 - 20 μm.

[0036] The beneficial effects that this application can achieve are as follows:

[0037] 1. Compared with the prior art where the isolation groove is opened in the first semiconductor region, in the present invention, a crack ink is formed in the region directly above the side of the second semiconductor opening, and then a conductive film layer is deposited. The deposited conductive film layer is isolated by the crack ink to form an insulating channel, which has a larger insulation resistance, can reduce micro - short - circuits, and thus improve the battery efficiency.

[0038] 2. In the prior art, there is also a situation where the isolation groove is opened at the junction of the first semiconductor and the second semiconductor. However, when the isolation groove is opened at the junction of the first semiconductor and the second semiconductor, the process window is narrow, the difficulty of using the laser process is large, and the mass production difficulty is high. If the chemical etching method is used, the process flow will be complicated. While adopting the crack ink technical solution of this application, the process difficulty is small, the process flow is simple, and it has higher mass - productivity.

[0039] 3. In the prior art, there is a situation where an insulating ink layer is used for insulation (such as CN117174776B). However, it still etches an isolation groove in the conductive film layer on the insulating ink layer, and if the operation is improper, laser etching is likely to damage the battery, thereby affecting the battery conversion efficiency and the battery yield. While adopting the crack ink technology of this application, the formed insulating channel has a larger insulation resistance compared with the insulating groove, and there is no need to specifically perform a process to form an insulating isolation groove after depositing the conductive film, thus simplifying the process flow and improving the battery production yield.

[0040] 4. The UV-curable crack ink of the present application comprises 70-85% resin, 2-10% additives, 0.5-5% solvent, 5-15% filler and 1-5% photoinitiator. The crack ink of the present application has stable properties and can be retained on the battery chip for a long time. In a preferred embodiment of the present application, a UV-curable crack ink is used and formed by UV curing after printing. Through specific formulations and process parameters of the crack ink, a number of cracks extending to its surface can be formed in the crack ink, and the width of the cracks is ≤20um. The existence of these cracks can significantly improve the insulation isolation effect.

[0041] 5. In the prior art, the conductive film layer on the surface of the second conductive semiconductor layer will span the side edge of the second semiconductor opening region in the horizontal direction, making it easy for serious leakage to occur between the first semiconductor layer and the second semiconductor layer, thereby reducing the parallel resistance of the battery, and further reducing the battery efficiency and the battery yield. The crack ink of the present application is disposed on the side edge of the second semiconductor opening region. When the conductive film layer is disconnected at the crack on the surface of the crack ink and forms an insulating channel together with the crack, the conductive film layer will not span the side edge of the second semiconductor opening region in the horizontal direction of the silicon wafer, avoiding the leakage phenomenon between the first semiconductor layer and the second semiconductor layer, thereby significantly increasing the parallel resistance of the battery, and further increasing the battery efficiency and the battery yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] To more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of the present application and should not be regarded as limiting the scope. For those of ordinary skill in the art, other related drawings can be obtained based on these drawings without creative efforts.

[0043] Figure 1 It is a schematic structural diagram of the back-contact battery of step S101 in Embodiment 1 of the present invention;

[0044] Figure 2 It is a schematic structural diagram of printing crack ink at the edge of the second semiconductor opening region in step S102 of Embodiment 1 of the present invention;

[0045] Figure 3 It is a schematic structural diagram of UV-curing crack ink at the edge of the second semiconductor opening region in step S102 of Embodiment 1 of the present invention;

[0046] Figure 4 It is a schematic structural diagram of depositing a conductive film layer on the back surface of the silicon wafer in step S103 of Embodiment 1 of the present invention;

[0047] Figure 5Schematic diagram of forming metal electrodes at the first semiconductor opening region and the second semiconductor opening region on the back surface of the silicon wafer in step S104 of Embodiment 1 of the present invention;

[0048] Figure 6 Schematic diagram of the structure of a conventional back-contact battery in the prior art.

[0049] Description of reference numerals:

[0050] 1. Silicon wafer; 2. First intrinsic semiconductor film layer; 3. First conductive semiconductor film layer; 4. Second intrinsic semiconductor film layer; 5. Second conductive semiconductor film layer; 6. Front film layer; 7. Crack ink; 8. Conductive film layer; 9. Metal electrode; 10. Mask layer; 101. Surface of the silicon wafer in the second semiconductor opening region; 102. Side edge. Detailed implementation manners

[0051] In the specification, claims and drawings of the present application, the terms "comprising", "including", "containing" or "characterized by" are synonymous, and are inclusive of endpoints or open-ended, and do not exclude additional unrecited elements or method steps. "Comprising" is a technical term used in claim language, meaning that the element exists, but other elements can also be added and still form a structure or method within the scope of the claim.

[0052] It should be noted that: Similar reference numerals and letters represent similar items in the following drawings. Therefore, once an item is defined in one drawing, it does not need to be further defined and explained in subsequent drawings. In addition, the terms "first", "second", "third", etc. are only used for distinguishing descriptions and cannot be understood as indicating or implying relative importance. In the present application, the term "about" means including a small change (up to + / - 10%) of the value.

[0053] In a first aspect, the present application provides a back-contact battery, including a silicon wafer, a first semiconductor layer, a second semiconductor layer, crack ink and a conductive film layer; the silicon wafer has a front surface and a back surface; the first semiconductor layer is disposed on the back surface of the silicon wafer, and second semiconductor opening regions are uniformly spaced on the first semiconductor layer; the second semiconductor layer is continuously disposed on the outer surface of the first semiconductor layer and within the second semiconductor opening regions, and first semiconductor opening regions are arranged at intervals with the second semiconductor opening regions on the second semiconductor layer; the crack ink is disposed at the side edge of the second semiconductor opening region and is in direct contact with the second semiconductor layer, and both ends of the crack ink extend a preset distance along the horizontal direction of the silicon wafer respectively; wherein, a plurality of cracks extending to its surface are formed in the crack ink, and the width of the cracks ≤ 20 μm; the conductive film layer is continuously disposed on the outer surface of the second semiconductor layer, on the crack ink and within the first semiconductor opening regions, and the conductive film layer is disconnected at the cracks on the surface of the crack ink and forms an insulating channel together with the cracks.

[0054] It should be noted that the width of the crack ≤ 20 μm means that the width of each crack on each crack ink is not greater than 20 μm, but the minimum width of the crack should be greater than 0. Cracks must exist on the crack ink to form an insulating channel with the conductive film layer. Specifically, the insulating channel refers to that when the conductive film layer is deposited on the surface of the crack ink, it is only deposited on the complete and continuous surface of the crack ink, and the area with cracks on the surface of the crack ink will be naturally disconnected. The break of the conductive film layer and the crack extending inward of the crack ink together form an insulating channel. Compared with the insulating groove, the penetration depth of the insulating channel is deeper and the number is more, which can greatly improve the insulating isolation effect.

[0055] In this application, the width of the crack ≤ 20 μm. Although the insulating isolation effect will increase with the increase of the width of the crack, the size of the crack ink is limited. If the width of the crack is too large, the number of cracks on each crack ink will decrease, which will instead affect the insulating isolation effect. At the same time, too large a width of the crack will also increase the instability of the crack ink. Therefore, on the basis of ensuring the insulating isolation effect of a single crack, the width of the crack is limited to not more than 20 μm, which can increase the number of cracks on the crack ink to a certain extent and is beneficial to improving the insulating isolation effect.

[0056] It should be noted that the shape of the crack in the crack ink in this application can be various. The shape of the crack can be straight tube type, curved, etc. Multiple cracks can also communicate with each other inside the crack ink, but the above situations will not affect the technical effect of this application, and this application does not limit it either.

[0057] Preferably, the crack ink of this application is arranged on the side edge of the second semiconductor opening area. When the conductive film layer is disconnected at the crack on the surface of the crack ink and forms an insulating channel with the crack, the conductive film layer will not cross the side edge of the second semiconductor opening area in the horizontal direction of the silicon wafer, avoiding the leakage phenomenon between the first semiconductor layer and the second semiconductor layer, thereby greatly increasing the parallel resistance of the battery, and then improving the battery efficiency and the battery yield.

[0058] In some embodiments, the width of both ends of the crack ink in the horizontal direction of the silicon wafer is 20 - 200 μm, the extension distance of one end of the crack ink in the direction of the first semiconductor layer ≥ 10 μm, and the extension distance of the other end of the crack ink in the direction of the second semiconductor opening area ≥ 10 μm. The crack ink with appropriate different ranges of width can further reduce the short-circuit leakage between the first semiconductor layer and the second semiconductor layer, and is more conducive to improving the parallel resistance of the battery and the battery conversion efficiency.

[0059] It should be noted that the horizontal direction of the silicon wafer refers to the extension direction of the first semiconductor layer or the second semiconductor layer.

[0060] In some embodiments, the maximum thickness of the crack ink in the vertical direction of the silicon wafer is 2 - 20 μm. Preferably, the maximum thickness of the crack ink in the vertical direction of the silicon wafer is 5 - 15 μm. It can be understood that the thickness of each crack ink generally shows a situation of being lower at both ends and higher in the middle. Therefore, the maximum thickness generally appears at the middle position of each crack ink. At the same time, there are differences in the thickness between different crack inks. Therefore, the maximum thickness in this application refers to the maximum thickness of any crack ink in the vertical direction of the silicon wafer, and it is within the range of 2 - 20 μm. Reasonably setting the thickness of the crack ink can further improve the battery conversion efficiency and the battery yield.

[0061] It should be noted that the vertical direction of the silicon wafer refers to the stacking direction of each layer on the back surface of the silicon wafer.

[0062] In some embodiments, the width of the first semiconductor opening region is 0.15 - 0.5 mm, and the width of the second semiconductor opening region is 0.3 - 0.6 mm.

[0063] In some embodiments, the crack ink is a UV - curable crack ink or a thermosetting crack ink. Preferably, the crack ink is a UV - curable crack ink. Compared with the thermosetting crack ink, the UV - curable crack ink is formed by the post - printing UV - curing method. This method is more conducive to the formation of cracks. The possible reasons are guessed as follows: The thermosetting crack ink mainly forms cracks by thermal - curing shrinkage. The formation conditions are relatively single, and the thermal - curing time is relatively long, which is not conducive to the formation of internal stress in the material to form cracks. While for UV - curing, first, different wavelengths of UV light can be used to irradiate the crack ink, which can better control the formation conditions. At the same time, the UV - curing time is very fast, and the volume shrinkage inside the material is faster, making it easier to generate internal stress in the material to form cracks.

[0064] In some embodiments, the UV - curable crack ink is composed of the following components by mass percentage: 70 - 85% resin, 2 - 10% additives, 0.5 - 5% solvent, 5 - 15% fillers, and 1 - 5% photoinitiator.

[0065] In some embodiments, the resin is one or a combination of acrylic resin, phenolic resin, and epoxy resin. Preferably, the resin is acrylic resin. Among them, the dosage and type of the resin affect the width of the cracks. The specific reason is that different types of resins have differences in chemical structure and properties, which will lead to different behaviors of the ink during drying and curing. Some resins have high flexibility, which will reduce the generation of cracks. While the preferred acrylic resin in this application is relatively rigid and is more likely to generate shrinkage and stress during drying, thus increasing the number of cracks.

[0066] In some embodiments, the auxiliary agent is one or a combination of benzophenone, tertiary amine acrylate, polyester solution, polyether compound, silicone oil, and mineral oil. Preferably, the auxiliary agent is a polyester solution. The purpose of adding the auxiliary agent is to modify the ink, such as viscosity, flexibility, bubbles, etc. It should be noted that the above-mentioned auxiliary agents added in this application can all reduce the flexibility of the ink to a certain extent, thereby making the ink more likely to shrink and generate stress during the curing process, resulting in cracks.

[0067] In some embodiments, the solvent is one or a combination of propylene glycol, ethyl acetate, butyl acetate, acetone, toluene, and ethanol. Preferably, the solvent is ethyl acetate. The purpose of adding the solvent is to dissolve and dilute other components in the ink.

[0068] In some embodiments, the filler is one or a combination of calcium carbonate, magnesium carbonate, barium sulfate, aluminum hydroxide, lithopone, and aluminum silicate. Among them, kaolin can also be used instead of aluminum silicate. Preferably, the filler is calcium carbonate. The purpose of adding the filler is to utilize the significant difference in the coefficient of thermal expansion between the filler and the resin matrix to generate shear stress at the interface during curing to form appropriate cracks.

[0069] It should be noted that there are no special requirements for the photoinitiator in this application, and commercially available products common in the art can be used.

[0070] In some embodiments, the composition of the thermosetting crack ink is similar to that of the above-mentioned UV-curable crack ink, except that the thermosetting crack ink does not contain a photoinitiator, and the lack of the photoinitiator content is supplemented by the solvent.

[0071] Preferably, the crack ink of this application has stable properties and can be retained on the battery chip for a long time. Through a specific crack ink formulation of this application, a number of cracks extending to its surface can be formed in the crack ink, and the cracks have a specific width. The existence of these cracks can significantly improve the insulation isolation effect.

[0072] In some embodiments, the size and number of cracks can be adjusted by adjusting the ratio of the resin to the auxiliary agent and / or the filler.

[0073] In some embodiments, the first semiconductor layer includes a first intrinsic semiconductor film layer and a first conductive semiconductor film layer, and the second semiconductor layer includes a second intrinsic semiconductor film layer and a second conductive semiconductor film layer. Preferably, the first intrinsic semiconductor film layer is a tunneling oxide layer, the first conductive semiconductor film layer is an N-type doped polysilicon layer, the second intrinsic semiconductor film layer is an intrinsic amorphous silicon layer, and the second conductive semiconductor film layer is a P-type doped amorphous / microcrystalline silicon layer.

[0074] Those skilled in the art can select the thickness of the second semiconductor layer, as well as the thickness ratio of the intrinsic amorphous silicon layer and the P-type doped amorphous / microcrystalline silicon layer, and the doping concentration of the P-type doped amorphous / microcrystalline silicon layer according to actual needs. Exemplarily, the thickness of the second semiconductor layer can be 10 - 20 nm, the thickness ratio of the intrinsic amorphous silicon layer and the P-type doped amorphous / microcrystalline silicon layer can be 1:1 - 3, and the effective doping concentration of the P-type doped amorphous / microcrystalline silicon layer is 3e18 - 3e20 cm -3 .

[0075] Those skilled in the art can select the thickness of the first semiconductor layer, as well as the thickness ratio of the tunneling oxide layer and the N-type doped polysilicon layer, the doping concentration of the N-type doped polysilicon layer, and the thickness of the conductive film layer according to actual needs. Exemplarily, the thickness of the first semiconductor layer can be 60 - 150 nm, the thickness ratio of the tunneling oxide layer and the N-type doped polysilicon layer can be 1:40 - 100, and the effective doping concentration of the N-type doped polysilicon layer is 1e18 - 1e21 cm -3 . Exemplarily, the thickness of the conductive film layer can be 40 - 100 nm.

[0076] It should be noted that the present invention can be applied to both heterojunction passivation structures and combined passivation structures with a greater risk of short-circuit leakage, and can solve the short-circuit leakage problem between the first semiconductor layer and the second semiconductor layer in both cases.

[0077] In some embodiments, the back-contact battery further includes metal electrodes, which are disposed on the outer surface of the conductive film layer and are disposed within the first semiconductor opening region and the second semiconductor opening region. The metal electrodes are divided into two types of electrodes with different polarities, and the polarities of the metal electrodes disposed on the first semiconductor opening region and the metal electrodes disposed on the second semiconductor opening region are different.

[0078] In some embodiments, the back-contact battery further includes a front film layer, which is disposed on the front surface of the silicon wafer. The front film layer includes a silicon dielectric passivation layer and a silicon dielectric antireflection layer. Those skilled in the art can select the thickness of the front film layer according to actual needs. For example, the thickness of the front film layer can be 50 - 120 nm. Those skilled in the art can select the thickness ratio of the silicon dielectric passivation layer and the silicon dielectric antireflection layer according to actual needs. The silicon dielectric passivation layer can be, for example, a silicon dioxide, amorphous silicon, or microcrystalline silicon layer, etc., and the silicon dielectric antireflection layer can be, for example, a silicon nitride, silicon oxynitride, or silicon dioxide layer, etc.

[0079] In some embodiments, the front surface of the silicon wafer is a textured surface, and the surface of the silicon wafer at the second semiconductor opening region is a textured surface or a polished surface.

[0080] In some embodiments, those skilled in the art can select the type of the silicon wafer according to actual needs. For example, the silicon wafer can be an N-type wafer.

[0081] In a second aspect, the present application also provides a method for manufacturing a back-contact battery, and the manufacturing method includes the following steps:

[0082] S101. Form a first semiconductor layer with a second semiconductor opening region on the back surface of the silicon wafer, dispose a second semiconductor layer on the outer surface of the first semiconductor layer and within the second semiconductor opening region, and a first semiconductor opening region spaced apart from the second semiconductor opening region is provided on the second semiconductor layer;

[0083] S102. Print and cure to form crack ink on the side edges of the second semiconductor opening region on the back surface obtained in S101;

[0084] Wherein, a plurality of cracks extending to its surface are formed in each crack ink, and the width of the cracks ≤ 20 μm;

[0085] S103. Deposit a conductive film layer on the back surface obtained in S102;

[0086] Wherein, the conductive film layer is disconnected at the cracks on the surface of the crack ink and forms an insulating channel together with the cracks.

[0087] In some embodiments, in S102, when the crack ink is a UV-curable crack ink, the crack ink is formed by UV curing after printing, and the UV curing energy is 500 - 10000 mj / cm 2 , it can be, 500 mj / cm 2 , 1000 mj / cm 2 , 2000 mj / cm 2 , 3000 mj / cm 2 , 4000 mj / cm 2 , 5000 mj / cm 2 , 6000 mj / cm 2 , 7000 mj / cm 2 , 8000 mj / cm 2 , 9000 mj / cm 2 , 10000 mj / cm 2 and any value therebetween. Preferably, the UV curing energy is 3000 - 6000 mj / cm 2 .

[0088] The UV curing temperature is 50 - 200 °C, it can be 50 °C, 100 °C, 150 °C, 200 °C. Preferably, the UV curing temperature is 100 - 150 °C.

[0089] Preferably, the UV curing energy is 3000 - 6000 mj / cm 2, the UV curing temperature is 100 - 150 °C. The UV curing energy and temperature can affect the number and width of the cracks. The possible reasons are speculated as follows: The UV curing energy and temperature directly affect the curing speed. Appropriate UV energy and temperature can accelerate the curing speed of the ink. Rapid curing helps to form a crack pattern because the surface layer of the ink cures rapidly while the interior remains soft, and this difference makes it easier to form cracks. Controlling the UV curing energy and temperature can also adjust the morphology of the cracks. When the UV curing energy and UV curing temperature are in the preferred conditions, ideal crack width and number of cracks can be obtained. Excessive or too low energy and temperature may lead to a reduction in the number of cracks or uneven width.

[0090] In some embodiments, in S102, when the crack ink is a thermosetting crack ink, after printing, thermal curing is used to form the crack ink. The thermal curing temperature is 150 - 200 °C, and the thermal curing time is 5 - 30 min.

[0091] In some embodiments, before S101, it further includes forming a textured surface on the front side of the silicon wafer and forming a front side film layer.

[0092] In some embodiments, the conductive film layer is deposited by physical vapor deposition technology (PVD) or reactive plasma deposition technology (RPD). The conductive film layer is an indium oxide-based thin film doped with tin, zinc, tungsten, titanium, etc. or a zinc oxide-based thin film doped with aluminum, boron, gallium, etc.

[0093] In some embodiments, after S103, it further includes forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the regions of the first semiconductor opening area and the second semiconductor opening area respectively. The metal electrodes can be formed by printing silver paste to form silver paste grid line electrodes, electroplating to form grid line electrodes, etc. It can be seen that by adopting the technical solution of the present application, after depositing the conductive film layer in S103, S104 can be directly carried out to form metal electrodes. By using the crack ink technology of the present application, the formed insulating channel has a greater insulation resistance relative to the insulating groove, and there is no need to specifically perform a process to form an insulating isolation groove after depositing the conductive film, thus simplifying the process flow and improving the production yield of the battery.

[0094] In some embodiments, during the formation of the metal electrode, the number of cracks in the crack ink will increase, and the width of the cracks in the crack ink increases until it is 5 - 20 μm. The reason is that pressure will be applied to the crack ink during the preparation of the metal electrode, so it will promote an increase in the number of cracks and a deepening of the crack width, which can further improve the insulation isolation effect.

[0095] It should be noted that the width of each crack in each crack ink is not uniform. Therefore, when the width of the crack in the crack ink increases up to 5 - 20 μm, it means that the minimum width of the crack in the crack ink is 5 μm and the maximum width of the crack in the crack ink is 20 μm.

[0096] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0097] Embodiment 1

[0098] A method for preparing a back-contact battery, the preparation method comprising the following steps:

[0099] S101, as Figure 1 shown, provide an N-type silicon wafer 1, form a first semiconductor layer with a second semiconductor opening region on the back surface of the silicon wafer 1, provide a second semiconductor layer on the outer surface of the first semiconductor layer and within the second semiconductor opening region, and a first semiconductor opening region spaced apart from the second semiconductor opening region is provided on the second semiconductor layer;

[0100] The first semiconductor layer includes a first intrinsic semiconductor film layer 2 (specifically, a tunneling oxide layer with a thickness of 1.7 nm) and a first conductive semiconductor film layer 3 (specifically, an N-type doped polysilicon layer with a thickness of 100 nm and an effective doping concentration of 1e20 cm -3 ), the second semiconductor layer includes a second intrinsic semiconductor film layer 4 (specifically, an intrinsic amorphous silicon layer with a thickness of 6 nm) and a second conductive semiconductor film layer 5 (specifically, a P-type doped amorphous silicon layer with a thickness of 10 nm and an effective doping concentration of 5e19 cm -3 ), and a front film layer 6 is formed on the front surface of the silicon wafer 1. The front film layer 6 includes a silicon dielectric passivation layer (specifically, an intrinsic amorphous silicon layer with a thickness of 10 nm) and a silicon dielectric antireflection layer (specifically, silicon nitride with a thickness of 75 nm). The width W1 of the first semiconductor opening region is 0.2 mm, the width W2 of the second semiconductor opening region is 0.4 mm, and the surface 101 of the silicon wafer in the second semiconductor opening region is a polished surface.

[0101] S102, as Figure 2As shown, crack ink 7 is printed on the side edge 102 of the second semiconductor opening region. The width of both ends of the crack ink 7 in the horizontal direction of the silicon wafer 1 is 90 μm. The extension distance W11 of one end of the crack ink 7 in the direction of the first semiconductor layer is 50 μm, and the extension distance W12 of the other end of the crack ink 7 in the direction of the second semiconductor opening region is 40 μm. The maximum thickness of the crack ink 7 in the vertical direction of the silicon wafer 1 is 5 - 15 μm;

[0102] As Figure 3 shown, the crack ink 7 is a UV-curable crack ink (specifically composed of 83% acrylic resin, 5% polyester solution, 1% ethyl acetate, 10% calcium carbonate, and 1% photoinitiator). After printing, the crack ink 7 is formed by UV curing, and the UV curing energy is 5000 mj / cm 2 , and the UV curing temperature is 130 °C; among them, several cracks extending to its surface are formed in each crack ink 7, and the width W3 of the cracks ≤ 20 μm.

[0103] S103. As Figure 4 shown, a conductive film layer 8 is deposited on the back surface obtained in S102, and the thickness of the conductive film layer 8 is 60 nm. The conductive film layer 8 is deposited by physical vapor deposition technology (PVD), and the conductive film layer 8 is an indium tin oxide-based thin film.

[0104] Among them, the conductive film layer 8 is disconnected at the cracks on the surface of the crack ink 7 and jointly forms an insulating channel with the cracks.

[0105] S104. As Figure 5 shown, metal electrodes 9 are respectively formed on the outer surfaces of the corresponding conductive film layers 8 in the regions of the first semiconductor opening region and the second semiconductor opening region. The metal electrodes 9 are formed by printing silver paste to form silver paste grid line electrodes. During the formation of the metal electrodes, the number of cracks in the crack ink increases and the width of the cracks in the crack ink increases until it is 5 - 20 μm.

[0106] Example 2

[0107] It is carried out by referring to the method of Example 1, the difference is that in S102, the crack ink is a thermosetting crack ink (specifically composed of 80% acrylic resin, 6% polyester solution, 6% ethyl acetate, and 8% calcium carbonate). After printing, the crack ink is formed by thermal curing, the thermal curing temperature is 170 °C, and the thermal curing time is 20 min.

[0108] Example 3

[0109] It is carried out by referring to the method of Example 1, the difference is that in S101, the maximum thickness of the crack ink in the vertical direction of the silicon wafer is 2 - 5 μm.

[0110] Example 4

[0111] It is carried out according to the method of Example 1, except that in S104, the final width of the crack of the crack ink is 5-15 μm, and the process parameters that need to be adjusted to meet this condition are: in S102, the crack ink is a UV-curable crack ink, and the composition of the crack ink is adjusted to 78% acrylic resin, 5% polyester solution, 1% ethyl acetate, 15% calcium carbonate and 1% photoinitiator.

[0112] Example 5

[0113] It is carried out according to the method of Example 1, except that in S104, the final width of the crack of the crack ink is 5-15 μm, and the process parameters that need to be adjusted to meet this condition are: adjust the UV curing energy to 8000 mj / cm 2 , and the UV curing temperature is 150 °C.

[0114] Example 6

[0115] It is carried out according to the method of Example 1, except that a conventional heterojunction passivation structure is adopted, the tunneling oxide layer in the first semiconductor layer is replaced with intrinsic amorphous silicon, and the N-type doped polysilicon layer is replaced with an N-type doped amorphous layer. The thickness of the intrinsic amorphous silicon is 8 nm, and the thickness of the N-type doped amorphous layer is 12 nm.

[0116] Comparative Example 1

[0117] As Figure 6 shown, the crack ink 7 is not provided on the side edge 102, the second semiconductor layer is in direct contact with the conductive film layer 8, and a mask layer 10 (specifically silicon nitride) is provided in the region between the first semiconductor opening region and the second semiconductor opening region in the horizontal direction of the silicon wafer 1, and the mask layer 10 is located between the first semiconductor layer and the second semiconductor layer. The isolation groove is opened on the first semiconductor and does not cross the side edge of the first semiconductor. Its preparation method is carried out according to the method in the prior art.

[0118] Comparative Example 2

[0119] It is carried out according to the method of Example 1, except that the P / N types of the two semiconductor layers are different. Specifically, the doped polysilicon layer in the first semiconductor layer is a P-type doped polysilicon layer, and the doped amorphous silicon layer in the second semiconductor layer is an N-type doped amorphous silicon layer.

[0120] Comparative Example 3

[0121] It is carried out according to the method of Embodiment 1, with the difference that in S104, the final width of the crack of the crack ink is greater than 20 μm. The process parameters that need to be adjusted to meet this condition are: in S102, the crack ink is a UV-curable crack ink, and the composition of the crack ink is adjusted to 90% acrylic resin, 5% polyester solution, 1% ethyl acetate, 3% calcium carbonate, and 1% photoinitiator.

[0122] Adjust the UV curing energy to 6000 mj / cm 2 , and the UV curing temperature is 150 °C.

[0123] Test example

[0124] Perform various performance tests on the back contact batteries obtained in the above embodiments and comparative examples, and the results are shown in Table 1. Among them, the battery yield refers to the battery qualification rate when the batch production quantity is 1000 pieces.

[0125] Table 1

[0126]

[0127] From the above results, it can be seen that compared with the comparative example, by adopting the embodiment scheme of the present invention, a more preferable crack width of the crack ink can be obtained, thereby improving the shunt resistance of the back contact battery, effectively avoiding the leakage phenomenon, and taking into account the improvement of the battery conversion efficiency and the battery yield. At the same time, the crack ink technology of the present application forms an insulating channel with a larger insulation resistance compared to the insulating groove, and there is no need to specifically perform a process to form an insulating isolation groove after depositing the conductive film, thereby simplifying the process flow and further improving the battery production yield.

[0128] Furthermore, according to Embodiment 1 and Embodiment 2, it can be seen that compared with the thermally curable crack ink, by adopting the scheme of the preferred UV-curable crack ink and its forming method of the present invention, the battery conversion efficiency and the battery yield can be further improved.

[0129] Furthermore, according to Embodiment 1 and Embodiment 3, it can be seen that by adopting the scheme of the preferred crack ink with the maximum thickness of the present invention, the battery conversion efficiency and the battery yield can be further improved.

[0130] Furthermore, according to Embodiment 1 and Embodiment 4, it can be seen that by adopting the preferred crack ink composition content of the present invention, a more preferable crack width can be obtained, and the battery conversion efficiency and the battery yield can be further improved.

[0131] Furthermore, according to Embodiment 1 and Embodiment 5, it can be seen that by adopting the preferred UV curing parameters of the present invention, a more preferable crack width can be obtained, and the battery conversion efficiency and the battery yield can be further improved.

[0132] Furthermore, according to Embodiment 1 and Embodiment 6, it can be seen that the solution of the present invention is particularly applicable to the solution of the combined passivation structure, which can further improve the battery conversion efficiency and the battery yield.

[0133] Reference to "embodiment" in this context means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The phrase appears in various places in the specification and does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments.

[0134] The embodiments of the present application have been introduced in detail above. Specific examples are used herein to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application; at the same time, for those of ordinary skill in the art, according to the idea of the present application, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present application.

Claims

1. A back-contact battery, comprising: A silicon wafer having a front side and a back side; A first semiconductor layer disposed on the back surface of the silicon wafer, and second semiconductor opening regions are evenly spaced on the first semiconductor layer; A second semiconductor layer continuously disposed on the outer surface of the first semiconductor layer and within the second semiconductor opening regions, and first semiconductor opening regions arranged at intervals with the second semiconductor opening regions are provided on the second semiconductor layer; It is characterized in that it further comprises: Crack ink disposed on the side edges of the second semiconductor opening regions and in direct contact with the second semiconductor layer, and both ends of the crack ink extend a preset distance along the horizontal direction of the silicon wafer; wherein, a plurality of cracks extending to its surface are formed within the crack ink, and the width of the cracks ≤ 20 μm; A conductive film layer continuously disposed on the outer surface of the second semiconductor layer, on the crack ink, and within the first semiconductor opening regions, and the conductive film layer is disconnected at the cracks on the surface of the crack ink and forms an insulating channel together with the cracks.

2. The back contact battery according to claim 1, characterized in that, The width of both ends of the crack ink along the horizontal direction of the silicon wafer is 20 - 200 μm, the extension distance of one end of the crack ink along the direction of the first semiconductor layer ≥ 10 μm, and the extension distance of the other end of the crack ink along the direction of the second semiconductor opening region ≥ 10 μm; And / or, The maximum thickness of the crack ink along the vertical direction of the silicon wafer is 2 - 20 μm.

3. The back-contact battery according to claim 1, characterized in that, The width of the first semiconductor opening region is 0.15 - 0.5 mm, and the width of the second semiconductor opening region is 0.3 - 0.6 mm.

4. The back contact battery according to claim 1, characterized in that, The crack ink is a UV-curable crack ink or a thermosetting crack ink.

5. The back-contact battery according to claim 4, wherein, The UV-curable crack ink is composed of the following components by mass percentage: 70 - 85% resin, 2 - 10% additives, 0.5 - 5% solvent, 5 - 15% fillers, and 1 - 5% photoinitiator.

6. The back contact battery according to claim 5, characterized in that, The resin is one or a combination of acrylic resin, phenolic resin, and epoxy resin; And / or, The additives are one or a combination of benzophenone, tertiary amine acrylate, polyester solution, polyether compounds, silicone oil, and mineral oil; And / or, The solvent is one or a combination of propylene glycol, ethyl acetate, butyl ester, acetone, toluene, and ethanol; And / or, The fillers are one or a combination of calcium carbonate, magnesium carbonate, barium sulfate, aluminum hydroxide, lithopone, and aluminum silicate.

7. The back-contact battery according to claim 1, characterized in that, The first semiconductor layer includes a first intrinsic semiconductor film layer and a first conductive semiconductor film layer, and the second semiconductor layer includes a second intrinsic semiconductor film layer and a second conductive semiconductor film layer.

8. The back contact battery according to claim 1, wherein, The back-contact battery further includes metal electrodes disposed on the outer surface of the conductive film layer and within the first semiconductor opening regions and the second semiconductor opening regions; And / or, The back-contact battery further includes a front film layer disposed on the front side of the silicon wafer, and the front film layer includes a silicon dielectric passivation layer and a silicon dielectric antireflection layer; And / or, The front side of the silicon wafer is the textured surface, and the surface of the silicon wafer at the second semiconductor opening area is the textured surface or the polished surface.

9. A method for preparing a back-contact battery, characterized in that, The preparation method is used to prepare the back-contact battery as described in any one of claims 1 to 8, and the preparation method includes the following steps: S101: Form a first semiconductor layer with a second semiconductor opening area on the back side of the silicon wafer, arrange a second semiconductor layer on the outer surface of the first semiconductor layer and in the second semiconductor opening area, and a first semiconductor opening area arranged at intervals with the second semiconductor opening area is provided on the second semiconductor layer; S102: Print and cure to form crack ink on the side edge of the second semiconductor opening area on the back side obtained in S101; Wherein, a plurality of cracks extending to its surface are formed in the crack ink, and the width of the cracks ≤ 20 μm; S103: Deposit a conductive film layer on the back side obtained in S102; Wherein, the conductive film layer is disconnected at the cracks on the surface of the crack ink and jointly forms an insulating channel with the cracks.

10. The preparation method according to claim 9, characterized in that, In S102, when the crack ink is UV-curable crack ink, the crack ink is formed by UV curing after printing, and the UV curing energy is 500 - 10000 mj / cm 2 , and the UV curing temperature is 50 - 200 °C; And / or In S102, when the crack ink is a thermosetting crack ink, it is thermally cured to form crack ink after printing, the thermal curing temperature is 150 - 200 °C, and the thermal curing time is 5 - 30 min.

11. The preparation method according to claim 9, wherein Before S101, it further includes forming a textured surface on the front side of the silicon wafer and forming a front-side film layer; And / or After S103, it further includes forming metal electrodes on the outer surfaces of the corresponding conductive film layers in the areas where the first semiconductor opening area and the second semiconductor opening area are located, respectively.

12. The preparation method according to claim 11, characterized in that, During the formation of the metal electrodes, the number of cracks in the crack ink increases; And / or During the formation of the metal electrodes, the width of the cracks in the crack ink increases until it is 5 - 20 μm.

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