Solar cell preparation method and solar cell

Abstract

The invention discloses a solar cell preparation method and a solar cell. The solar cell preparation method comprises the following steps: providing a textured N-type raw material silicon wafer; the N-type raw material silicon wafer after texturing is loaded into quartz glass; the source temperature rising process is divided into four temperature rising stages, the percentage of the total heating power of a heating wire and the temperature rising rate of each temperature rising stage are set, and boron diffusion treatment is conducted on the N-type raw material silicon wafer; the four temperature rising stages are respectively a first temperature rising stage, a second temperature rising stage, a third temperature rising stage and a fourth temperature rising stage; and carrying out borosilicate glass layer removal cleaning on the N-type raw material silicon wafer after boron diffusion treatment, carrying out alkali polishing treatment on the back surface of the raw material silicon wafer, and preparing a finished product solar cell through the silicon wafer. On one hand, the boron source concentration on the surface of the silicon wafer can be reduced, the passivation performance of the surface of the silicon wafer is improved, and on the other hand, the in-chip and inter-chip uniformity of the square resistor is not affected.

Description

Technical Field

[0001] The present application relates to the technical field of solar cell preparation, and in particular to a solar cell preparation method and a solar cell. Background Art

[0002] The traditional method to improve the surface passivation performance of silicon wafers after boron diffusion is to reduce the flow rate of the boron source or the time of the source flow to achieve the purpose of reducing the boron concentration on the silicon wafer surface, and ultimately achieve an increase in the battery start-up voltage; however, the disadvantage of this method is that the reduction in source quantity will inevitably lead to a deterioration in the uniformity of the square resistance within and between silicon wafers.

[0003] At the same time, after the N-type silicon wafer is treated with boron diffusion, a P / N junction is formed on the surface of the silicon wafer (the surface layer is P-type, the lower layer is N-type, and the P / N junction forms the positive and negative poles of the silicon wafer). If the boron concentration on the surface of the silicon wafer is too high after boron diffusion, it will cause serious Auger recombination, thereby reducing the open circuit voltage of the finished battery; while if the boron concentration is too low, the contact resistance between the printed gate line and the silicon wafer will increase, thereby reducing the fill factor of the finished battery; therefore, the size of the boron concentration is crucial.

[0004] Existing technologies usually reduce the boron concentration on the silicon wafer surface by reducing the flow rate of the boron source or the time the source is turned on, ultimately increasing the battery start-up voltage. However, this solution will cause the uniformity of the square resistance of the entire battery surface to deteriorate.

[0005] In order to solve this problem, the commonly used solutions are to deal with it through boron source deposition, temperature rise cycle or multi-step boron source deposition. However, these solutions all improve the open circuit voltage from the perspective of square resistance uniformity, and cannot avoid the problem of internal dislocation or stress of the silicon wafer caused by rapid temperature rise, which leads to a decrease in the battery open voltage. Summary of the invention

[0006] The present application provides a method for preparing solar cells and solar cells, including the following steps: providing a textured N-type raw silicon wafer; loading the textured N-type raw silicon wafer into quartz glass; dividing the source temperature rising process into four heating stages, and setting the percentage of the total heating power of the heating wire and the heating rate in each heating stage, and performing boron expansion treatment on the N-type raw silicon wafer; the four heating stages are respectively the first heating stage, the second heating stage, the third heating stage and the fourth heating stage; cleaning the N-type raw silicon wafer after the boron expansion treatment to remove the borosilicate glass layer, and performing alkali polishing on the back of the raw silicon wafer, and generating a finished solar cell through silicon wafer preparation. On the one hand, the present application can reduce the boron source concentration on the surface of the silicon wafer and improve the passivation performance of the silicon wafer surface, and on the other hand, it can not affect the uniformity of the block resistance within and between the wafers.

[0007] According to some embodiments, the present application provides a method for preparing a solar cell, comprising the following steps: providing a textured N-type raw silicon wafer;

[0008] Putting the textured N-type raw silicon wafer into quartz glass;

[0009] The Tongyuan temperature rising process is divided into four heating stages, and the percentage of the total heating power of the heating wire and the heating rate in each heating stage are set to perform boron diffusion treatment on the N-type raw silicon wafer; the four heating stages are respectively the first heating stage, the second heating stage, the third heating stage and the fourth heating stage, wherein the heating rate of the fourth heating stage is the first percentage threshold of the average heating rate of the four heating stages of the Tongyuan temperature rising;

[0010] The borosilicate glass layer of the N-type raw silicon wafer after the boron diffusion treatment is cleaned, and the back of the raw silicon wafer is subjected to alkali polishing treatment, and the finished solar cell is generated through silicon wafer preparation.

[0011] Preferably, before providing the N-type raw silicon wafer after texturing, the method further comprises:

[0012] The N-type raw silicon wafer is placed in a sodium hydroxide solution and a surfactant additive system alkali solution to react on the front and back sides of the N-type raw silicon wafer to form a pyramid-shaped velvet surface;

[0013] Wherein, the surfactant additive includes isopropanol.

[0014] Preferably, the first temperature rising stage is 850-930°C, the second temperature rising stage is 930-950°C, the third temperature rising stage is 950-970°C, and the fourth temperature rising stage is 970-980°C.

[0015] Preferably, the setting of the percentage of the total heating power of the heating wire and the heating rate in each heating stage includes:

[0016] The percentage of the total heating power of the heating wire in the first heating stage is set to 100%, and the heating rate of the first heating stage is controlled to be 15-20°C / min, and the heating time is 10min; the percentage of the total heating power of the heating wire in the second heating stage is set to 60%, and the heating rate of the second heating stage is controlled to be 10-15°C / min, and the heating time is 5min; the percentage of the total heating power of the heating wire in the third heating stage is set to 30%, and the heating rate of the third heating stage is controlled to be 5-10°C / min, and the heating time is 5min; the percentage range of the total heating power of the heating wire in the fourth heating stage is set to 5-10%, and the heating rate of the fourth heating stage is controlled to be 2-3°C / min, and the heating time is 5min;

[0017] The first percentage threshold range of the heating rate in the fourth heating stage and the average heating rate in the four heating stages of the through-source temperature rise is 14%-32%.

[0018] Preferably, the borosilicate glass layer is removed from the N-type raw silicon wafer after the boron diffusion treatment, and the back of the raw silicon wafer is subjected to alkali polishing treatment, including:

[0019] Under the conditions of reaction temperature of 25-35° C. and belt speed of 2.5-3.5 m / s, using a hydrofluoric acid solution in a chain cleaning machine to clean the borosilicate glass layer on the back of the N-type raw silicon wafer;

[0020] Using sodium hydroxide solution and additives at an alkali polishing tank temperature of 55-70°C, the back side of the N-type raw silicon wafer after the borosilicate glass layer is removed and cleaned is subjected to alkali polishing treatment, and the alkali polishing treatment reaction time is controlled to be 130-200S;

[0021] Wherein, the concentration of the hydrofluoric acid solution is 50%-60%, and the concentration of the sodium hydroxide solution is 15-25%.

[0022] Preferably, after the back side of the raw silicon wafer is subjected to alkali polishing, the following steps are further performed:

[0023] The raw silicon wafer after alkali polishing is placed in a graphite boat and enters a tubular diffusion furnace tube, and a tunneling silicon dioxide oxide layer with a thickness of 1-2 nm and a polysilicon layer with a thickness of 80-200 nm are plated on the back of the N-type raw silicon wafer by hydrogen, silane, nitrous oxide and phosphine, so as to passivate the back of the raw silicon wafer;

[0024] An aluminum oxide layer and a silicon nitride film layer are respectively plated on the front and back sides of the N-type raw silicon wafer.

[0025] Preferably, before the production of finished solar cells by silicon wafer preparation, the process further includes: printing and sintering the raw silicon wafers treated with silicon nitride thin film layer; after the production of finished solar cells by silicon wafer preparation, the process further includes: testing the cell efficiency of the finished solar cells.

[0026] Preferably, the printing and sintering of the raw silicon wafer after the silicon nitride film layer is processed comprises:

[0027] Silver electrodes and solder joints are printed on the front and back sides of the raw silicon wafer after the silicon nitride film layer is plated, and the raw silicon wafer is sintered, and the temperature of the sintering furnace is controlled to be 700-800°C.

[0028] Preferably, the testing of the battery efficiency of the finished solar cell comprises:

[0029] Obtaining the current of the finished solar cell, obtaining the opening voltage of the finished solar cell, obtaining the filling factor of the finished solar cell, and obtaining the area of ​​the finished solar cell;

[0030] The cell efficiency of the finished solar cell is calculated by the formula: the current of the finished solar cell×the opening voltage of the finished solar cell×the fill factor of the finished solar cell / the area of ​​the finished solar cell.

[0031] According to some embodiments, the present application also provides a solar cell prepared by the solar cell preparation method described above.

[0032] The embodiments of the present disclosure have at least the following advantages:

[0033] The solar cell preparation method provided by the present application provides a textured N-type raw silicon wafer; the textured N-type raw silicon wafer is loaded into quartz glass; the source temperature rising process is divided into four heating stages, and the percentage of the total heating power of the heating wire and the heating rate of each heating stage are set, and the N-type raw silicon wafer is subjected to boron expansion treatment; the four heating stages are respectively the first heating stage, the second heating stage, the third heating stage and the fourth heating stage, wherein the heating rate of the fourth heating stage is the first percentage threshold of the average heating rate of the four heating stages of the source temperature rise; the borosilicate glass layer of the N-type raw silicon wafer after the boron expansion treatment is removed and cleaned, and the back of the raw silicon wafer is subjected to alkali polishing treatment, and the finished solar cell is generated by silicon wafer preparation. On the one hand, the present application can reduce the boron source concentration on the surface of the silicon wafer and improve the passivation performance of the silicon wafer surface. On the other hand, it can not affect the uniformity of the block resistance within and between the wafers, and at the same time will not cause the contact resistance between the printed grid line and the silicon wafer to increase, nor will it cause the fill factor of the finished battery to decrease.

[0034] The technical solution provided in the present application can achieve the purpose of reducing the boron concentration on the surface of the silicon wafer by controlling the heating rate. This method is simple to operate, will not affect the uniformity of the square resistance within and between silicon wafers after boron diffusion, and is more conducive to the stability of field data.

[0035] The technical solution provided in the present application controls the temperature so that the boron diffusion process proceeds smoothly, preventing the problem of excessive source entering the silicon wafer due to excessive temperature rise, thereby affecting the passivation of the silicon wafer surface. The opening voltage of the semi-finished battery tested with a double-sided passivation sheet can be increased by 19mV, the opening voltage of the finished battery can be increased by 1-2mV, and the efficiency of the finished battery can be increased by 0.1%. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the conventional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is a schematic diagram of the first step of the method for preparing a solar cell in an embodiment of the present application;

[0038] Figure 2 is a schematic diagram of the second step of the solar cell preparation method used in the embodiment of the present application;

[0039] Figure 3 It is a flow chart of the boron diffusion process in the embodiment of the present application. DETAILED DESCRIPTION

[0040] To make the purpose, technical scheme and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below in conjunction with the accompanying drawings. However, it will be appreciated by those skilled in the art that in the embodiments of the present application, many technical details are proposed in order to enable the reader to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical scheme claimed in the present application can also be implemented. The division of the following embodiments is for the convenience of description, and the specific implementation of the present application should not be construed as any limitation, and the various embodiments can be combined with each other and quoted from each other without contradiction.

[0041] At present, the ways to improve the passivation performance of silicon wafers are: 1. Reduce the total doping amount of boron source; 2. Reduce the number of recombination centers on the surface and inside of silicon wafers. In the process of heating the furnace temperature from 850℃ to 980℃ after the boron source deposition: 1. Too fast a temperature advancement rate will cause dislocations inside the silicon wafer due to the size difference between atoms inside the silicon wafer, and dislocations will form recombination centers inside the silicon wafer, resulting in a decrease in the passivation performance of the silicon wafer; 2. Too fast a temperature advancement rate will cause a large temperature difference inside the silicon wafer, resulting in greater stress inside the silicon wafer, and ultimately leading to the generation of dislocations, which in turn affects the passivation performance of the silicon wafer.

[0042] In view of this, in order to overcome the shortcomings of the prior art, in the boron expansion process structure, the present application controls the heating rate by temperature setting or software control in the process of the source temperature rising to the high-temperature advancement temperature. From the process of the furnace entry temperature rising to the specified temperature, the entire heating process is divided into four stages: rapid heating, slow heating, low-speed heating and precise temperature control. At the same time, the heating rate in the precise temperature control stage is the first percentage threshold of the average heating rate of the four heating stages of the source temperature rising. On the one hand, this scheme can reduce the boron source concentration on the silicon wafer surface and improve the passivation performance of the silicon wafer surface. On the other hand, it can not affect the uniformity of the block resistance within and between wafers.

[0043] The following is a detailed description of a method for preparing a solar cell provided by this embodiment in conjunction with the accompanying drawings. Figure 1 As shown, the following steps are included:

[0044] S1. Provide N-type raw silicon wafer after texturing;

[0045] S2, placing the textured N-type raw silicon wafer into quartz glass;

[0046] S3, the Tongyuan temperature rising process is divided into four heating stages, and the percentage of the total heating power of the heating wire and the heating rate in each heating stage are set to perform boron diffusion treatment on the N-type raw silicon wafer; the four heating stages are respectively the first heating stage, the second heating stage, the third heating stage and the fourth heating stage, wherein the heating rate of the fourth heating stage is the first percentage threshold of the average heating rate of the four heating stages of the Tongyuan temperature rising;

[0047] S4. The borosilicate glass layer of the N-type raw silicon wafer after the boron diffusion treatment is removed and cleaned, and the back of the raw silicon wafer is subjected to alkali polishing treatment, and a finished solar cell is generated through silicon wafer preparation.

[0048] Specifically, the solar cell preparation process flow is: raw silicon wafer - double-sided texturing treatment - double-sided boron diffusion treatment - double-sided cleaning - double-sided aluminum oxide - double-sided silicon nitride film layer - printing and sintering - battery testing.

[0049] The technical solution provided in this application can, on the one hand, reduce the boron source concentration on the surface of the silicon wafer and improve the passivation performance of the silicon wafer surface; on the other hand, it can maintain the uniformity of the block resistance within and between wafers, and at the same time will not cause the contact resistance between the printed gate line and the silicon wafer to increase, nor will it cause the fill factor of the finished battery to decrease.

[0050] The technical solution provided in the present application can achieve the purpose of reducing the boron concentration on the surface of the silicon wafer by controlling the heating rate. This method is simple to operate, will not affect the uniformity of the square resistance within and between silicon wafers after boron diffusion, and is more conducive to the stability of field data.

[0051] The technical solution provided in the present application controls the temperature so that the boron diffusion process proceeds smoothly, preventing the problem of excessive source entering the silicon wafer due to excessive temperature rise, thereby affecting the passivation of the silicon wafer surface. The opening voltage of the semi-finished battery tested with a double-sided passivation sheet can be increased by 19mV, the opening voltage of the finished battery can be increased by 1-2mV, and the efficiency of the finished battery can be increased by 0.1%.

[0052] Each step of the solar cell manufacturing method is described in detail below.

[0053] Please refer to Figure 2 As shown, step S101, placing an N-type raw silicon wafer into a sodium hydroxide solution and a surfactant additive system alkali solution to react on the front and back sides of the N-type raw silicon wafer to form a pyramid-shaped velvet surface;

[0054] Wherein, the surfactant additive includes isopropanol.

[0055] In this embodiment, it should be noted that the N-type raw silicon wafer forms a pyramid-shaped velvet surface on both sides in an alkali solution of a sodium hydroxide solution and a surfactant additive (isopropyl alcohol) system at a certain time and temperature.

[0056] Step S102, providing a textured N-type raw silicon wafer.

[0057] Step S103, placing the textured N-type raw silicon wafer into quartz glass.

[0058] In this embodiment, it should be noted that the silicon wafer after texturing is loaded into a quartz boat (quartz glass) and enters a boron expansion furnace to run a boron expansion process.

[0059] Step S104: Figure 3 As shown, during the source temperature rising process, the N-type raw silicon wafer is subjected to boron diffusion treatment by dividing the heating process into four heating stages and setting the percentage of the total heating power of the heating wire and the heating rate in each heating stage by software control.

[0060] The specific steps that can be implemented in step S104 also include:

[0061] Step S1041, dividing the heating process into a first heating stage, a second heating stage, a third heating stage, and a fourth heating stage;

[0062] Wherein, the first temperature rising stage is 850-930°C, the second temperature rising stage is 930-950°C, the third temperature rising stage is 950-970°C, and the fourth temperature rising stage is 970-980°C.

[0063] Specifically, the furnace entry temperature is 800°C, the furnace door is closed, the temperature inside the furnace is raised to 850°C, BCl3 is introduced for boron source deposition, and after the source is introduced, the temperature is continued to be raised to 980°C. This process is decomposed into four stages: rapid heating (850-930°C), slow heating (930-950°C), low-speed heating (950-970°C) and precise temperature control (970-980°C).

[0064] Among them, the first heating stage is a rapid heating stage, the second heating stage is a slow heating stage, the third heating stage is a low-speed heating stage, and the fourth heating stage is a precise temperature control stage.

[0065] Step S1042: Figure 3 As shown, the percentage of the total heating power of the heating wire in the first heating stage is set to 100%, the heating rate of the first heating stage is controlled to be 15-20℃ / min, the heating time is 10min, the nitrogen flow rate is 4000-5000sccm, and the pressure is 600-800PA; the percentage of the total heating power of the heating wire in the second heating stage is set to 60%, the heating rate of the second heating stage is controlled to be 10-15℃ / min, the heating time is 5min, the nitrogen flow rate is 4000-5000sccm, and the pressure is 600-800PA A; setting the percentage of the total heating power of the heating wire in the third heating stage to 30%, controlling the heating rate of the third heating stage to 5-10°C / min, the heating time to 5min, the nitrogen flow rate to 4000-5000sccm, and the pressure to 600-800PA; setting the percentage range of the total heating power of the heating wire in the fourth heating stage to 5-10%, controlling the heating rate of the fourth heating stage to 2-3°C / min, the heating time to 5min, the nitrogen flow rate to 4000-5000sccm, and the pressure to 600-800PA;

[0066] The first percentage threshold range of the heating rate in the fourth heating stage and the average heating rate in the four heating stages of the through-source temperature rise is 14%-32%.

[0067] Specifically, different heating rates are set in each stage according to requirements using background software or processes: rapid heating stage (setting the percentage of the total heating power of the heating wire to 100%, and the heating rate to 15-20°C / min), slow heating stage (setting the percentage of the total heating power of the heating wire to 60%, and the heating rate to 10-15°C / min), low-speed heating stage (setting the percentage of the total heating power of the heating wire to 30%, and the heating rate to 5-10°C / min) and precise temperature control stage (setting the percentage of the total heating power of the heating wire to 5-10%, and the heating rate to 2-3°C / min).

[0068] By controlling the temperature at different stages, we can prevent the problem of excessive source entering the silicon wafer due to rapid temperature increase, thereby affecting surface passivation.

[0069] In addition, it should be noted that after the boron expansion process, oxygen oxidation is carried out and the temperature is lowered before the furnace is taken out.

[0070] For example, when the heating rate of the first heating stage is 15°C / min, the heating rate of the second heating stage is 10°C / min, the heating rate of the third heating stage is 5°C / min, and the heating rate of the fourth heating stage is controlled to be 3°C / min, the first percentage threshold of the heating rate of the fourth heating stage and the average heating rate of the four heating stages of the source temperature rise is calculated to be 31.25%. By setting the heating rate of the fourth heating stage to the first percentage threshold of the average heating rate of the four heating stages of the source temperature rise, the problem of internal dislocation or stress of the silicon wafer caused by rapid heating, which leads to a decrease in the battery start-up voltage, can be avoided.

[0071] Step S105, cleaning the borosilicate glass layer of the N-type raw silicon wafer after the boron diffusion treatment, and performing alkali polishing on the back of the raw silicon wafer.

[0072] The specific steps that can be implemented in step S105 also include:

[0073] Step S1051, cleaning the borosilicate glass layer on the back of the N-type raw silicon wafer with a hydrofluoric acid solution in a chain cleaning machine at a reaction temperature of 25-35° C. and a belt speed of 2.5-3.5 m / s;

[0074] Using sodium hydroxide solution and additives at an alkali polishing tank temperature of 55-70°C, the back side of the N-type raw silicon wafer after the borosilicate glass layer is removed and cleaned is subjected to alkali polishing treatment, and the alkali polishing treatment reaction time is controlled to be 130-200S;

[0075] Wherein, the concentration of the hydrofluoric acid solution is 50%-60%, and the concentration of the sodium hydroxide solution is 15-25%.

[0076] Specifically, after the boron expansion process, the raw silicon wafer is cleaned to remove the BSG (borosilicate glass layer): a hydrofluoric acid solution (concentration of 50%-60%) is used to clean the borosilicate glass layer on the back of the silicon wafer in a chain cleaning machine. Here, the reaction temperature is 25-35°C and the belt speed is 2.5-3.5m / s.

[0077] After BSG removal and cleaning, the back side is subjected to alkali polishing treatment using sodium hydroxide solution and additives. Here, the alkali polishing tank temperature is 55-70°C, the reaction time is 130-200S, and the sodium hydroxide concentration is 15-25%.

[0078] Step S106, placing the raw silicon wafer after the alkali polishing treatment into a graphite boat, entering the tubular diffusion furnace, and using hydrogen, silane, nitrous oxide and phosphine to plate a 1-2 nm thick tunneling silicon dioxide oxide layer and a 80-200 nm thick polysilicon layer on the back of the N-type raw silicon wafer, so as to perform a passivation treatment on the back of the raw silicon wafer;

[0079] An aluminum oxide layer and a silicon nitride film layer are respectively plated on the front and back sides of the N-type raw silicon wafer.

[0080] In this embodiment, it should also be noted that the raw silicon wafer after alkali polishing is placed in a graphite boat, enters a tubular diffusion furnace tube (PECVD furnace tube), and hydrogen, silane, laughing gas (nitrous oxide) and phosphine are introduced to plate a 1-2nm tunneling silicon dioxide oxide layer and a polysilicon layer with a thickness of 80-200nm on the back of the raw silicon wafer, and the back of the raw silicon wafer is passivated.

[0081] Then, after the surface of the raw silicon wafer is cleaned by wrapping around, an aluminum oxide layer and a silicon nitride film layer (anti-reflection passivation layer) are respectively plated on the front and back sides of the N-type raw silicon wafer.

[0082] Step S107, printing and sintering the raw silicon wafer after being plated with the silicon nitride thin film layer.

[0083] The specific steps that can be implemented in step S107 also include:

[0084] Step S1071, printing silver electrodes and solder joints on the front and back sides of the raw silicon wafer after the silicon nitride film layer is processed, and sintering the raw silicon wafer, controlling the temperature of the sintering furnace to 700-800°C.

[0085] Step S108: producing a finished solar cell by silicon wafer preparation.

[0086] Step S109: performing a battery efficiency test on the finished solar cell.

[0087] The specific steps that can be implemented in step S109 also include:

[0088] Step S1091, obtaining the current of the finished solar cell, obtaining the opening voltage of the finished solar cell, obtaining the filling factor of the finished solar cell, and obtaining the area of ​​the finished solar cell;

[0089] The cell efficiency of the finished solar cell is calculated by the formula: the current of the finished solar cell×the opening voltage of the finished solar cell×the fill factor of the finished solar cell / the area of ​​the finished solar cell.

[0090] In this embodiment, it should also be noted that an IV testing machine is used to test the efficiency of the finished solar cell.

[0091] The above implementation examples are only examples of embodiments of the present application, and the present application will not be limited to the above embodiments. Through the content of the present application, relevant technical personnel can make various deductions and modifications without departing from the scope of the present application, which should all fall within the scope of protection of the claims of the present application.

[0092] The technical solution provided in this application can, on the one hand, reduce the boron source concentration on the surface of the silicon wafer and improve the passivation performance of the silicon wafer surface; on the other hand, it can maintain the uniformity of the block resistance within and between wafers, and at the same time will not cause the contact resistance between the printed gate line and the silicon wafer to increase, nor will it cause the fill factor of the finished battery to decrease.

[0093] The technical solution provided in the present application can achieve the purpose of reducing the boron concentration on the surface of the silicon wafer by controlling the heating rate. This method is simple to operate, will not affect the uniformity of the square resistance within and between silicon wafers after boron diffusion, and is more conducive to the stability of field data.

[0094] The technical solution provided in the present application controls the temperature so that the boron diffusion process proceeds smoothly, preventing the problem of excessive source entering the silicon wafer due to excessive temperature rise, thereby affecting the passivation of the silicon wafer surface. The opening voltage of the semi-finished battery tested with a double-sided passivation sheet can be increased by 19mV, the opening voltage of the finished battery can be increased by 1-2mV, and the efficiency of the finished battery can be increased by 0.1%.

[0095] As shown in Table 1 below, after the boron diffusion process, the opening voltage Voc comparison data of the semi-finished battery of the passivation film was tested by a universal minority carrier lifetime tester. The test temperature was 25±2°C. It can be seen that the opening voltage of the semi-finished battery tested by the double-sided passivation film of the technical solution of the present application increased by 19mV.

[0096] Here, the brand of the minority carrier lifetime tester is Sinton of the United States, and the model of the minority carrier lifetime tester is WCT-120.

[0097] Table 1

[0098] Minority carrier lifetime (Us) <![CDATA[Current density (A / cm 2 )]]> Semi-finished battery opening voltage (V) Existing process 359.57 <![CDATA[3.05*10 -14 ]]> 0.6970 This application process 721.67 <![CDATA[2.31*10 -14 ]]> 0.7159

[0099] Table 2 below shows the test comparison data of finished battery efficiency. It can be seen that the efficiency of the finished battery is improved by 0.1% through the technical solution of this application:

[0100] Table 2

[0101]

[0102] The present application also provides a solar cell prepared by the solar cell preparation method. The solar cell preparation method comprises:

[0103] Provide N-type raw silicon wafers after texturing;

[0104] Putting the textured N-type raw silicon wafer into quartz glass;

[0105] The Tongyuan temperature rising process is divided into four heating stages, and the percentage of the total heating power of the heating wire and the heating rate in each heating stage are set to perform boron diffusion treatment on the N-type raw silicon wafer; the four heating stages are respectively the first heating stage, the second heating stage, the third heating stage and the fourth heating stage, wherein the heating rate of the fourth heating stage is the first percentage threshold of the average heating rate of the four heating stages of the Tongyuan temperature rising;

[0106] The borosilicate glass layer of the N-type raw silicon wafer after the boron diffusion treatment is cleaned, and the back of the raw silicon wafer is subjected to alkali polishing treatment, and the finished solar cell is generated through silicon wafer preparation.

[0107] The technical solution provided in the present application controls the temperature so that the boron diffusion process proceeds smoothly, preventing the problem of excessive source entering the silicon wafer due to excessive temperature rise, thereby affecting the passivation of the silicon wafer surface. The opening voltage of the semi-finished battery tested with a double-sided passivation sheet can be increased by 19mV, the opening voltage of the finished battery can be increased by 1-2mV, and the efficiency of the finished battery can be increased by 0.1%.

[0108] It should be understood that the above specific embodiments of the present application are only used to illustrate or explain the principles of the present application, and do not constitute a limitation to the present application. Therefore, any modifications, equivalent substitutions, improvements, etc. made without departing from the spirit and scope of the present application should be included in the protection scope of the present application. In addition, the claims attached to the present application are intended to cover all changes and modifications that fall within the scope and boundaries of the attached claims, or the equivalent forms of such scope and boundaries.

Claims

1. A method for preparing a solar cell, characterized in that: The following steps are involved: Provide N-type raw silicon wafers after texturing; Putting the textured N-type raw silicon wafer into quartz glass; The Tongyuan temperature rising process is divided into four heating stages, and the percentage of the total heating power of the heating wire and the heating rate in each heating stage are set to perform boron diffusion treatment on the N-type raw silicon wafer; the four heating stages are respectively the first heating stage, the second heating stage, the third heating stage and the fourth heating stage, wherein the heating rate of the fourth heating stage is the first percentage threshold of the average heating rate of the four heating stages of the Tongyuan temperature rising; The borosilicate glass layer of the N-type raw silicon wafer after the boron diffusion treatment is cleaned, and the back of the raw silicon wafer is subjected to alkali polishing treatment, and the finished solar cell is generated through silicon wafer preparation.

2. The method for preparing a solar cell according to claim 1, characterized in that: Before providing the N-type raw silicon wafer after texturing, the method further includes: The N-type raw silicon wafer is placed in a sodium hydroxide solution and a surfactant additive system alkali solution to react on the front and back sides of the N-type raw silicon wafer to form a pyramid-shaped velvet surface; Wherein, the surfactant additive includes isopropanol.

3. The method for preparing a solar cell according to claim 1, characterized in that: The first temperature rising stage is 850-930°C, the second temperature rising stage is 930-950°C, the third temperature rising stage is 950-970°C, and the fourth temperature rising stage is 970-980°C.

4. The method for preparing a solar cell according to claim 3, characterized in that: The setting of the percentage of the total heating power of the heating wire and the heating rate in each heating stage includes: The percentage of the total heating power of the heating wire in the first heating stage is set to 100%, and the heating rate of the first heating stage is controlled to be 15-20°C / min, and the heating time is 10min; the percentage of the total heating power of the heating wire in the second heating stage is set to 60%, and the heating rate of the second heating stage is controlled to be 10-15°C / min, and the heating time is 5min; the percentage of the total heating power of the heating wire in the third heating stage is set to 30%, and the heating rate of the third heating stage is controlled to be 5-10°C / min, and the heating time is 5min; the percentage range of the total heating power of the heating wire in the fourth heating stage is set to 5-10%, and the heating rate of the fourth heating stage is controlled to be 2-3°C / min, and the heating time is 5min; The first percentage threshold range of the heating rate in the fourth heating stage and the average heating rate in the four heating stages of the through-source temperature rise is 14%-32%.

5. The method for preparing a solar cell according to claim 1, characterized in that: The method of removing the borosilicate glass layer from the N-type raw silicon wafer after the boron diffusion treatment and performing alkali polishing on the back of the raw silicon wafer comprises: Under the conditions of reaction temperature of 25-35° C. and belt speed of 2.5-3.5 m / s, using a hydrofluoric acid solution in a chain cleaning machine to clean the borosilicate glass layer on the back of the N-type raw silicon wafer; Using sodium hydroxide solution and additives at an alkali polishing tank temperature of 55-70°C, the back side of the N-type raw silicon wafer after the borosilicate glass layer is removed and cleaned is subjected to alkali polishing treatment, and the alkali polishing treatment reaction time is controlled to be 130-200S; Wherein, the concentration of the hydrofluoric acid solution is 50%-60%, and the concentration of the sodium hydroxide solution is 15-25%.

6. The method for preparing a solar cell according to claim 1, characterized in that: After the back side of the raw silicon wafer is subjected to alkali polishing, the method comprises: The raw silicon wafer after alkali polishing is placed in a graphite boat and enters a tubular diffusion furnace tube, and a tunneling silicon dioxide oxide layer with a thickness of 1-2 nm and a polysilicon layer with a thickness of 80-200 nm are plated on the back of the N-type raw silicon wafer by hydrogen, silane, nitrous oxide and phosphine, so as to passivate the back of the raw silicon wafer; An aluminum oxide layer and a silicon nitride film layer are respectively plated on the front and back sides of the N-type raw silicon wafer.

7. The method for preparing a solar cell according to claim 6, characterized in that: Before the finished solar cell is produced by silicon wafer preparation, the method further includes: printing and sintering the raw silicon wafer after the silicon nitride film layer is processed; after the finished solar cell is produced by silicon wafer preparation, the method further includes: testing the cell efficiency of the finished solar cell.

8. The method for preparing a solar cell according to claim 7, characterized in that: The method of printing and sintering the raw silicon wafer after the silicon nitride film layer is processed comprises: Silver electrodes and solder joints are printed on the front and back sides of the raw silicon wafer after the silicon nitride film layer is plated, and the raw silicon wafer is sintered, and the temperature of the sintering furnace is controlled to be 700-800°C.

9. The method for preparing a solar cell according to claim 7, characterized in that: The method of testing the efficiency of the finished solar cell comprises: Obtaining the current of the finished solar cell, obtaining the opening voltage of the finished solar cell, obtaining the filling factor of the finished solar cell, and obtaining the area of ​​the finished solar cell; The cell efficiency of the finished solar cell is calculated by the formula: the current of the finished solar cell×the opening voltage of the finished solar cell×the fill factor of the finished solar cell / the area of ​​the finished solar cell.

10. A solar cell prepared by the solar cell preparation method according to any one of claims 1 to 9.

Images