System and method for matrix multiplication

Abstract

The embodiment of the invention provides a system for matrix multiplication. In accordance with the proposed system, a remainder system (RNS) is used to implement support of a variety of sizes in matrix multiplication hardware acceleration. And the forward conversion unit and the reverse conversion unit realize support of various sizes under a special control signal. The expansion of the forward conversion unit of the RNS can explain 64-bit input values in different ways according to control signal values and perform modular reduction operation on a single 64-bit value or two 32-bit values or four 16-bit values. The extension of the inverse conversion unit of the RNS enables the reconstruction of values of different size types using efficient hierarchical control accumulation. Thus, the proposed system for matrix multiplication provides support for multiple sizes of matrix multiplication and achieves lower power consumption without increasing the hardware area.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of matrix multiplication, and more specifically, to a system and method for matrix multiplication. Background Art

[0002] Dedicated matrix multiplication acceleration is widely used in high performance computing (HPC) and artificial intelligence (AI), but the two fields have different requirements for size types - integer32(int32) / integer64(int64) is mainly used in HPC, while int8 / int16 is commonly used in AI. For hardware manufacturers, this provides two strategic directions - create dedicated accelerators for AI and HPC, or minimize development costs by creating accelerators suitable for both fields. A common way to support different size types in hardware is to have a dedicated accelerator for each integer length (e.g. CDNA TM Matrix core technology) to implement a separate multiply accumulator (MAC) unit. However, this often makes the final product less competitive than domain-specific matrix multiplication accelerators due to partially unused hardware and higher power consumption. Summary of the invention

[0003] Embodiments of the present application provide a system and method for matrix multiplication, which provide reconfigurable matrix multiplication support of various sizes.

[0004] According to a first aspect, there is provided a system for matrix multiplication, the system comprising a forward transform unit, a modular arithmetic unit and an inverse transform unit.

[0005] Wherein, the forward conversion unit is used for:

[0006] Receiving a binary input value and a control signal, wherein the control signal is used to indicate the size type of the input value;

[0007] Performing a forward conversion on the input value according to the size type to obtain a conversion value of the input value, wherein the conversion value of each input value is a set of remainders of the input value in a residue number system (RNS);

[0008] The converted value is output to the modulo arithmetic unit.

[0009] Wherein, the modular arithmetic unit is used for:

[0010] receiving the conversion value from the forward conversion unit;

[0011] Performing a modular arithmetic operation on the conversion value according to the modulus set of the RNS to obtain an operation result;

[0012] The operation result is output to the inverse conversion unit.

[0013] Wherein, the reverse conversion unit is used for:

[0014] receiving the operation result and the control signal;

[0015] The operation result is inversely converted according to the control signal to obtain a binary output value, wherein the binary output value and the binary input value have the same size type.

[0016] For example, the size type includes one of the following types: a 64-bit type, a 32-bit type, or a 16-bit type.

[0017] In addition, as an example, the inverse conversion unit is used to perform inverse conversion on the operation result according to the control signal and the Chinese Remainder Theorem (CRT) to obtain a binary output value. Optionally, the CRT can also be replaced by an extended CRT (EXCRT) or a mixed-radix conversion (MRC).

[0018] According to the system proposed in the present application, the residue number system (RNS) is used to implement support for multiple sizes in matrix multiplication hardware acceleration. The forward conversion unit and the reverse conversion unit implement support for multiple sizes under a dedicated control signal. The extension of the forward conversion unit of RNS can interpret the 64-bit input value in different ways according to the control signal value, and perform a modular reduction operation on a single 64-bit value or two 32-bit values ​​or four 16-bit values. The extension of the reverse conversion unit of RNS based on the Chinese Remainder Theorem (CRT) (only an example) can use efficient hierarchical control accumulation to reconstruct values ​​of different sizes. Therefore, the proposed system for matrix multiplication provides support for multiple sizes of matrix multiplication and achieves lower power consumption without increasing the hardware area.

[0019] In some implementations, the forward conversion unit includes M multiplexers, wherein the M multiplexers correspond to M modular reduction unit groups, and the system supports value processing of multiple size types, wherein the multiple size types include a first size type and a second size type, and the first size type corresponds to the maximum size supported by the system.

[0020] In the case where the control signal indicates the first size type, the M multiplexers respectively obtain each value of the binary input value as an input of a corresponding modular reduction unit group; or

[0021] When the control signal indicates the second size type, the M multiplexers respectively obtain partial bits of each value in the binary input value as input of the corresponding modular reduction unit group, and M is an integer greater than or equal to 2.

[0022] In some implementations, each of the M modular reduction unit groups includes P modular reduction units, where P is an integer greater than or equal to 2.

[0023] For example, M=4, P=4, that is, the forward conversion unit includes four modular reduction unit groups, and each of the four modular reduction unit groups corresponding to the four multiplexers includes four modular reduction units.

[0024] Furthermore, M·P is the number of moduli included in the moduli set corresponding to the RNS of the proposed application.

[0025] In some implementations, the forward conversion unit includes four multiplexers and four modular reduction unit groups, wherein the four multiplexers correspond one-to-one to the four modular reduction unit groups; each of the four modular reduction unit groups includes four modular reduction units, and the four modular reduction unit groups include a total of 16 modular reduction units, wherein the 16 modular reduction units correspond one-to-one to the 16 moduli of the RNS.

[0026] Wherein, the four multiplexers are specifically used for:

[0027] receiving the control signal;

[0028] In a case where the value of the control signal is equal to the first value, determining the size type of the input value as a 64-bit type;

[0029] The input values ​​are obtained, and each input value is output to each modular reduction unit of the 16 modular reduction units.

[0030] The 16 modular reduction units are specifically used for:

[0031] A reduction operation is performed on each input value so as to obtain 16 conversion values ​​according to the corresponding moduli of the 16 modular reduction units, respectively, wherein each of the 16 modular reduction units obtains one conversion value among the 16 conversion values.

[0032] According to this embodiment, the extension of the RNS forward conversion unit can interpret each 64-bit input value as a single 64-bit value according to the control signal value, and the forward conversion unit performs a forward conversion on the input 64-bit value to obtain a remainder of the input 64-bit value.

[0033] It should be noted that, in this embodiment, 16 is taken as an example, because 16 is easily divisible by 4, and in fact, it can be any number other than the total modulus 16 used. In addition, there is no strict requirement that different groups have the same number of moduli, for example, a group can have three, four, five or other numbers of moduli. These requirements are only related to the multiplication value of the modulus, and the multiplication value of the modulus should be higher than the binary range covered.

[0034] In some implementations, the forward conversion unit includes four multiplexers and four modular reduction unit groups, wherein the four multiplexers correspond one-to-one to the four modular reduction unit groups; each of the four modular reduction unit groups includes four modular reduction units, and the four modular reduction unit groups include a total of 16 modular reduction units, wherein the 16 modular reduction units correspond one-to-one to the 16 moduli of the RNS.

[0035] Wherein, the four multiplexers are specifically used for:

[0036] receiving the control signal;

[0037] In a case where the value of the control signal is equal to the second value, the size type of the input value is determined to be a 32-bit type.

[0038] Among them, the first multiplexer and the third multiplexer of the four multiplexers respectively obtain the lower 32 bits of each input value, the first multiplexer outputs the lower 32 bits to the corresponding first modular reduction unit group, and the third multiplexer outputs the lower 32 bits to the corresponding third modular reduction unit group.

[0039] Among them, the second multiplexer and the fourth multiplexer of the four multiplexers respectively obtain the upper 32 bits of each input value, the second multiplexer outputs the upper 32 bits to the corresponding second modular reduction unit group, and the fourth multiplexer outputs the upper 32 bits to the corresponding fourth modular reduction unit group.

[0040] The four modular reduction units are specifically used for:

[0041] The first modular reduction unit group and the third modular reduction unit group respectively perform modular reduction operations on the lower 32 bits according to four moduli corresponding to the four modular reduction units included in each of the first modular reduction unit group and the third modular reduction unit group, so as to obtain four conversion values ​​respectively;

[0042] The second modular reduction unit group and the fourth modular reduction unit group respectively perform modular reduction operations on the upper 32 bits according to four moduli corresponding to the four modular reduction units included in each modular reduction unit group in the second modular reduction unit group and the fourth modular reduction unit group, so as to obtain four conversion values ​​respectively.

[0043] According to this embodiment, the extension of the RNS forward conversion unit can interpret each 64-bit input value as two 32-bit values ​​according to the control signal value, and the forward conversion unit performs forward conversion on the two 32-bit values ​​respectively to obtain the remainders of the two 32-bit values.

[0044] In some implementations, the forward conversion unit includes four multiplexers and four modular reduction unit groups, wherein the four multiplexers correspond one-to-one to the four modular reduction unit groups; each of the four modular reduction unit groups includes four modular reduction units, and the four modular reduction unit groups include a total of 16 modular reduction units, wherein the 16 modular reduction units correspond one-to-one to the 16 moduli of the RNS.

[0045] Wherein, each of the four multiplexers is specifically used for:

[0046] receiving the control signal;

[0047] When the value of the control signal is equal to the third value, determining the size type of the input value as a 16-bit type;

[0048] One of the four segments constituting each input value is obtained, and the obtained segments are respectively output to corresponding modular reduction unit groups.

[0049] Wherein, each of the modular reduction unit groups is specifically used for:

[0050] According to four moduli corresponding to the four modular reduction units included in each of the four modular reduction unit groups, modular reduction operations are respectively performed on the corresponding segments to obtain four converted values ​​respectively.

[0051] According to this embodiment, the extension of the RNS forward conversion unit can interpret each 64-bit input value as four 16-bit values ​​according to the control signal value, and the forward conversion unit performs forward conversion on the four 16-bit values ​​respectively to obtain remainders of the four 16-bit values.

[0052] In some implementations, the modular arithmetic unit includes 16 multiply accumulator (MAC) units, wherein the 16 MAC units correspond one-to-one to the 16 moduli, and the 16 MAC units correspond one-to-one to the 16 modular reduction units.

[0053] Wherein, each of the 16 MAC units is specifically used for:

[0054] The conversion values ​​are received from the corresponding modular reduction units, and modular multiplication and modular accumulation operations are performed on each conversion value according to the corresponding modulus to obtain a corresponding operation result.

[0055] Wherein, when performing the modular multiplication and the modular accumulation operation, the 16 MAC units are formed into different groups in the following manner:

[0056] In a case where the size type of the input value is a 64-bit type, the 16 MAC units form a group, wherein the group is used to perform the modular multiplication and the modular accumulation operations on the 16 conversion values ​​from the 16 modular reduction units, and output 16 operation results corresponding to the 16 conversion values; or

[0057] In the case where the size type of the input value is a 32-bit type, the 16 MAC units are formed into two groups, wherein each of the two groups includes eight MAC units, and one of the two groups is used to perform the modular multiplication and the modular accumulation operations on eight conversion values, and output eight operation results corresponding to the eight conversion values, and the eight conversion values ​​respectively include the four conversion values ​​from the first modular reduction unit and the third modular reduction unit; wherein the other group of the two groups is used to perform the modular multiplication and the modular accumulation operations on the other eight conversion values, and output eight operation results corresponding to the other eight conversion values, and the other eight conversion values ​​respectively include the four conversion values ​​from the second modular reduction unit and the fourth modular reduction unit; or

[0058] In the case where the size type of the input value is a 16-bit type, the 16 MAC units are organized into four groups, wherein each of the four groups includes four MAC units, and the four groups correspond one-to-one to the four modular reduction unit groups, and each of the four groups is used to perform the modular multiplication and the modular accumulation operations on the four conversion values ​​from the four modular reduction units included in the corresponding modular reduction group, and respectively output four operation results corresponding to the four conversion values.

[0059] In some implementations, the reverse conversion unit supports reverse conversion of multiple size types, wherein the multiple size types further include a third size type, and the third size type corresponds to a minimum size supported by the system.

[0060] The inverse conversion unit includes: a first multiplexer set including M·P multiplexers and a second multiplexer set including V multiplexers, the M·P multiplexers respectively corresponding to the M·P operation results of the modular arithmetic unit, and the V multiplexers are used to output the binary output value.

[0061] In a case where the value of the control signal indicates the first size type, each of the V multiplexers respectively obtains a segment of the modular reduction result associated with all the M·P operation results as an output, and the V segments corresponding to the V multiplexers reconstruct the binary output value corresponding to the first size type; or

[0062] In a case where the value of the control signal indicates a third size type, each of the V multiplexers obtains as output a modular reduction result associated with P of the M·P operation results, and the modular reduction result obtained by each multiplexer reconstructs a binary output value corresponding to the third size type; or

[0063] In the case where the value of the control signal indicates the second size type, each of the V multiplexers obtains as output a modular reduction result associated with L operation results of the M·P operation results, and the modular reduction result obtained by each of the V multiplexers is a segment of a binary output corresponding to the second size type, where L is an integer multiple of P.

[0064] For example, M=4, P=4, V=4, the first multiplexer set includes 16 multiplexers, and the second multiplexer set includes 4 multiplexers.

[0065] In some implementations, the first multiplexer set includes 16 multiplexers, wherein the 16 multiplexers correspond one-to-one to the 16 MAC units, the 16 multiplexers are divided into four multiplexer groups, and each of the four multiplexer groups includes four multiplexers.

[0066] The 16 multiplexers included in the first multiplexer set are respectively used to receive the control signal, and return constant values ​​from three pre-calculated constant values ​​according to the control signal.

[0067] Wherein, the inverse conversion unit also includes a multiplier set, the multiplier set includes 16 multipliers, the 16 multipliers correspond one-to-one to the 16 multiplexers included in the first multiplexer set, and the 16 multipliers correspond one-to-one to the 16 MAC units; wherein each of the 16 multipliers is used to perform multiplication operations on the outputs of the corresponding multipliers in the 16 multipliers and the outputs of the corresponding MAC units in the 16 MAC units, and output the corresponding operation results.

[0068] The inverse conversion unit also includes three adder sets, wherein the first adder set of the three adder sets includes four adders, the four adders correspond one-to-one to the four multiplexer groups, and the input of each of the four adders includes the output of four multipliers corresponding to the four multiplexers in the corresponding multiplexer group.

[0069] The second adder set of the three adder sets includes two adders, wherein the first adder of the two adders is used to receive the output of the first adder and the output of the second adder included in the first adder set, and the second adder of the two adders is used to receive the output of the third adder and the output of the fourth adder included in the first adder set.

[0070] The third adder set of the three adder sets includes an adder, wherein the adder is used to receive outputs of the two adders included in the second adder set.

[0071] Among them, the second multiplexer set includes the four multiplexers, the input of each multiplexer included in the four multiplexers is obtained by performing the modular reduction operation on the outputs of the four adders included in the first adder set, the input of each multiplexer included in the four multiplexers is obtained by performing the modular reduction operation on the outputs of the two adders included in the second adder set, or the input of each multiplexer included in the four multiplexers is obtained by performing the modular reduction operation on the outputs of the adders included in the third adder set.

[0072] The four multiplexers included in the second multiplexer set are used to receive the control signal and determine corresponding output values ​​according to the control signal.

[0073] In some implementations, the three pre-calculated constant values ​​for the i-th multiplexer of the 16 multiplexers included in the first set of multiplexers include: and Wherein, 1≤i≤16 and i is a positive integer.

[0074] Wherein, the i-th multiplexer is specifically used for:

[0075] Output when the value of the control signal is equal to the first value

[0076] Output when the value of the control signal is equal to the second value

[0077] Output when the value of the control signal is equal to the third value

[0078] In some implementations, the set of 16 moduli of the RNS is {m1, m2, ..., m 16}, wherein the 16 moduli satisfy the following criteria:

[0079] (1)

[0080] (2)m1×m5×m9×m 13 ×m3×m7×m 11 ×m 15 >2 64 ;

[0081] (3)m2×m6×m 10 ×m 14 ×m4×m8×m 12 ×m 16 >2 64 ;

[0082] (4)m1×m5×m9×m 13 >2 32 ;

[0083] (5)m2×m6×m 10 ×m 14 >2 32 ;

[0084] (6)m3×m7×m 11 ×m 15 >2 32 ;

[0085] (7)m4×m8×m 12 ×m 16 >2 32 .

[0086] In some implementations, the four modular reduction unit groups correspond one-to-one to four modular groups consisting of the 16 modular numbers, and the four modular groups are: {m1, m5, m9, m 13}, {m2,m6,m 10 ,m 14}、{m3,m7,m 11 ,m 15} and {m4,m8,m 12 ,m 16}, where {m1,m2,…,m 16}={512,511,509,489,487,485,481,479,473,467,431,167,151,139,137,131}.

[0087] It should be noted that the values ​​of the sixteen moduli are only examples, and the standards that the sixteen moduli must meet are as described above.

[0088] In some implementations, the four multiplexers included in the second multiplexer set are specifically used to:

[0089] When the value of the control signal is equal to the first value, the output of each of the four multiplexers is a modular reduction operation s%M performed on the output of the adder included in the third adder set. 64 , wherein s is the output of the adder included in the third adder set, The outputs of the four multiplexers are four segments of the operation results, wherein the four segments are o 64 [15:0], o 64 [31:16], o 64 [47:32] and o 64 [63:48].

[0090] In some implementations, the four multiplexers included in the second multiplexer set are specifically used to:

[0091] When the value of the control signal is equal to the second value, the output of the first multiplexer and the second multiplexer among the four multiplexers is a modular reduction operation performed on the output of the first adder included in the second adder set. , wherein t1 is the output of the first adder included in the second adder set, The outputs of the first multiplexer and the second multiplexer are two segments of the operation result, respectively, wherein the two segments are and

[0092] The outputs of the third multiplexer and the fourth multiplexer among the four multiplexers are modular reduction operations performed on the outputs of the second adders included in the second adder set. t2 is the output of the second adder included in the second adder set, The outputs of the third multiplexer and the fourth multiplexer are two segments of the operation result, wherein the two segments are and

[0093] In some implementations, the four multiplexers included in the second multiplexer set are specifically used to:

[0094] When the value of the control signal is equal to the third value, the output of the j-th multiplexer among the four multiplexers is a modular reduction operation performed on the output of the j-th adder included in the first adder set. The result of the operation, where p j is the output of the j-th adder, 1≤j≤4 and j is an integer, the outputs of the four multiplexers are

[0095] According to a second aspect, there is provided a method for matrix multiplication, the method comprising:

[0096] A binary input value and a control signal are received, wherein the control signal is used to indicate the size type of element values ​​of two matrices on which matrix multiplication is to be performed.

[0097] The element value is obtained according to the input value and the control signal.

[0098] Performing a forward conversion on the element value to obtain a conversion value of the element value, wherein the conversion value of each element value is a set of remainders of the element value in a residue number system (RNS);

[0099] Perform a modular arithmetic operation on the conversion value according to the modulus set of the RNS to obtain an operation result, wherein the modular arithmetic operation includes the matrix multiplication.

[0100] The operation result is inversely converted according to the control signal to obtain the binary output value, wherein the output value and the input value have the same size type, and an output matrix includes the output value.

[0101] In some implementations, obtaining the element value according to the input value and the control signal further includes:

[0102] In a case where the value of the control signal is equal to the first value, obtaining the element value by determining each input value as a single 64-bit element value;

[0103] In a case where the value of the control signal is equal to a second value, obtaining the element value by splitting each input value into two 32-bit element values; or

[0104] In a case where the value of the control signal is equal to a third value, the element value is obtained by splitting each input value into four 16-bit element values.

[0105] In some implementations, the set of 16 moduli of the RNS is {m1, m2, ..., m 16}, wherein the 16 moduli satisfy the following criteria:

[0106] (1)

[0107] (2)m1×m5×m9×m 13 ×m3×m7×m 11 ×m 15 >2 64 ;

[0108] (3)m2×m6×m 10 ×m 14 ×m4×m8×m 12 ×m 16 >2 6 ;

[0109] (4)m1×m5×m9×m 13 >2 32 ;

[0110] (5)m2×m6×m 10 ×m 14 >2 32 ;

[0111] (6)m3×m7×m 11 ×m 15 >2 32 ;

[0112] (7)m4×m8×m 12 ×m 16 >2 32 .

[0113] According to a third aspect, a computing device is provided. The computing device has the function of implementing the method in the second aspect and any possible implementation of the second aspect. The function can be implemented by hardware. The hardware or software includes one or more units corresponding to the above functions. Optionally, the computing device is a chip or a chip system.

[0114] According to a fourth aspect, a chip is provided, wherein the chip includes a plurality of circuits, wherein the plurality of circuits are used to implement the functions of the units included in the system provided according to the first aspect and any possible implementation manner of the first aspect. BRIEF DESCRIPTION OF THE DRAWINGS

[0115] One or more embodiments are described exemplarily by corresponding drawings, and these exemplary descriptions and drawings do not constitute limitations on the embodiments. The same reference numerals are used in the drawings to refer to the same elements, and the drawings are not drawn to scale. In the drawings:

[0116] Figure 1 is a schematic block diagram of a system for supporting matrix multiplication of various sizes provided by the present application;

[0117] Figure 2 It is an example of the basic process of RNS;

[0118] Figure 3 is a schematic structural diagram of a forward conversion unit provided by the present application;

[0119] Figure 4 is an example of a forward conversion unit provided in the present application;

[0120] Figure 5 is a schematic diagram of the structure of the modular arithmetic unit provided by the present application;

[0121] Figure 6 It is a schematic diagram of the structure of the reverse conversion provided by this application;

[0122] Figure 7 It is a schematic diagram of the method for matrix multiplication provided by the present application. DETAILED DESCRIPTION

[0123] In order to understand the features and technical contents of the embodiments of the present invention in detail, the implementation of the embodiments of the present invention will be described in detail below in conjunction with the accompanying drawings, which are only used for reference and illustration purposes and are not used to limit the embodiments of the present invention. In the following technical description, for ease of explanation, many details are described to help a thorough understanding of the disclosed embodiments. However, one or more embodiments may be implemented without these details. In other cases, in order to simplify the drawings, known structures and devices may be simplified.

[0124] 1. Residue number system (RNS)

[0125] RNS consists of a set of k modules called modules {m1,m2,…,m k It is usually assumed that k moduli are pairwise relatively prime, that is, GCD(m i ,mj )=1,i,j∈[1,k],i≠j. Let M be all m i The product of: Then the set x→{x1,x2,…,x k} means, that is

[0126] One of the most significant features of RNS is that the addition and multiplication between corresponding residue pairs are independent and can be performed in parallel. In this application, it is proposed to use RNS to implement hardware-efficient and reconfigurable support for matrix multiplication and integrate support for different integer types (including int64, int32, and int16).

[0127] A common approach to supporting various integer types is to add a dedicated multiply accumulator (MAC) unit for each size. The advantage of this approach is that calculations of various integer types and sizes can be performed in parallel. When only large (such as HPC) or small (such as AI) integer calculations are required, hardware efficiency cannot be improved by equipping each size with a dedicated MAC. A similar idea to support calculations of multiple sizes is to use smaller multiplications to create larger multiplications. This can be done in a variety of ways. Multipliers are used to build D×D multipliers. Implementing 64-bit multiplication via 4×32-bit multiplications adds 17% to 20% additional hardware and consumes 23% to 25% more power than dedicated 64-bit multiplication. A typical implementation of a dedicated 64-bit multiplier is 3.2x to 3.9x larger in area than a 32-bit multiplier, and an additional 128-bit accumulator is required to implement a 64-bit multiplier. By splitting the D×D multiplier into The reconfigurable multiple-size feature of the multiplier requires full reconstruction of the final value as a result of the multiplication operation, which incurs significant additional cost in hardware.

[0128] In view of this, a system for matrix multiplication is proposed, wherein the system provides support for matrix integer multiplication of various sizes without increasing hardware area, and the system achieves lower power consumption compared with conventional 64-bit integer matrix multiplication.

[0129] This application proposes to use the remainder-independent computational features of RNS to provide support for multiple sizes for matrix multiplication. The main idea of ​​the scheme proposed in this application is to split 64-bit multiplication into 16 modular multiplications, which has a series of advantages. The proposed scheme should be used in matrix multiplication hardware systems by switching all multiplication and accumulation operations to RNS. Although switching to RNS requires additional forward and reverse conversion costs, in the case of matrix multiplication, it can be ignored because the number of conversion operations is an order of magnitude less than the number of multiplications and additions.

[0130] The solution proposed in this application is described below.

[0131] Figure 1 is a schematic block diagram of a system for supporting matrix multiplication of various sizes provided by the present application. Figure 1 As shown, the system (100) includes a forward conversion unit (110), a modular arithmetic unit (120) and a reverse conversion unit (130). The forward conversion unit (110) is used to receive binary values ​​of input matrices A and B, and perform forward conversion on the binary values ​​to obtain conversion values, that is, to perform conversion from a binary number system (BNS) to RNS. In addition, the forward conversion unit (110) interprets the input value in different ways according to the input control signal of the system (100). In the present application, the forward conversion unit (110) interprets the 64-bit input value as a single 64-bit value, two 32-bit values, or four 16-bit values ​​according to the value of the control signal (represented by the control signal value in the following embodiments). For example, if the control signal value is equal to 0, the 64-bit input value is interpreted as a single 64-bit value, or if the control signal value is equal to 1, the 64-bit input value is interpreted as two 32-bit values, or if the control signal value is equal to 2, the 64-bit input value is interpreted as four 16-bit values. The forward conversion unit (110) outputs the conversion value to the modular arithmetic unit (120). The modular arithmetic unit (120) performs modular arithmetic operations on the conversion value to obtain an operation result according to the control signal. For matrix multiplication, the modular arithmetic operation includes modular multiplication and modular accumulation. The modular arithmetic unit (120) outputs the operation result to the reverse conversion unit (130). The reverse conversion unit (130) is used to reversely convert the operation result according to the control signal value and the Chinese Remainder Theorem (CRT) to reconstruct the binary output value of the output matrix C. Specifically, the reverse conversion is a conversion from RNS to BNS. In the proposed scheme, all multiplication and accumulation operations are performed in RNS.

[0132] Figure 2 is an example of the basic RNS process. Figure 2As shown, in RNS, values ​​are converted to k remainders by performing modular arithmetic on the values ​​according to a set of k moduli. After forward conversion, binary arithmetic operations can be converted to arithmetic operations under RNS. k}, for input matrices A and B, represents the binary value a of the matrix elements that satisfies the dynamic range ij and b ij can be expressed as {x 1 ij ,x 2 ij ,…,x k ij} and {y 1 ij ,y 2 ij ,…,y k ij}, 1≤(i,j)≤n. In the matrix multiplication process, first the elements of matrix A are multiplied by the elements of matrix B: When the operation result Z also meets the dynamic range, the elements of the obtained matrix Z can be expressed as k remainders: 1≤(i,j)≤n, and then converted to binary value.

[0133] Figure 3 Schematic diagram of the structure of the forward conversion unit provided by the present application. Figure 3 As shown, the forward conversion unit includes four multiplexers and four modular reduction unit groups, wherein each modular reduction unit group includes four modular reduction units, and thus the four modular reduction unit groups include 16 modular reduction units in total. Figure 3 As shown, the four multiplexers are MUX 1, MUX 2, MUX 3 and MUX 4, and the 16 modular reduction units are modular reduction unit 1, modular reduction unit 5... modular reduction unit 16. The 16 modular reduction units correspond one-to-one to the 16 moduli provided in the present application, and the set of the 16 moduli is represented by {m1, m2, ..., m 16}.

[0134] The input value A (64 bits) represents a single 64-bit value, or two 32-bit values, or four 16-bit values, depending on the control signals (such as Figure 3 The CTRL) value shown in the following example:

[0135] (1) When CTRL=0, the input value A represents a single 64-bit value, represented here as A[63:0];

[0136] (2) When CTRL=1, the input value A represents two 32-bit values, represented here as {A[63:32], A[31:0]};

[0137] (3) When CTRL=2, the input value A represents four 16-bit values, represented here as {A[63:48], A[47:32], A[31:16], A[15:0]}.

[0138] It should be understood that if the input value represents two 32-bit values, the two 32-bit values ​​are respectively the low 32 bits and the high 32 bits of the input value (64 bits); if the input value represents four 16-bit values, the four 16-bit values ​​are respectively four segments of the input value (64 bits), each of the four segments including 16 bits. In addition, A is an example of an input value. In practice, a large number of input values ​​of two matrices need to perform matrix multiplication.

[0139] like Figure 3 As shown, the forward conversion is based on four multiplexers that provide appropriate inputs to 16 modular reduction units based on the value of the CTRL signal. Four groups of modular reduction units reduce the 64-bit input value.

[0140] The following is a set of 16 moduli {m1,m2,…,m 16} for example.

[0141] Consider the following set of pairwise coprime moduli (m1 = 512, m2 = 511, m3 = 509, m4 = 489, m5 = 487, m6 = 485, m7 = 481, m8 = 479, m9 = 473, m 10 =467, m 11 =431, m 12 =167, m 13 =151, m 14 =139, m 15 =137, m 16 =131) has the following characteristics:

[0142] (1)

[0143] (2)512×509×487×481×473×431×151×137>2 64 ;

[0144] (3)511×489×485×479×467×167×139×131>2 64 ;

[0145] (4)512×487×473×151>2 32 ;

[0146] (5)509×481×431×137>2 32 ;

[0147] (6)511×485×467×139>2 32 ;

[0148] (7)489×479×167×131>2 32 .

[0149] Therefore, the entire set of moduli can be used for 64-bit multiplication. When CTRL=0, all 16 modular reduction units will obtain A. At this time, the outputs of the four multiplexers, namely A0[63:0], A1[63:0], A2[63:0] and A3[63:0] are the same, namely A.

[0150] Two subsets of moduli can be used for 32-bit multiplication, namely, the first subset is represented by {m1,m3,m5,m7,m9,m 11 ,m 13 ,m 15}=[512,509,487,481,473,431,151,137], the second subset is represented by {m2,m4,m6,m8,m 10 ,m 12 ,m 14 ,m 16}=[511,489,485,479,467,167,139,131]. When CTRL=1, the first subset is processed by the first multiplexer and the third multiplexer, and the first multiplexer and the third multiplexer both return the lower 32 bits of the input value A; the second subset is processed by the second multiplexer and the fourth multiplexer, and the second multiplexer and the fourth multiplexer both return the upper 32 bits of the input value A. In this case, the first group and the third group both get A[31:0], and the second group and the fourth group both get A[63:32].

[0151] Four subsets of moduli can be used for 16-bit multiplication, namely {m1,m5,m9,m 13}=[512,487,473,151]、{m3,m7,m 11 ,m 15}=[509,481,431,137]、{m2,m6,m 10 ,m 14}=[511,485,467,139]、{m4,m8,m 12 ,m 14 = [489,479,167,131]. When CTRL = 2, each multiplexer returns the corresponding 16 bits of the input value A, and each group of modular reduction units processes a single 16-bit value. In this case, the first group gets A[15:0], the second group gets A[31:16], the third group gets A[47:32], and the fourth group gets A[63:48].

[0152] In the above different situations, the modular reduction unit performs a modular reduction operation on the value received from the corresponding multiplexer to obtain a conversion value in the RNS corresponding to the input value. It should be noted that the conversion value is actually the RNS remainder of the input value.

[0153] For example, when CTRL=0, the input value is a single 64-bit value, and each modular reduction unit obtains a single 64-bit value, and then processes the single 64-bit value according to the corresponding modulus. Modular reduction unit 1 performs modular reduction operation on the single 64-bit value according to the modulus corresponding to modular reduction unit 1, that is, m1, and modular reduction unit 5 performs modular reduction operation on the single 64-bit value according to the modulus corresponding to modular reduction unit 5, that is, m5, and so on. The 16 modular reduction units return 16 remainders, that is, Figure 3 The {x1,x2,x3,…,x 16}.

[0154] When CTRL=1, the input value is two 32-bit values. The modular reduction units of the first and third groups obtain the lower 32 bits of the input value, which are called the first 32-bit value, and the modular reduction units of the second and fourth groups obtain the upper 32 bits of the input value, which are called the second 32-bit value. The modular reduction units of the first and third groups process the first 32-bit value according to the corresponding modulus, respectively. Specifically, each modular reduction unit of the first and third groups performs a modular reduction operation on the first 32-bit value according to the corresponding modulus to obtain the corresponding remainder. Each modular reduction unit of the second and fourth groups performs a modular reduction operation on the second 32-bit value according to the corresponding modulus to obtain the corresponding remainder. Therefore, the first 32-bit value is obtained by the modulus set {m1,m5,m9,m 13 ,m3,m7,m 11 ,m 15} is converted to a remainder set in RNS, where the remainder set is {x1,x5,x9,x 13 ,x2,x6,x 10 ,x 14}; The second 32-bit value is also passed through the modulus set {m2,m6,m 10 ,m 14 ,m4,m8,m 12 ,m 16} is converted to a remainder set in RNS, where the remainder set is {x2,x6,x 10 ,x 14 ,x4,x8,x 12 ,x 16}.

[0155] When CTRL=2, the input value is four 16-bit values. Each group of modular reduction units obtains a corresponding single 16-bit value, and then processes the single 16-bit value. Specifically, the first group is processed by the modular set, that is, {m1,m5,m9,m 13}, perform modular reduction to obtain the remainder set, namely {x1,x5,x9,x 13}; The second group is through the modulus set, that is, {m3,m7,m 11 ,m 15}, perform modular reduction operation to obtain the remainder set, that is, {x3,x7,x 11 ,x 15}, and so on.

[0156] In addition, Figure 3 In the example, "32'b0" or "48'b0" comes from the Verilog symbol, "32'b0" means "32 bits with 0", and "48'b0" means "48 bits with 0". Taking the first multiplexer as an example, {32'b0, A[31:0]} means that for a 64-bit input value, only the least significant 32 bits are processed, that is, the lower 32 bits of the 64-bit input value, and the first multiplexer regards the most significant 32 bits of the 64-bit input value as zero (as shown in MUX 1). For another example, {48'b0, A[15:0]} means that for a 64-bit input value, only the least significant 16 bits are processed, and the first multiplexer regards the most significant 48 bits of the 64-bit input value as zero. "32'b0" or "48'b0" corresponding to other multiplexers have similar meanings, which can be understood by those skilled in the art based on the above examples and will not be explained one by one here.

[0157] The latency of the forward conversion remains the same regardless of the operation mode (CTRL signal). This is mainly because all modular reduction units work with 64-bit input values ​​independently of the CTRL signal value. When only 16 bits need to be converted, the most significant bits are simply filled with 0s.

[0158] It should be understood that Figure 3 The architecture shown is only an example of a forward conversion unit, and the architecture is applied to the case where the system supports 64-bit size types, 32-bit size types, and 16-bit size types. For another example, according to the set of 16 moduli listed above in this application, if only 64-bit size types and 32-bit size types are supported, the architecture of the forward conversion unit can be as follows: Figure 4 shown.

[0159] Figure 4 is an example of a forward conversion unit provided in this application. Figure 4It can be seen that the forward conversion unit includes two multiplexers, namely MUX 1 and MUX 2. The control signal indicates a 64-bit size type or a 32-bit size type. In the case where the control signal indicates a 64-bit size type, both MUX 1 and MUX 2 obtain an input value A, and the input value A is input into the modular reduction unit groups corresponding to MUX 1 and MUX 2, respectively. In this case, A0=A1. In the case where the control signal indicates a 32-bit size type, the input value A is interpreted as two 32-bit values, MUX 1 obtains the upper 32 bits of the input value, and MUX 2 obtains the lower 32 bits of the input value. The upper 32 bits of the input value are input into the modular reduction unit group corresponding to MUX 1, and the lower 32 bits of the input value are input into the modular reduction unit group corresponding to MUX 2. It can be seen that in this example, MUX 1 and MUX 2 correspond to Figure 4 The two modular reduction unit groups shown, each modular reduction unit group includes eight modular reduction units. The 16 modular reduction units correspond one-to-one to the 16 moduli of the RNS proposed in this application.

[0160] Below Figure 3 The illustrated architecture is used as an example of a forward conversion unit to illustrate other structures of the system proposed in this application.

[0161] Figure 5 Schematic diagram of the structure of the modular arithmetic unit provided by this application. Figure 5 As shown, the modular arithmetic unit includes 16 multiply accumulator (MAC) units, wherein the 16 MAC units and the 16 moduli provided in the present application, namely {m1, m2, ..., m 16}One-to-one correspondence. Each MAC unit includes a modular adder and a modular multiplier. Since modular operations can be performed independently, no additional support for multiple sizes is required in the MAC unit, except for a dedicated mode (in other words, dedicated signals) for 8-bit addition and multiplication, which should bypass the reduction. The 16 MAC units are implicitly grouped according to the control signals, processing a single 64-bit value or two 32-bit values ​​or four 16-bit values.

[0162] It should be understood that each modular multiplier calculates Each modular adder calculates Where 1≤i≤16, i is an integer. Here, x i is the i-th remainder in the set of remainders of the element values ​​of matrix A, y i is the i-th remainder of the element value of matrix B.

[0163] The 16 MAC units are implicitly grouped according to the control signal value to process a single 64-bit value, two 32-bit values, or four 16-bit values. For example, if CTRL = 0, the 16 MAC units form a group and process a single 64-bit value; if CTRL = 1, the 16 MAC units form two groups, one of which includes 8 MAC units, corresponding to 8 moduli, namely m1, m5, m9, m1, m2, m3, m4, m5, m6, m7, m8, m9, m1, m2, m3, m4, m5, m6, m7, m8, m9, m1, m2 13 , m3, m7, m 11 and m 15 , the other group includes 8 MAC units, corresponding to the other 8 moduli, namely m2, m6, m 10 、m 14 ,m4,m8,m 12 and m 16 .

[0164] Figure 6 This is a schematic diagram of the reverse conversion structure provided by this application. Figure 6 As shown, this structure indicates that the CRT is used according to the control signal: A mechanism for reconstructing a single 64-bit value or two 32-bit values ​​or four 16-bit binary values ​​in the RNS. The input to the inverse conversion unit is the result of the arithmetic operation z i , z i First multiply by a precomputed constant This constant is different for each ADC and CTRL signal value. Only the CRT for reverse conversion is used as an example. Figure 6 It is shown how to use CRT to achieve support for multiple sizes. However, the present application may not be limited to the CRT method for inverse conversion, because other methods such as extended CRT (EXCRT) or mixed-radix conversion (MRC) can also be used to achieve support for multiple sizes.

[0165] Specifically, Figure 6 As shown, the reverse conversion unit includes a first multiplexer set and a second multiplexer set. The first multiplexer set includes 16 multiplexers, wherein the 16 multiplexers correspond to the 16 MAC units one by one, and the 16 multiplexers are divided into four groups, each group including four multiplexers. The 16 multiplexers are used to receive control signals and return pre-calculated constant values ​​from three pre-calculated constant values.

[0166] The inverse conversion unit also includes a multiplier set, which includes 16 multipliers, wherein the 16 multipliers correspond one-to-one to the 16 multiplexers, and the 16 multipliers correspond one-to-one to the 16 MAC units. Each of the 16 multipliers included in the multiplier set is used to perform a multiplication operation on the output of the corresponding multiplexer and the output of the corresponding MAC unit.

[0167] The inverse conversion unit further comprises three adder sets. The first adder set of the three adder sets comprises four adders, wherein the four adders correspond one-to-one to the four multiplexer groups, and the input of each of the four adders comprises the outputs of four multipliers corresponding to the four multiplexer groups.

[0168] The second adder set in the three adder sets includes two adders, wherein the first adder of the two adders is used to receive the output of the first adder and the output of the second adder included in the first adder set, and the second adder of the two adders is used to receive the output of the third adder and the output of the fourth adder included in the first adder set.

[0169] The third adder set of the three adder sets includes an adder configured to receive outputs of two adders included in the second adder set.

[0170] The second multiplexer set includes four multiplexers, wherein the input of each multiplexer is the result of a modular reduction operation on the outputs of four adders included in the first adder set, the outputs of two adders included in the second adder set, or the output of one adder included in the third adder set.

[0171] The second multiplexer set includes four multiplexers for receiving control signals and determining corresponding output values ​​according to the control signal values.

[0172] like Figure 6 As shown, each multiplexer contained in the first multiplexer set returns the corresponding constant value, and then each z i Multiply by the constant to get the product of grouping and accumulating the four moduli. The result of the accumulation is determined based on the following:

[0173] (1) If CTRL = 2 (representing a 16-bit value), use the corresponding constant value 1≤j≤4 Reduce the accumulated result to get the final 32-bit value;

[0174] (2) If CTRL = 1 (representing a 32-bit value), add the product of the adjacent group and then use the corresponding constant value 1≤j≤2 is reduced to obtain the final 64-bit value;

[0175] (3) The sum of the products of all groups is accumulated and then used Perform reduction to get the final 128-bit value.

[0176] The final set of multiplexers (ie, the second set of multiplexers) forms the correct output value according to the CTRL signal value, ie, a single 128-bit value or two 64-bit values ​​or four 32-bit output values.

[0177] from Figure 6 It can be seen that the three pre-calculated constant values ​​of the i-th multiplexer in the first multiplexer set are and 1≤i≤16, i is a positive integer. The i-th multiplexer is specifically used to: if the control signal value is equal to the first value, then output If the control signal value is equal to the first value, the output If the control signal value is equal to the third value, the output As mentioned above, the three pre-computed constant values ​​for the ith multiplexer of the 16 multiplexers are and In fact, the three pre-computed constant values ​​of the i-th multiplexer are M 64 |M ；1 | 64 , and Among them, For m1, m5, m9, m 13 , m3, m7, m 11 or m 15 , j is equal to 1; for m2, m6, m 10、 m 14 ,m4,m8,m 12 or m 16 , j is equal to 2. For m1, m5, m9 or m 13 , j is equal to 1; for m2, m 6、 m 10 or m 14 , j is equal to 2; for m3, m 7、 m 11、 m 15 , j is equal to 3; for m4, m 8、 m 12 、m 16 , j is equal to 4. That is, the subscripts of the three precomputed constant values ​​are related to the corresponding modulo arrays. For example, for 64-bit input types, there should be no subscripts at all, that is, Actually, it is M 64 |M ；1 | 64 For 32-bit input types, the subscript can be 1 or 2, i.e. The actual or The value of the subscript depends on m iAs we all know, for 32-bit input type, there are two module arrays. 13 , m3, m7, m 11 or m 15 Belongs to the first module array, for m1, m5, m9, m 13 , m3, m7, m 11 or m 15 , for Due to m2, m6, m 10 、m 14 ,m4,m 8、 m 12 or m 16 Belongs to the second module array, for m2, m6, m 10 、m 14 ,m4,m8,m 12 or m 16 , for For 16-bit input types, the subscript can be 1, 2, 3, or 4, i.e. The actual or The value of the subscript depends on m i The module array to which it belongs. The 16-bit input type has four module arrays, {m1,m5,m9,m 13}, {m2,m6,m 10 ,m 14}、{m3,m7,m 11 ,m 15} and {m4,m8,m 12 ,m 16} corresponds to the four groups one by one. Therefore, for m1, m5, m9 or m 13 , for For m2, m6, m 10 or m 14 , for For m3, m7, m 11 or m 15 , for For m4, m8, m 12、 m 16 , for

[0178] The four multiplexers included in the second multiplexer set are specifically used for:

[0179] If the control signal value is equal to the first value, the output of each of the four multiplexers is a modular reduction operation (ie, s%M) performed on the output of the adder included in the third adder set. 64 ), where s is the output of the adder included in the third adder set, Here M 64 It refers to "M of 64-bit input type". The output of the four multiplexers is four segments of the modular reduction operation result (referred to as "modular reduction result"), which are o 64 [15:0], o 64 [31:16], o 64 [47:32] and o 64 [63:48].

[0180] If the control signal value is equal to the second value, the outputs of the first multiplexer and the second multiplexer in the four multiplexers are the outputs of the first adder included in the second adder set subjected to a modular reduction operation (ie, ), wherein t1 is the output of the first adder included in the second adder set, here refers to "32-bit input type M", The subscript (1) of refers to the first modular array of 32-bit input type. The outputs of the first and second multiplexers of the four multiplexers are two segments of the modular reduction operation results, which are and The outputs of the third multiplexer and the fourth multiplexer are the outputs of the second adders included in the second adder set subjected to a modular reduction operation (i.e. ), wherein t2 is the output of the second adder included in the second adder set, here refers to "32-bit input type M", The subscript (2) of refers to the second modular array of 32-bit input type. The outputs of the third and fourth multiplexers of the four multiplexers are two segments of the modular reduction operation results, which are and

[0181] If the control signal value is equal to the third value, the output of the j-th multiplexer among the four multiplexers is a modular reduction operation performed on the output of the j-th adder included in the first adder set (ie ), where p j is the output of the jth adder, 1≤j≤4, and j is an integer, here Refers to "16-bit input type M", The subscript (j) of refers to the first, second, third or fourth module array of 16-bit input type. The outputs of the four multiplexers are

[0182] Alternatively, the element size type of the output matrix is ​​twice as large, which can be used to correctly handle overflow or implement fixed-point data types.

[0183] This application has the following advantages:

[0184] (1) The same set of t modular multipliers and adders can be implemented as a single 64-bit, two 32-bit, four 16-bit, and sixteen 8-bit MAC units by properly grouping the moduli.

[0185] (2) Due to the complex carry propagation logic of the 64-bit adder and multiplier, 16 8-bit / 9-bit modular multipliers (need to fully cover [0,2 128 –1] binary range) is smaller than the area and power of a single 64-bit multiplier.

[0186] In addition to the dedicated processing of 8-bit multiplication, there is no need for any dedicated support of multiple sizes in the modular multiplier, which can directly disable the modular reduction in this application. The logic of other size types is completely handled by the RNS to BNS / BNS to RNS converter. A separate control signal is added to the converter to maintain all possible input / output types that the matrix multiplier can handle. Depending on the control signal value, the input 64-bit value can be interpreted as a 1×64-bit value or a 2×32-bit value or a 4×16-bit value or a 16×8-bit value.

[0187] The RNS forward conversion is implemented by taking the remainder of a 64-bit value for each modulus, this logic can be fully used for different size types to handle 64-bit input values ​​and only needs to be scaled for smaller sizes. The forward conversion latency remains the same for all integer size types. The correct grouping of the modulus is architecturally defined and fixed in hardware. For 8-bit input types, the forward conversion is simply bypassed.

[0188] The reverse conversion is based on hierarchical accumulation of intermediate values, where 64-bit size types require accumulation across all layers, while 32-bit size types avoid accumulation at the last level, 16-bit size types avoid accumulation at the last two levels, and 8-bit size types bypass the reverse conversion.

[0189] Compared to modular multipliers, forward and inverse conversions take up more area and consume more power, but they only need to convert all the values ​​of the input matrix and convert the values ​​of the output matrix back. For an n×n matrix, the number of forward converters required is 2×n 2 , the number of reverse converters required is n 2Assuming that the matrix is ​​multiplied in one cycle, the total number of modular arithmetic units is n 3 , so that all the costs of the forward / reverse conversion are hidden behind the benefits of a small modular multiplier. If the matrix multiplication hardware accelerator operates on a single row and column in one cycle, the ratio between converters and modular arithmetic units remains the same, that is, 2×n forward converters, n reverse converters, and a total of n modular arithmetic units. 2 .

[0190] RNS multiplier (for the entire modulus set conversion [0,2 128 –1] range) can be implemented in 40% less area and consume 50% less power than a single 64-bit multiplier. Assuming that a 64×64 multiplier takes up 1 hardware area and consumes 1 power, we can construct the following table based on the cost of RNS-based matrix multiplication (all the following numbers are actual experimental results using the best-known forward / inverse transformation and modular reduction algorithms).

[0191] Table 1

[0192] Hardware Area Power consumption RNS Multiplier 0.6 0.5 RNS forward conversion 0.7 0.5 RNS reverse conversion 1.6 1.7

[0193] Therefore, the RNS matrix multiplication area is 2×0.7n 2 +0.6n 3 +1.6n 2 Compare When n=8, the RNS matrix multiplication area is 0.975 of the 64×64 matrix multiplication area. When n=16, the RNS matrix multiplication area is 0.79 of the 64×64 matrix multiplication area.

[0194] RNS matrix multiplication power consumption is 2×0.5n 2 +0.5n 3 +1.7n 2 Compare When n=8, the power consumption of RNS matrix multiplication is 0.775 of that of 64×64 matrix multiplication. When n=16, the power consumption of RNS matrix multiplication is 0.64 of that of 64×64 matrix multiplication. It should be noted that these figures may vary depending on the actual process.

[0195] Accordingly, the present application also provides a method for matrix multiplication.

[0196] Figure 7 A schematic diagram of a method for matrix multiplication provided by the present application is shown. The method can be executed by a system for matrix multiplication proposed by the present application. A method (600) specifically includes the following steps:

[0197] Step 610: Receive a binary input value and a control signal, wherein the control signal is used to indicate the size type of element values ​​of two matrices to be subjected to matrix multiplication.

[0198] For example, the size type includes one of the following types: a 64-bit type, a 32-bit type, or a 16-bit type.

[0199] Step 620: Obtain the element value according to the input value and the control signal, for example, when the value of the control signal is equal to the first value, obtain the element value by determining each input value as a single 64-bit element value; or, when the value of the control signal is equal to the second value, obtain the element value by splitting each input value into two 32-bit element values; or, when the value of the control signal is equal to the third value, obtain the element value by splitting each input value into four 16-bit element values.

[0200] Step 630: Perform a forward conversion on the element value to obtain a conversion value of the element value, wherein the conversion value of each element value is a set of remainders of the element value in a residue number system (RNS).

[0201] Step 640: Perform a modular arithmetic operation on the conversion value to obtain an operation result, wherein the modular arithmetic operation includes the matrix multiplication.

[0202] Step 650: Perform a reverse conversion on the operation result according to the control signal to obtain the binary output value, wherein the output value and the input value have the same size type, and the output matrix includes the output value.

[0203] For example, the system uses Chinese Remainder Theorem (CRT), EXCRT, or MRC to inversely convert the operation result according to the control signal to obtain a binary output value.

[0204] All relevant contents of each step in the method embodiment have been described in detail in the above system embodiment, and will not be repeated here to avoid repetition.

[0205] The present application also provides a chip or chip system including a plurality of circuits, wherein the plurality of circuits are used to have the functions of the units included in the system for matrix multiplication provided by the present application.

[0206] In several embodiments provided in the present application, it should be understood that the disclosed systems and methods can be implemented in other ways. For example, the device embodiments described are merely examples. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be merged or integrated into another system, or some features can be ignored or not executed. In addition, the mutual coupling or direct coupling or communication connection shown or described can be implemented through some interfaces. The direct coupling or communication connection between devices or units can be implemented in electronic, mechanical or other forms.

[0207] Units described as separate components may or may not be physically separate, and components shown as units may or may not be physical units, and may be located in one location or distributed across multiple network units. Some or all of the units may be selected based on actual needs to achieve the purpose of the embodiments.

[0208] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0209] The above description is only a specific implementation of the present application and is not intended to limit the scope of protection of the present application. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed in the present application should belong to the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A system for matrix multiplication, characterized in that The system includes a forward conversion unit, a modular arithmetic unit, and a reverse conversion unit; Wherein, the forward conversion unit is used for: Receiving a binary input value and a control signal, wherein the control signal is used to indicate the size type of the input value; Performing a forward conversion on the input value according to the size type to obtain a conversion value of the input value, wherein the conversion value of each input value is a set of remainders of the input value in a residue number system (RNS); outputting the converted value to the modulo arithmetic unit; Wherein, the modular arithmetic unit is used for: receiving the conversion value from the forward conversion unit; Performing a modular arithmetic operation on the conversion value according to the modulus set of the RNS to obtain an operation result; Outputting the operation result to the inverse conversion unit; Wherein, the reverse conversion unit is used for: receiving the operation result and the control signal; The operation result is inversely converted according to the control signal to obtain the binary output value, wherein the binary output value and the binary input value have the same size type.

2. The system according to claim 1, characterized in that The forward conversion unit includes M multiplexers, wherein the M multiplexers correspond to M modular reduction unit groups, the system supports value processing of multiple size types, the multiple size types include a first size type and a second size type, and the first size type corresponds to a maximum size supported by the system; In the case where the control signal indicates the first size type, the M multiplexers respectively obtain each value of the binary input value as an input of the corresponding modular reduction unit group; or When the control signal indicates the second size type, the M multiplexers respectively obtain partial bits of each value in the binary input value as input of the corresponding modular reduction unit group, and M is an integer greater than or equal to 2.

3. The system according to claim 2, characterized in that Each of the M modular reduction unit groups includes P modular reduction units, where P is an integer greater than or equal to 2.

4. The system according to claim 2 or 3, characterized in that: The forward conversion unit includes four multiplexers and four modular reduction unit groups, wherein the four multiplexers correspond to the four modular reduction unit groups one by one; each of the four modular reduction unit groups includes four modular reduction units, and the four modular reduction unit groups include 16 modular reduction units in total, wherein the 16 modular reduction units correspond to the 16 moduli of the RNS one by one; Wherein, the four multiplexers are specifically used for: receiving the control signal; In a case where the value of the control signal is equal to the first value, determining the size type of the input value as a 64-bit type; Obtaining the input value, and outputting each input value to each modular reduction unit of the 16 modular reduction units; The 16 modular reduction units are specifically used for: A reduction operation is performed on each input value so as to obtain 16 conversion values ​​according to the corresponding moduli of the 16 modular reduction units, respectively, wherein each of the 16 modular reduction units obtains one conversion value among the 16 conversion values.

5. The system according to claim 4, characterized in that When the value of the control signal is equal to the second value, determining the size type of the input value as a 32-bit type; Among them, the first multiplexer and the third multiplexer of the four multiplexers respectively obtain the lower 32 bits of each input value, the first multiplexer outputs the lower 32 bits to the corresponding first modular reduction unit group, and the third multiplexer outputs the lower 32 bits to the corresponding third modular reduction unit group; Among them, the second multiplexer and the fourth multiplexer of the four multiplexers respectively obtain the upper 32 bits of each input value, the second multiplexer outputs the upper 32 bits to the corresponding second modular reduction unit group, and the fourth multiplexer outputs the upper 32 bits to the corresponding fourth modular reduction unit group; The four modular reduction units are specifically used for: The first modular reduction unit group and the third modular reduction unit group respectively perform modular reduction operations on the lower 32 bits according to four moduli corresponding to the four modular reduction units included in each of the first modular reduction unit group and the third modular reduction unit group, so as to obtain four conversion values ​​respectively; The second modular reduction unit group and the fourth modular reduction unit group respectively perform modular reduction operations on the upper 32 bits according to four moduli corresponding to the four modular reduction units included in each modular reduction unit group in the second modular reduction unit group and the fourth modular reduction unit group, so as to obtain four conversion values ​​respectively.

6. The system according to claim 5, characterized in that Each of the four multiplexers is specifically used for: receiving the control signal; When the value of the control signal is equal to the third value, determining the size type of the input value as a 16-bit type; Obtain one of the four segments constituting each input value, and output the obtained segments to corresponding modular reduction unit groups respectively; Wherein, each of the modular reduction unit groups is specifically used for: According to four moduli corresponding to the four modular reduction units included in each of the four modular reduction unit groups, modular reduction operations are respectively performed on the corresponding segments to obtain four converted values ​​respectively.

7. The system according to any one of claims 4 to 6, characterized in that The modular arithmetic unit includes 16 multiply accumulator (MAC) units, wherein the 16 MAC units correspond one-to-one to the 16 moduli, and the 16 MAC units correspond one-to-one to the 16 modular reduction units; Wherein, each of the 16 MAC units is specifically used for: receiving conversion values ​​from corresponding modular reduction units, and performing modular multiplication and modular accumulation operations on each conversion value to obtain corresponding operation results; Wherein, when performing the modular multiplication and the modular accumulation operation, the 16 MAC units are formed into different groups in the following manner: In a case where the size type of the input value is a 64-bit type, the 16 MAC units form a group, wherein the group is used to perform the modular multiplication and the modular accumulation operations on the 16 conversion values ​​from the 16 modular reduction units, and output 16 operation results corresponding to the 16 conversion values; or In the case where the size type of the input value is a 32-bit type, the 16 MAC units are formed into two groups, wherein each of the two groups includes eight MAC units, and one of the two groups is used to perform the modular multiplication and the modular accumulation operations on eight conversion values, and output eight operation results corresponding to the eight conversion values, and the eight conversion values ​​respectively include the four conversion values ​​from the first modular reduction unit and the third modular reduction unit; wherein the other group of the two groups is used to perform the modular multiplication and the modular accumulation operations on the other eight conversion values, and output eight operation results corresponding to the other eight conversion values, and the other eight conversion values ​​respectively include the four conversion values ​​from the second modular reduction unit and the fourth modular reduction unit; or In the case where the size type of the input value is a 16-bit type, the 16 MAC units are organized into four groups, wherein each of the four groups includes four MAC units, and the four groups correspond one-to-one to the four modular reduction unit groups, and each of the four groups is used to perform the modular multiplication and the modular accumulation operations on the four conversion values ​​from the four modular reduction units included in the corresponding modular reduction group, and respectively output four operation results corresponding to the four conversion values.

8. The system according to any one of claims 2 to 7, characterized in that The reverse conversion unit supports reverse conversion of multiple size types, wherein the multiple size types further include a third size type, and the third size type corresponds to a minimum size supported by the system; The reverse conversion unit comprises: a first multiplexer set including M·P multiplexers and a second multiplexer set including V multiplexers, the M·P multiplexers respectively corresponding to the M·P operation results of the modular arithmetic unit, and the V multiplexers are used to output the binary output value; In a case where the value of the control signal indicates the first size type, each of the V multiplexers respectively obtains a segment of the modular reduction result associated with all the M·P operation results as an output, and the V segments corresponding to the V multiplexers reconstruct the binary output value corresponding to the first size type; or In a case where the value of the control signal indicates the third size type, each of the V multiplexers obtains as output a modular reduction result associated with P of the M·P operation results, and the modular reduction result obtained by each multiplexer reconstructs a binary output value corresponding to the third size type; or In the case where the value of the control signal indicates the second size type, each of the V multiplexers obtains as output a modular reduction result associated with L operation results of the M·P operation results, and the modular reduction result obtained by each of the V multiplexers is a segment of a binary output corresponding to the second size type, where L is an integer multiple of P.

9. The system according to claim 8, characterized in that The first multiplexer set includes 16 multiplexers, wherein the 16 multiplexers correspond to the 16 MAC units one by one, the 16 multiplexers are four multiplexer groups, and each of the four multiplexer groups includes four multiplexers; The 16 multiplexers included in the first multiplexer set are respectively used to receive the control signal, and return constant values ​​from three pre-calculated constant values ​​according to the control signal; The inverse conversion unit further includes a multiplier set, the multiplier set includes 16 multipliers, the 16 multipliers correspond one-to-one to the 16 multiplexers included in the first multiplexer set, and the 16 multipliers correspond one-to-one to the 16 MAC units; wherein each of the 16 multipliers is used to perform a multiplication operation on an output of a corresponding multiplier in the 16 multipliers and an output of a corresponding MAC unit in the 16 MAC units, and output a corresponding operation result; The inverse conversion unit further comprises three adder sets, wherein a first adder set of the three adder sets comprises four adders, the four adders correspond one-to-one to the four multiplexer groups, and an input of each of the four adders comprises outputs of four multipliers corresponding to the four multiplexers in the corresponding multiplexer group; The second adder set of the three adder sets includes two adders, wherein the first adder of the two adders is used to receive the output of the first adder and the output of the second adder included in the first adder set, and the second adder of the two adders is used to receive the output of the third adder and the output of the fourth adder included in the first adder set; A third adder set of the three adder sets includes an adder, wherein the adder is used to receive outputs of the two adders included in the second adder set; The second multiplexer set includes the four multiplexers, the input of each multiplexer included in the four multiplexers is obtained by performing the modular reduction operation on the outputs of the four adders included in the first adder set, the input of each multiplexer included in the four multiplexers is obtained by performing the modular reduction operation on the outputs of the two adders included in the second adder set, or the input of each multiplexer included in the four multiplexers is obtained by performing the modular reduction operation on the outputs of the adders included in the third adder set; The four multiplexers included in the second multiplexer set are used to receive the control signal and determine corresponding output values ​​according to the control signal.

10. The system according to claim 9, characterized in that The three pre-calculated constant values ​​of the i-th multiplexer among the 16 multiplexers included in the first set of multiplexers include: and Wherein, 1≤i≤16 and i is a positive integer; Wherein, the i-th multiplexer is specifically used for: Output when the value of the control signal is equal to the first value Output when the value of the control signal is equal to the second value Output when the value of the control signal is equal to the third value 11. The system according to any one of claims 2 to 10, characterized in that The set of the 16 moduli of the RNS is {m1,m2,…,m 16 }, wherein the 16 moduli satisfy the following criteria: (1) (2)m1×m5×m9×m 13 ×m3×m7×m 11 ×m 15 >2 64 ; (3)m2×m6×m 10 ×m 14 ×m4×m8×m 12 ×m 16 >2 64 ; (4)m1×m5×m9×m 13 >2 32 ; (5)m2×m6×m 10 ×m 14 >2 32 ; (6)m3×m7×m 11 ×m 15 >2 32 ; (7)m4×m8×m 12 ×m 16 >2 32 。 12. The system according to claim 11, characterized in that The four modular reduction unit groups correspond one-to-one to the four modular groups composed of the 16 modular numbers, and the four modular groups are: {m1, m5, m9, m 13 }, {m2,m6,m 10 ,m 14 }、{m3,m7,m 11 ,m 15 } and {m4,m8,m 12 ,m 16 }, where {m1,m2,…,m 16 }={512,511,509,489,487,485,481,479,473,467,431,167,151,139,137,131}.

13. The system according to claim 11 or 12, characterized in that The four multiplexers included in the second multiplexer set are specifically used for: When the value of the control signal is equal to the first value, the output of each of the four multiplexers is a modular reduction operation s%M performed on the output of the adder included in the third adder set. 64 , wherein s is the output of the adder included in the third adder set, The outputs of the four multiplexers are four segments of the operation results, wherein the four segments are o 64 [15:0], o 64 [31:16], o 64 [47:32] and o 64 [63:48].

14. The system according to claim 11 or 12, characterized in that: The four multiplexers included in the second multiplexer set are specifically used for: When the value of the control signal is equal to the second value, the output of the first multiplexer and the second multiplexer among the four multiplexers is a modular reduction operation performed on the output of the first adder included in the second adder set. , wherein t1 is the output of the first adder included in the second adder set, The outputs of the first multiplexer and the second multiplexer are two segments of the operation result, respectively, wherein the two segments are and The outputs of the third multiplexer and the fourth multiplexer among the four multiplexers are the outputs of the second adders included in the second adder set subjected to a modular reduction operation. t2 is the output of the second adder included in the second adder set, The outputs of the third multiplexer and the fourth multiplexer are two segments of the operation result, wherein the two segments are and 15. The system according to claim 11 or 12, characterized in that The four multiplexers included in the second multiplexer set are specifically used for: In the case where the value of the control signal is equal to the third value, the output of the j-th multiplexer among the four multiplexers is a modular reduction operation performed on the output of the j-th adder included in the first adder set. The result of the operation, where p j is the output of the j-th adder, and j is an integer, the outputs of the four multiplexers are 16. A method for matrix multiplication, characterized in that The method comprises: Receiving a binary input value and a control signal, wherein the control signal is used to indicate the size type of element values ​​of two matrices on which matrix multiplication is to be performed; Acquire the element value according to the input value and the control signal; Performing a forward conversion on the element value to obtain a conversion value of the element value, wherein the conversion value of each element value is a set of remainders of the element value in a residue number system (RNS); performing a modular arithmetic operation on the conversion value according to the modular set of the RNS to obtain an operation result, wherein the modular arithmetic operation includes the matrix multiplication; The operation result is inversely converted according to the control signal to obtain the binary output value, wherein the output value and the input value have the same size type, and an output matrix includes the output value.

17. The method according to claim 16, characterized in that The acquiring the element value according to the input value and the control signal further comprises: In a case where the value of the control signal is equal to the first value, obtaining the element value by determining each input value as a single 64-bit element value; In a case where the value of the control signal is equal to a second value, obtaining the element value by splitting each input value into two 32-bit element values; or In a case where the value of the control signal is equal to a third value, the element value is obtained by splitting each input value into four 16-bit element values.

18. The method according to claims 16 and 17, characterized in that The set of 16 moduli of the RNS is {m1,m2,…,m 16 }, wherein the 16 moduli satisfy the following criteria: (1) (2)m1×m5×m9×m 13 ×m3×m7×m 11 ×m 15 >2 64 ; (3)m2×m6×m 10 ×m 14 ×m4×m8×m 12 ×m 16 >2 64 ; (4)m1×m5×m9×m 13 >2 32 ; (5)m2×m6×m 10 ×m 14 >2 32 ; (6)m3×m7×m 11 ×m 15 >2 32 ; (7)m4×m8×m 12 ×m 16 >2 32 。 19. A chip comprising a plurality of circuits, characterized in that: The plurality of circuits are configured to have the function of a unit included in the system according to any one of claims 1 to 15.

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