Semiconductor device, display device, and electronic apparatus

Abstract

Provided is a semiconductor device that operates stably. A semiconductor device includes a first transistor, a second transistor, a third transistor, and a first capacitor. One of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the second transistor, and the other of the source and the drain of the third transistor is electrically connected to a gate of the first transistor and a first terminal of the first capacitor. In addition, one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and a second terminal of the first capacitor. In addition, the semiconductor device may be provided in a driving circuit having a function of transmitting a signal for displaying an image to a display device.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device, a display device, and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. The technical field of the invention disclosed in this specification and the like relates to an object, a working method, or a manufacturing method. In addition, one embodiment of the present invention relates to a process, a machine, a product, or a composition of matter. Therefore, more specifically, as examples of the technical field of one embodiment of the present invention disclosed in this specification, semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, storage devices, signal processing devices, sensors, processors, electronic devices, systems, their driving methods, their manufacturing methods, or their inspection methods can be cited. Background Art

[0003] In recent years, various improvements have been made to display devices used in electronic devices such as VR (Virtual Reality), AR (Augmented Reality), XR (Extended Reality, or Cross Reality), mobile phones (e.g., smartphones), tablet computers, and notebook PCs. For example, display devices are being developed to increase resolution, improve color reproduction (NTSC ratio), reduce driver circuit size, and reduce power consumption.

[0004] For example, to improve the display quality of display devices, circuits that can reduce characteristic variations of drive transistors in pixels are being actively developed. In particular, Patent Document 1 describes an invention of a pixel circuit including a circuit that can correct the threshold voltage of a drive transistor.

[0005] Another example is a technology of applying a transistor using an oxide semiconductor for a semiconductor thin film as a switching element included in a pixel circuit in a display device.

[0006] Silicon-based semiconductor materials are known as semiconductor thin films that can be used for transistors. Furthermore, oxide semiconductors are attracting attention as materials other than silicon-based semiconductor materials. For example, oxide semiconductors are known to include oxides of single-element metals such as indium oxide and zinc oxide, as well as oxides of multi-element metals. Among multi-element metal oxides, research on In-Ga-Zn oxide (hereinafter also referred to as IGZO) is particularly intense.

[0007] Transistors using IGZO in their active layers have been reported to have extremely low off-state current (see Non-Patent Document 1), as well as LSIs (Large Scale Integrations) and display devices that utilize this characteristic (see Non-Patent Documents 2 and 3). Furthermore, Patent Document 2 discloses an invention in which a transistor containing IGZO in its active layer is used in a pixel circuit of a display device. [Prior technical literature] [Patent Document]

[0008] [Patent Document 1] Japanese Patent Application Publication No. 2017-10000 [Patent Document 2] Japanese Patent Application Publication No. 2010-156963 [Non-patent literature]

[0009] [Non-patent document 1] K. Kato et al., “Japanese Journal of Applied Physics,” 2012, volume 51, pp. 021201-1-021201-7 [Non-Patent Document 2] S. Matsuda et al., “2015 Symposium on VLSI Technology Digest of Technical Papers,” 2015, pp. T216-T217 [Non-patent document 3] S.Amano et al., “SID Symposium Digest of Technical Papers”, 2010, volume 41, issue 1, pp. 626-629 Summary of the Invention Technical problem to be solved by the invention

[0010] Generally, an image is displayed on a display portion of a display device by driving a source driver circuit or a gate driver circuit included in the display device. The driver circuit includes a shift register to transmit a specific signal to each row or column.

[0011] A shift register has a structure in which a signal input to a serially connected holding circuit is sequentially transmitted to the adjacent holding circuit. If a malfunction occurs in one of these holding circuits, the waveform of the output signal from that holding circuit may suffer from defects or distortion. If a waveform defect occurs in the signal output from a holding circuit, the signal is fed to the holding circuits in the next stage and beyond, affecting the entire shift register. Consequently, the output signal from the shift register may suffer from defects or distortion.

[0012] In particular, when noise is input to the holding node, which holds signal information as a potential in a shift register's holding circuit, the waveform of the signal output from the holding circuit may be affected. Consequently, there is a tendency for signals containing defects such as flaws and distortion to be transmitted to the holding circuit at the subsequent stage within the shift register.

[0013] One object of one embodiment of the present invention is to provide a semiconductor device that operates stably. Another object of one embodiment of the present invention is to provide a semiconductor device with a high drive speed. Another object of one embodiment of the present invention is to provide a semiconductor device with high reliability. Another object of one embodiment of the present invention is to provide a display device including the semiconductor device. Another object of one embodiment of the present invention is to provide an electronic device including the display device. Another object of one embodiment of the present invention is to provide a novel semiconductor device, novel display device, or novel electronic device.

[0014] Note that the purpose of one embodiment of the present invention is not limited to the purposes listed above. The purposes listed above do not prevent the existence of other purposes. Other purposes refer to purposes other than those mentioned above, which will be described in the following description. A person skilled in the art can derive and appropriately extract purposes not mentioned above from the description in the specification or drawings, etc. In addition, one embodiment of the present invention achieves at least one of the purposes listed above and other purposes. Therefore, one embodiment of the present invention does not need to achieve all of the above-mentioned purposes and other purposes. Means of solving technical problems

[0015] The aforementioned malfunction in the signal output from the holding circuit of the shift register is thought to be caused by unintentional fluctuations in the potential of a holding node within the holding circuit that holds signal information during the operation of the shift register. Therefore, in one embodiment of the present invention, the holding circuit is configured to prevent unintentional fluctuations in the potential of the holding node during the operation of the shift register.

[0016] An example of a semiconductor device (holding circuit), a display device, and an electronic device for solving the above-mentioned problems will be described below. (1) One embodiment of the present invention is a semiconductor device comprising a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the second transistor, one of the source and drain of the seventh transistor, and one of the source and drain of the eighth transistor. The other of the source and drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor. In addition, one of the source and drain of the first transistor is electrically connected to the gate of the second transistor, one of the source and drain of the fourth transistor, and the second terminal of the first capacitor. In addition, the gate of the fourth transistor is electrically connected to one of the source and drain of the fifth transistor, one of the source and drain of the sixth transistor, the gate of the eighth transistor, and the first terminal of the second capacitor. In addition, the gate of the seventh transistor is electrically connected to the gate of the sixth transistor. (2) In addition, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor and having a structure different from that of (1) above. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the second transistor, one of the source and drain of the seventh transistor, and one of the source and drain of the eighth transistor. The other of the source and drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor. In addition, one of the source and drain of the first transistor is electrically connected to the gate of the second transistor, the gate of the second transistor, one of the source and drain of the fourth transistor, and the second terminal of the first capacitor. In addition, the gate of the fourth transistor is electrically connected to one of the source and drain of the fifth transistor, one of the source and drain of the sixth transistor, the gate of the eighth transistor, and the first terminal of the second capacitor. In addition, the gate of the seventh transistor is electrically connected to the gate of the sixth transistor. (3) In addition, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a ninth transistor, a first capacitor, a second capacitor, and a third capacitor. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the second transistor, one of the source and drain of the fourth transistor, one of the source and drain of the eighth transistor, and one of the source and drain of the ninth transistor. The other of the source and drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor. One of the source and drain of the first transistor is electrically connected to one of the source and drain of the fifth transistor, the second terminal of the first capacitor, and the first terminal of the second capacitor. The gate of the second transistor is electrically connected to the other of the source and drain of the fourth transistor and the second terminal of the second capacitor. The gate of the fifth transistor is electrically connected to one of the source and drain of the sixth transistor, one of the source and drain of the seventh transistor, the gate of the ninth transistor, and the first terminal of the third capacitor. The gate of the ninth transistor is electrically connected to the gate of the seventh transistor. (4) In addition, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, an eighth transistor, a first capacitor, and a second capacitor, and having a structure different from (1) and (2) above. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the seventh transistor and one of the source and drain of the eighth transistor. In addition, the other of the source and drain of the third transistor is electrically connected to the gate of the first transistor, one of the source and drain of the second transistor, and the first terminal of the first capacitor. In addition, one of the source and drain of the first transistor is electrically connected to the gate of the second transistor, one of the source and drain of the fourth transistor, and the second terminal of the first capacitor. In addition, the gate of the fourth transistor is electrically connected to one of the source and drain of the fifth transistor, one of the source and drain of the sixth transistor, the gate of the eighth transistor, and the first terminal of the second capacitor. In addition, the gate of the seventh transistor is electrically connected to the gate of the sixth transistor. (5) In addition, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, and a first capacitor. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the second transistor, and the other of the source and drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor. In addition, one of the source and drain of the first transistor is electrically connected to the gate of the second transistor and the second terminal of the first capacitor. (6) In addition, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, and a first capacitor, and having a structure different from that of (5) above. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the second transistor, and the other of the source and drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor. In addition, one of the source and drain of the first transistor is electrically connected to the gate of the second transistor, the other of the source and drain of the second transistor, and the second terminal of the first capacitor. (7) In addition, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a buffer circuit, and a first capacitor. The buffer circuit includes an input terminal and an output terminal. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the second transistor, and the other of the source and drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor. Furthermore, the input terminal of the buffer circuit is electrically connected to one of the source and drain of the first transistor and the second terminal of the first capacitor, and the output terminal of the buffer circuit is electrically connected to the gate of the second transistor. (8) In addition, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, a fourth transistor, a first capacitor, and a second capacitor. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the second transistor and one of the source and drain of the fourth transistor, and the other of the source and drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor. In addition, one of the source and drain of the first transistor is electrically connected to the gate of the second transistor, the second terminal of the first capacitor, and the first terminal of the second capacitor, and the gate of the second transistor is electrically connected to the other of the source and drain of the fourth transistor and the second terminal of the second capacitor. (9) In addition, one embodiment of the present invention is a semiconductor device including a first transistor, a second transistor, a third transistor, and a first capacitor, and having a structure different from (5) and (6) above. One of the source and drain of the third transistor is electrically connected to one of the source and drain of the second transistor. In addition, the other of the source and drain of the third transistor is electrically connected to the gate of the first transistor, the gate of the second transistor, and the first terminal of the first capacitor. In addition, one of the source and drain of the first transistor is electrically connected to the second terminal of the first capacitor. (10) Another embodiment of the present invention is a display device including a driver circuit and a display device. The driver circuit includes a semiconductor device described in any one of (1) to (9) above. The driver circuit has a function of transmitting a signal for displaying an image to the display device. (11) In one embodiment of the present invention having the display device of (10) above, the display device may include a light-emitting device or a liquid crystal display device. (12) Furthermore, one embodiment of the present invention is an electronic device including the display device described in (11) above and a housing. Effects of the Invention

[0029] By applying the structure of the above-described semiconductor device to a holding circuit in a shift register, the output signal of the holding circuit can be fed back to the holding node. By receiving this output signal feedback on the holding node, a fixed potential, such as from a power line, is applied to the holding node, preventing the holding node from floating. This suppresses fluctuations in the holding node's potential, thereby stabilizing the output signal of the holding circuit. Furthermore, this fixed potential is preferably equal to the potential corresponding to the information held by the holding circuit.

[0030] According to one embodiment of the present invention, a semiconductor device that operates stably can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with a high drive speed can be provided. Furthermore, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. Furthermore, according to one embodiment of the present invention, a display device including the aforementioned semiconductor device can be provided. Furthermore, according to one embodiment of the present invention, an electronic device including the aforementioned display device can be provided. Furthermore, according to one embodiment of the present invention, a novel semiconductor device, novel display device, or novel electronic device can be provided.

[0031] Note that the effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not prevent the existence of other effects. Other effects refer to effects other than those described above, which will be described in the following description. A person skilled in the art can derive and appropriately extract effects not mentioned above from the description in the specification or drawings, etc. In addition, one embodiment of the present invention achieves at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention does not need to have all of the above effects depending on the circumstances. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figures 1A to 1C : is a circuit diagram showing an example of an amplifier circuit. Figures 2A to 2C : is a circuit diagram showing an example of an amplifier circuit. Figures 3A to 3C : is a circuit diagram showing an example of an amplifier circuit. Figures 4A to 4D : is a circuit diagram showing an example of an amplifier circuit. Figure 5 : is a circuit diagram showing an example of an amplifier circuit. Figure 6A and Figure 6B : is a circuit diagram showing an example of an amplifier circuit. Figure 7A and Figure 7B : is a circuit diagram showing an example of an amplifier circuit. Figures 8A to 8C : is a circuit diagram showing an example of an amplifier circuit. 9A to 9F : is a circuit diagram showing an example of an amplifier circuit. Figures 10A to 10C : is a circuit diagram showing an example of an amplifier circuit. Figure 11 is a layout diagram showing an example of an amplifier circuit. Figure 12 is a block diagram showing an example of a display device. Figure 13A and Figure 13B is a block diagram showing an example of a driving circuit. Figure 14 : is a circuit diagram showing an example of a circuit in a driving circuit. Figure 15 1 is a timing chart showing an operation example of a circuit in the driving circuit. Figure 16 : is a circuit diagram showing an example of a circuit in a driving circuit. Figure 17 : is a circuit diagram showing an example of a circuit in a driving circuit. Figure 18 : is a circuit diagram showing an example of a circuit in a driving circuit. Figure 19 : is a circuit diagram showing an example of a circuit in a driving circuit. Figure 20 is a block diagram showing an example of a driving circuit. Figure 21 is a timing chart showing an example of the operation of the driving circuit. Figure 22 : is a circuit diagram showing an example of a circuit in a driving circuit. Figure 23 : is a circuit diagram showing an example of a circuit in a driving circuit. Figure 24 : is a circuit diagram showing an example of a circuit in a driving circuit. Figure 25A and Figure 25B It is a perspective schematic diagram showing a structural example of a display device. Figure 26 is a block diagram showing a structural example of a display device. Figure 27 is a schematic cross-sectional view illustrating a structural example of a display device. Figures 28A to 28C is a schematic cross-sectional view illustrating a structural example of a display device. Figure 29 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 30A and Figure 30B is a schematic cross-sectional view illustrating a structural example of a transistor in a semiconductor device. Figure 31 is a schematic cross-sectional view illustrating a structural example of a transistor in a semiconductor device. Figure 32 is a schematic cross-sectional view illustrating a structural example of a display device. Figures 33A to 33C is a schematic plan view showing a structural example of a transistor in a semiconductor device, Figure 33D is a schematic cross-sectional view illustrating a structural example of a transistor in a semiconductor device. Figure 34A is a schematic plan view showing a structural example of a transistor in a semiconductor device, Figure 34B is a schematic cross-sectional view illustrating a structural example of a transistor in a semiconductor device. Figure 35 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 36 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 37 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 38 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 39 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 40 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 41 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 42 is a schematic cross-sectional view illustrating a structural example of a display device. Figure 43 is a schematic cross-sectional view illustrating a structural example of a display device. Figures 44A to 44D is a schematic cross-sectional view showing a structural example of an LED package. Figure 45A and Figure 45B 1 is a schematic plan view showing a structural example of an LED package. Figures 46A to 46F is a diagram showing a structural example of a light emitting device. Figures 47A to 47C is a diagram showing a structural example of a light emitting device. Figure 48A is a circuit diagram showing a structural example of a pixel circuit included in a display device, Figure 48B It is a perspective schematic diagram showing a structural example of a pixel circuit included in a display device. Figures 49A to 49G 2 is a plan view schematically illustrating an example of a pixel. Figures 50A to 50F 2 is a plan view schematically illustrating an example of a pixel. Figures 51A to 51H 2 is a plan view schematically illustrating an example of a pixel. Figures 52A to 52D 2 is a plan view schematically illustrating an example of a pixel. Figures 53A to 53G 2 is a plan view schematically showing an example of a pixel. Figures 54A to 54I It is a perspective view showing an example of an electronic device. Modes for Carrying Out the Invention

[0033] In this specification, etc., a semiconductor device refers to a device that utilizes semiconductor characteristics, a circuit including a semiconductor element (for example, a transistor, a diode, a photodiode), and a device including the circuit. In addition, a semiconductor device refers to all devices that can function by utilizing semiconductor characteristics. As an example of a semiconductor device, an integrated circuit can be cited. In addition, as an example of a semiconductor device, a chip having an integrated circuit can also be cited. In addition, as an example of a semiconductor device, an electronic component in which a chip is housed in a package can also be cited. In addition, for example, a storage device, a display device, a light-emitting device, a lighting device, and an electronic device are sometimes themselves semiconductor devices, or sometimes include a semiconductor device.

[0034] In this specification, the phrase "X and Y are connected" indicates that the following are disclosed: X and Y are electrically connected; X and Y are functionally connected; and X and Y are directly connected. Therefore, connections other than those shown in the drawings or text are not limited to those specified in the specification. Connections other than those shown in the drawings or text are also considered to be those described in the drawings or text. X and Y are each an object (e.g., a device, element, circuit, wiring, electrode, terminal, conductive film, or layer).

[0035] As an example of electrically connecting X and Y, one or more elements capable of electrically connecting X and Y (e.g., switches, transistors, capacitors, inductors, resistors, diodes, display devices, light-emitting devices, loads, etc.) may be connected between X and Y. Furthermore, a switch has the function of controlling whether to turn it on or off. In other words, whether current flows is controlled by placing the switch in a conductive state (on) or a non-conductive state (off).

[0036] Furthermore, if both X and Y have components and power lines (e.g., VDD (high power supply potential), VSS (low power supply potential), GND (ground potential), or wiring that applies a desired potential) between them, then X and Y cannot be said to be electrically connected. Furthermore, if only a power line is provided between X and Y, and no other components are between them, then X and Y can be said to be directly connected. Therefore, even if only a power line is provided between X and Y, it can be said that "X and Y are electrically connected." However, if both X and Y have components and power lines between them, it can be said that X is electrically connected to the power line (through the components) and that Y is electrically connected to the power line, rather than that X and Y are electrically connected. Furthermore, if the gate and source of a transistor are between X and Y, then X and Y cannot be said to be electrically connected. Furthermore, if the gate and drain of a transistor are between X and Y, then X and Y cannot be said to be electrically connected. That is, with respect to a transistor, if the drain and source of the transistor are between X and Y, then X and Y can be said to be electrically connected. Furthermore, when a capacitor is placed between X and Y, it may be said that X and Y are electrically connected, but it may not be said that X and Y are electrically connected. For example, in the configuration of a digital circuit or a logic circuit, when a capacitor is placed between X and Y, it may not be said that X and Y are electrically connected. On the other hand, in the configuration of an analog circuit, for example, when a capacitor is placed between X and Y, it may be said that X and Y are electrically connected.

[0037] As an example of a case where X and Y are functionally connected, one or more circuits capable of functionally connecting X and Y (e.g., logic circuits (e.g., inverters, NAND circuits, NOR circuits), signal conversion circuits (e.g., digital-to-analog conversion circuits, analog-to-digital conversion circuits, gamma correction circuits), potential level conversion circuits (e.g., power supply circuits such as boost circuits and buck circuits, and level shift circuits that change the potential level of a signal), voltage sources, current sources, switching circuits, amplifier circuits (e.g., circuits capable of increasing signal amplitude or current, operational amplifiers, differential amplifiers, source follower circuits, buffer circuits), signal generation circuits, storage circuits, control circuits, etc.) may be connected between X and Y. Note that, for example, even if other circuits are interposed between X and Y, when a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0038] Alternatively, for example, it can be expressed as “X, Y, the source of the transistor (sometimes referred to as one of the first and second terminals), and the drain of the transistor (sometimes referred to as the other of the first and second terminals) are electrically connected to each other, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence.” Alternatively, it can be expressed as “the source of the transistor is electrically connected to X, the drain of the transistor is electrically connected to Y, and X, the source of the transistor, the drain of the transistor, and Y are electrically connected in sequence.” Alternatively, it can be expressed as “X is electrically connected to Y through the source and drain of the transistor, and X, the source of the transistor, the drain of the transistor, and Y are connected to each other in sequence.” By specifying the connection order in the circuit structure using the same notation as these examples, the source and drain of the transistor can be distinguished, thereby determining the technical scope. Note that this notation is only an example and is not limited to the above-mentioned notation. Here, X and Y are objects (for example, devices, elements, circuits, wiring, electrodes, terminals, conductive films, or layers).

[0039] Furthermore, even when independent components are electrically connected on a circuit diagram, a single component may sometimes perform the functions of multiple components. For example, when a portion of a wiring serves as an electrode, a single conductive film may perform both wiring and electrode functions. Therefore, the term "electrically connected" in this specification also encompasses situations where a single conductive film performs the functions of multiple components.

[0040] In this specification, etc., a "resistor" may be, for example, a circuit element having a resistance value higher than 0Ω or a wiring having a resistance value higher than 0Ω. Therefore, in this specification, etc., a "resistor" includes a wiring having a resistance value, a transistor, a diode, or a coil through which current flows between a source and a drain. Therefore, a "resistor" may sometimes be referred to as a "resistor," a "load," or a "region having a resistance value." In contrast, a "resistor," a "load," or a "region having a resistance value" may sometimes be referred to as a "resistor." As a resistance value, for example, it is preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. In addition, for example, it may be 1 Ω or more and 1×10 9 Ω or less.

[0041] In this specification, etc., a "capacitor" may be, for example, a circuit element having an electrostatic capacitance value higher than 0F, a region of wiring having an electrostatic capacitance value higher than 0F, a parasitic capacitance, or a gate capacitance of a transistor. In addition, "capacitor", "parasitic capacitance" or "gate capacitance" etc. may sometimes be referred to as "capacitor". In contrast, "capacitor" may sometimes be referred to as "capacitor", "parasitic capacitance" or "gate capacitance". In addition, a "capacitor" (including "capacitors" with three or more terminals) has a structure including an insulator and a pair of conductors sandwiching the insulator. Thus, the "pair of conductors" of the "capacitor" may be referred to as a "pair of electrodes", "a pair of conductive regions", "a pair of regions" or "a pair of terminals". In addition, "one of a pair of terminals" and "the other of a pair of terminals" are sometimes referred to as the first terminal and the second terminal, respectively. The electrostatic capacitance value may be, for example, greater than 0.05fF and less than 10pF. In addition, for example, it may also be greater than 1pF and less than 10μF.

[0042] In this specification, etc., a transistor includes three terminals: a gate, a source, and a drain. The gate is used as a control terminal to control the conduction state of the transistor. The two terminals used as the source or drain are the input and output terminals of the transistor. Depending on the conductivity type of the transistor (n-channel type, p-channel type) and the level of the potential applied to the three terminals of the transistor, one of the two input and output terminals is used as the source and the other as the drain. Therefore, in this specification, etc., the source and drain can be interchanged. In this specification, etc., when describing the connection relationship of the transistor, the expressions "one of the source and drain" (first electrode or first terminal) and "the other of the source and drain" (second electrode or second terminal) are used. In addition, depending on the structure of the transistor, a back gate is sometimes included in addition to the above three terminals. In this case, in this specification, etc., one of the gate and back gate of the transistor is sometimes referred to as the first gate, and the other of the gate and back gate of the transistor is sometimes referred to as the second gate. Moreover, in the same transistor, "gate" and "back gate" can sometimes be interchanged. In addition, when a transistor includes three or more gates, each gate may be referred to as a first gate, a second gate, a third gate, etc. in this specification and the like.

[0043] For example, in this specification, etc., a multi-gate structure transistor having two or more gate electrodes can be used as an example of a transistor. When a multi-gate structure is adopted, since the channel forming regions are connected in series, a structure in which multiple transistors are connected in series is formed. Therefore, by adopting a multi-gate structure, the off-state current can be reduced and the voltage resistance of the transistor can be improved (improving reliability). Alternatively, by utilizing a multi-gate structure, when the transistor operates in the saturation region, even if the voltage between the drain and the source changes, the change in the current between the drain and the source is not too large, so that a voltage-current characteristic with a flat tilt angle can be obtained. When utilizing a voltage-current characteristic with a flat tilt angle, an ideal current source circuit or an active load with an extremely high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with good characteristics can be realized.

[0044] Furthermore, a circuit diagram showing a circuit element sometimes includes a case where the circuit element includes a plurality of circuit elements. For example, a circuit diagram showing a resistor includes a case where two or more resistors are electrically connected in series. Furthermore, for example, a circuit diagram showing a capacitor includes a case where two or more capacitors are electrically connected in parallel. Furthermore, for example, a circuit diagram showing a transistor includes a case where two or more transistors are electrically connected in series and the gates of each transistor are electrically connected to each other. Similarly, for example, a circuit diagram showing a switch includes a case where the switch includes two or more transistors, the two or more transistors being electrically connected in series or in parallel and the gates of each transistor being electrically connected to each other.

[0045] In this specification, etc., a node may be referred to as a terminal, wiring, electrode, conductive layer, conductor, or impurity region depending on the circuit structure or device structure. In addition, terminals, wiring, etc. may also be referred to as nodes.

[0046] In this specification, the terms "voltage" and "potential" may be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, when the reference potential is ground potential (e.g., ground potential), "voltage" may be referred to as "potential." Ground potential does not necessarily mean 0V. Furthermore, potential is relative; changes in the reference potential also cause changes in the potential applied to wiring, applied to circuits, and output from circuits.

[0047] In this specification and other documents, the terms "high-level potential" and "low-level potential" do not necessarily refer to specific potentials. For example, even if two wirings are described as "wirings for supplying a high-level potential," the high-level potentials applied to the two wirings may be different. Similarly, even if two wirings are described as "wirings for supplying a low-level potential," the low-level potentials applied to the two wirings may be different.

[0048] In addition, "current" refers to the phenomenon of charge movement (conduction). For example, the description of "conduction occurs in a positively charged body" can be replaced by the description of "conduction occurs in a negatively charged body in the opposite direction". Therefore, in this specification, etc., unless otherwise specified, "current" refers to the phenomenon of charge movement (conduction) when carriers move. Here, as carriers, for example, electrons, holes, anions, cations, complex ions, etc. can be cited. The carriers are different depending on the system through which the current flows (for example, semiconductors, metals, electrolytes, and vacuum). In addition, the "direction of current" in wiring, etc. is the direction in which positively charged carriers move, and is recorded as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current and is recorded as a negative current amount. Therefore, in this specification, etc., unless otherwise specified, regarding the positive and negative signs of current (or the direction of current), the description of "current flows from element A to element B" can be replaced by the description of "current flows from element B to element A". In addition, the description of "current is input to element A" can be replaced by the description of "current is output from element A".

[0049] Furthermore, in this specification, etc., ordinal numbers such as "first," "second," and "third" are added to avoid confusion between components. Therefore, these ordinal numbers do not limit the number of components. Furthermore, these ordinal numbers do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification, etc., may be referred to as "second" in another embodiment or claim. Furthermore, for example, in this specification, etc., a component referred to as "first" in one embodiment may be omitted in another embodiment or claim.

[0050] In this specification, etc., for the sake of convenience, words and phrases such as "upper" and "lower" that represent configurations are sometimes used to describe the positional relationship of components with reference to the accompanying drawings. In addition, the positional relationship of the components is appropriately changed depending on the direction in which each structure is described. Therefore, the wording is not limited to the words and phrases described in the specification, etc., and words and phrases can be appropriately replaced according to the situation. For example, in the expression "an insulator located on the top surface of a conductor", by rotating the direction of the illustrated drawing by 180 degrees, it can also be referred to as "an insulator located below the conductor".

[0051] In addition, the words "above" or "below" are not limited to the case where the positional relationship of the components is "directly above" or "directly below" and in direct contact. For example, if it is an expression "electrode B on insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included. In addition, similarly, for example, if it is an expression "electrode B above insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included. In addition, similarly, for example, if it is an expression "electrode B below insulating layer A", it is not necessarily necessary that electrode B is formed in direct contact with insulating layer A below insulating layer A, and the case where other components are included between insulating layer A and electrode B may also be included.

[0052] In addition, in this specification, etc., words such as "row" and "column" are sometimes used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships of the components vary depending on the direction in which each structure is described. Therefore, the terms are not limited to those described in the specification, etc., and may be replaced as appropriate depending on the situation. For example, when referring to the "row direction," the term "column direction" may sometimes be referred to as "row direction" by rotating the illustrated drawing 90 degrees.

[0053] In this specification, etc., the terms "film" and "layer" may be interchanged depending on the situation. For example, "conductive layer" may be interchanged with "conductive film." Also, "insulating film" may be interchanged with "insulating layer." Furthermore, depending on the situation or circumstances, other terms may be used in place of "film" and "layer." For example, "conductive layer" or "conductive film" may be interchanged with "conductive body." Also, for example, "insulating layer" or "insulating film" may be interchanged with "insulator."

[0054] Note that in this specification, etc., the words "electrode", "wiring" and "terminal" do not functionally limit their constituent elements. For example, sometimes an "electrode" is used as a part of a "wiring", and vice versa. Furthermore, the words "electrode" or "wiring" also include the case where a plurality of "electrodes" or "wirings" are formed into one. In addition, for example, sometimes a "terminal" is used as a part of a "wiring" or "electrode", and vice versa. Furthermore, the words "terminal" also include the case where one or more selected from "electrode", "wiring" and "terminal" are formed into one. Therefore, for example, an "electrode" can be a part of a "wiring" or "terminal", for example, a "terminal" can be a part of a "wiring" or "electrode". In addition, the words "electrode", "wiring" or "terminal" are sometimes replaced with words such as "region" depending on the circumstances.

[0055] In this specification, etc., depending on the situation or circumstances, the words "wiring", "signal line" or "power line" can be interchanged. For example, "wiring" can sometimes be replaced with "signal line". In addition, for example, "wiring" can sometimes be replaced with "power line". Vice versa, "signal line" or "power line" can sometimes be replaced with "wiring". In addition, "power line" can sometimes be replaced with "signal line". Vice versa, "signal line" can sometimes be replaced with "power line". In addition, depending on the situation or circumstances, "potential" applied to the wiring can sometimes be replaced with "signal". In addition, "signal" can sometimes be replaced with "potential".

[0056] In addition, in this specification, etc., the working method of the semiconductor device is sometimes described with reference to a timing diagram. In addition, the timing diagram used in this specification, etc. shows an ideal working example, and is not limited to the period, signal (for example, potential or current) and timing shown in the timing diagram unless otherwise specified. In the timing diagram of this specification, etc., the size and timing of the signal (for example, potential or current) input to each wiring (including nodes) in the timing diagram can be changed according to the situation. For example, even if two periods of equal intervals are shown in the timing diagram, the lengths of the two periods are sometimes different. In addition, for example, even if one of the two periods is shown to be long and the other is short, the lengths of the two periods may sometimes be the same, or one of the two periods may sometimes be short and the other may be long.

[0057] In this specification, etc., metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors) and oxide semiconductors (Oxide Semiconductor, also referred to as OS), etc. For example, when the channel formation region of a transistor contains a metal oxide, the metal oxide is sometimes referred to as an oxide semiconductor. In other words, when the metal oxide can constitute the channel formation region of a transistor having at least one of an amplification effect, a rectification effect and a switching effect, the metal oxide can be referred to as a metal oxide semiconductor (metal oxide semiconductor). In addition, an OS transistor can be referred to as a transistor comprising a metal oxide or an oxide semiconductor.

[0058] In this specification and other documents, metal oxides containing nitrogen may also be referred to as metal oxides (metal oxides). In addition, metal oxides containing nitrogen may also be referred to as metal oxynitrides (metal oxynitrides).

[0059] In addition, in this specification, etc., impurities of a semiconductor refer to substances other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic% is an impurity. When impurities are contained, sometimes one or more of the following occurs: an increase in the defect state density in the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor properties include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, or transition metals other than the main components, and in particular, for example, hydrogen (contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen.

[0060] In this specification, etc., a switch refers to an element that has a function of controlling whether current flows by changing to a conductive state (on state) or a non-conductive state (off state). Alternatively, a switch refers to an element that has a function of selecting and switching a current path. Therefore, a switch sometimes includes two or more terminals through which current flows in addition to a control terminal. As an example of a switch, an electric switch or a mechanical switch can be used. In other words, a switch is not limited to a specific element as long as it can control current.

[0061] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, metal-insulator-metal (MIM: Metal Insulator Metal) diodes, metal-insulator-semiconductor (MIS: Metal Insulator Semiconductor) diodes, or diode-connected transistors), or logic circuits combining these elements. When a transistor is used as a switch, the "on state" of the transistor refers to, for example, a state in which the source electrode and the drain electrode of the transistor are electrically short-circuited or a state in which current can flow between the source electrode and the drain electrode. In addition, the "non-conducting state" of the transistor refers to a state in which the source electrode and the drain electrode of the transistor are electrically disconnected. When a transistor is used only as a switch, there is no particular restriction on the polarity (conductivity type) of the transistor.

[0062] An example of a mechanical switch is a switch using MEMS (Micro Electro Mechanical System) technology, which has a mechanically movable electrode and operates by controlling conduction and non-conduction by moving the electrode.

[0063] In this specification, devices manufactured using a metal mask or FMM (Fine Metal Mask) are sometimes referred to as devices having an MM (Metal Mask) structure. In this specification, devices manufactured without using a metal mask or FMM are sometimes referred to as devices having an MML (Metal Mask Less) structure.

[0064] Note that in this specification and other documents, a structure in which light-emitting layers are formed or applied separately in light-emitting devices of each color (here, blue (B), green (G), and red (R)) is sometimes referred to as an SBS (Side-by-Side) structure. Furthermore, in this specification and other documents, a light-emitting device that can emit white light is sometimes referred to as a white light-emitting device. A white light-emitting device, when combined with a coloring layer (e.g., a color filter), can realize a display device capable of full-color display.

[0065] In addition, light-emitting devices can be roughly divided into single structures and series structures. A single-structure device preferably has the following structure: a light-emitting unit is included between a pair of electrodes, and the light-emitting unit includes one or more light-emitting layers. In the case of using two light-emitting layers to obtain white light, the light-emitting layers can be selected in such a way that the light-emitting colors of the two light-emitting layers are in a complementary color relationship. For example, by making the light-emitting colors of the first light-emitting layer and the light-emitting colors of the second light-emitting layer complementary colors, a structure in which the light-emitting device as a whole emits white light can be obtained. In addition, in the case of using three or more light-emitting layers to obtain white light, the light-emitting colors of the three or more light-emitting layers are combined to obtain a structure in which the light-emitting device as a whole emits white light.

[0066] Tandem devices preferably have a structure comprising two or more light-emitting units between a pair of electrodes, each unit comprising one or more light-emitting layers. To achieve white light, a structure can be employed in which the light emitted from the light-emitting layers of multiple light-emitting units is combined to produce white light. Note that the structure for achieving white light is the same as that for a single device. Furthermore, in tandem devices, an intermediate layer, such as a charge generation layer, is preferably provided between the multiple light-emitting units.

[0067] Furthermore, when comparing the aforementioned white light-emitting devices (single or tandem) with SBS-structured light-emitting devices, SBS-structured light-emitting devices can be made to consume less power than white light-emitting devices. SBS-structured light-emitting devices are preferred for devices that require lower power consumption. Furthermore, the manufacturing process for white light-emitting devices is simpler than that for SBS-structured devices, which can reduce manufacturing costs or increase manufacturing yields, making them preferable.

[0068] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°. Therefore, a state where the angle is greater than -5° and less than 5° is also included. "Approximately parallel" refers to a state where the angle formed by two straight lines is greater than -30° and less than 30°. In addition, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°. Therefore, a state where the angle is greater than 85° and less than 95° is also included. "Approximately perpendicular" refers to a state where the angle formed by two straight lines is greater than 60° and less than 120°.

[0069] In this specification, the structure shown in each embodiment can be appropriately combined with the structure shown in other embodiments to constitute one mode of the present invention. In addition, when multiple structural examples are shown in one embodiment, these structural examples can be appropriately combined.

[0070] In addition, the content (or part thereof) described in a certain embodiment may be applied / combined / replaced with other content (or part thereof) described in that embodiment and at least one of the content (or part thereof) described in one or more other embodiments.

[0071] Note that the contents described in the embodiments refer to the contents described in the various drawings in each embodiment or the contents described in the text described in the specification.

[0072] In addition, more figures can be formed by combining a figure (or part thereof) shown in a certain embodiment with other parts of the figure, other figures (or parts thereof) shown in the embodiment, and at least one figure (or part thereof) shown in one or more other embodiments.

[0073] The embodiments described in this specification are described with reference to the accompanying drawings. However, a person skilled in the art can easily understand the fact that the embodiments can be implemented in a plurality of different forms, and the methods and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments. Note that in the structure of the invention in the embodiments, the same symbols are sometimes used in different drawings to represent the same parts or parts with the same functions, and repeated descriptions are omitted. In stereograms, etc., for the sake of clarity, the illustration of some constituent elements is sometimes omitted.

[0074] In this specification, etc., when the same reference numeral is used for multiple elements and it is necessary to distinguish them, the reference numeral may be appended with an identifying symbol such as "_1," "[n]," or "[m,n]." Furthermore, in the drawings, etc., when a reference numeral is appended with an identifying symbol such as "_1," "[n]," or "[m,n]," the identifying symbol may not be appended if it is not necessary to distinguish them in this specification, etc.

[0075] In the drawings of this specification, sizes, layer thicknesses, and regions are sometimes exaggerated for clarity. Therefore, the present invention is not limited to the dimensions shown in the drawings. Furthermore, the drawings schematically illustrate idealized examples and are not limited to the shapes or numerical values ​​shown. For example, variations in signals, voltages, or currents due to noise or timing variations may be included.

[0076] (Implementation 1) In this embodiment, an amplifier circuit of a semiconductor device which is one embodiment of the present invention is described.

[0077] <Configuration Example 1 of Amplifier Circuit> Figure 2A The illustrated circuit BSPR is an example of an amplifier circuit and includes a circuit BB, a transistor MNb, and a capacitor Ca. Furthermore, for example, the circuit BSPR includes a terminal Ti serving as an input terminal and a terminal To serving as an output terminal. Furthermore, for example, the circuit BB includes a terminal Bi serving as an input terminal and a terminal Bo serving as an output terminal.

[0078] As the transistor MNb, for example, an OS transistor is preferably used. In particular, as the metal oxide contained in the channel formation region of the OS transistor, for example, an In-M-Zn oxide containing indium, element M, and zinc is preferably used (the element M is one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, cobalt, magnesium, and antimony). In addition, as the transistor MNb, a transistor containing silicon in the channel formation region (hereinafter referred to as a Si transistor) can also be used. In addition, as silicon, for example, single crystal silicon, amorphous silicon (sometimes referred to as hydrogenated amorphous silicon), microcrystalline silicon, or polycrystalline silicon can be used. In addition, as transistors other than OS transistors and Si transistors, for example, transistors containing germanium (Ge) in the channel formation region, transistors containing compound semiconductors such as zinc selenide (ZnSe), cadmium sulfide (CdS), gallium arsenide (GaAs), indium phosphide (InP), gallium nitride (GaN) or silicon germanium (SiGe) in the channel formation region, transistors containing carbon nanotubes in the channel formation region, or transistors containing organic semiconductors in the channel formation region can be used.

[0079] Figure 2AThe transistor MNb shown, for example, adopts an n-channel transistor with a multi-gate structure including gates above and below the channel, and the transistor MNb includes a first gate and a second gate. Note that in this specification, etc., for convenience, for example, the first gate is recorded as the gate (sometimes recorded as the front gate) and the second gate is recorded as the back gate to distinguish them. In addition, in this specification, etc., the first gate and the second gate can be interchanged, so the "gate" can be recorded as the "back gate". Similarly, the "back gate" can be recorded as the "gate". Specifically, the connection structure of "the gate is electrically connected to the first wiring and the back gate is electrically connected to the second wiring" can be replaced with the connection structure of "the back gate is electrically connected to the first wiring and the gate is electrically connected to the second wiring".

[0080] Although Figure 2A The transistor MNb shown in the figure shows a back gate, but the connection structure of the back gate is not shown. The electrical connection object of the back gate can be determined during the design. For example, in a transistor including a back gate, in order to increase the on-state current of the transistor, the gate and the back gate can be electrically connected. In other words, for example, the gate of the transistor MNb can be electrically connected to the back gate. In addition, for example, in a transistor including a back gate, in order to change the threshold voltage of the transistor or reduce the off-state current of the transistor, a wiring for electrically connecting the back gate of the transistor to an external circuit can be provided, and a potential can be applied to the back gate of the transistor through the external circuit.

[0081] In addition, ideally, the transistor MNb is a normally-off transistor, and the threshold voltage of the transistor MNb is denoted as V th_MNb In addition, the threshold voltage V th_MNb To meet V High -V Low >V th_MNb Note that V High is a high level potential, V Low It is a low level potential.

[0082] Note that in this specification, etc., normally off refers to a state in which no current flows through a transistor when the gate-source voltage is 0 V. Furthermore, the normally off state of an OS transistor refers to a state in which the current flowing through the transistor per channel width of 1 μm when the gate-source voltage is 0 V is 1×10 -20 Below A, at 85℃, it is 1×10 -18 A or less, or 1×10 -16 On the other hand, normally-on refers to a state in which a channel exists and current flows through the transistor even when the gate-source voltage is 0 V.

[0083] In addition, the semiconductor device of one embodiment of the present invention does not depend on the structure of the transistor included in the semiconductor device. For example, Figure 2A The transistor MNb shown may also be a structure not including a back gate, that is, a transistor with a single gate structure (see Figure 2B ). In addition, a structure in which some transistors include a back gate and other transistors do not include a back gate may be adopted.

[0084] In addition, Figure 2A In FIG. 4 , the transistor MNb is an n-channel transistor, but the transistor MNb may be a p-channel transistor depending on the situation.

[0085] Note that, except for the description of the transistor Figure 2A In addition, the same applies to transistors described in other parts of the specification or transistors shown in other drawings.

[0086] Terminal Bi of circuit BB is electrically connected to terminal Ti, and terminal Bo of circuit BB is electrically connected to the gate of transistor MNb and the first terminal of capacitor Ca. Furthermore, the first terminal of transistor MNb is electrically connected to wiring VAL1, and the second terminal of transistor MNb is electrically connected to the second terminal of capacitor Ca and terminal To.

[0087] Note that in this embodiment, a portion where the terminal Bo of the circuit BB, the gate of the transistor MNb, and the first terminal of the capacitor Ca are electrically connected is referred to as a node N.

[0088] Circuit BB has, for example, a function of floating node N. Therefore, circuit BB may include, for example, a switching element. In addition, circuit BB has a function of outputting a potential corresponding to the potential input to terminal Bi to terminal Bo. For example, circuit BB may have a function of outputting a potential corresponding to the potential input to terminal Bi to terminal Bo. High When the potential V is output to the terminal Bo Mid Note that V Mid Lower than the high level potential V High and higher than the low level potential V Low In addition, V Mid To meet V Mid -V Low >V th_MNb voltage.

[0089] in addition, Figure 2A Wiring VAL1 in the circuit is used, for example, as a wiring for applying a fixed potential or a variable potential. Examples of the fixed potential include a high-level potential, a low-level potential, a ground potential, or a negative potential. Furthermore, examples of the variable potential include a pulse signal (sometimes referred to as a pulse voltage). Furthermore, an example of a pulse signal includes a clock signal.

[0090] In addition, Figure 2AIn the example, the potentials of terminals Ti and To are denoted as V in and V out .

[0091] Here, assuming Figure 2A The potential of the node N of the BSPR circuit becomes lower than the high-level potential V High The potential V Mid In addition, it is assumed that the node N is not in a floating state at this time. In addition, it is assumed that a low-level potential V is applied from the wiring VAL1 to the first terminal of the transistor MNb. Low .

[0092] At this time, the gate-source voltage of the transistor MNb (at this time, the gate-first terminal voltage) becomes V Mid -V Low In addition, the V Mid -V Low To meet V Mid -V Low >V th_MNb Therefore, the wiring VAL1 outputs the low-level potential V to the terminal To of the circuit BSPR through the transistor MNb. Low In other words, becoming V out =V Low .

[0093] Next, it is assumed that the potential applied from the wiring VAL1 to the first terminal of the transistor MNb is changed from the low-level potential V Low becomes a high level potential V High In addition, it is assumed that the node N is made to float using the circuit BB. At this time, the gate-source voltage of the transistor MNb (at this time, the gate-second terminal voltage) is V Mid -V Low , whereby the transistor MNb turns on. Therefore, current flows from the wiring VAL1 through the transistor MNb to the terminal To of the circuit BSPR, and the potential of the terminal To increases from V Low In addition, the node N is in a floating state, so through the capacitive coupling of the capacitor Ca, the potential of the node N also increases from V to Mid As a result, the gate-source voltage of the transistor MNb is maintained by the capacitor Ca, and the potential of the terminal To is increased to V High In addition, ideally, the potential of the node N is V Mid +V High -V Low .

[0094] Thus, in the circuit BSPR, when a voltage lower than the high level potential is input to the node N, MidA high-level potential V is applied to the first terminal of the transistor MNb via the wiring VAL1. High When the terminal To is used as the potential output V High In this specification and other documents, the process of increasing the gate potential as the potential of the first terminal or the second terminal of a transistor increases by utilizing capacitive coupling is referred to as bootstrapping.

[0095] exist Figure 2A In the circuit BSPR, a high-level potential V is applied to the first terminal of the transistor MNb via the wiring VAL1. High A high level potential V is applied to the node N. High When the potential of node N rises to V Mid +V High -V Low , the potential of the terminal To output to the circuit BSPR becomes V High .

[0096] In addition, when the gate capacitance between the gate of the transistor MNb and the channel formation region (which may include one or both of the first terminal and the second terminal depending on the situation) is large, as shown in FIG. Figure 2C As shown, the circuit BSPR may have a structure without the capacitor Ca. In this case, the circuit area of ​​the circuit BSPR can be reduced.

[0097] The potential of the terminal Ti of the BSPR circuit is V High When terminal Ti is in a floating state (not electrically connected to the wiring that applies a potential), the potential of terminal Ti may fluctuate due to various factors. For example, in a transistor that maintains the potential of terminal Ti, if the off-state current flowing between the source and drain, or the leakage current flowing between the gate and source or gate and drain, increases, the potential of terminal Ti fluctuates. Furthermore, the potential of terminal Ti also fluctuates when a noise signal is input to terminal Ti. In other words, fluctuations in the potential of terminal Bi applied to circuit BB affect the potential of node N, resulting in instability in the potential output from terminal To of circuit BSPR.

[0098] then, Figure 1A An amplifier circuit of a semiconductor device according to one embodiment of the present invention that solves the above-mentioned problems will be described. Figure 1A The circuit BSFB shown is composed of Figure 2A The BSPR circuit and the FB circuit.

[0099] The circuit FB includes a terminal Fi and a terminal Fo.

[0100] The terminal Ti of the circuit BSPR and the terminal Fo of the circuit FB are electrically connected to each other. In addition, the terminal To of the circuit BSPR and the terminal Fi of the circuit FB are electrically connected to each other. Figure 1A, the terminal Ti of the circuit BSPR and the terminal Fo of the circuit FB are combined and shown as one terminal TMi, and the terminal To of the circuit BSPR and the terminal Fi of the circuit FB are combined and shown as one terminal TMo.

[0101] For example, circuit FB has a function of obtaining the potential output from terminal To of circuit BSPR and applying a fixed potential to terminal Ti of circuit BSPR. In other words, circuit FB is a circuit that provides feedback to circuit BSPR based on the potential output from terminal To of circuit BSPR. Specifically, for example, circuit FB may also have a function of receiving a high-level potential V at terminal Fi. High When a fixed potential (e.g., a high level potential V High ) structure.

[0102] By making the circuit FB have the above-mentioned structure, for example, when the high-level potential V is output from the terminal To of the circuit BSPR, High When a fixed potential is applied to terminal Ti of circuit BSPR, the fixed potential output from terminal Fo of circuit FB is applied. Therefore, for example, in a transistor that maintains the potential at terminal Ti (terminal TMi), even if the off-state current flowing between the source and drain or the leakage current flowing between the gate and source or gate and drain increases, the potential at terminal Ti (terminal TMi) remains at the fixed potential applied by circuit FB. Furthermore, when a noise signal is input to terminal Ti (terminal TMi), the potential at terminal Ti (terminal TMi) remains at the fixed potential applied by circuit FB. Therefore, the potential at terminal To of circuit BSPR does not change due to the aforementioned factors, and the potential at node N is not easily affected. Consequently, the potential output from terminal To of circuit BSPR is stable.

[0103] Note that the semiconductor device of one embodiment of the present invention is not limited to Figure 1A The semiconductor device of one embodiment of the present invention may also have, for example, the circuit BSFB shown. Figure 1B The circuit shown in BSFBA is as in Figure 1A A structure in which a transistor MNg is provided in the circuit BSFB.

[0104] As the transistor MNg, for example, a transistor that can be used as the transistor MNb can be used.

[0105] in addition, Figure 1B The circuit BSFB shown includes terminals TMi1 and TMi2 serving as input terminals and terminal TMo serving as an output terminal. Figure 1A In addition, the terminal TMi Figure 1B In the example, the potentials of terminal TMi1 and terminal TMi2 are respectively denoted as V in1 and Vin2 .

[0106] The first terminal of transistor MNg is electrically connected to the second terminal of transistor MNb, the second terminal of capacitor Ca, and terminal TMo. The second terminal of transistor MNg is electrically connected to wiring VAL4. The gate of transistor MNg is electrically connected to terminal TMi2.

[0107] Wiring VAL4 is used, for example, as a wiring for applying a fixed potential. A low-level potential can be used as a fixed potential. Other fixed potentials include ground potential or a negative potential. Wiring VAL4 can also be used as a wiring for applying a variable potential, depending on circumstances.

[0108] For example, the circuit BSFBA outputs a low-level potential V when the wiring VAL4 is set to Low When wiring, a low-level potential V can be output from terminal TMo. Low .

[0109] Here, it is explained Figure 1B For example, it is assumed that a high-level potential V is applied from the wiring VAL1 to the first terminal of the transistor MNb. High In addition, it is assumed that a low-level potential V is applied to the second terminal of the transistor MNg from the wiring VAL4. Low .

[0110] When the high-level potential V is output from the terminal TMo of the slave circuit BSFBA High When the low level potential V is input to the terminal TMi2, Low The transistor MNg is turned off. Then, a high-level potential V is input to the terminal TMi1. High , thus outputting a high-level potential V from terminal TMo High In addition, the high-level potential V is output from the terminal TMo. High For work, please refer to Figure 1A A working example of the circuit BSFB.

[0111] Then, the terminal TMo of the circuit BSFBA outputs a low-level potential V Low When a high level potential V is input to terminal TMi2 High The transistor MNg is turned on. This causes the terminal TMo and the wiring VAL4 to be in a conductive state, and the charge accumulated at the terminal TMo flows through the wiring VAL4. As a result, the potential of the terminal TMo becomes a low-level potential V Low In addition, at this time, by applying a low-level potential V to the terminal TMi1 Low The gate potential of the transistor MNb is set to a low level potential V Low, the transistor MNb becomes off, and the wiring VAL1 and the terminal TMo become non-conductive, thereby increasing the potential of the terminal TMo and reducing it to the low-level potential V Low speed.

[0112] In addition, the semiconductor device of one embodiment of the present invention may also adopt, for example, Figure 1C The circuit BSPR shown in FIG. 1 is a circuit BSFBB in which the capacitor Ca is not provided. Specifically, Figure 1C The circuit BSFBB has the Figure 1A The circuit BSPR is replaced by Figure 2C The structure of the circuit BSPR. Figure 2C As explained above, when the gate capacitance of transistor MNb is large, Figure 1A The BSPR of the circuit is not provided with capacitor Ca, thereby reducing Figure 1A The circuit area of ​​the circuit BSFB.

[0113] <<Configuration Example 1 of Circuit FB>> Next, explain Figure 1A The circuit BSFB or Figure 1B An example of the structure of the circuit BSFBA.

[0114] exist Figure 3A In the circuit BSFB1 shown, the circuit FB includes a transistor MNFa. As the transistor MNFa, for example, a transistor that can be used for the transistor MNb can be used. Note that, as an example, Figure 3A 2 shows an example in which the transistor MNFa is an n-channel transistor having a multi-gate structure including gates above and below a channel.

[0115] A first terminal of the transistor MNFa is electrically connected to the terminal Fo, a second terminal of the transistor MNFa is electrically connected to the wiring VAL41, and a gate of the transistor MNFa is electrically connected to the terminal Fi.

[0116] Like wiring VAL1, wiring VAL41 is used, for example, as a wiring for applying a fixed potential or a variable potential. Examples of the fixed potential include a high-level potential, a low-level potential, a ground potential, or a negative potential. Examples of the variable potential include a pulse signal (sometimes referred to as a pulse voltage).

[0117] Furthermore, the wiring VAL41 may be electrically connected to the wiring VAL1. In other words, the wiring VAL41 may be the same wiring as the wiring VAL1.

[0118] Here, it is explained Figure 3A A working example of the circuit BSFB1 is shown.

[0119] Regarding the operation of the circuit BSPR, please refer to Figure 2A Example of operation of circuit BSPR. For example, a high-level potential V is input to terminal TMi of circuit BSFB1. High When (ie, V in =V High When , circuit BB outputs potential V to terminal Bo Mid As a result, V is applied to the gate of the transistor MNb (the first terminal of the capacitor Ca). Mid In addition, it is assumed that a low-level potential V is applied from the wiring VAL1 to the first terminal of the transistor MNb. Low In addition, it is assumed that a high-level potential V is applied from the wiring VAL41 to the second terminal of the transistor MNFa. High .

[0120] At this time, the gate-source voltage of the transistor MNb (at this time, the gate-first terminal voltage) becomes V Mid -V Low , so the transistor MNb is turned on. Therefore, the wiring VAL1 outputs the low-level potential V to the terminal To of the circuit BSPR through the transistor MNb. Low In other words, becoming V out =V Low .

[0121] Therefore, the terminal Fi of the circuit FB is input with the same potential as the terminal To. Low As a result, a low-level potential V is applied to the gate of the transistor MNFa. Low .

[0122] In addition, the transistor MNFa is a normally closed transistor, and the threshold voltage of the transistor MNFa is denoted as V th_MNFa In addition, the threshold voltage V th_MNFa To meet V High -V Low >V th_MNFa voltage.

[0123] Here, the gate-source voltage of the transistor MNFa (here, the gate-first terminal voltage) is V Low -V High <V th_MNFa , so the transistor MNFa becomes off.

[0124] Next, it is assumed that the potential applied from the wiring VAL1 to the first terminal of the transistor MNb is changed from the low-level potential V Low becomes a high level potential V HighIn addition, it is assumed that the node N is made to float using the circuit BB. At this time, the gate-source voltage of the transistor MNb (at this time, the gate-second terminal voltage) becomes V Mid -V Low , so the transistor MNb is turned on. Therefore, current flows from the wiring VAL1 through the transistor MNb to the terminal To of the circuit BSPR, and the potential of the terminal To increases from V Low In addition, the node N is in a floating state, so through the capacitive coupling of the capacitor Ca, the potential of the node N also increases from V to Mid As a result, the gate-source voltage of the transistor MNb is maintained by the capacitor Ca, and the potential of the terminal To is increased to V High In addition, ideally, the potential of the node N is V Mid +V High -V Low .

[0125] At this time, the terminal Fi of the circuit FB is input with the same potential as the terminal To. High As a result, a high-level potential V is applied to the gate of the transistor MNFa. High .

[0126] Here, the gate-source voltage of the transistor MNFa (here, the gate-first terminal voltage) is, for example, V High -V High = 0. Since the transistor MNFa is a normally-off transistor, the transistor MNFa is in an off state.

[0127] In this state, when the potential of the terminal Ti (the first terminal of the transistor MNFa) of the circuit BSPR changes from the high-level potential V High When the voltage between the gate and the first terminal of the transistor MNFa decreases and becomes higher than the threshold voltage, the transistor MNFa turns on. At this time, the charge from the wiring VAL41 accumulates in the terminal Ti of the circuit BSPR, and the potential of the terminal Ti of the circuit BSPR increases. Specifically, the gate-source voltage of the transistor MNFa becomes V th_MNFa When the transistor MNFa is turned off, the potential of the terminal Ti (the first terminal of the transistor MNFa) of the circuit BSPR becomes V High -V th_MNFa .

[0128] As described above, in the circuit BSFB1, when the high-level potential V is output from the terminal TMo, High When the potential of the terminal Ti of the circuit BSPR drops, the circuit FB can apply a potential V to the terminal Ti. High -V th_MNFaTherefore, the potential of terminal Ti is kept roughly V High -V th_MNFa , the potential output from the terminal To of the circuit BSPR is stabilized.

[0129] Note that the semiconductor device of one embodiment of the present invention is not limited to Figure 3A The circuit BSFB1 is shown. For example, Figure 1B As in the circuit BSFB1A shown, the semiconductor device according to one embodiment of the present invention may have a structure in which the transistor MNFa is a transistor having a single-gate structure. In other words, the transistor MNFa may not include a back gate.

[0130] In addition, the semiconductor device according to one embodiment of the present invention may have, for example, Figure 3C The circuit BSFB1B shown in Figure 3A The structure of transistor MNg is set in the circuit BSFB1. Specifically, Figure 3C The circuit BSFB1B has the Figure 3A The circuit FB shown is used for Figure 1B The structure of the circuit FB in the circuit BSFBA. Figure 1B Similarly to the circuit BSFBA, the circuit BSFB1B is capable of outputting a high-level potential V from the terminal TMo. High Or low level potential V Low amplifier circuit.

[0131] <<Configuration Example 2 of Circuit FB>> Figure 4A The circuit BSFB2 shown is Figure 3A This modification example of the circuit BSFB1 is different from the circuit BSFB1 in that the back gate of the transistor MNFa is electrically connected to the gate of the transistor MNFa.

[0132] As described above, by electrically connecting the gate and back gate of a transistor, the on-state current of the transistor can be increased. That is, in the transistor MNFa of the circuit BSFB2, by electrically connecting the gate and back gate, the on-state current flowing through the transistor MNFa when it is in the on state can be increased. This can increase the fixed potential (for example, V) outputted from the potential of the terminal TMi to the terminal Fo of the circuit FB. High -V th_MNFa ) transfer speed.

[0133] in addition, Figure 4B The circuit BSFB3 shown is Figure 3A This modification example of the circuit BSFB1 is different from the circuit BSFB1 in that the back gate of the transistor MNFa is electrically connected to the wiring VAL51.

[0134] Like wiring VAL4, wiring VAL51 is used, for example, as a wiring for applying a fixed potential. Examples of the fixed potential include a low-level potential. Other examples of fixed potentials include ground potential or a negative potential. Furthermore, depending on circumstances, wiring VAL51 can also be used as a wiring for applying a variable potential.

[0135] As described above, when the low-level potential output from the wiring VAL4 is input to the back gate of the transistor MNFa, for example, the threshold voltage of the transistor MNFa increases, thereby making the transistor MNFa normally off, thereby reducing the off-state current flowing between the source and drain of the transistor MNFa.

[0136] in addition, Figure 4C The circuit BSFB4 shown is Figure 3A This modification example of the circuit BSFB1 is different from the circuit BSFB1 in that the back gate of the transistor MNFa is electrically connected to the terminal TMi, the terminal Fo, and the terminal Ti.

[0137] In the transistor MNFa in the circuit BSFB4, a low-level potential V is input to the terminal TMi. Low When the back gate of transistor MNFa is input with a low level potential V Low , so the threshold voltage of the transistor MNFa becomes high. In addition, at this time, the low level potential V is output from the terminal TMo. Low In the case of a low-level potential V Low , so the transistor MNFa becomes off, and the amount of off-state current flowing between the source and drain of the transistor MNFa at this time can be reduced.

[0138] In addition, in the transistor MNFa in the circuit BSFB4, a high-level potential V is input to the terminal TMi. High When the back gate of transistor MNFa is input with a high level potential V High , so the threshold voltage of transistor MNFa becomes low. At this time, the high level potential V High When outputting to the terminal TMo, the gate of the transistor MNFa is input with a high-level potential V High , so the transistor MNFa becomes on. At this time, the amount of on-state current flowing between the source and drain of the transistor MNFa is increased due to the input of the high-level potential V to the back gate of the transistor MNFa. High As a result, the fixed potential (for example, V High -V th_MNFa ) transfer speed.

[0139] <<Configuration Example 3 of Circuit FB>> Figure 4D The circuit BSFB5 shown is Figure 3A This modification of circuit BSFB1 differs from circuit BSFB1 in that the second terminal of transistor MNFa is electrically connected to the gate of transistor MNFa instead of to wiring VAL41. That is, transistor MNFa in circuit BSFB5 has a diode-connected structure.

[0140] A high-level potential V is input to the gate of the transistor MNFa. High (A high-level potential V is output from the terminal To of the circuit BSPR. High ), the potential of the first terminal of the transistor MNFa is lower than V High -V th_MNFa When , the transistor MNFa becomes on. At this time, the current output from the terminal To passes through the circuit FB and flows through the source-drain of the transistor MNFa to the terminal TMi. In addition, when the current flows through the terminal TMi and the potential of the first terminal of the transistor MNFa becomes V High -V th_MNFa , the transistor MNFa becomes off.

[0141] Similar to the circuit BSFB, when the circuit BSFB5 is used, the potential output from the terminal To of the circuit BSPR may be fed back to apply a fixed potential to the terminal Ti of the circuit BSPR.

[0142] <<Configuration Example 4 of Circuit FB>> Figure 5 The circuit BSFB6 shown is Figure 3A This modification of circuit BSFB1 differs from circuit BSFB1 in that circuit FB includes circuit BUF. Circuit BSFB6 also differs from circuit BSFB1 in that terminal Fi is not directly electrically connected to the gate of transistor MNFa, but is directly electrically connected to terminal BFi (described later), and the gate of transistor MNFa is directly electrically connected to terminal BFo (described later).

[0143] The circuit BUF includes a terminal BFi and a terminal BFo.

[0144] The circuit BUF has a function of, for example, amplifying a potential input to the terminal BFi and outputting the amplified potential to the terminal BFo. In particular, the circuit BUF is used as a buffer circuit.

[0145] In the circuit BSFB6 , by using the circuit BUF as a buffer circuit, even if the potential output from the terminal TMo slightly fluctuates due to a noise signal or the like, a stable fixed potential can be applied to the gate of the transistor MNFa.

[0146] Figure 6A Show Figure 5 The circuit BSFB6 is an example of the structure of the circuit BUF shown in FIG. Figure 6A In order to illustrate the electrical connection structure, the circuit BSPR, the terminal TMi and the terminal TMo are also shown.

[0147] exist Figure 6A In the illustrated circuit BSFB6A, circuit BUF includes logic circuit INV1 and logic circuit INV2.

[0148] An input terminal of the logic circuit INV1 is electrically connected to the terminal BFi, an output terminal of the logic circuit INV1 is electrically connected to an input terminal of the logic circuit INV2, and an output terminal of the logic circuit INV2 is electrically connected to the terminal BFo.

[0149] Both logic circuit INV1 and logic circuit INV2 have the function of generating and outputting an inverted signal of a signal input to an input terminal. For example, inverter circuits can be used as logic circuits INV1 and INV2. In addition to inverter circuits, for example, NAND circuits, NOR circuits, XOR circuits, or logic circuits combining these circuits can also be used.

[0150] Figure 6B Show Figure 6A The illustrated circuit BSFB6A shows an example of the configuration of the logic circuit INV1 and the logic circuit INV2 included in the circuit BUF.

[0151] exist Figure 6B In the circuit BSFB6B shown, the logic circuit INV1 and the logic circuit INV2 both include a transistor M1 , a transistor M2 , a transistor M3 , and a transistor M4 .

[0152] Furthermore, as the transistors M1 to M4 , for example, transistors that can be used for the transistor MNb can be used.

[0153] In logic circuit INV1, the gate of transistor M1 and the gate of transistor M3 are each electrically connected to an input terminal of logic circuit INV1 (terminal BFi of circuit BUF). Furthermore, a first terminal of transistor M1 is electrically connected to a first terminal of transistor M2 and a gate of transistor M4. A second terminal of transistor M1 is electrically connected to wiring VAL52. A second terminal of transistor M2 is electrically connected to a gate of transistor M2 and wiring VAL42. A first terminal of transistor M3 is electrically connected to a first terminal of transistor M4 and an output terminal of logic circuit INV1. A second terminal of transistor M3 is electrically connected to wiring VAL52. A second terminal of transistor M4 is electrically connected to wiring VAL42.

[0154] In logic circuit INV2, the gates of transistor M1 and transistor M3 are both electrically connected to the input terminal of logic circuit INV2 (the output terminal of logic circuit INV1). Furthermore, the first terminal of transistor M1 is electrically connected to the first terminal of transistor M2 and the gate of transistor M4. The second terminal of transistor M1 is electrically connected to wiring VAL52. The second terminal of transistor M2 is electrically connected to the gate of transistor M2 and wiring VAL42. The first terminal of transistor M3 is electrically connected to the first terminal of transistor M4 and the output terminal of logic circuit INV2 (terminal BFo of circuit BUF). The second terminal of transistor M3 is electrically connected to wiring VAL52. The second terminal of transistor M4 is electrically connected to wiring VAL42.

[0155] Wiring VAL42 is used, for example, as a power supply line for applying a high-level potential to each of logic circuits INV1 and INV2. Note that wiring VAL42 may be a wiring that applies a low-level potential, a ground potential, or a negative potential instead of a high-level potential. Alternatively, wiring VAL42 may be a wiring that applies a variable potential instead of a fixed potential.

[0156] Wiring VAL52 is used, for example, as a power supply line for applying a low-level potential to each of logic circuits INV1 and INV2. Note that wiring VAL52 may be a wiring that applies a high-level potential, a ground potential, or a negative potential instead of a low-level potential. Alternatively, wiring VAL52 may be a wiring that applies a variable potential instead of a fixed potential.

[0157] Furthermore, the second terminal of transistor M2 and the second terminal of transistor M4 included in each of logic circuits INV1 and INV2 are electrically connected to a single wiring VAL42. However, the second terminal of transistor M2 and the second terminal of transistor M4 included in each of logic circuits INV1 and INV2 may be electrically connected to different wirings. Similarly, the second terminal of transistor M1 and the second terminal of transistor M3 included in each of logic circuits INV1 and INV2 are electrically connected to a single wiring VAL52. However, the second terminal of transistor M1 and the second terminal of transistor M3 included in each of logic circuits INV1 and INV2 may be electrically connected to different wirings.

[0158] in addition, Figure 7A Show Figure 5 The circuit BSFB6 shown is an example of the structure of the circuit BUF. Figure 7A The circuit shown in BSFB6C is also Figure 6B A modified example of circuit BSFB6B includes circuit BUF, in which the number and connection structure of transistors are different from those of circuit BSFB6B.

[0159] Circuit BUF of circuit BSFB6 includes transistor M1 , transistor M2 , transistor M3 , transistor M4 , transistor M5 , transistor M6 , and transistor M7 .

[0160] Furthermore, as the transistors M1 to M7 , for example, transistors that can be used for the transistor MNb can be used.

[0161] exist Figure 7A In circuit BUF of circuit BSFB6C, the gate of transistor M1, the gate of transistor M3, and the first terminal of transistor M5 are all electrically connected to terminal BFi of circuit BUF (terminal Fi of circuit FB). Furthermore, the first terminal of transistor M1 is electrically connected to the first terminal of transistor M2 and the gate of transistor M4. The second terminal of transistor M1 is electrically connected to wiring VAL52. The second terminal of transistor M2 is electrically connected to the gate of transistor M2 and wiring VAL42. The first terminal of transistor M3 is electrically connected to the first terminal of transistor M4 and the gate of transistor M6. The second terminal of transistor M3 is electrically connected to wiring VAL52. The second terminal of transistor M4 is electrically connected to wiring VAL42. The second terminal of transistor M5 is electrically connected to the gate of transistor M7, and the gate of transistor M5 is electrically connected to wiring VAL42. The first terminal of transistor M6 is electrically connected to the first terminal of transistor M2 and terminal BFo of circuit BUF. The second terminal of transistor M6 is electrically connected to wiring VAL52. The second terminal of transistor M7 is electrically connected to wiring VAL42.

[0162] Note that the second terminal of transistor M2, the second terminal of transistor M4, the gate of transistor M5, and the second terminal of transistor M7 are all electrically connected to a single wiring VAL42. However, the second terminal of transistor M2, the second terminal of transistor M4, the gate of transistor M5, and the second terminal of transistor M7 may be electrically connected to different wirings. Similarly, the second terminal of transistor M1, the second terminal of transistor M3, and the second terminal of transistor M6 are all electrically connected to a single wiring VAL52. However, the second terminal of transistor M1, the second terminal of transistor M3, and the second terminal of transistor M6 may be electrically connected to different wirings.

[0163] in addition, Figure 7B Shown with Figure 7A The circuit of BSFB6C is different Figure 5 The circuit BSFB6 shown is an example of the structure of the circuit BUF. Figure 7B The circuit shown in BSFB6D is also Figure 7A A modified example of circuit BSFB6C includes circuit BUF, in which the number and connection structure of transistors are different from those of circuit BSFB6C.

[0164] Circuit BUF of circuit BSFB6D includes, for example, a transistor M1 , a transistor M2 , a transistor M5 , a transistor M6 , and a transistor M7 .

[0165] exist Figure 7B In circuit BUF of circuit BSFB6D, the gate of transistor M1 and the first terminal of transistor M5 are both electrically connected to terminal BFi of circuit BUF (terminal Fi of circuit FB). Furthermore, the first terminal of transistor M1 is electrically connected to the first terminal of transistor M2 and the gate of transistor M6. The second terminal of transistor M1 is electrically connected to wiring VAL52. The second terminal of transistor M2 is electrically connected to the gate of transistor M2 and wiring VAL42. The second terminal of transistor M5 is electrically connected to the gate of transistor M7, and the gate of transistor M5 is electrically connected to wiring VAL42. The first terminal of transistor M6 is electrically connected to the first terminal of transistor M7 and terminal BFo of circuit BUF. The second terminal of transistor M6 is electrically connected to wiring VAL52. The second terminal of transistor M7 is electrically connected to wiring VAL42.

[0166] By making Figure 5 The circuit BUF of the circuit BSFB6 shown has Figure 6A The circuit BSFB6A( Figure 6B Circuit BSFB6B), Figure 7A The circuit BSFB6C, Figure 7B The structure of any circuit BUF in the circuit BSFB6D can apply a stable fixed potential to the gate of the transistor MNFa.

[0167] Note that circuit BSFB6 can be Figure 6B The circuit BSFB6B, Figure 7A The circuit of BSFB6C and Figure 7B The circuit BSFB6D may be configured as a unipolar circuit using n-channel transistors, or may be configured as a CMOS circuit including p-channel transistors.

[0168] <<Configuration Example 5 of Circuit FB>> and Figure 1A The circuit BSFB is similarly, Figure 8A The circuit BSFB7 shown is an amplifier circuit that feeds back the potential output from the terminal To of the circuit BSPR to the terminal Ti (terminal TMi). Figure 8A The circuit FB of the circuit BSFB7 includes the terminal Fi1 and the terminal Fi2 used as input terminals, which is similar to the circuit BSFB7. Figure 1A The circuit BSFB is different.

[0169] exist Figure 8A In the circuit BSFB7, the circuit FB includes a transistor MNFa, a capacitor Caf, and a circuit BBF. As described above, Figure 8A The circuit FB included in the circuit BSFB7 includes the terminal Fi1 and the terminal Fi2 used as input terminals and the terminal Fo used as an output terminal. Note that the terminal Fi2 is equivalent to Figure 1A Terminal Fi shown.

[0170] As the transistor MNFa, a transistor that can be used as the transistor MNb can be used.

[0171] Circuit BBF can be used for Figure 2A The circuit BSPR shown includes the circuit BB. Therefore, in Figure 8A , as terminals of circuit BBF, terminal Bi and terminal Bo are shown similarly to circuit BB.

[0172] Terminal Fi1 is electrically connected to terminal Bi of circuit BBF. Terminal Fi1 is also electrically connected to terminal Ti of circuit BSPR, terminal TMi of circuit BSFB7, and terminal Fo of circuit FB. Terminal Fi2 is electrically connected to a first terminal of capacitor Caf. Terminal Fi2 is electrically connected to terminal To of circuit BSPR and terminal TMo of circuit BSFB7. The second terminal of capacitor Caf is electrically connected to terminal Bo of circuit BBF and the gate of transistor MNFa. Terminal Fo is also electrically connected to a first terminal of transistor MNFa, and a second terminal of transistor MNFa is electrically connected to wiring VAL41.

[0173] Note that in this embodiment, a portion where the terminal Bo of the circuit BBF, the gate of the transistor MNFa, and the second terminal of the capacitor Caf are electrically connected is referred to as a node Nf.

[0174] Circuit BBF, for example, has the function of floating node Nf. Therefore, circuit BBF may include, for example, a switching element. Furthermore, circuit BBF has the function of outputting a potential corresponding to the potential input to terminal Bi to terminal Bo. For example, circuit BBF may have the function of outputting a potential corresponding to the potential input to terminal Bi to terminal Bo. High When the potential V Mid_f Output to terminal Bo. Note that V Mid_f Lower than the high level potential V High and higher than the low level potential V Low .

[0175] For wiring VAL41, please refer to Figure 3A Record of wiring VAL41 described in circuit BSFB1.

[0176] Here, it is explained Figure 8A The circuit of BSFB7 is a working example.

[0177] Regarding the operation of the circuit BSPR, please refer to Figure 2A Example of operation of circuit BSPR. For example, a high-level potential V is input to terminal TMi of circuit BSFB7. High When (ie, V in =V High When , circuit BB outputs potential V to terminal Bo Mid As a result, V is applied to the gate of the transistor MNb (the first terminal of the capacitor Ca). Mid In addition, it is assumed at this time that the node N is placed in a floating state using the circuit BB.

[0178] In addition, it is assumed that a low-level potential V is applied from the wiring VAL1 to the first terminal of the transistor MNb. Low At this time, the gate-source voltage of the transistor MNb (at this time, the gate-first terminal voltage) becomes V Mid -V Low , so the transistor MNb is turned on. Therefore, the wiring VAL1 outputs a low-level potential V to the terminal TMo of the circuit BSPR through the transistor MNb. Low In other words, becoming V out =V Low .

[0179] Therefore, the terminal Fi2 of the circuit FB is input with the same potential as the terminal To. Low As a result, a low-level potential V is applied to the first terminal of the capacitor Caf.Low .

[0180] In addition, in the circuit FB, a high-level potential V is input to the terminal TMi of the circuit BSFB7. High When (ie, V in =V High When , the circuit BBF outputs a potential V to the terminal Bo. Mid_f As a result, V is applied to the gate of the transistor MNFa (the second terminal of the capacitor Caf and the node Nf). Mid_f Therefore, when the node Nf is used as a reference, the voltage held in the capacitor Caf becomes V Mid_f -V Low .

[0181] In addition, the transistor MNFa is a normally closed transistor, and the threshold voltage of the transistor MNFa is denoted as V th_MNFa In addition, the threshold voltage V th_MNFa To meet V High -V Low >V th_MNFa voltage.

[0182] In addition, it is assumed that a high-level potential V is applied from the wiring VAL41 to the second terminal of the transistor MNFa. High At this time, the potentials of the first terminal and the second terminal of the transistor MNFa are both V High , the gate of transistor MNFa becomes V Mid_f At this time, the gate-source voltage of the transistor MNFa (at this timing, for example, the gate-first terminal voltage) becomes V Mid_f -V High . As a result of becoming V Mid_f -V High <V th_MNFa , so the transistor MNFa is turned off. In addition, at this time, it is assumed that the node Nf is in a floating state by the circuit BBF.

[0183] Next, it is assumed that the potential applied from the wiring VAL1 to the first terminal of the transistor MNb is changed from the low-level potential V Low becomes a high level potential V High At this time, the gate-source voltage of the transistor MNb (at this time, the gate-second terminal voltage) becomes V Mid -V Low , so the transistor MNb is turned on. Therefore, current flows from the wiring VAL1 through the transistor MNb to the terminal TMo of the circuit BSPR, and the potential of the terminal To increases from V Low In addition, the node N is in a floating state, so through the capacitive coupling of the capacitor Ca, the potential of the node N also increases from V toMid As a result, the gate-source voltage of the transistor MNb is maintained by the capacitor Ca, and the potential of the terminal To is increased to V High In addition, ideally, the potential of the node N is V Mid +V High -V Low .

[0184] At this time, the terminal Fi2 of the circuit FB is input with the same potential as the terminal To. High As a result, the potential of the first terminal of the capacitor Caf is increased from the low level potential V Low becomes a high level potential V High In addition, the node Nf is in a floating state, so due to the capacitive coupling of the capacitor Caf, the potential of the node Nf also rises from V to Mid Note that here, the potential of node Nf becomes V Mid_f +V High -V Low .

[0185] As a result, the gate potential of the transistor MNFa becomes V Mid_f +V High -V Low In addition, since the potentials of the first terminal and the second terminal of the transistor MNFa are V High , so the gate-source voltage of transistor MNFa at this time becomes V Mid_f -V Low By meeting V Mid_f -V Low >V th_MNFa , the transistor MNFa is turned on. In other words, the terminal TMi of the circuit BSFB7 and the wiring VAL41 are in conduction.

[0186] Furthermore, as mentioned above, the gate potential of the transistor MNFa is V Mid_f +V High -V Low Here, when the gate potential of transistor MNFa is V Mid_f +V High -V Low Greater than V High +V th_MNFa When (ie, V Mid_f -V Low Higher than V th_MNFa When the potential applied from the wiring VAL41 to the terminal TMi of the circuit BSFB7 (the terminal Ti of the circuit BSPR) via the transistor MNFa does not generate the threshold voltage V th_MNFaThat is, since the voltage drop in the transistor MNFa is hardly affected, the potential of the terminal TMi of the circuit BSFB7 (the terminal Ti of the circuit BSPR) can be changed to the high-level potential V applied from the wiring VAL41. High .

[0187] Thus, for example, in a transistor for maintaining the potential of the terminal Ti (terminal TMi), even if the off-state current flowing between the source and the drain or the leakage current flowing between the gate and the source or between the gate and the drain increases, the potential of the terminal Ti (terminal TMi) is maintained at the fixed potential (high-level potential V High ). In addition, when a noise signal is input to the terminal Ti (terminal TMi), the potential of the terminal Ti (terminal TMi) also maintains the fixed potential (high-level potential V High ). Therefore, the potential of the terminal To of the circuit BSPR does not change due to the above-mentioned factors, and thus the potential of the node N is not easily affected. Therefore, the potential output from the terminal To of the circuit BSPR is stable.

[0188] Figure 8B Shown in Figure 8A The circuit BSFB7 will be described later Figure 9A Circuit BB is used as a structural example of circuit BBF. Figure 8B Circuit BSFB7A has a structure in which circuit BBF includes transistor MNFb.

[0189] A first terminal of the transistor MNFb is electrically connected to the terminal Bi of the circuit BBF, a second terminal of the transistor MNFb is electrically connected to the terminal Bo of the circuit BBF, and a gate of the transistor MNFb is electrically connected to the wiring VAL42.

[0190] Regarding the wiring VAL42, reference can be made to the description of the wiring VAL41 described above.

[0191] In addition, the transistor MNFb is a normally off transistor, and the threshold voltage of the transistor MNFb is denoted as V th_MNFb In addition, the threshold voltage V th_MNFb To meet V High -V Low >V th_MNFb voltage.

[0192] Here, it is explained Figure 8B The circuit FB in the circuit BSFB7A is an example of circuit operation. First, in the circuit FB, the potential of the node Nf is the low level potential V Low In addition, a high-level potential V is applied to the gate of the transistor MNFb from the wiring VAL4. HighAt this time, the gate-source voltage of the transistor MNFb (at this time, the gate-second terminal voltage) becomes V High -V Low , so the transistor MNFb is turned on. In addition, here, the high level potential V is input to the terminal TMi of the circuit BSFB7A. High When (ie, V in =V High When the potential of the second terminal of the transistor MNFb rises to the gate-source voltage at which the transistor MNFb turns off. Specifically, when the potential of the second terminal of the transistor MNFb (the potential of the node Nf) reaches V High -V th_MNFb When V High -V th_MNFb Equivalent to the above V Mid_f .

[0193] Then, the high-level potential V is output from the terminal To by the circuit BSPR. High Therefore, the potential of the node Nf increases from V to High -V th_MNFb becomes 2V High -V th_MNFb -V Low That is, the gate potential of transistor MNFa becomes 2V High -V th_MNFb -V Low , and the first terminal and the second terminal of the transistor MNFa both become V High , so the gate-source voltage of transistor MNFa becomes V High -V th_MNFb -V Low By meeting V High -V th_MNFb -V Low >V th_MNFa , the transistor MNFa is turned on, and the wiring VAL41 and the terminal Ti (terminal TMi) are conductively connected.

[0194] In addition, when the gate potential of transistor MNFa is 2V High -V th_MNFb -V Low Greater than V High +V th_MNFa When (ie, V High -V Low -V th_MNFb Higher than V th_MNFaWhen the potential applied from the wiring VAL41 to the terminal TMi of the circuit BSFB7 (the terminal Ti of the circuit BSPR) via the transistor MNFa does not generate the threshold voltage V th_MNFa That is, since the influence of the voltage drop in the transistor MNFa can be almost eliminated, the potential of the terminal TMi of the circuit BSFB7 (the terminal Ti of the circuit BSPR) can be set to the high-level potential V applied from the wiring VAL41. High As a result, the terminal Ti (terminal TMi) is not in a floating state, so the potential of the terminal Ti (terminal TMi) does not change due to factors such as leakage current and noise signals.

[0195] Note that the semiconductor device of one embodiment of the present invention is not limited to Figure 8A The circuit shown in BSFB7 and Figure 8B The semiconductor device of one embodiment of the present invention may also have, for example, a circuit BSFB7A. Figure 8A The circuit of BSFB7 is changed to Figure 8C The circuit structure of the circuit BSFB7B is shown.

[0196] Figure 8C The circuit BSFB7B has the following structure: Figure 8A The capacitor Caf included in the circuit FB in the circuit BSFB7 is combined into the capacitor Ca included in the circuit BSPR, and the circuit BBF included in the circuit FB is combined into the circuit BB included in the circuit BSPR. Therefore, the node Nf of the circuit FB is combined into the node N of the circuit BSPR.

[0197] exist Figure 8C In the circuit BSFB7B, the input terminal of the circuit FB is not the terminal Fi1 and the terminal Fi2 but the terminal Fi. Figure 8C In the circuit BSFB7B, the terminal Fi of the circuit FB is electrically connected to the terminal Bo of the circuit BB, the gate of the transistor MNb, and the first terminal of the capacitor Ca.

[0198] Notice, Figure 8C The circuit BSFB7B has the following structure: Figure 3A In the circuit BSFB1, the terminal Fi of the circuit FB is not electrically connected to the terminal To and the terminal TMo, but is electrically connected to the terminal Bo of the circuit BB, the gate of the transistor MNb, and the first terminal of the capacitor Ca. In other words, Figure 8C The circuit of BSFB7B is Figure 3A A modified example of the circuit BSFB1 is shown in FIG.

[0199] exist Figure 8C The operation of the circuit BSFB7B can be referred to Figure 2A The circuit BSPR working example. Therefore, by the potential at node N is V Mid After the node N is placed in a floating state, the potential applied from the wiring VAL1 to the first terminal of the transistor MNb is lowered from the low-level potential V Low becomes a high level potential V High , the potential of node N can be set to V by bootstrapping Mid +V High -V Low As a result, V is applied to the gate of transistor MNFa. Mid +V High -V Low Here, when the gate potential of transistor MNFa is V Mid +V High -V Low Greater than V High +V th_MNFa When the potential applied from the wiring VAL41 to the terminal TMi of the circuit BSFB7 (the terminal Ti of the circuit BSPR) via the transistor MNFa does not generate the threshold voltage V th_MNFa That is, with Figure 8A Similarly, since the influence of the voltage drop in the transistor MNFa can be almost eliminated, the potential of the terminal TMi of the circuit BSFB7B (the terminal Ti of the circuit BSPR) can be set to the high-level potential V applied from the wiring VAL41. High .

[0200] <<Configuration Example 1 of Circuit BB>> Next, explain Figure 1A and Figure 1B The configuration example of the circuit BB in each circuit BSPR. Note that the circuit BB described below can also be used for Figure 8A The circuit FB is in the circuit BBF.

[0201] exist Figure 9A In the circuit BSPR shown in FIG. 1 , the circuit BB includes a transistor MNa. For example, a transistor that can be used as the transistor MNb can be used as the transistor MNa.

[0202] A first terminal of the transistor MNa is electrically connected to the terminal Bi, and a second terminal of the transistor MNa is electrically connected to the terminal Bo. In addition, a gate of the transistor MNa is electrically connected to the wiring VAL2.

[0203] For example, wiring VAL2, like wiring VAL1, is used as a wiring for applying a fixed potential or a variable potential. Examples of the fixed potential include a high-level potential, a low-level potential, a ground potential, or a negative potential. Examples of the variable potential include a pulse signal.

[0204] Furthermore, the wiring VAL2 may be electrically connected to the wiring VAL1. In other words, the wiring VAL2 may be the same wiring as the wiring VAL1.

[0205] Here, it is explained Figure 9A For example, suppose that a high-level potential V is input to the terminal Ti of the circuit BSPR. High In other words, becoming V in =V High In addition, it is assumed that a high-level potential V is applied to the gate of the transistor MNa from the wiring VAL2. High In addition, the potential of the node N (the potential of the gate of the transistor MNb or the potential of the first terminal of the capacitor Ca) is a low-level potential V Low .

[0206] In addition, the transistor MNa is a normally closed transistor, and the threshold voltage of the transistor MNa is recorded as V th_MNa In addition, the threshold voltage V th_MNa To meet V High -V Low >V th_MNa voltage.

[0207] The gate-source voltage of the transistor MNa (at this time, the gate-second terminal voltage) becomes V High -V Low , so the transistor MNa becomes on. Therefore, a current flows from the terminal Ti through the transistor MNa in the node N, and charge accumulates until the transistor MNa becomes off, and the potential of the node N rises. Specifically, the gate-source voltage of the transistor MNa drops to V th_MNa When the transistor MNa is turned off, the potential of the node N (the potential of the second terminal of the transistor MNa) becomes V High -V th_MNa . Note that V High -V th_MNa Equivalent to Figure 2A The V Mid .

[0208] <<Configuration Example 2 of Circuit BB>> Figure 9B The BSPR of the circuit shown is Figure 9A In the modified example of the circuit BB of the circuit BSPR, the gate of the transistor MNa is not electrically connected to the wiring VAL2 but is electrically connected to the first terminal of the transistor MNa. Figure 9A The circuit BSPR is different from the circuit BB.

[0209] exist Figure 9BIn FIG, the first terminal of the transistor MNa is electrically connected to the gate of the transistor MNa, so the transistor MNa can be said to be diode-connected. Therefore, for example, when a high-level potential V is input to the terminal Ti of the circuit BSPR, High When the potential of each of the first terminal and the gate of the transistor MNa becomes a high-level potential V High , so the potential of the node N (the potential of the second terminal of the transistor MNa) becomes V High -V th_MNa .

[0210] Note that when the potential of the node N (the potential of the second terminal of the transistor MNa) is to be lowered V High -V th_MNa , that is, when you want to release the charge accumulated at node N, you need to further change Figure 9B The BSPR circuit is the BB circuit.

[0211] Figure 9C The BSPR of the circuit shown in circuit BB is Figure 9B The circuit BSPR is a modified example of the circuit BB, which can release the charge accumulated in the node N. Figure 9B The circuit BSPR is different from the circuit BB.

[0212] exist Figure 9C In the circuit BSPR, the circuit BB includes a transistor MNd in addition to the transistor MNa.

[0213] As the transistor MNd, for example, a transistor that can be used for the transistor MNa or the transistor MNb can be used.

[0214] A first terminal of the transistor MNd is electrically connected to the second terminal of the transistor MNa and the terminal Bo, a second terminal of the transistor MNd is electrically connected to the wiring VAL3 , and a gate of the transistor MNd is electrically connected to the wiring RST.

[0215] Wiring VAL3, for example, is used as a wiring for applying a fixed potential, similar to wiring BAL2 or wiring VAL52. Examples of the fixed potential include a low-level potential. Other examples of fixed potentials include ground potential or a negative potential. Depending on circumstances, wiring VAL3 can also be used as a wiring for applying a variable potential.

[0216] The wiring RST is used as, for example, a wiring for transmitting a signal for selecting whether to discharge the charge accumulated in the node N. Specifically, for example, when the charge of the node N is not discharged, a low-level potential V may be applied to the wiring RST. Low As a signal, the transistor MNd is turned off. For example, when the charge of the node N is released, a high-level potential V may be applied to the wiring RST. HighThe transistor MNd is turned on as a signal.

[0217] When you want to increase the potential of node N (you want to set the potential of node N to V High -V th_MNa ), for example, a low-level potential V is applied to the wiring RST. Low The transistor MNd is turned off, and a high-level potential V is applied to the terminal Ti. High , then. In addition, if you want to lower the potential of node N (you want to set the potential of node N to V Low ), for example, a low level potential V is applied to the terminal Ti. Low The transistor MNa is turned off, and a high-level potential V is applied to the wiring RST. High Here, the potential applied to the wiring VAL3 is set to the low level potential V Low When the charge at the node N flows to the wiring VAL3, the potential of the node N becomes V Low .

[0218] <<Configuration Example 3 of Circuit BB>> Figure 9D The BSPR of the circuit shown in circuit BB is Figure 9A In a modified example of the circuit BSPR, the gate of the transistor MNa is not electrically connected to the wiring VAL2 but to the terminal Bi, and the first terminal of the transistor MNa is not electrically connected to the terminal Bi but to the wiring VAL2. Figure 9A The circuit BSPR is different from the circuit BB.

[0219] illustrate Figure 9D For example, suppose that a high-level potential V is input to the terminal Ti of the circuit BSPR. High In addition, a high-level potential V is applied to the first terminal of the transistor MNa from the wiring VAL2. High In addition, the potential of the node N is a low level potential V Low .

[0220] The gate-source voltage of the transistor MNa (at this time, the gate-second terminal voltage) becomes V High -V Low , so the transistor MNa becomes on. Therefore, a current flows from the wiring VAL2 through the transistor MNa in the node N, and charge accumulates until the transistor MNa becomes off, and the potential of the node N rises. Specifically, the gate-source voltage of the transistor MNa drops to V th_MNa When the transistor MNa is turned off, the potential of the node N (the potential of the second terminal of the transistor MNa) becomes VHigh -V th_MNa . V High -V th_MNa Equivalent to Figure 2A The V Mid .

[0221] In addition, when the potential of the node N (the potential of the second terminal of the transistor MNa) is to be lowered V High -V th_MNa When you want to release the charge accumulated in node N, you need to further change Figure 9D The BSPR circuit is the BB circuit.

[0222] Figure 9E The BSPR of the circuit shown in circuit BB is Figure 9D The circuit BSPR is a modified example of the circuit BB, which can release the charge accumulated in the node N. Figure 9D The circuit BSPR is different from the circuit BB.

[0223] exist Figure 9E In the circuit BSPR, the circuit BB includes a transistor MNd in addition to the transistor MNa.

[0224] A first terminal of the transistor MNd is electrically connected to the second terminal of the transistor MNa and the terminal Bo, a second terminal of the transistor MNd is electrically connected to the wiring VAL3 , and a gate of the transistor MNd is electrically connected to the wiring RST.

[0225] The transistor MNd, the wiring VAL3, and the wiring RST can be referred to as Figure 9C Description of the transistor MNd, wiring VAL3, and wiring RST in the circuit BSPR.

[0226] When you want to increase the potential of the node N (you want to set the potential of the node N to V High -V th_MNa When, for example, a low-level potential V is applied to the wiring RST Low The transistor MNd is turned off, and a high-level potential V is applied to the terminal Ti. High , then. In addition, when you want to lower the potential of node N (you want to set the potential of node N to V Low When, for example, a low level potential V is applied to the terminal Ti Low The transistor MNa is turned off, and a high-level potential V is applied to the wiring RST. High Here, the potential applied to the wiring VAL3 is set to the low level potential V Low When the charge at the node N flows to the wiring VAL3, the potential of the node N becomes V Low.

[0227] <<Configuration Example 4 of Circuit BB>> exist Figure 9F In the circuit BSPR shown, the circuit BB includes an inverter circuit. Specifically, the circuit BB includes a transistor MNe and a transistor MNf, and the transistors MNe and MNf constitute the inverter circuit.

[0228] As the transistor MNe and the transistor MNf, for example, transistors that can be used for the transistor MNb can be used.

[0229] A first terminal of transistor MNe is electrically connected to its gate and wiring VAL2 , a second terminal of transistor MNe is electrically connected to terminal Bo and a first terminal of transistor MNf, a second terminal of transistor MNf is electrically connected to wiring VAL3 , and a gate of transistor MNf is electrically connected to terminal Bi.

[0230] For wiring VAL2, please refer to Figure 9A The wiring VAL2 in the circuit BSPR is described below. Figure 9C Description of the wiring VAL3 in the BSPR circuit.

[0231] Note that in Figure 9F In the example, the potential output from terminal To is denoted as V outb Instead of V out .

[0232] Here, it is explained Figure 9F For example, suppose that a high-level potential V is applied from wiring VAL2 to the first terminal and gate of transistor MNe. High In addition, it is assumed that a low-level potential V is applied to the second terminal of the transistor MNf from the wiring VAL3. Low In addition, the potential of the node N (the potential of the gate of the transistor MNb or the potential of the first terminal of the capacitor Ca) is a low-level potential V Low .

[0233] In addition, the transistor MNe and the transistor MNf are normally off transistors. In particular, the threshold voltage of the transistor MNe is V th_MNe , V th_MNe To meet V High -V Low >V th_MNe voltage.

[0234] First, consider that a low-level potential V is input to the terminal Ti. Low At this time, the gate of transistor MNf is input with V Low, so the transistor MNf becomes off. In addition, the gate-source voltage of the transistor MNe (at this time, the gate-second terminal voltage) becomes V High -V Low , so the transistor MNe turns on. As a result, a current flows from the wiring VAL2 through the transistor MNe in the node N, and charge accumulates. The potential of the node N rises until the transistor MNe turns off. Specifically, the gate-source voltage of the transistor MNe drops to V th_MNe When the transistor is turned off, the potential of the node N (the potential of the second terminal of the transistor MNe) becomes V High -V th_MNe . Note that V High -V th_MNe Equivalent to Figure 2A The V Mid .

[0235] Next, consider that a high-level potential V is input to the terminal Ti. High At this time, the gate of transistor MNf is input with V High , so the transistor MNf is turned on. In addition, since the transistor MNf is turned on, current flows from the node N through the transistor MNf to the wiring VAL3, and the charge is released. Ideally, the potential of the node N becomes the low-level potential V applied by the wiring VAL3. Low In fact, when the potential of the second terminal of the transistor MNe (the potential of the node N) decreases, the transistor MNe becomes on, so the potential of the node N becomes a low-level potential V Low Above and high level potential V High the following.

[0236] <Configuration Example 2 of Amplifier Circuit> Next, explain Figure 1A The circuit BSFB is an example of a different amplifier circuit structure.

[0237] Figure 10A The circuit BSFC shown is Figure 1A In a modified example of the circuit BSFB, the terminal Fo of the circuit FB is not electrically connected to the terminal TMi (terminal Bi of the circuit BB), but is electrically connected to the terminal Bo of the circuit BB, the gate of the transistor MNb, and the first terminal of the capacitor Ca. Figure 1A The circuit BSFB is different.

[0238] In addition, as Figure 10A The circuit FB of the circuit BSFC shown can be used, for example, as described above. Figure 3A 、 Figure 3B and Figures 4A to 7B The circuit FB is shown.

[0239] As an example, Figure 10B Show that Figure 3A The circuit BSFB1 and the circuit FB are used Figure 10A This is a configuration example of the circuit BSFC and the circuit FB.

[0240] Figure 10B The circuit BSFC1 includes Figure 3A The circuit FB is shown in the structure. Therefore, Figure 10B In circuit BSFC1, a first terminal of transistor MNFa is electrically connected to terminal Bo of circuit BB, a gate of transistor MNb, and a first terminal of capacitor Ca.

[0241] Next, explain Figure 10B A working example of the circuit BSFC1.

[0242] Regarding the operation of the circuit BSPR, please refer to Figure 2A Example of operation of circuit BSPR. For example, a high-level potential V is input to terminal TMi of circuit BSFC1. High When (ie, V in =V High When , circuit BB outputs potential V to terminal Bo Mid As a result, V is applied to the gate of the transistor MNb (the first terminal of the capacitor Ca). Mid In addition, it is assumed that a low-level potential V is applied from the wiring VAL1 to the first terminal of the transistor MNb. Low In addition, it is assumed that a high-level potential V is applied from the wiring VAL41 to the second terminal of the transistor MNFa. High .

[0243] At this time, the gate-source voltage of the transistor MNb (at this time, the gate-first terminal voltage) becomes V Mid -V Low , so the transistor MNb is turned on. Therefore, the wiring VAL1 outputs the low-level potential V to the terminal To of the circuit BSPR through the transistor MNb. Low In other words, becoming V out =V Low .

[0244] At this time, the terminal Fi of the circuit FB is input with the same potential as the terminal To. Low As a result, a low-level potential V is applied to the gate of the transistor MNFa. Low .

[0245] In addition, the transistor MNFa is a normally closed transistor, and the threshold voltage of the transistor MNFa is denoted as V th_MNFa In addition, the threshold voltage Vth_MNFa To meet V High -V Low >V th_MNFa voltage.

[0246] Here, the gate-source voltage of the transistor MNFa (here, the gate-first terminal voltage) is V Low -V Mid <V th_MNFa , so the transistor MNFa becomes off.

[0247] Next, it is assumed that the potential applied from the wiring VAL1 to the first terminal of the transistor MNb is changed from the low-level potential V Low becomes a high level potential V High In addition, it is assumed that the node N is made to float using the circuit BB. At this time, the gate-source voltage of the transistor MNb (at this time, the gate-second terminal voltage) becomes V Mid -V Low , so the transistor MNb is turned on. Therefore, current flows from the wiring VAL1 through the transistor MNb to the terminal To of the circuit BSPR, and the potential of the terminal To increases from V Low Note that the node N is in a floating state, so through the capacitive coupling of the capacitor Ca, the potential of the node N also increases from V Mid As a result, the gate-source voltage of the transistor MNb is maintained by the capacitor Ca, and the potential of the terminal To is increased to V High In addition, ideally, the potential of the node N is V Mid +V High -V Low .

[0248] At this time, the terminal Fi of the circuit FB is input with the same potential as the terminal To. High As a result, a high-level potential V is applied to the gate of the transistor MNFa. High .

[0249] Here, the gate-source voltage of the transistor MNFa (here, the gate-second terminal voltage) is, for example, V High -V High = 0. Since the transistor MNFa is a normally-off transistor, the transistor MNFa is in an off state.

[0250] In this state, when the potential of the terminal Bo of the circuit BB (the first terminal of the transistor MNFa) changes from V Mid +V High -V LowWhen the voltage between the gate and the first terminal of the transistor MNFa decreases and becomes higher than the threshold voltage, the transistor MNFa turns on. At this time, the charge from the wiring VAL41 accumulates in the node N, and the potential of the terminal Ti of the circuit BSPR rises. Specifically, the gate-source voltage of the transistor MNFa becomes V th_MNFa When the transistor MNFa is turned off, the potential of the node N (the potential of the first terminal of the transistor MNFa) becomes V High -V th_MNFa .

[0251] As described above, in the circuit BSFC1, when the high-level potential V is output from the terminal TMo, High When the potential of the terminal Bo of the circuit BB drops, the circuit FB can apply a potential V to the terminal Bo (node ​​N). High -V th_MNFa Then, the circuit BSPR is bootstrapped again, and a high-level potential V is output from the terminal To of the circuit BSPR. High Through the above-described operation, the potential output from the terminal To of the circuit BSPR becomes stable.

[0252] As another example, Figure 10C Show that Figure 4D The circuit BSFB5 and the circuit FB are used Figure 10A This is a configuration example of the circuit BSFC and the circuit FB.

[0253] Figure 10C The circuit BSFC2 includes Figure 4D The circuit FB is shown in the structure. Therefore, Figure 10C In circuit BSFC2, a first terminal of transistor MNFa is electrically connected to terminal Bo of circuit BB, a gate of transistor MNb, and a first terminal of capacitor Ca. Furthermore, a second terminal and a gate of transistor MNFa are electrically connected to terminal To of circuit BSPR and terminal TMo of circuit BSFC2.

[0254] exist Figure 10C In the circuit BSFC2, a high-level potential V is input to the gate of the transistor MNFa. High When (the high level potential V is output from the terminal To of the circuit BSPR High When the potential of the first terminal of the transistor MNFa becomes V High -V th_MNFa When the voltage of the transistor MNFa is below 1, the transistor MNFa turns on. At this time, the current output from the terminal To flows through the source-drain of the transistor MNFa to the terminal Bo (node ​​N). In addition, the potential of the first terminal of the transistor MNFa rises to V High -V th_MNFaIn addition, when the potential of the first terminal of the transistor MNFa reaches V High -V th_MNFa Then, the transistor MNFa becomes off. Then, the circuit BSPR is bootstrapped again, and a high-level potential V is output from the terminal To of the circuit BSPR. High Through the above-described operation, the potential output from the terminal To of the circuit BSPR becomes stable.

[0255] As mentioned above, by using Figure 10A Circuit BSFC, Figure 10B The circuit BSFC1 or Figure 10C Circuit BSFC2 can feed back the potential output from terminal To of circuit BSPR to apply a fixed potential to terminal Bo (node ​​N) of circuit BB. As a result, the potential output from terminal To of circuit BSPR can be stabilized.

[0256] <Layout Example of Amplifier Circuit> Next, an example of a layout diagram (schematic plan view) of the above-mentioned amplifier circuit will be described.

[0257] Figure 11 yes Figure 3C The layout diagram of the circuit BSFB1B is shown. In particular, Figure 3C The circuit BSFB1B includes the circuit BB using Figure 9A The circuit shown is BB. Note that although Figure 11 The back gate of each of the transistors MNFa, MNa, MNb, and MNg is not shown in the layout diagram of FIG. Figure 11 The back gate is set in the layout diagram.

[0258] In addition, Figure 11 In FIG. 1 , the circuit BSFB1B includes a conductor GEM, a conductor SDM, a semiconductor SMC, and a conductor PLG. Note that Figure 11 The insulator included in the circuit BSFB1B is not shown.

[0259] As an example, the semiconductor SMC is located below the conductive body GEM. In addition, as an example, the conductive body GEM is located below the conductive body SDM. That is, Figure 11 In the circuit BSFB1B, a semiconductor SMC, a conductor GEM, and a conductor SDM are formed in this order from the bottom.

[0260] As an example, a portion of the electrical conductor GEM is used as a gate (sometimes referred to as a first gate) of each of the transistors MNFa, MNa, MNb, and MNg.

[0261] The semiconductor SMC, the conductive GEM, and the conductive SDM can all be formed using, for example, photolithography. Specifically, when forming the conductive GEM, the conductive material that will become the conductive GEM is formed using one or more methods selected from sputtering, CVD (Chemical Vapor Deposition), PLD (Pulsed Laser Deposition), and ALD (Atomic Layer Deposition). The desired pattern is then formed using photolithography. Furthermore, the semiconductor SMC and the conductive SDM can also be formed using the same methods described above.

[0262] Furthermore, an insulator may be provided between the semiconductor SMC and the conductive body GEM. In particular, the insulator provided between the semiconductor SMC and the conductive body GEM is sometimes used as a gate insulating film (sometimes referred to as a first gate insulating film or a front gate insulating film). Furthermore, an insulator may be provided between the conductive body GEM and the conductive body SDM.

[0263] Furthermore, a conductive PLG serving as a wiring or plug is provided between the semiconductor SMC and the conductive body SDM. Similarly, a conductive PLG serving as a wiring or plug is provided between the conductive body GEM and the conductive body SDM. For example, the conductive PLG can be formed by forming an opening in the aforementioned insulator and filling the opening with a conductive material to serve as the conductive PLG. After the conductive PLG is formed, a planarization process such as chemical mechanical polishing can be used to uniformize the surface heights of the conductive PLG and the adjacent insulator films.

[0264] As an example, Figure 11 Each of the transistors MNFa, MNa, MNb, and MNg shown includes a portion of a semiconductor SMC, a conductor GEM, an insulator, and a conductor PLG.

[0265] in addition, Figure 11 The illustrated capacitor Ca includes portions of the conductor SDM and the conductor GEM. Specifically, the capacitor Ca includes a region where portions of the conductor SDM and the conductor GEM overlap. In other words, in the capacitor Ca, a portion of the conductor SDM serves as one of a pair of electrodes, and a portion of the conductor GEM serves as the other of the pair of electrodes. Note that an insulator with a high dielectric constant is preferably provided between the conductor SDM and the conductor GEM in the capacitor Ca.

[0266] Note that the layout diagram of the display device according to one embodiment of the present invention is not limited to Figure 11The layout diagram of the display device according to one embodiment of the present invention may be appropriately changed. Figure 11 The resulting layout diagram.

[0267] <Application Example for Display Device> Next, a driving circuit including the above-described amplifier circuit and a display device including the driving circuit will be described.

[0268] First, the display device will be described. Figure 12 An example of a structure of a display device having a driving circuit including the above-mentioned amplifier circuit is shown. For example, Figure 12 The display device DSP shown includes a driving circuit GD, a driving circuit SD and a pixel array PA.

[0269] Notice, Figure 12 The abstract shows the driving circuit GD, the driving circuit SD, the pixel array PA, the wiring GL[1], the wiring GL[m], the wiring SL[1], the wiring SL[n], the pixel circuit PX[1,1], the pixel circuit PX[m,1], the pixel circuit PX[1,n] and the pixel circuit PX[m,n] (m is an integer greater than 1, and n is an integer greater than 1).

[0270] For example, the pixel array PA includes a plurality of pixel circuits PX. The pixel circuits PX are arranged in a matrix of m rows and n columns in the pixel array PA.

[0271] Figure 12 The symbols of the pixel circuits PX shown in the figure represent the addresses of the pixel circuits. For example, the symbol of pixel circuit PX[1,1] represents the pixel circuit PX configured at the position of row 1 and column 1 in the pixel array PA. Also, for example, the symbol of pixel circuit PX[m,1] represents the pixel circuit PX configured at the position of row m and column 1 in the pixel array PA. Also, for example, the symbol of pixel circuit PX[1,n] represents the pixel circuit PX configured at the position of row 1 and column n in the pixel array PA. Also, for example, the symbol of pixel circuit PX[m,n] represents the pixel circuit PX configured at the position of row m and column n in the pixel array PA.

[0272] Furthermore, a pixel circuit PX arranged in row i and column j (i is an integer from 1 to m, and j is an integer from 1 to n) in the pixel array PA is referred to as a pixel circuit PX[i, j] (not shown). Pixel circuit PX[i, j] is electrically connected to, for example, wiring GL[i] (not shown). Furthermore, pixel circuit PX[i, j] is electrically connected to, for example, wiring SL[j] (not shown).

[0273] For example, the drive circuit GD is electrically connected to the wiring GL[1] to the wiring GL[m]. In addition, for example, the drive circuit SD is electrically connected to the wiring SL[1] to the wiring SL[n].

[0274] For example, wiring GL[1] to wiring GL[m] can all be wiring extending in the row direction in the pixel array PA. Furthermore, the "x" appended to a wiring GL indicates the row number to which the wiring extends. For example, the symbol for wiring GL[1] indicates a wiring extending in the first row in the pixel array PA. Furthermore, for example, the symbol for wiring GL[m] indicates a wiring extending in the mth row in the pixel array PA.

[0275] For example, wiring SL[1] to wiring SL[n] may be wiring extending in the column direction in the pixel array PA. Furthermore, the "y" appended to a wiring SL indicates the column number to which the wiring extends. For example, the symbol for wiring SL[1] indicates a wiring extending in the first column in the pixel array PA. Furthermore, for example, the symbol for wiring SL[n] indicates a wiring extending in the nth column in the pixel array PA.

[0276] The pixel circuit PX may be, for example, a pixel circuit using one or more of a liquid crystal display device, a light-emitting device including an organic EL material, a light-emitting device including an inorganic EL material, and a light-emitting diode (for example, a micro-LED (Light Emitting Diode)). Note that in this embodiment, a case where a light-emitting device including an organic EL material is used in the pixel circuit PX of the pixel array PA is described. In particular, as the brightness of light emitted from a light-emitting device that can emit light at high brightness, for example, 500 cd / m 2 Above, preferably 1000 cd / m 2 Above and 10000cd / m 2 Below, more preferably 2000 cd / m 2 Above and 5000cd / m 2 the following.

[0277] For example, in the pixel array PA of the display device DSP, the driver circuit GD has a function of selecting the pixel circuit PX to which image data is to be transmitted. Therefore, the driver circuit GD can be called a gate driver circuit or the like.

[0278] Thus, the wiring GL electrically connecting the drive circuit GD and the pixel circuit PX is used as, for example, a wiring for transmitting a selection signal. The wiring GL may be used as, for example, a wiring for supplying a fixed potential instead of being used as a wiring for transmitting a selection signal.

[0279] The drive circuit SD has a function of transmitting image data to the pixel circuits PX in the pixel array PA of the display device DSP, for example. Therefore, the drive circuit SD can be called a source driver circuit or the like.

[0280] Thus, the wiring SL electrically connecting the drive circuit SD and the pixel circuit PX is used as, for example, a wiring for transmitting image data as a signal. The wiring SL may also be used as a wiring for supplying a fixed potential instead of being used as a wiring for transmitting image data.

[0281] In addition, Figure 12 In the display device DSP shown, wiring other than the wiring GL[1] to the wiring GL[m] and the wiring SL[1] to the wiring SL[n] may be extended. For example, in the display device DSP, wiring for applying a fixed potential to the pixel circuit PX may be extended.

[0282] <<Configuration Example of Drive Circuit GD>> Figure 13A Shown to be applicable to Figure 12 FIG. 1 is a configuration example of a drive circuit GD according to one embodiment of the present invention for a display device DSP. Figure 13A The driving circuit GD shown includes, for example, circuits 100 [ 1 ] to 100 [ m ].

[0283] For example, circuits 100 [ 1 ] to 100 [ m ] all include a terminal IT, a terminal OT, a terminal CLK1 , a terminal CLK2 , a terminal PWC, and a terminal GT.

[0284] For example, in each of the circuits 100 [ 1 ] to 100 [ m ], the terminal CLK1 is electrically connected to the wiring CL1 , the terminal CLK2 is electrically connected to the wiring CL2 , and the terminal PWC is electrically connected to the wiring PL.

[0285] Each of wiring CL1, wiring CL2, and wiring PL is used, for example, as a wiring for applying a variable potential (sometimes referred to as a pulse voltage in this specification) such as a clock signal. However, one or more selected from wiring CL1, wiring CL2, and wiring PL may be a wiring for applying a fixed potential instead of a variable potential.

[0286] For example, the terminal OT of the circuit 100 [k] (k is an integer greater than or equal to 1 and less than or equal to m−1) is electrically connected to the terminal IT of the circuit 100 [k+1].

[0287] The terminal GT of the circuit 100[i] is electrically connected to, for example, the wiring GL[i].

[0288] Each of the circuits 100 [ 1 ] to 100 [ m ] has, for example, the following functions: a function of holding information input to the terminal IT; and a function of outputting the held information to one or both of the terminal OT and the terminal GT.

[0289] For example, circuit 100[i] has a function of outputting information held in circuit 100[i] to terminal OT when a high-level potential is input to terminal CLK1. Furthermore, for example, circuit 100[i] has a function of outputting information held in circuit 100[i] to terminal GT when a high-level potential is input to terminal PWC. Furthermore, for example, circuit 100[i] has a function of resetting information held in circuit 100[i] when a high-level potential is input to terminal CLK2. Furthermore, circuit 100[i] preferably has a configuration in which new information is input to terminal IT of circuit 100[i] after resetting the information held in circuit 100[i], thereby causing circuit 100[i] to hold new information.

[0290] As described above, in circuits 100[1] to 100[m], by inputting information to terminal IT of circuit 100[1] and then inputting variable potentials to terminals CLK1 and CLK2 at appropriate timing, the information can be sequentially transmitted to circuits from circuit 100[2] onward. Furthermore, by inputting information to terminal IT of circuit 100[1] and then inputting variable potentials to terminal PWC at appropriate timing, the information held by each of circuits 100[1] to 100[m] can be output from terminal GT of each of circuits 100[1] to 100[m]. Therefore, in this specification and other documents, the structures of circuits 100[1] to 100[m] can be referred to as shift registers.

[0291] In addition, the above information may be, for example, a selection signal for selecting a pixel circuit PX to write image data in the pixel array PA. Figure 13A In the example, the selection signal is recorded as signal SS.

[0292] exist Figure 13A In the driving circuit GD shown, the terminal OT is shown in the circuit 100 [m], but the circuits 100 [1] to 100 [m] adopt a shift register structure, so the circuit 100 [m] may not be provided with the terminal OT.

[0293] In addition, it can be applied to Figure 12 The structure of the driving circuit GD of the display device DSP is not limited to Figure 13A For example, as can be applied to Figure 12 The structure of the driving circuit GD of the display device DSP can also be adopted Figure 13B The driving circuit GD shown. Figure 13B The driving circuit GD includes circuits BF[1] to BF[m], which is the same as Figure 13A The driving circuit GD is different.

[0294] exist Figure 13BIn the driving circuit GD, the input terminal of each circuit BF[1] to circuit BF[m] is electrically connected one-to-one to the terminal GT of each circuit 100[1] to circuit 100[m], and the output terminal of each circuit BF[1] to circuit BF[m] is electrically connected one-to-one to each wiring GL[1] to wiring GL[m].

[0295] Each of circuits BF[1] to BF[m] can be configured to include, for example, an amplifier circuit such as a buffer circuit, an inverter circuit, or a latch circuit. Specifically, each of circuits BF[1] to BF[m] can have a function of outputting a potential obtained by amplifying the potential of terminal GT to wiring GL with reference to the potential of terminal GT.

[0296] In addition, Figure 13A and Figure 13B In the driving circuit GD shown, wirings other than the wirings CL1, CL2, and PL may be extended. For example, wirings for applying a fixed potential for driving each of the circuits 100[1] to 100[m] may be extended.

[0297] Figure 14 The circuit 100A is applicable to Figure 13A and Figure 13B The circuits of each of the circuits 100 [ 1 ] to 100 [ m ] in the driving circuit GD are shown.

[0298] For example, circuit 100A includes circuit BSPRc, circuit BSPRd, circuit FBc, transistors MN1, MN4, MN5, MN8, MN12, MN16, and capacitor C5. Also, for example, circuit 100A includes terminal IT, terminal PWC, terminal CLK1, terminal CLK2, terminal GT, and terminal OT.

[0299] In addition, Figure 14 In the circuit 100A, both the circuit BSPRc and the circuit BSPRd adopt Figure 2A Circuit BSPRc includes transistor MN11, capacitor C3, and circuit BBc, and circuit BSPRd includes transistor MN15, capacitor C4, and circuit BBd.

[0300] Note that regarding the transistor MN11 and the transistor MN15, reference can be made to Figure 2A The description of transistor MNb in circuit BSPR is as follows. In addition, for capacitors C3 and C4, please refer to Figure 2A For details about the capacitor Ca in the circuit BSPR, refer to Figure 2ACircuit BSPR is an illustration of circuit BB.

[0301] The first gate of transistor MN1 is electrically connected to the first gate of transistor MN8 and terminal IT, and the first terminal of transistor MN1 is electrically connected to wiring VDE1. In addition, the second terminal of transistor MN1 is electrically connected to the first terminal of transistor MN4, terminal Bi of circuit BBc, terminal Fo of circuit FBc, and terminal Bi of circuit BBd.

[0302] The first gate of transistor MN5 is electrically connected to terminal CLK2, and the first terminal of transistor MN5 is electrically connected to wiring VDE2. In addition, the second terminal of transistor MN5 is electrically connected to the first gate of transistor MN4, the first terminal of capacitor C5, the first terminal of transistor MN8, the first gate of transistor MN12, and the first gate of transistor MN16.

[0303] The first gate of transistor MN11 is electrically connected to terminal Bo of circuit BBc and the first terminal of capacitor C3. The first terminal of transistor MN11 is electrically connected to terminal CLK1. The second terminal of transistor MN11 is electrically connected to the second terminal of capacitor C3, the first terminal of transistor MN12, terminal OT, and terminal Fi of circuit FBc.

[0304] The first gate of transistor MN15 is electrically connected to terminal Bo of circuit BBd and the first terminal of capacitor C4, and the first terminal of transistor MN15 is electrically connected to terminal PWC. The second terminal of transistor MN15 is electrically connected to the second terminal of capacitor C4, the first terminal of transistor MN16, and terminal GT.

[0305] The second terminal of transistor MN4 is electrically connected to wiring VSE1. Furthermore, the second terminal of capacitor C5 is electrically connected to wiring VSE2. Furthermore, the second terminal of transistor MN8 is electrically connected to wiring VSE3. Furthermore, the second terminal of transistor MN12 is electrically connected to wiring VSE4. Furthermore, the second terminal of transistor MN16 is electrically connected to wiring VSE5.

[0306] Note that in Figure 14 In FIG, the electrical connection point of the second terminal of the transistor MN1, the first terminal of the transistor MN4, the terminal Bi of the circuit BBc, the terminal Bi of the circuit BBd, and the terminal Fo of the circuit FBc is referred to as a node N1. Figure 14 In FIG, an electrical connection point of the second terminal of the transistor MN5, the first gate of the transistor MN4, the first terminal of the transistor MN8, the first gate of the transistor MN12, the first gate of the transistor MN16, and the first terminal of the capacitor C5 is referred to as a node N2.

[0307] As mentioned above, both circuit BSPRc and circuit BSPRd are equivalent to Figure 2A The BSPR of the circuit shown. In addition, Figure 14 The combination of circuit BSPRc and circuit FBc is equivalent to Figure 1A The circuit BSFB is shown.

[0308] Wiring VDE1 and wiring VDE2 are both used, for example, as wirings to which a fixed potential is applied. This fixed potential can be, for example, a high-level potential. Wiring VDE1 and wiring VDE2 can have equal or unequal fixed potentials applied. Furthermore, for example, when wiring VDE1 and wiring VDE2 have equal fixed potentials applied, wiring VDE1 and wiring VDE2 can be the same wiring.

[0309] Alternatively, one or both of the wiring VDE1 and the wiring VDE2 may be a wiring to which a variable potential is applied instead of a fixed potential.

[0310] For example, each of the wirings VSE1 to VSE5 is used as a wiring for applying a fixed potential. This fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential. The wirings VSE1 to VSE5 can apply equal or unequal fixed potentials. Furthermore, two or more wirings within the wirings VSE1 to VSE5 can apply equal fixed potentials, while the remaining wirings can apply potentials different from the fixed potential. Furthermore, two or more wirings within the wirings VSE1 to VSE5 that apply equal fixed potentials can be the same wiring. For example, when the wirings VSE1 and VSE2 apply equal fixed potentials, the wirings VSE1 and VSE2 can be the same wiring.

[0311] In addition, one or more selected from the wirings VSE1 to VSE5 may be wirings to which a variable potential is applied instead of a fixed potential.

[0312] As mentioned above Figure 14 By using a circuit that connects circuit BSPRc and circuit FBc in parallel, as in circuit 100A shown, the potential of the output terminal of circuit BSPRc (equivalent to the potential of the second terminal of transistor MN11 or the potential of the second terminal of capacitor C3) can be stabilized. That is, in circuit 100A, the potential of terminal OT can be stabilized.

[0313] <<Operation Example of Circuit 100A>> Figure 15 is a timing chart showing an example of the operation of the circuit 100A. For example, Figure 15The timing chart shown in FIG. 1 shows the potential changes of each of the terminal IT, the terminal PWC, the terminal CLK1, the terminal CLK2, the node N1, the node N2, the terminal GT, and the terminal OT. Figure 15 In, V High Indicates high level potential, V Low Indicates a low level potential.

[0314] Note that for simplicity of explanation of the operation of circuit 100A, Figure 15 The length of the signal input period, the length of the output period, etc. shown in the timing diagram may differ from the actual circuit operation.

[0315] In this working example, the fixed potentials applied to the wiring VDE1 and the wiring VDE2 are equal to each other in high-level potential V High In addition, the fixed potentials applied to the wirings VSE1 to VSE5 are the same low-level potentials V Low .

[0316] Note that the high level potential V High and low level potential V Low The potential is preferably a high level potential V High and low level potential V Low The difference is higher than Figure 14 The threshold voltage potential of each transistor is shown.

[0317] [Time T1 to Time T2] During the period from time T1 to time T2, a low-level potential V is applied to the terminal IT. Low , a low level potential V is applied to the terminal PWC Low , terminal CLK1 is applied with V Low , a low level potential V is applied to the terminal CLK2 Low In addition, the node N2 maintains a low level potential V LOW .

[0318] A low-level potential V is applied to the terminal CLK2. Low When the first gate potential of the transistor MN5 becomes a low level potential V Low In addition, it is assumed that the threshold voltage of the transistor MN5 is within an appropriate range. Therefore, the transistor MN5 is turned off.

[0319] The potential of the first gate of the transistor MN4 (the potential of the node N2) is the high level potential V High The low-level potential V is applied to the second terminal of the transistor MN4 from the wiring VSE1. Low, so the transistor MN4 is turned on. Therefore, the node N1 and the wiring VSE1 are turned on, and the potential of the node N1 becomes a low-level potential V Low .

[0320] In addition, a low-level potential V is applied to the terminal IT. Low When the first gate potential of the transistor MN1 becomes a low level potential V Low In addition, it is assumed that the threshold voltage of the transistor MN1 is within an appropriate range. Therefore, the transistor MN1 is turned off.

[0321] The potential of the first gate of the transistor MN12 (the potential of the node N2) is the low level potential V Low The low-level potential V is applied to the second terminal of the transistor MN12 from the wiring VSE4. Low , so the transistor MN12 becomes off.

[0322] The potential of the first gate of the transistor MN16 (the potential of the node N2) is the low level potential V Low The low-level potential V is applied to the second terminal of the transistor MN16 from the wiring VSE5. Low , so the transistor MN16 becomes off.

[0323] The potential of the first gate of the transistor MN8 (the potential of the terminal IT) is a low-level potential V Low The second terminal of the transistor MN8 is applied with the low-level potential V from the wiring VSE3. Low , so the transistor MN8 becomes off.

[0324] Note that in Figure 15 During the period from time T1 to time T2 of the timing chart, the potentials of the terminals OT and GT are each at a low level potential V Low During the period from time T1 to time T2, the potentials of the terminal OT and the terminal GT may be at the high level potential V High .

[0325] [Time T2 to Time T3] During the period from time T2 to time T3, a high-level potential V is applied to the terminal CLK2. High .

[0326] A high-level potential V is applied to the terminal CLK2. High When the gate potential of transistor MN5 becomes a high level potential V High .

[0327] Here, the transistor MN5 is a normally-off transistor, and the threshold voltage of the transistor MN5 is V th_MN5In addition, the threshold voltage V th_MN5 To meet V High -V Low >V th_MN5 voltage.

[0328] When the potential of the second terminal of the transistor MN5 (the potential of the node N2) is at the low level potential V Low When the transistor MN5 is turned on, the charge from the wiring VDE2 is accumulated in the second terminal (node ​​N2) of the transistor MN5. High -V th_MN5 When the charge is accumulated in the node N2, the transistor MN5 is turned off. As a result, the node N2 maintains the potential V High -V th_MN5 .

[0329] Note that when the potential of the second terminal of the transistor MN5 (the potential of the node N2) is higher than the high-level potential V High When the first terminal of the transistor MN5 is used as a source, the charge is discharged from the node N2 to the wiring VDE1. In addition, the potential of the second terminal of the transistor MN5 (the potential of the node N2) becomes V High -V th_MN5 When , the transistor MN5 becomes off. Thus, as described above, the node N2 maintains the potential V High -V th_MN5 .

[0330] In addition, during the period from time T2 to time T3, the terminal CLK2 is applied with the high-level potential V High Then a low level potential V is applied Low Therefore, it is assumed that the first gate potential of the transistor MN5 becomes the low level potential V Low .

[0331] Through the above operation, a high-level potential V is applied to the terminal CLK2 in the circuit 100A. High The potential of the node N2 can be refreshed to a high level potential V High .

[0332] In addition, since the potential of node N2 is V High -V th_MN5 , so the potential of the first gate of the transistor MN12 (the potential of the node N2) becomes V High -V th_MN5 , and the second terminal of the transistor MN12 is applied with the low-level potential V from the wiring VSE4. Low, whereby the transistor MN12 is turned on. Therefore, the terminal OT and the wiring VSE4 are turned on, and the potential of the terminal OT becomes a low-level potential V Low .

[0333] In addition, since the potential of node N2 is V High -V th_MN5 , so the potential of the first gate of the transistor MN16 (the potential of the node N2) becomes V High -V th_MN5 , and the second terminal of the transistor MN16 is applied with the low-level potential V from the wiring VSE5. Low , whereby the transistor MN16 is turned on. Therefore, the terminal GT and the wiring VSE5 are turned on, and the potential of the terminal GT becomes a low-level potential V Low .

[0334] [Time T3 to Time T4] During the period from time T3 to time T4, a low-level potential V is applied to the terminal IT. Low , a low level potential V is applied to the terminal PWC Low , terminal CLK1 is applied with V Low , a low level potential V is applied to the terminal CLK2 Low The potentials input to the terminal IT, the terminal PWC, the terminal CLK1, and the terminal CLK2 during the period from time T3 to time T4 are respectively equal to the potentials input to the terminal IT, the terminal PWC, the terminal CLK1, and the terminal CLK2 during the period from time T1 to time T2. Therefore, the operation example of the circuit 100A during the period from time T3 to time T4 can refer to the description of the operation example during the period from time T1 to time T2.

[0335] [Time T4 to Time T5] During the period from time T4 to time T5, a high-level potential V is applied to the terminal IT. High .

[0336] A high-level potential V is applied to the first gate of the transistor MN8 from the terminal IT. High The second terminal of the transistor MN8 is applied with V from the wiring VSE3. Low , so the transistor MN8 becomes on. As a result, the node N2 and the wiring VSE3 become conductive, so the potential of the node N2 changes from the high level potential V High becomes a low level potential V Low .

[0337] As a result, the potential of the first gate of the transistor MN4 (the potential of the node N2) is at a low level potential V LowThe low-level potential V is applied to the second terminal of the transistor MN4 from the wiring VSE1. Low , so the transistor MN4 becomes off.

[0338] In addition, the potential of the first gate of the transistor MN12 (the potential of the node N2) is the low-level potential V Low The low-level potential V is applied to the second terminal of the transistor MN12 from the wiring VSE4. Low , so the transistor MN12 becomes off.

[0339] In addition, the potential of the first gate of the transistor MN16 (the potential of the node N2) is the low-level potential V Low The low-level potential V is applied to the second terminal of the transistor MN16 from the wiring VSE5. Low , so the transistor MN16 becomes off.

[0340] In addition, a high-level potential V is applied through the terminal IT. High , the potential of the gate of transistor MN1 becomes a high level potential V High In addition, since the potential of the second terminal of the transistor MN1 (the potential of the node N1) is the low level potential V Low , so the transistor MN1 is turned on. Therefore, the charge flowing from the wiring VDE1 is accumulated in the second terminal (node ​​N1) of the transistor MN1.

[0341] Here, transistor MN1 is a normally off transistor, and the threshold voltage of transistor MN1 is V th_MN1 In addition, the threshold voltage V th_MN1 To meet V High -V Low >V th_MN1 voltage.

[0342] Thus, until the gate-source voltage of the transistor MN1 (at this timing, the gate-second terminal voltage) reaches V High -V th_MN1 When the charge is stored in the node N1, the transistor MN1 is turned off. As a result, the node N1 maintains the potential V High -V th_MN1 .

[0343] In addition, during the period from time T4 to time T5, the terminal IT is applied with the high-level potential V High Then a low level potential V is applied Low As a result, the potential of the first gate of the transistor MN1 becomes a low-level potential V Low .

[0344] A low-level potential V is applied to the first gate of the transistor MN8 from the terminal IT. Low The second terminal of the transistor MN8 is applied with the low-level potential V from the wiring VSE3. Low , so the transistor MN8 becomes off. As a result, the node N2 maintains the low level potential V Low .

[0345] [Time T5 to Time T6] During the period from time T5 to time T6, a high-level potential V is applied to the terminal CLK1. High .

[0346] During the period from time T4 to time T5, the potential of the node N1 is at a high level potential V High -V th_MN1 At this time, according to Figure 2A In the BSPR circuit, a high potential V is applied to the terminal CLK1. High When the potential of the second terminal (terminal OT) of the transistor MN11 becomes a high-level potential V High .

[0347] Furthermore, the high-level potential V , which is the potential of the second terminal (terminal OT) of the transistor MN11, is applied to the terminal Fi of the circuit FBc. High In the circuit FBc is Figure 3A When the circuit FB of the circuit BSFB1 is connected to the circuit FBc, the circuit FBc outputs V to the terminal Fo. High -V th_MNFa That is, the potential of node N1 becomes V High -V th_MNFa .

[0348] Note that in Figure 15 In the timing diagram, V High -V th_MNFa Higher than V High -V th_MN1 , but V High -V th_MNF a can also be equal to V High -V th_MN1 or lower than V High -V th_MN1 .

[0349] [Time T6 to Time T7] During the period from time T6 to time T7, the high-level potential V is applied to the terminal PWC. High .

[0350] In addition, during the period from time T5 to time T6, the potential of the node N1 is V High -V th_MNFa At this time, according to Figure 2A In the BSPR circuit, a high potential V is applied to the terminal PWC. High When the potential of the second terminal (terminal GT) of the transistor MN15 also becomes the high level potential V High .

[0351] In addition, during the period from time T6 to time T7, the terminal PWC is applied with the high-level potential V High Then a low level potential V is applied Low As a result, the potential of the second terminal (terminal GT) of the transistor MN15 becomes the low-level potential V Low .

[0352] [Time T8 to Time T9] During the period from time T8 to time T9, a low-level potential V is applied to the terminal CLK1. Low .

[0353] As a result, the potential of the second terminal (terminal OT) of the transistor MN11 becomes the low-level potential V Low .

[0354] Furthermore, a low-level potential V , which is the potential of the second terminal (terminal OT) of the transistor MN11, is applied to the terminal Fi of the circuit FBc. Low In the circuit FBc is Figure 3A When the circuit FB of the circuit BSFB1 is turned off, the transistor MNFa of the circuit FBc is turned off. In addition, since the transistor MNFa is turned off, the node N1 is in a floating state. In addition, when there is no current leakage in the node N1, the potential of the node N1 remains at V High -V th_MNFa .

[0355] [Time T9 to Time T10] During the period from time T9 to time T10, a high-level potential V is applied to the terminal CLK2. High At this time, the operation of the circuit 100A during the period from time T9 to time T10 is the same as the operation during the period from time T2 to time T3.

[0356] For example, a high-level potential V is applied to the terminal CLK2. High When the potential of the second terminal of the transistor MN5 (the potential of the node N2) becomes a high level potential V High As a result, the transistors MN4, MN12, and MN16 are turned on, and the potentials of the node N1, the terminal OT, and the terminal GT all become V Low .

[0357] [After time T10] For example, after time T10, a low-level potential V is input to the terminal CLK2. Low The variable potential of node N1 is V Low And the potential of node N2 becomes V High -V th_MN5 , then do not input V to terminal IT High When V is applied to the terminal CLK1 or the terminal PWC High The following describes a specific working example.

[0358] [Time T11 to Time T12] During the period from time T11 to time T12, V is applied to the terminal CLK1. High .

[0359] The potential of the first gate of transistor MN11 is V Low The first terminal of the transistor MN11 is applied with V from the terminal CLK1. High , the potential of the second terminal of transistor MN11 is V Low At this time, the potential of the second terminal of the transistor MN11 is lower than the potential of the first terminal, so the second terminal of the transistor MN11 functions as a source and the transistor MN11 is turned off. As a result, the terminal CLK1 and the terminal OT are in a non-conductive state.

[0360] In addition, the potential of the first gate of the transistor MN12 is V High -V th_MN5 The second terminal of the transistor MN12 is supplied with V from the wiring VSE4. Low , so the transistor MN12 is turned on. Therefore, the terminal OT and the wiring VSE4 are turned on, and the potential of the terminal OT becomes V Low .

[0361] In addition, during the period from time T11 to time T12, the terminal CLK1 is applied with V High After that, V Low The potential of the first gate of transistor MN11 is V Low , the first terminal of the transistor MN11 is applied with V from the terminal CLK1 Low , the potential of the second terminal of the transistor MN11 becomes V Low , whereby the transistor MN11 is turned off when the threshold voltage of the transistor MN11 is within an appropriate range.

[0362] Furthermore, a low-level potential V , which is the potential of the second terminal (terminal OT) of the transistor MN11, is applied to the terminal Fi of the circuit FBc. LowIn the circuit FBc is Figure 3A When the circuit FB of the circuit BSFB1 is turned on, the transistor MNFa of the circuit FBc is turned off. Therefore, the potential of the node N1 does not change.

[0363] As described above, even when V is input to terminal CLK2 Low The variable potential of the node N1 becomes V Low And the potential of node N2 becomes V High -V th_MN5 After that, do not input V to terminal IT High And V is applied to terminal CLK1 High , the transistor MN11 also remains in the off state. In addition, even if V is applied to the terminal CLK1 thereafter Low , the transistor MN11 also remains in the off state.

[0364] [Time T12 to Time T13] During the period from time T12 to time T13, V is applied to the terminal PWC. High .

[0365] The potential of the first gate of transistor MN15 is V Low The first terminal of the transistor MN15 is applied with V from the terminal PWC. High , the potential of the second terminal of transistor MN15 is V Low At this time, the potential of the second terminal of the transistor MN15 is lower than the potential of the first terminal, so the second terminal of the transistor MN15 functions as a source and the transistor MN15 is turned off. As a result, the terminal PWC and the terminal GT are in a non-conductive state.

[0366] In addition, the potential of the first gate of the transistor MN16 is V High -V th_MN5 The second terminal of the transistor MN16 is applied with V from the wiring VSE5. Low , so the transistor MN16 is turned on. Therefore, the terminal GT and the wiring VSE5 are turned on, and the potential of the terminal GT becomes V Low .

[0367] In addition, during the period from time T12 to time T13, the terminal PWC is applied with V High After that, V Low The potential of the first gate of transistor MN15 is V Low , the first terminal of the transistor MN15 is applied with V from the terminal PWC Low , the potential of the second terminal of the transistor MN15 becomes V Low , whereby the transistor MN15 becomes off.

[0368] As described above, even when V is input to terminal CLK2 Low When the variable potential of node N1 is V Low And the potential of node N2 is set to V High -V th_MN5 After that, do not input V to terminal IT High Apply V to terminal PWC High , the transistor MN15 also remains in the off state. In addition, even if V is applied to the terminal PWC thereafter Low , transistor MN15 also remains in the off state.

[0369] <<Modification Example of Circuit 100A>> For example, the circuits 100[1] to 100[m] of the driving circuit GD may also adopt Figure 16 The circuit 100A1 is shown.

[0370] Circuit 100A1 is Figure 14 A modified example of the circuit 100A is shown in FIG. 1 , in which the circuit BSPRd is electrically connected in parallel with the circuit FBd. Note that the circuit FBd is a circuit that can be used for the circuit FBc.

[0371] Specifically, terminal Fo of circuit FBd is electrically connected to terminal Bi of circuit BBd, terminal Fo of circuit FBc, terminal Bi of circuit BBc, the second terminal of transistor MN1, and the first terminal of transistor MN4. Furthermore, terminal Fi of circuit FBd is electrically connected to the second terminal of transistor MN15, the first terminal of transistor MN16, the second terminal of capacitor C4, and terminal GT.

[0372] In addition, for example, the circuits 100[1] to 100[m] of the drive circuit GD may also adopt Figure 17 Circuit 100A2 is shown.

[0373] Circuit 100A2 is to Figure 9A The circuit BSPR of the circuit BSPR is used for the circuit BSPRc and the circuit BSPRd and Figure 3A The circuit FB is used as a structural example of the circuit FBc. Therefore, the circuit FBc includes the transistor MN9, the circuit BBc includes the transistor MN10, and the circuit BBd includes the transistor MN14.

[0374] The gate of transistor MN9 is electrically connected to terminal Fi of circuit FBc, the first terminal of transistor MN9 is electrically connected to wiring VDE11, and the second terminal of transistor MN9 is electrically connected to terminal Fo of circuit FBc. The gate of transistor MN10 is electrically connected to wiring VDE3, the first terminal of transistor MN10 is electrically connected to terminal Bi of circuit BBc, and the second terminal of transistor MN10 is electrically connected to terminal Bo of circuit BBc. The gate of transistor MN14 is electrically connected to wiring VDE4, the first terminal of transistor MN14 is electrically connected to terminal Bi of circuit BBd, and the second terminal of transistor MN14 is electrically connected to terminal Bo of circuit BBd.

[0375] The description of wiring VDE1 and wiring VDE2 can be referred to regarding wiring VDE11, wiring VDE3, and wiring VDE4. Furthermore, wirings VDE1 through VDE4 and wiring VDE11 may each be applied with an equal fixed potential, or with unequal fixed potentials. Furthermore, among wirings VDE1 through VDE4 and wiring VDE11, two or more wirings may be applied with an equal fixed potential, and the remaining wirings may be applied with a potential different from the fixed potential. Furthermore, among wirings VDE1 through VDE4 and wiring VDE11, two or more wirings to which an equal fixed potential is applied may be the same wiring.

[0376] In addition, for example, the circuits 100[1] to 100[m] of the drive circuit GD may also adopt Figure 18 Circuit 100A3 is shown.

[0377] Circuit 100A3 is Figure 17 In the modified example of the circuit 100A2, the connection destination of the second gate of each of the transistors MN1, MN4, MN5, MN8 to MN12, and MN14 to MN16 is clearly defined.

[0378] In each of transistors MN1, MN5, MN9 to MN11, MN14, and MN15, the first gate and the second gate are electrically connected. Furthermore, the second gate of transistor MN4 is electrically connected to wiring BG1. Furthermore, the second gate of transistor MN8 is electrically connected to wiring BG2. Furthermore, the second gate of each of transistors MN12 and MN16 is electrically connected to wiring BG3.

[0379] For example, each of wirings BG1 to BG3 is used as a wiring to which a fixed potential is applied. This fixed potential can be, for example, a low-level potential, a ground potential, or a negative potential. Each of wirings BG1 to BG3 can have an equal fixed potential applied, or can have unequal fixed potentials applied. Furthermore, when two or more selected from wirings BG1 to BG3 have an equal fixed potential applied, the selected two or more wirings can be the same wiring. Furthermore, one or more selected from wirings BG1 to BG3 can have a variable potential applied instead of a fixed potential.

[0380] When wirings BG1 to BG3 are different from one another, different fixed potentials can be applied to the second gates of transistors MN4, MN8, MN12, and MN16. In other words, the threshold voltages of transistors MN4, MN8, MN12, and MN16 can be independently controlled.

[0381] Therefore, for example, by applying a negative potential to the second gate of the transistor MN4 and applying a ground potential or a low-level potential (a potential higher than the negative potential) to the second gates of the transistors MN12 and MN16, the off-state currents of the transistors MN12 and MN16 can be made larger than the off-state current of the transistor MN4. Figure 13A or Figure 13B The drive circuit GD of circuits 100[1] to 100[m] all adopt Figure 18 The circuit 100A3 can further improve the driving speed of the driving circuit GD.

[0382] In addition, for example, the circuits 100[1] to 100[m] of the drive circuit GD may also adopt Figure 19 Circuit 100A4 is shown.

[0383] Circuit 100A4 is Figure 16 In a modified example of circuit 100A1, the first terminal of capacitor C3 of circuit BSPRc is electrically connected to terminal Fo of circuit FBc, and the first terminal of capacitor C4 of circuit BSPRd is electrically connected to terminal Fo of circuit FBd. Note that the combination of circuit BSPRc and circuit FBc and the combination of circuit BSPRd and circuit FBd are equivalent to Figure 10A The circuit shown is BSFC.

[0384] <<Configuration Example of Drive Circuit SD>> Next, a configuration example of the drive circuit SD will be described.

[0385] Figure 20 Shown to be applicable to Figure 12 An example of a structure of a drive circuit SD of a display device DSP according to one embodiment of the present invention is shown. For example, Figure 20 The driving circuit SD shown includes a circuit SR, a circuit LAT, and a circuit DAC. In particular, the circuit SR includes, for example, circuits 200[1] to 200[n+2]. In addition, the circuit 200[n+1] is a circuit for transmitting data from the terminal SRT of the circuit 200[n+1] to the terminal RT of the circuit 200[n-1], and the circuit 200[n+2] is a circuit for transmitting data from the terminal SRT of the circuit 200[n+2] to the terminal RT of the circuit 200[n]. In addition, Figure 20 In FIG, circuits 200[1] to 200[6] are summarized.

[0386] For example, circuits 200 [ 1 ] to 200 [ n ] all include a terminal IT, a terminal OT, a terminal CLK1 , a terminal CLK2 , a terminal CLK3 , a terminal SRT, a terminal PWC, and a terminal RT.

[0387] Furthermore, in circuit SR, the wiring CLKLA to the wiring CLKLD and the wiring PWCLA to the wiring PWCLD are extended.

[0388] In circuit 200[4k-3] (where k is an integer greater than or equal to 1 and satisfies 1≤4k-3≤n), terminal CLK1 is electrically connected to wiring CLKLA, terminal CLK2 is electrically connected to wiring CLKLB, terminal CLK3 is electrically connected to wiring CLKLC, and terminal PWC is electrically connected to wiring PWCLA. Furthermore, in circuit 200[4k-2] (where k is an integer greater than or equal to 1 and satisfies 2≤4k-2≤n), terminal CLK1 is electrically connected to wiring CLKLB, terminal CLK2 is electrically connected to wiring CLKLC, terminal CLK3 is electrically connected to wiring CLKLD, and terminal PWC is electrically connected to wiring PWCLB. Furthermore, in circuit 200[4k-1] (where k is an integer greater than or equal to 1 and satisfies 3≤4k-1≤n), terminal CLK1 is electrically connected to wiring CLKLC, terminal CLK2 is electrically connected to wiring CLKLD, terminal CLK3 is electrically connected to wiring CLKLA, and terminal PWC is electrically connected to wiring PWCLC. In circuit 200 [4k] (where k is an integer greater than or equal to 1 satisfying 4≤4k≤n), terminal CLK1 is electrically connected to wiring CLKLD, terminal CLK2 is electrically connected to wiring CLKLA, terminal CLK3 is electrically connected to wiring CLKLB, and terminal PWC is electrically connected to wiring PWCLD.

[0389] The terminal SRT of the circuit 200[j] (where j is an integer from 1 to n) is electrically connected to the terminal IT of the circuit 200[j+1]. In addition, the terminal RT of the circuit 200[j] is electrically connected to the terminal SRT of the circuit 200[j+2].

[0390] The terminal OT of each of the circuits 200[1] to 200[n] is electrically connected to the input terminals of the circuit LAT. In addition, the output terminals of the circuit LAT are electrically connected to the input terminals of the circuit DAC. In addition, the circuit LAT is electrically connected to the wiring VDL. In addition, the circuit LAT is electrically connected to the wiring SPR. In addition, the output terminals of the circuit DAC are electrically connected to the wiring SL[1] to the wiring SL[n]. In addition, Figure 20 Schematically showing the wirings SL[1] to SL[6].

[0391] Each of the circuits 200 [ 1 ] to 200 [ n ] has, for example, the following functions: a function of holding information input to the terminal IT; and a function of outputting the held information to one or both of the terminal OT and the terminal SRT.

[0392] For example, circuit 200[j] has a function of outputting information held in circuit 200[j] to terminal SRT when a high-level potential is input to terminal CLK1. Furthermore, for example, circuit 200[j] has a function of outputting information held in circuit 200[j] to terminal OT when a high-level potential is input to terminal PWC. Furthermore, for example, circuit 200[j] has a function of resetting information held in circuit 200[j] when a high-level potential is input to one or both of terminal CLK2, terminal CLK3, and terminal RT. Furthermore, circuit 200[j] preferably has a configuration in which new information is input to terminal IT of circuit 200[j] after resetting the information held in circuit 200[j], thereby causing circuit 200[j] to hold new information.

[0393] In other words, with Figure 13A and Figure 13B The driving circuit GD is similar, Figure 20 The circuit SR shown is used as a shift register.

[0394] The wiring VDL is used as, for example, a wiring for transmitting a video signal displayed on the pixel circuit PX in the pixel array PA. Figure 20 , the wiring VDL is shown as a wiring for transmitting digital data.

[0395] For example, circuit LAT includes holding circuits for n columns. Furthermore, circuit LAT has the function of holding the video signal input to wiring VDL in the holding circuits based on the signal from terminal OT of each of circuits 200[1] to 200[n]. Specifically, for example, when the potential of terminal OT of circuit 200[j] is high, circuit LAT holds the video signal input to wiring VDL in the holding circuit for the jth column. Furthermore, for example, when a high potential is input to wiring SPR, circuit LAT has the function of simultaneously outputting each video signal held in the holding circuits for n columns to each output terminal of circuit LAT.

[0396] For example, the circuit DAC has a function of converting a video signal of digital data output from each output terminal of the circuit LAT into analog data (analog potential). Note that this analog data (analog potential) is sent to the wiring SL on the column.

[0397] Note that in Figure 20 In the driving circuit SD shown in the figure, wirings other than the wiring CLKLA to the wiring CLKLD and the wiring PWCLA to the wiring PWCLD may be extended. Figure 20 The structure of the driving circuit SD shown is an example, and the number of wirings, the electrical connection structure, etc. may be changed as appropriate.

[0398] Figure 21 : is a timing chart showing an example of the operation of the drive circuit SD. Figure 21 The potential changes of each of the wiring CLKLA to wiring CLKLD, wiring PWCLA to wiring PWCLD, terminal IT, terminal OT[1], terminal OT[2], terminal OT[3], terminal OT[n], and wiring SPR from time T21 to time T36 and in the vicinity thereof are shown. Terminal OT[j] is the terminal OT of circuit 200[j]. In addition, Figure 21 The video signal V DT [1] to V DT [n] An example of sequential input to the wiring VDL.

[0399] During the period from time T21 to time T22, a high-level potential V is applied to the wiring CLKLA and the wiring PWCLA. High In addition, during the period from time T22 to time T23, the high-level potential V is applied to the wiring CLKLB and the wiring PWCLB. High In addition, during the period from time T23 to time T24, the high-level potential V is applied to the wiring CLKLC and the wiring PWCLC. High In addition, during the period from time T24 to time T25, the high-level potential V is applied to the wiring CLKLD and the wiring PWCLD. HighAfter time T25, a high-level potential V is applied to the wirings CLKLA to CLKLD and the wirings PWCLA to PWCLD at the same timing as during the period from time T21 to time T25. High .

[0400] By applying the high-level potential V to each of the wirings CLKLA to CLKLD and the wirings PWCLA to PWCLD at the above timing, High Before time T21, a high level potential V is applied to the terminal IT. High When the high level potential V is outputted from each terminal OT[1] to terminal OT[n] at a predetermined timing, High For example, during the period from time T21 to time T22, a high-level potential V is output from the terminal OT[1]. High , a high level potential V is output from terminal OT[2] during the period from time T22 to time T23. High , a high level potential V is output from the terminal OT[3] during the period from time T23 to time T24. High For example, during the period from time T31 to time T32, a high-level potential V is output from the terminal OT[n-2]. High , a high-level potential V is output from the terminal OT[n-1] during the period from time T32 to time T33. High , a high-level potential V is output from the terminal OT[n] during the period from time T33 to time T34. High .

[0401] Note that in Figure 21 The timing diagram shows the case where n is a multiple of 4. In the drive circuit SD, when n is not a multiple of 4, the potentials applied to the wirings CLKLA to CLKLD and the wirings PWCLA to PWCLD during the period from time T30 to time T34 may be appropriately changed.

[0402] In addition, the circuit LAT outputs a high-level potential V from the terminal OT[1]. High The timing of the video signal V input to the wiring VDL DT [1] is held in the holding circuit of the first column. In addition, a high level potential V is output from the terminal OT[2]. High The timing of the video signal V input to the wiring VDL DT [2] The holding circuit in the second column outputs a high level potential V from the terminal OT[3]. High The timing of the video signal V input to the wiring VDL DT [3] is held in the holding circuit of the third column. The same operation is performed sequentially, and a high level potential V is output from the terminal OT[n]. HighThe timing of the video signal V input to the wiring VDL DT [n] is held in the holding circuit for column n.

[0403] In addition, during the period from time T34 to time T35, the potential of the wiring SPR is changed to the high-level potential V High The circuit LAT stores the video signal V held by the holding circuits of the n columns in the circuit LAT. DT [1] to V DT [n] is output to the circuit DAC through each output terminal of the circuit LAT.

[0404] The drive circuit SD performs the above Figure 21 The working example of the timing diagram can send a video signal to each pixel circuit of the pixel array PA.

[0405] Figure 22 The circuit structure of the circuit 200A can be applied to each of the circuits 200[1] to 200[n] in the driving circuit SD.

[0406] For example, circuit 200A includes circuit BSPRi, circuit FBi1, transistors MN21, MN24, MN25, MN28, MN31, MN34, MN40, MN41, and capacitor C26. Furthermore, for example, circuit 200A includes terminal IT, terminal PWC, terminal CLK1, terminal CLK2, terminal CLK3, terminal RT, terminal SRT, and terminal OT.

[0407] In addition, Figure 22 In the circuit 200A, the circuit BSPRi adopts the change Figure 2A Specifically, the circuit BSPRi adopts a circuit structure of Figure 2A The circuit shown has a BSPR circuit structure with one additional transistor.

[0408] The circuit BSPRi includes the equivalent of Figure 2A The circuit BSPR of the circuit BB of the circuit BBi is equivalent to Figure 2A The transistor MNb of the circuit BSPR is equivalent to the transistor MN37. Figure 2A The capacitor Ca of the circuit BSPR is the capacitor C25 and the transistor MN36.

[0409] The first gate of transistor MN21 is electrically connected to the first gate of transistor MN34 and terminal IT, and the first terminal of transistor MN21 is electrically connected to wiring VDE21. In addition, the second terminal of transistor MN21 is electrically connected to the first terminal of transistor MN24, terminal Bi of circuit BBi, and terminal Fo of circuit FBi1.

[0410] The first gate of transistor MN25 is electrically connected to terminal CLK3, and the first terminal of transistor MN25 is electrically connected to wiring VDE22. The second terminal of transistor MN25 is electrically connected to the first terminal of transistor MN28. The first gate of transistor MN28 is electrically connected to terminal CLK2.

[0411] A first gate of transistor MN31 is electrically connected to terminal RT, and a first terminal of transistor MN31 is electrically connected to wiring VDE23. Furthermore, a second terminal of transistor MN31 is electrically connected to the second terminal of transistor MN28, the first gate of transistor MN24, the first terminal of capacitor C26, the first terminal of transistor MN34, the first gate of transistor MN40, and the first gate of transistor MN41.

[0412] A first gate of transistor MN36 is electrically connected to terminal Bo of circuit BBi, a first terminal of capacitor C25, and a first gate of transistor MN37. A first terminal of transistor MN36 is electrically connected to terminal CLK1. A second terminal of transistor MN36 is electrically connected to terminal Fi of circuit FBi1, a first terminal of transistor MN40, and terminal SRT. Furthermore, a first terminal of transistor MN37 is electrically connected to terminal PWC. Furthermore, a second terminal of transistor MN37 is electrically connected to the second terminal of capacitor C25, a first terminal of transistor MN41, and terminal OT.

[0413] The second terminal of transistor MN24 is electrically connected to wiring VSE11. Furthermore, the second terminal of capacitor C26 is electrically connected to wiring VSE12. Furthermore, the second terminal of transistor MN34 is electrically connected to wiring VSE13. Furthermore, the second terminal of transistor MN40 is electrically connected to wiring VSE14. Furthermore, the second terminal of transistor MN41 is electrically connected to wiring VSE15.

[0414] For example, the wirings VDE21 to VDE23 can refer to the descriptions of the wirings VDE11, VDE3, and VDE4, respectively.

[0415] For the wirings VSE11 to VSE15 , for example, the description of the wirings VSE1 to VSE5 can be referred to, respectively.

[0416] In the circuit 200A, the potential at the terminal SRT becomes a high-level potential V High When the second terminal of the transistor MN21, the first terminal of the transistor MN24, and the terminal Bi of the circuit BBi are electrically connected to a wiring (eg, Figures 3A to 3CThus, even if the charge stored in the electrical connection point changes unintentionally, the potential of the electrical connection point can be kept constant by making the wiring and the electrical connection point conductive.

[0417] As mentioned above Figure 22 As shown in the circuit 200A, by using the circuit BBi of the circuit BSPRi and the circuit in which the transistor MN36 is connected in parallel with the circuit FBi1, the potential of the output terminal of the circuit BSPRi (the second terminal of the transistor MN36) can be stabilized. In other words, in the circuit 200A, the potential of the terminal SRT can be stabilized.

[0418] <<Modification of Circuit 200A>> For example, the circuits 200[1] to 200[n] of the drive circuit SD may also adopt Figure 23 Circuit 200A1 is shown.

[0419] Circuit 200A1 is Figure 22 A modified example of the circuit 200A has Figure 22 The circuit 200A is provided with the structure of the circuit FBi2. Note that the circuit structure of the circuit FBi2 may be the same as the circuit structure of the circuit FBi1.

[0420] Specifically, terminal Fo of circuit FBi2 is electrically connected to terminal Fo of circuit FBi1, terminal Bi of circuit BBi, the second terminal of transistor MN21, and the first terminal of transistor MN24. Terminal Fi of circuit FBi2 is electrically connected to the second terminal of transistor MN37, the first terminal of transistor MN41, the second terminal of capacitor C25, and terminal OT.

[0421] In the circuit 200A1, the potential of one or both of the terminal SRT and the terminal OT becomes the high-level potential V High When the second terminal of the transistor MN21, the first terminal of the transistor MN24, and the terminal Bi of the circuit BBi are electrically connected to a wiring (eg, Figures 3A to 3C Thus, even if the charge stored in the electrical connection point changes unintentionally, the potential of the electrical connection point can be kept constant by making the wiring and the electrical connection point conductive.

[0422] In addition, for example, the circuits 200[1] to 200[n] of the drive circuit SD may also adopt Figure 24 Circuit 200A2 is shown.

[0423] Figure 24The circuit 200A2 has the following structure: Figure 22 In the circuit 200A, the circuit BBi is used as Figure 9A The BSPR of the circuit is the circuit BB, and is used as the circuit FBi1 Figure 3A Therefore, circuit BBi includes transistor MN35, and circuit FBi1 includes transistor MN31.

[0424] A first terminal of transistor MN35 is electrically connected to terminal Bi of circuit BBi, a second terminal of transistor MN35 is electrically connected to terminal Bo of circuit BBi, and a gate of transistor MN35 is electrically connected to wiring VDE35. A first terminal of transistor MN31 is electrically connected to wiring VDE36, a second terminal of transistor MN31 is electrically connected to terminal Fo of circuit FBi1, and a gate of transistor MN31 is electrically connected to terminal Fi of circuit FBi1.

[0425] For example, the wirings VVDE35 and VDE36 can refer to the description of the wirings VDE21 to VDE23 .

[0426] Note that this embodiment mode can be combined with other embodiment modes described in this specification as appropriate. For example, the configuration, structure, and method described in this embodiment mode can be used in combination with the configuration, structure, and method described in other embodiment modes as appropriate.

[0427] (Implementation Method 2) In this embodiment, a configuration example of a display device according to one embodiment of the present invention is described.

[0428] <Configuration Example of Display Device> Figure 25A This is a perspective schematic diagram illustrating a display device according to one embodiment of the present invention. For example, the display device DSP1 includes a display area DIS, a drive circuit area DRV, and a terminal area TMR. Furthermore, the display device DSP1 includes a substrate BS, on which the display area DIS, the drive circuit area DRV, and the terminal area TMR are located.

[0429] In addition, for example, the driving circuit region DRV includes a driving circuit GDR1 , a driving circuit GDR2 , and a driving circuit SDR.

[0430] As the substrate BS, for example, a semiconductor substrate (for example, a semiconductor substrate made of silicon or germanium) can be used. In addition, as the substrate BS, in addition to the semiconductor substrate, for example, an SOI (Silicon On Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate including a stainless steel foil, a tungsten substrate, a substrate including a tungsten foil, a flexible substrate, a laminated film, a paper including a fibrous material, or a base film can be used. As an example of a glass substrate, for example, barium borosilicate glass, aluminoborosilicate glass, or soda-lime glass can be mentioned. As an example of a flexible substrate, a laminated film, a base film, etc., plastics represented by polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE) can be mentioned. In addition, as another example, a synthetic resin such as an acrylic resin can be mentioned. In addition, as another example, polypropylene, polyester, polyvinyl fluoride, or polyvinyl chloride can be mentioned. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor-deposited film, or paper. When the manufacturing process of the display device DSP1 includes heat treatment, a highly heat-resistant material is preferably used as the substrate BS.

[0431] For example, when a semiconductor substrate made of silicon is used as the substrate BS, Si transistors can be used as transistors in the display region DIS and the driver circuit region DRV, and these can be formed on the substrate BS.

[0432] Furthermore, for example, when a glass substrate is used as the substrate BS, OS transistors can be used as transistors in the display region DIS and the driver circuit region DRV, and these can be formed over the substrate BS.

[0433] Furthermore, one or more of the driver circuits GDR1 , GDR2 , and SDR selected from the driver circuit region DRV may be mounted as an IC (Integrated Circuit) on the substrate BS using COG (Chip On Glass) technology.

[0434] For example, the drive circuit GDR1 and the drive circuit GDR2 are both used as drive circuits for displaying an image on the display area DIS. Specifically, for example, the drive circuit GDR1 and the drive circuit GDR2 are both used as gate driver circuits for the display area DIS. Also, for example, the drive circuit SDR is used as a source driver circuit for the display area DIS.

[0435] Therefore, as each of the drive circuit GDR1 and the drive circuit GDR2, for example, the drive circuit GDR1 and the drive circuit GDR2 described in the above embodiment can be used. Figure 13A or Figure 13B In addition, as the driving circuit SDR, for example, the one described in the above embodiment can be used. Figure 20 The driving circuit SD.

[0436] The terminal region TMR includes terminals for supplying image signals and power supply voltage from outside the display device DSP1 to the inside of the display device DSP1. Alternatively, a flexible printed circuit (FPC) may be electrically connected to the terminal region TMR. Furthermore, an integrated circuit (IC) chip may be mounted on the FPC using COF (chip-on-film) technology. This IC may include, for example, a driver circuit for displaying images on the display region DIS.

[0437] The display area DIS includes, for example, a plurality of pixels. In addition, the plurality of pixels may be arranged in a matrix in the display area DIS.

[0438] In addition, each of the multiple pixels can represent one color or multiple colors. In particular, the multiple colors can be, for example, three colors: red, green, and blue. In addition, the multiple colors can also be, for example, two or more selected from red, green, blue, cyan, magenta, yellow, and white. When each pixel representing a different color is referred to as a sub-pixel and white is represented by the multiple sub-pixels of different colors, the multiple sub-pixels are sometimes collectively referred to as pixels. In this specification, for convenience, sub-pixels are referred to as pixels for explanation.

[0439] Furthermore, the display device of one embodiment of the present invention is not limited to Figure 25A For example, a display device according to one embodiment of the present invention may also be configured as a display device DSP1. Figure 25B The structure of the display device DSP2 is shown.

[0440] For example, Figure 25B The display device DSP2 shown includes a display area DIS, a circuit area SIC, and a terminal area TMR. Like the display device DSP1, the display device DSP2 also includes a substrate BS. The display device DSP2 differs from the display device DSP1 in that the circuit area SIC and the terminal area TMR are provided on the substrate BS, and the display area DIS is provided on the circuit area SIC.

[0441] For example, the circuit region SIC includes the aforementioned driver circuit region DRV. Furthermore, the circuit region SIC may also include various functional circuits other than the driver circuit region DRV. In this embodiment, these functional circuits are included in the functional circuit region MFNC.

[0442] For example, the functional circuit region MFNC may include a GPU (Graphics Processing Unit). Furthermore, when the display device DSP2 includes a touch panel, the functional circuit region MFNC may include a sensor controller that controls a touch sensor included in the touch panel.

[0443] Furthermore, when a light-emitting device using an organic EL material is used as the display element of the display device DSP2, the functional circuit region MFNC may also include a correction circuit. The correction circuit, for example, has the function of appropriately adjusting the amount of current input to the light-emitting device containing the organic EL material. The brightness of a light-emitting device containing the organic EL material is proportional to the current. Therefore, if the characteristics of the driving transistor electrically connected to the light-emitting device are poor, the brightness of the light emitted by the light-emitting device may be lower than the desired brightness. For example, the correction circuit may monitor the amount of current flowing through the light-emitting device and, if the current is less than the desired amount, increase the current flowing through the light-emitting device to improve the brightness of the light emitted by the light-emitting device. Conversely, if the current is greater than the desired amount, the current flowing through the light-emitting device may be adjusted to a lower level.

[0444] Furthermore, when a liquid crystal device is used as a display element of the display device DSP2, the functional circuit region MFNC may include a gamma correction circuit.

[0445] Figure 26 It shows Figure 25B FIG. 1 is a block diagram showing an example of the structure of the display device DSP2. Figure 26 The display device DSP2 shown includes a display area DIS and a circuit area SIC. Figure 26 The sensor PDA is shown, and the sensor PDA can be configured inside or outside the display device DSP2.

[0446] in addition, Figure 25A The display device DSP1 can also be electrically connected to the functional circuit area MFNC located outside the display device DSP1 through the terminal area TMR. In this case, the structure of the display device DSP1 can be regarded as the same as that of the display device DSP1. Figure 26 The display device DSP2 shown has the same structure.

[0447] exist Figure 26 , thick solid lines represent multiple wires or buses.

[0448] In addition, Figure 26 For example, in the display area DIS, a plurality of pixel circuits PX are arranged in a matrix. The pixel circuits PX may be, for example, pixel circuits using one or more light-emitting devices selected from a liquid crystal display device, a light-emitting device including an organic EL material, a light-emitting device including an inorganic EL material, and a light-emitting diode such as a micro-LED. Note that this embodiment describes a case where a light-emitting device including an organic EL material is used in the pixel circuits PX of the display area DIS.

[0449] In addition, as mentioned above, Figure 26 The middle circuit region SIC includes a driving circuit region DRV and a functional circuit region MFNC.

[0450] The driving circuit region DRV is used as a peripheral circuit for driving the display region DIS. Specifically, the driving circuit region DRV includes, for example, a driving circuit SDR, a digital-to-analog conversion circuit DAD, a driving circuit GDR, and a level converter LVS. The driving circuit SDR is equivalent to Figure 12 The drive circuit SD and the drive circuit GDR are equivalent to Figure 12 The driving circuit GD in.

[0451] In addition, for example, the functional circuit area MFNC may be provided with: a storage device for storing image data displayed on the display area DIS; a decoder for decoding coded image data; a GPU, a power supply circuit, a correction circuit or a CPU for processing image data. Figure 26 For example, the functional circuit region MFNC includes a memory device MEM, a GPU 22 , a correction circuit ECR, a timing controller TMC, a CPU (NoffCPU (registered trademark)) 21 , a sensor controller SCC, and a power supply circuit EPS.

[0452] In addition, for example, Figure 26 In the display device DSP2, the circuits included in the drive circuit region DRV and the circuits included in the functional circuit region MFNC are electrically connected to the bus line BSL.

[0453] The drive circuit SDR has a function of transmitting image data to the pixel circuits PX included in the display area DIS, for example. Therefore, the drive circuit SDR is electrically connected to the pixel circuits PX via the wiring SL.

[0454] The digital-to-analog conversion circuit DAD, for example, converts image data digitally processed by a GPU or correction circuit (described later) into analog data. The converted image data is transmitted to the display area DIS via the drive circuit SDR. The digital-to-analog conversion circuit DAD may be included in the drive circuit SDR, or may sequentially transmit image data to the drive circuit SDR, the digital-to-analog conversion circuit DAD, and the display area DIS.

[0455] For example, in the display area DIS, the drive circuit GDR has a function of selecting the pixel circuit PX to which image data is to be transmitted. Therefore, the drive circuit GDR is electrically connected to the pixel circuit PX via the wiring GL.

[0456] The level converter LVS has a function of converting a signal input to the driver circuit SDR, the digital-to-analog converter circuit DAD, the driver circuit GDR, etc., into an appropriate level, for example.

[0457] The memory device MEM has a function of storing, for example, image data displayed on the display area DIS. Note that the memory device MEM may have a structure for storing image data as digital data or analog data.

[0458] When storing image data in the memory device MEM, it is preferable to use a nonvolatile memory as the memory device MEM. In this case, for example, a NAND memory or the like can be used as the memory device MEM.

[0459] When storing temporary data generated by the GPU 22, the correction circuit ECR, the CPU 21, etc., in the memory device MEM, it is preferable to use a volatile memory as the memory device MEM. In this case, for example, an SRAM (Static Random Access Memory) or a DRAM (Dynamic Random Access Memory) can be used as the memory device MEM.

[0460] The GPU 22, for example, has the function of processing image data read from the memory device MEM and rendering it on the display area DIS. In particular, because the GPU 22 has a parallel pipeline processing structure, it can process image data displayed on the display area DIS at high speed. Furthermore, the GPU 22 can also be used as a decoder for decoding encoded images.

[0461] Furthermore, the functional circuit region MFNC may also include multiple circuits capable of improving the display quality of the display region DIS. For example, a correction circuit (a circuit for color adjustment or dimming) may be provided as one of these circuits. This circuit detects color unevenness in the image displayed in the display region DIS and corrects this unevenness to achieve an optimal image. Furthermore, when light-emitting devices containing organic EL materials are used in the pixels of the display region DIS, a correction circuit may also be provided in the functional circuit region MFNC. Note that this embodiment describes a case where the pixel circuits PX of the display region DIS use light-emitting devices containing organic EL materials. For example, the functional circuit region MFNC includes a correction circuit ECR.

[0462] Furthermore, artificial intelligence can also be utilized in the image correction described above. For example, the current flowing through the display device included in the pixel (or the voltage applied to the display device) can be monitored and obtained, and the image displayed on the display area DIS can be obtained by an image sensor or the like. The current (or voltage) and the image can be used as input data for artificial intelligence calculations (e.g., artificial neural networks), and the output result can be used to determine whether the image should be corrected.

[0463] Furthermore, AI calculations can be applied not only to image correction but also to up-conversion of image data. Thus, by up-converting image data with a lower resolution according to the resolution of the display area DIS, a high-quality image can be displayed on the display area DIS. Furthermore, AI calculations can be applied to down-conversion of image data.

[0464] Note that the aforementioned artificial intelligence calculations can be performed using the GPU 22 included in the functional circuit region MFNC. In other words, the GPU 22 can be used to perform various correction operations (such as color unevenness correction and up-conversion processing). Furthermore, the GPU 22 may also include a circuit 22a for correcting color unevenness and a circuit 22b for performing up-conversion processing.

[0465] Note that in this specification, a GPU that performs artificial intelligence calculations is referred to as an AI accelerator. That is, in this specification, the GPU included in the functional circuit region MFNC may sometimes be replaced with an AI accelerator for description.

[0466] The timing controller TMC, for example, has the function of increasing or decreasing the frame rate of images displayed on the display area DIS. For example, when displaying a static image on the display area DIS, the display device DSP2 can be driven by the timing controller TMC at a lower frame rate. For example, when displaying a dynamic image on the display area DIS, the display device DSP2 can be driven by the timing controller TMC at a higher frame rate. In other words, by providing the timing controller TMC in the display device DSP2, the frame rate can be changed depending on whether the image is static or dynamic. In particular, when displaying a static image on the display area DIS, the frame rate can be reduced to operate, thereby reducing the power consumption of the display device DSP2.

[0467] The CPU 21 has functions for general processing, such as operating system execution, data control, various calculations, and program execution. In the display device DSP2, the CPU 21 has functions for executing commands such as writing or reading image data from the memory device MEM, correcting image data, and operating sensors described later. Furthermore, the CPU 21 may also have functions for transmitting control signals to one or more circuits included in the functional circuit region MFNC, such as the memory device, GPU, correction circuit, timing controller, and high-frequency circuit.

[0468] In addition, the CPU 21 may also include a circuit for temporarily backing up data (hereinafter referred to as a backup circuit). Preferably, the backup circuit can maintain the data even if the supply of power supply voltage is stopped. For example, when a static image is displayed on the display area DIS, the CPU 21 can stop its function until an image different from the current static image is displayed. Thus, by temporarily backing up the data processed in the CPU 21 in the backup circuit and then stopping the supply of power supply voltage to the CPU 21 to stop the CPU 21, the dynamic power consumption of the CPU 21 can be reduced. In addition, in this specification, etc., a CPU including a backup circuit will be referred to as an NoffCPU.

[0469] The sensor controller SCC has the function of controlling the sensor PDA, for example. Figure 26 In FIG. 1 , wiring SNCL is shown as wiring for electrically connecting the sensor PDA and the sensor controller SCC.

[0470] The sensor PDA may be, for example, a touch sensor that can be provided above, below, or inside the display area DIS.

[0471] Furthermore, the sensor PDA may be, for example, an illuminance sensor. In particular, by obtaining the intensity of external light illuminating the display area DIS through the illuminance sensor, the brightness (luminance) of the image displayed on the display area DIS can be changed in accordance with the external light. For example, when external light is bright, the brightness of the image displayed on the display area DIS can be increased to improve the visibility of the image. Conversely, when external light is dim, the brightness of the image displayed on the display area DIS can be reduced to reduce power consumption.

[0472] The sensor PDA may be, for example, an image sensor. For example, by using the image sensor to acquire an image, the image may be displayed on the display area DIS.

[0473] The power supply circuit EPS, for example, has the function of generating voltages to be supplied to the circuits included in the driver circuit region DRV, the circuits included in the functional circuit region MFNC, and the pixels included in the display region DIS. Note that the power supply circuit EPS may also have the function of selecting the circuits to which voltages are supplied. For example, while a static image is being displayed on the display region DIS, the power supply circuit EPS can reduce the overall power consumption of the display device DSP by stopping the supply of voltages to the various circuits in the driver circuit region DRV (e.g., the driver circuit SDR, the digital-to-analog converter circuit DAD, etc.) and the various circuits in the functional circuit region MFNC (e.g., the CPU 21, the GPU 22, etc.).

[0474] <Example 1 of Cross-Sectional Structure of Display Device> Next, the cross-sectional view is explained. Figure 25A The structure example of the display device DSP1 is shown.

[0475] Figure 27 The display device DSP1A shown is viewed from a cross section. Figure 25A The display device DSP1A is shown in FIG. 1A. In the display device DSP1A, a pixel circuit, a driver circuit, etc. are provided on a substrate 310. Figure 27 The display device DSP1A shows Figure 25A The driving circuit area DRV and the display area DIS are shown.

[0476] Figure 27 The substrate 310 is equivalent to Figure 25AThe substrate BS shown. The diagonal size of the display device DSP1A can be determined, for example, by the type and size of the substrate 310. For example, when manufacturing a display device with a diagonal size of 30 inches or more, 50 inches or more, 70 inches or more, or 100 inches or more for a television or digital signage device, a glass substrate can be used as the substrate 310. Furthermore, when manufacturing a display device with a diagonal size of 10 inches or less, 5 inches or less, 1.5 inches or less, 1 inch or less, or 0.5 inches or less for an XR device or a wearable information terminal, a semiconductor substrate can be used as the substrate 310.

[0477] Note that in Figure 27 In the description of the display device DSP1A, the substrate 310 is a semiconductor substrate.

[0478] The screen ratio (aspect ratio) of the display device DSP1A is not particularly limited. For example, the display device DSP1A can support various screen ratios such as 1:1 (square), 4:3, 16:9, 16:10, 21:9, or 32:9.

[0479] exist Figure 27 In the display device DSP1A, a transistor 300p and a transistor 300d are formed on a substrate 310. Note that in this specification, the transistor 300p and the transistor 300d are collectively referred to as the transistor 300. In addition, a light emitting device 130 ( Figure 27 , light emitting device 130R, light emitting device 130G and light emitting device 130B).

[0480] The transistor 300p is included in the display region DIS and is used, for example, as a transistor included in the pixel circuit PX. Furthermore, the transistor 300d is used as a transistor included in the drive circuit region DRV. Therefore, the transistor 300d may be, for example, a transistor included in the circuits 100[1] to 100[m] or 200[1] to 200[n+2] described in Embodiment 1. Furthermore, the light-emitting device 130 may also be a light-emitting device included in the pixel circuit PX.

[0481] The transistor 300 is provided on a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 formed by a portion of the substrate 310, and a low resistance region 314a and a low resistance region 314b serving as a source region or a drain region. Therefore, the transistor 300 uses a Si transistor. Note that Figure 27Although the structure shown is such that one of the source and drain of transistor 300 is electrically connected to conductor 596 and conductors 112 (conductors 112a to 112c) via conductor 328 (described later), the electrical connection structure of the semiconductor device of one embodiment of the present invention is not limited to this. For example, the display device of one embodiment of the present invention may also have a structure in which the gate of transistor 300 is electrically connected to conductor 596 via conductor 328.

[0482] Transistor 300 can achieve a fin structure, for example, by employing a structure in which the top surface and side surfaces of semiconductor region 313 in the channel width direction are covered by conductor 316 via insulator 315 serving as a gate insulator. Forming a fin-type transistor 300 increases the effective channel width, thereby improving the on-state characteristics of transistor 300. Furthermore, since the influence of the electric field of the gate electrode can be increased, the off-state characteristics of transistor 300 can be improved. For example, transistor 300 can also have a planar structure instead of a fin-type structure.

[0483] Note that the transistor 300 may be a p-channel transistor or an n-channel transistor. A plurality of transistors 300 may be provided, and both p-channel transistors and n-channel transistors may be used.

[0484] The channel formation region of the semiconductor region 313, the region adjacent thereto, and the low-resistance region 314a and low-resistance region 314b serving as the source or drain region preferably comprise a silicon-based semiconductor, specifically, preferably single-crystalline silicon. Alternatively, each of the aforementioned regions may be formed using, for example, germanium, silicon germanium, gallium arsenide, aluminum gallium arsenide, or gallium nitride. Silicon may be used in which the effective mass is controlled by applying stress to the crystal lattice and changing the interplanar spacing. Furthermore, the transistor 300 may be, for example, a HEMT (High Electron Mobility Transistor) using gallium arsenide or aluminum gallium arsenide.

[0485] As the conductor 316 serving as the gate electrode, a semiconductor material such as silicon containing an element imparting n-type conductivity, such as arsenic or phosphorus, or an element imparting p-type conductivity, such as boron or aluminum, can be used. Alternatively, as the conductor 316, a conductive material such as a metal material, an alloy material, or a metal oxide material can be used.

[0486] Furthermore, since the material of the conductor determines the work function, the threshold voltage of the transistor can be adjusted by selecting the conductor material. Specifically, titanium nitride or tantalum nitride, or both, is preferably used as the conductor. To achieve both conductivity and embeddability, a laminate of one or both tungsten and aluminum is preferably used as the conductor, with tungsten being particularly preferred for its heat resistance.

[0487] An element isolation layer 312 is provided to isolate a plurality of transistors formed on a substrate 310. The element isolation layer can be formed using, for example, a LOCOS (Local Oxidation of Silicon) method, an STI (Shallow Trench Isolation) method, or a mesa isolation method.

[0488] Figure 27 In the transistor 300 shown, an insulator 320 and an insulator 322 are stacked in sequence from the substrate 310 side.

[0489] As the insulator 320 and the insulator 322 , for example, one or more selected from silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride can be used.

[0490] In this specification, etc., "oxynitride" refers to a material containing more oxygen than nitrogen, while "oxynitride" refers to a material containing more nitrogen than oxygen. For example, "silicon oxynitride" refers to a material containing more oxygen than nitrogen, while "silicon oxynitride" refers to a material containing more nitrogen than oxygen.

[0491] The insulator 322 can also be used as a planarization film to planarize steps formed by the insulator 320 and the transistor 300 covered by the insulator 322. For example, to improve the flatness of the top surface of the insulator 322, a planarization process using chemical mechanical polishing (CMP) can be performed.

[0492] An insulator 592 and an insulator 594 are sequentially stacked on the insulator 322 .

[0493] In addition, the insulator 592 preferably uses a blocking insulating film (referred to as a blocking insulating film) that prevents impurities such as water and hydrogen from diffusing from the substrate 310 or the transistor 300 to the region above the insulator 592 (e.g., the region where the light-emitting devices 130R, 130G, and 130B are provided). Therefore, the insulator 592 preferably uses an insulating material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (making it difficult for these impurities to pass through). In addition, depending on the circumstances, the insulator 592 preferably uses an insulating material that has the function of inhibiting the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and NO), and copper atoms (making it difficult for the above-mentioned oxygen to pass through). Alternatively, it is preferable to have the function of inhibiting the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules).

[0494] As an example of a film having a barrier property against hydrogen, silicon nitride formed by a CVD (Chemical Vapor Deposition) method can be used.

[0495] The amount of hydrogen released can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, when the amount of hydrogen released is converted to the amount per unit area of ​​the insulator 324 when the film surface temperature in TDS is within the range of 50°C to 500°C, the amount of hydrogen released from the insulator 324 is 10×10 15 atoms / cm 2 Below, preferably 5×10 15 atoms / cm 2 The following is enough.

[0496] Note that the dielectric constant of the insulator 594 is preferably lower than that of the insulator 592. For example, the relative dielectric constant of the insulator 594 is preferably less than 4, more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 594 is preferably 0.7 times or less, more preferably 0.6 times or less, that of the insulator 592. By using an interlayer film made of a material with a low dielectric constant as the insulator 594, parasitic capacitance generated between wirings can be reduced.

[0497] Insulators 320, 322, 592, and 594 also have embedded conductors 328 and 596, which are connected to light-emitting devices and the like disposed above insulator 594. Conductors 328 and 596 also function as plugs or wiring. Note that the same reference numeral may be used to represent multiple conductors serving as plugs or wiring. Furthermore, in this specification and other text, wiring and the plug connected thereto may be referred to as a single component. That is, a portion of a conductor may function as wiring, and a portion of a conductor may function as a plug.

[0498] As the material for each plug and wiring (e.g., conductor 328 and conductor 596), a single layer or a stack of one or more conductive materials selected from metal materials, alloy materials, metal nitride materials, and metal oxide materials can be used. Preferably, a high melting point material such as tungsten or molybdenum that has both heat resistance and conductivity is used, with tungsten being preferred. Alternatively, it is preferably formed using a low-resistance conductive material such as aluminum or copper. By using a low-resistance conductive material, the wiring resistance can be reduced.

[0499] An insulator 598 and an insulator 599 are sequentially formed on the insulator 594 and the conductor 328 .

[0500] For example, similar to insulator 592, insulator 598 is preferably an insulator having a barrier property against at least one of hydrogen, oxygen, and water. Furthermore, similar to insulator 594, insulator 599 is preferably an insulator having a low relative dielectric constant to reduce parasitic capacitance generated between wirings. Insulator 599 also functions as an interlayer insulating film and a planarizing film.

[0501] The light emitting device 130 and the connecting portion 140 are formed on the insulator 599 .

[0502] The connection portion 140 is sometimes referred to as a cathode contact portion and is electrically connected to the cathode electrode of each of the light emitting devices 130R, 130G, and 130B. Figure 27 In the figure, the connecting portion 140 includes: one or more conductors selected from conductors 112a to 112c to be described later; at least one conductor selected from conductors 126a to 126c to be described later; one or more conductors selected from conductors 129a to 129c to be described later; a common layer 114 to be described later; and a common electrode 115 to be described later.

[0503] Note that the connection portion 140 may be provided so as to surround the four sides of the display portion in a plan view, or may be provided within the display portion (for example, between adjacent light-emitting devices 130 ).

[0504] Light-emitting device 130R includes conductor 112a, conductor 126a on conductor 112a, and conductor 129a on conductor 126a. Conductors 112a, 126a, and 129a may all be referred to as pixel electrodes, or portions of conductors 112a, 126a, and 129a may all be referred to as pixel electrodes. Furthermore, light-emitting device 130G includes conductor 112b, conductor 126b on conductor 112b, and conductor 129b on conductor 126b. Similar to light-emitting device 130R, conductors 112b, 126b, and 129b may all be referred to as pixel electrodes, or portions of conductors 112b, 126b, and 129b may all be referred to as pixel electrodes. Light-emitting device 130B includes conductor 112c, conductor 126c on conductor 112c, and conductor 129c on conductor 126c. Similar to light-emitting devices 130R and 130G, conductor 112c, conductor 126c, and conductor 129c may all be referred to as pixel electrodes, or a portion of conductor 112c, conductor 126c, and conductor 129c may be referred to as pixel electrodes.

[0505] Conductors 112a to 112c and 126a to 126c may be, for example, conductive layers used as reflective electrodes. Conductors with high reflectivity for visible light, such as silver, aluminum, or an alloy film composed of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film), may be used as the reflective electrodes. Furthermore, conductors 112a to 112c and 126a to 126c may be, for example, a laminated film of aluminum sandwiched between a pair of titanium (a film comprising Ti, Al, and Ti laminated in this order), or a laminated film of silver sandwiched between a pair of indium tin oxide (a film comprising ITO, Ag, and ITO laminated in this order).

[0506] Alternatively, for example, a conductive layer serving as a reflective electrode may be used as the conductors 112a to 112c, and a highly translucent conductor may be used as the conductors 126a to 126c. Examples of highly translucent conductors include silver and magnesium alloys and indium tin oxide (sometimes referred to as ITO).

[0507] As the conductors 129a to 129c, for example, a conductive layer serving as a transparent electrode can be used. As the conductive layer serving as a transparent electrode, for example, the highly light-transmitting conductors described above can be used.

[0508] Furthermore, the light-emitting device 130, which will be described in detail later, may also employ a microcavity structure (a micro-resonator structure). A microcavity structure refers to a structure in which the distance between the bottom surface of the light-emitting layer and the top surface of the lower electrode is defined by a thickness corresponding to the wavelength of the color of light emitted by the light-emitting layer. In this case, it is preferred that the conductors 129a to 129c serving as the upper electrode (common electrode) be made of a light-transmitting and light-reflective conductive material, and that the conductors 112a to 112c and the conductors 126a to 126c serving as the lower electrode (pixel electrode) be made of a light-reflective conductive material.

[0509] A microcavity structure is one in which the optical distance between the lower electrode and the light-emitting layer is adjusted to (2n-1)λ / 4 (note that n is a natural number greater than 1, and λ is the wavelength of the light to be amplified). As a result, light reflected from the lower electrode (reflected light) significantly interferes with light directly incident from the light-emitting layer onto the upper electrode (incident light). This allows the phases of the reflected light at wavelengths λ to be aligned with the incident light, further amplifying the light emitted from the light-emitting layer. On the other hand, if the reflected light and incident light have wavelengths other than λ, the phases are misaligned, resulting in attenuation and no resonance.

[0510] Conductor 112a is connected to conductor 596 embedded in insulator 594 through an opening provided in insulator 599. Furthermore, the end of conductor 126a is located outside the end of conductor 112a. The end of conductor 126a is aligned or substantially aligned with the end of conductor 129a.

[0511] The conductor 112b in the light-emitting device 130G and the conductor 112c in the light-emitting device 130B are similar to the conductor 112a in the light-emitting device 130R, and therefore, detailed descriptions thereof are omitted. Furthermore, the conductor 126b in the light-emitting device 130G and the conductor 126c in the light-emitting device 130B are similar to the conductor 126a in the light-emitting device 130R, and therefore, detailed descriptions thereof are omitted. Furthermore, the conductor 129b in the light-emitting device 130G and the conductor 129c in the light-emitting device 130B are similar to the conductor 129a in the light-emitting device 130R, and therefore, detailed descriptions thereof are omitted.

[0512] Concave portions covering the openings provided in the insulator 599 are formed in the conductors 112a, 112b, and 112c. The layer 128 is embedded in the concave portions.

[0513] Layer 128 flattens the concave portions of conductors 112a and 112c. Conductors 126a and 126c are provided on conductors 112a and 112c and layer 128, electrically connected to conductors 112a and 112c. Therefore, the area overlapping the concave portions of conductors 112a and 112c can also function as a light-emitting area, thereby increasing the pixel aperture ratio.

[0514] The layer 128 may be an insulating layer or a conductive layer. For example, various inorganic insulating materials, organic insulating materials, and conductive materials can be used as the layer 128. In particular, the layer 128 is preferably formed using an insulating material.

[0515] As layer 128, an insulating layer composed of an organic material can be used as appropriate. For example, acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenolic resin, and precursors of these resins can be used as layer 128. Alternatively, a photosensitive resin can be used as layer 128. Examples of the photosensitive resin include positive-type and negative-type materials.

[0516] By using a photosensitive resin, layer 128 can be formed simply through exposure and development steps, which can reduce the effects of dry etching or wet etching on the surfaces of conductors 112a, 112b, and 112c. Furthermore, by using a negative-type photosensitive resin to form layer 128, the same photomask (exposure mask) as that used to form the openings in insulator 599 can be used to form layer 128.

[0517] Although Figure 27 Although an example is shown in which the top surface of the layer 128 has a flat portion, there is no particular limitation on the shape of the layer 128. Figure 28A As shown in FIG. 1 , the top surface of layer 128 may also have a shape having a concave surface in the center and its vicinity when viewed from a cross section. Alternatively, as shown in FIG. Figure 28B As shown in FIG. 1 , when viewed from a cross section, the layer 128 may have a shape having a convex surface in the center and its vicinity. Figure 28C As shown, the layer 128 may have a shape having a concave curved surface and a convex curved surface in the center portion and its vicinity.

[0518] The light emitting device 130R includes a first layer 113a, a common layer 114 on the first layer 113a, and a common electrode 115 on the common layer 114. In addition, the light emitting device 130G includes a second layer 113b, a common layer 114 on the second layer 113b, and a common electrode 115 on the common layer 114. In addition, the light emitting device 130B includes a third layer 113c, a common layer 114 on the third layer 113c, and a common electrode 115 on the common layer 114.

[0519] Furthermore, the first layer 113a is formed so as to cover the top and side surfaces of the conductor 126a and the top and side surfaces of the conductor 129a. Similarly, the second layer 113b is formed so as to cover the top and side surfaces of the conductor 126b and the top and side surfaces of the conductor 129b. Similarly, the third layer 113c is formed so as to cover the top and side surfaces of the conductor 126c and the top and side surfaces of the conductor 129c. Therefore, the entire region where the conductors 126a, 126b, and 126c are provided can be used as the light-emitting region of the light-emitting devices 130R, 130G, and 130B, thereby increasing the aperture ratio of the pixel.

[0520] In the light-emitting device 130R, the first layer 113a and the common layer 114 may be collectively referred to as an EL layer. Similarly, in the light-emitting device 130G, the second layer 113b and the common layer 114 may be collectively referred to as an EL layer. Similarly, in the light-emitting device 130B, the third layer 113c and the common layer 114 may be collectively referred to as an EL layer.

[0521] There is no particular limitation on the structure of the light-emitting device of this embodiment, and a single structure or a tandem structure may be employed.

[0522] The first layer 113a, the second layer 113b, and the third layer 113c are processed into island shapes using photolithography. Therefore, the angle formed between the top surface and the side surface of each of the first layer 113a, the second layer 113b, and the third layer 113c is close to 90 degrees. On the other hand, for example, the thickness of an organic film formed using FMM (Fine Metal Mask) tends to decrease toward the end. For example, the top surface of the film is formed into a slope within a range of 1 μm to 10 μm, making it difficult to distinguish between the top surface and the side surface.

[0523] The top surface and side surfaces of the first layer 113a, the second layer 113b, and the third layer 113c are clearly distinguished. Therefore, in adjacent first and second layers 113a, one side surface of the first layer 113a and one side surface of the second layer 113b face each other. This applies to any combination of the first layer 113a, the second layer 113b, and the third layer 113c.

[0524] The first layer 113a, the second layer 113b, and the third layer 113c each include at least a light-emitting layer. For example, the first layer 113a, the second layer 113b, and the third layer 113c preferably include a light-emitting layer that emits red light, a light-emitting layer that emits green light, and a light-emitting layer that emits blue light, respectively. In addition to the colors listed above, each light-emitting layer may also be cyan, magenta, yellow, or white.

[0525] The first layer 113a, the second layer 113b, and the third layer 113c preferably include a light-emitting layer and a carrier transport layer (electron transport layer or hole transport layer) on the light-emitting layer. Because the surfaces of the first layer 113a, the second layer 113b, and the third layer 113c are sometimes exposed during the manufacturing process of the display device, by providing a carrier transport layer on the light-emitting layer, the light-emitting layer can be prevented from being exposed to the outermost surface, thereby reducing damage to the light-emitting layer. This can improve the reliability of the light-emitting device.

[0526] Common layer 114 may include, for example, an electron injection layer or a hole injection layer. Alternatively, common layer 114 may include a stack of an electron transport layer and an electron injection layer, or a stack of a hole transport layer and a hole injection layer. Light-emitting devices 130R, 130G, and 130B all include common layer 114.

[0527] The light emitting device 130R, the light emitting device 130G and the light emitting device 130B all include a common electrode 115. Figure 27 As shown, the common electrode 115 commonly included in the plurality of light emitting devices is electrically connected to the conductor in the connection portion 140 .

[0528] The insulator 125 preferably has a function of a blocking insulating layer for one or both of water and oxygen. In addition, the insulator 125 preferably has a function of suppressing the diffusion of one or both of water and oxygen. In addition, the insulator 125 preferably has a function of capturing or fixing (also called doping) one or both of water and oxygen. When the insulator 125 has the function of a blocking insulating layer or a doping function, it can have a structure that suppresses the entry of impurities (typically, one or both of water and oxygen) that may diffuse from the outside to each light-emitting device. By adopting this structure, a light-emitting device with high reliability can be provided, and a display panel with high reliability can be provided.

[0529] Furthermore, the impurity concentration of the insulator 125 is preferably low. This can prevent impurities from entering the EL layer from the insulator 125 and degrading the EL layer. Furthermore, by reducing the impurity concentration in the insulator 125, the barrier properties against one or both of water and oxygen can be improved. For example, it is preferable that either the hydrogen concentration or the carbon concentration in the insulator 125 be sufficiently low, and preferably both the hydrogen concentration and the carbon concentration be sufficiently low.

[0530] As the insulator 127, an insulating layer containing an organic material can be appropriately used. As the organic material, a photosensitive organic resin is preferably used, for example, a photosensitive resin composition containing an acrylic resin is preferably used. In addition, the viscosity of the material of the insulator 127 can be greater than 1 cP and less than 1500 cP, preferably greater than 1 cP and less than 12 cP. By setting the viscosity of the material of the insulator 127 within the above range, the insulator 127 having a tapered shape described later can be formed more easily. Note that in this specification, etc., acrylic resin does not refer only to polymethacrylate or methacrylic resin, and sometimes refers to the entire acrylic polymer in a broad sense.

[0531] In this specification, a tapered shape refers to a shape in which at least a portion of a side surface of a component is inclined relative to the substrate surface. For example, a region in which the angle formed by the inclined side surface and the substrate surface (also called a taper angle) is less than 90° is preferably included.

[0532] Note that as described later, the insulator 127 only needs to have a tapered shape on the side, and the organic material that can be used for the insulator 127 is not limited to the above-mentioned materials. For example, acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimide amide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin and precursors of the above-mentioned resins can sometimes be used as the insulator 127. In addition, as the insulator 127, organic materials such as polyvinyl alcohol (PVA), polyvinyl butyral (PVB), polyvinyl pyrrolidone, polyethylene glycol, polyglycerol, pullulan, water-soluble cellulose or alcohol-soluble polyamide resin can sometimes be used. In addition, as the insulator 127, for example, a photoresist can sometimes be used as a photosensitive resin. As the photosensitive resin, positive materials or negative materials can be cited.

[0533] Insulator 127 can also be made of a material that absorbs visible light. By absorbing the light emitted by the light-emitting device, insulator 127 can suppress light leakage from the light-emitting device through insulator 127 to adjacent light-emitting devices (stray light). This improves the display quality of the display panel. Furthermore, even without using a polarizing plate in the display panel, display quality can be improved, thereby achieving a lighter and thinner display panel.

[0534] Examples of materials that absorb visible light include materials containing pigments such as black, materials containing dyes, light-absorbing resin materials (e.g., polyimide), and resin materials that can be used for color filters (color filter materials). In particular, the use of resin materials formed by mixing or laminating two or more color filter materials is preferred because it can enhance the visible light shielding effect. In particular, by mixing three or more color filter materials, a black or nearly black resin layer can be achieved.

[0535] The insulator 127 can be formed by a wet deposition method such as spin coating, dipping, spray coating, inkjet coating, dispenser coating, screen printing, offset printing, doctor blade coating, slit coating, roll coating, curtain coating, or blade coating. In particular, the organic insulating film to be the insulator 127 is preferably formed by spin coating.

[0536] The insulator 127 is formed at a temperature lower than the heat resistance temperature of the EL layer. The substrate temperature during formation of the insulator 127 is typically 200° C. or lower, preferably 180° C. or lower, more preferably 160° C. or lower, further preferably 150° C. or lower, and even more preferably 140° C. or lower.

[0537] The following description uses the structure of insulator 127 located between light-emitting devices 130R and 130G as an example to explain the structure of insulator 127 and other components. Note that the same applies to insulator 127 located between light-emitting devices 130G and 130B, and to insulator 127 located between light-emitting devices 130B and 130R. Furthermore, while the following description may use the end portion of insulator 127 located on second layer 113b as an example, the same applies to the end portion of insulator 127 located on first layer 113a and the end portion of insulator 127 located on third layer 113c.

[0538] Preferably, the side surfaces of the insulator 127 have a tapered shape with a taper angle θ1 when the display device is viewed in cross section. The taper angle θ1 is the angle formed between the side surfaces of the insulator 127 and the substrate surface. Note that the taper angle θ1 is not limited to the substrate surface; it may also be the angle formed between the top surface of the flat portion of the insulator 125 or the top surface of the flat portion of the second layer 113b and the side surfaces of the insulator 127. Furthermore, by tapering the side surfaces of the insulator 127, the side surfaces of the insulator 125 and the side surfaces of the mask layer 118a may also have tapered shapes.

[0539] The taper angle θ1 of the insulator 127 is less than 90°, preferably less than 60°, and more preferably less than 45°. By providing the side edges of the insulator 127 with this forward tapered shape, the common layer 114 and the common electrode 115 provided on the side edges of the insulator 127 can be deposited with high coverage without causing disconnection or localized thinning. This improves the in-plane uniformity of the common layer 114 and the common electrode 115, thereby enhancing the display quality of the display device.

[0540] In addition, in the cross-sectional view of the display device, the top surface of the insulator 127 preferably has a convex curved surface. The convex curved surface of the top surface of the insulator 127 preferably bulges gently toward the center. Furthermore, the top surface of the insulator 127 preferably has a convex curved portion in the center smoothly connected to the tapered portion at the side end. By adopting this shape for the insulator 127, the common layer 114 and the common electrode 115 can be deposited with high coverage over the entire top surface of the insulator 127.

[0541] Furthermore, the insulator 127 is formed in a region between two EL layers (for example, a region between the first layer 113a and the second layer 113b). In this case, a portion of the insulator 127 is positioned between a side edge of one EL layer (for example, the first layer 113a) and a side edge of the other EL layer (for example, the second layer 113b).

[0542] Furthermore, it is preferable that one end of the insulator 127 overlaps with the conductor 126a serving as the pixel electrode, and the other end of the insulator 127 overlaps with the conductor 126b serving as the pixel electrode. With this structure, the end of the insulator 127 can be formed on a substantially flat region of the first layer 113a (second layer 113b). This makes it easier to process the insulator 127 into the tapered shape described above.

[0543] As described above, the provision of the insulator 127 and the like prevents the occurrence of disconnected portions and locally thinned portions in the common layer 114 and the common electrode 115 between the substantially flat regions of the first layer 113a and the substantially flat regions of the second layer 113b. Consequently, poor connection due to disconnected portions and increased resistance due to locally thinned portions in the common layer 114 and the common electrode 115 between the light-emitting devices can be suppressed.

[0544] In the display device of this embodiment, the distance between the light-emitting devices can be reduced. Specifically, the distance between the light-emitting devices, the distance between the EL layers, or the distance between the pixel electrodes can be reduced to less than 10μm, less than 8μm, less than 5μm, less than 3μm, less than 2μm, less than 1μm, less than 500nm, less than 200nm, less than 100nm, less than 90nm, less than 70nm, less than 50nm, less than 30nm, less than 20nm, less than 15nm, or less than 10nm. In other words, the display device of this embodiment has a region where the interval between two adjacent island-shaped EL layers is less than 1μm, preferably has a region where the interval is less than 0.5μm (500nm), and more preferably has a region where the interval is less than 100nm. By reducing the distance between each light-emitting device as described above, a display device with high definition and high aperture ratio can be provided.

[0545] A protective layer 131 is provided on the light-emitting device 130. The protective layer 131 serves as a passivation film to protect the light-emitting device 130. By forming the protective layer 131 covering the light-emitting device, the intrusion of impurities such as water and oxygen into the light-emitting device can be suppressed, thereby improving the reliability of the light-emitting device 130. For example, aluminum oxide, silicon nitride, or silicon oxynitride can be used as the protective layer 131.

[0546] The protective layer 131 and the substrate 110 are bonded together by the adhesive layer 107. As a seal of the light emitting device, for example, a solid sealing structure or a hollow sealing structure may be used. Figure 27In the embodiment, the space between substrate 310 and substrate 110 is filled with adhesive layer 107, i.e., a solid sealing structure is adopted. Alternatively, a hollow sealing structure can be adopted in which the space is filled with an inert gas (such as nitrogen or argon). In this case, adhesive layer 107 can also be provided so as not to overlap with the light-emitting device. Alternatively, a resin different from the frame-shaped adhesive layer 107 can be used to fill the space.

[0547] As the adhesive layer 107, various curing adhesives such as light-curing adhesives such as ultraviolet curing adhesives, reaction-curing adhesives, heat-curing adhesives, or anaerobic adhesives can be used. Examples of these adhesives include epoxy resins, acrylic resins, silicone resins, phenolic resins, polyimide resins, imide resins, PVC (polyvinyl chloride) resins, PVB (polyvinyl butyral) resins, and EVA (ethylene vinyl acetate) resins. In particular, epoxy resins with low moisture permeability are preferably used. Alternatively, two-liquid mixed resins can be used. Furthermore, adhesive sheets can also be used.

[0548] Display device DSP1A has a top-emission structure. The light-emitting device emits light toward substrate 110. Therefore, substrate 110 preferably uses a material with high visible light transmittance. For example, among the substrates applicable to substrate 310 and substrate BS, substrate 110 can be selected to have high visible light transmittance. The pixel electrode is made of a material that reflects visible light, and the counter electrode (common electrode 115) is made of a material that transmits visible light.

[0549] Note that the display device of one embodiment of the present invention may employ a bottom emission structure, in which light emitted by the light-emitting device is emitted toward the substrate 310, rather than a top emission structure. Note that in this case, the substrate 310 may be a substrate having high transmittance to visible light.

[0550] <Example 2 of Cross-Sectional Structure of Display Device> Next, explain Figure 27 The display device DSP1A is different when viewed from a cross section Figure 25A The structure example of the display device DSP1 is shown. Figure 29 The display device DSP1B shown is a modified example of the display device DSP1A, and is different from the display device DSP1A in the structure of transistors provided on the substrate 310 .

[0551] In addition, Figure 29 In the display device DSP1B of FIG. 1B , a substrate applicable to the substrate BS is preferably used as the substrate 310. In the description of the display device DSP1B, the substrate 310 is a glass substrate.

[0552] exist Figure 29In the display device DSP1B, a transistor 500p and a transistor 500d are formed over a substrate 310. In this specification, transistors 500p and 500d are collectively referred to as transistors 500. Furthermore, transistor 500p in the display device DSP1B corresponds to transistor 300p in the display device DSP1A, and transistor 500d in the display device DSP1B corresponds to transistor 300d in the display device DSP1A.

[0553] In addition, regarding the light emitting device 130 ( Figure 29 The light emitting device 130R, the light emitting device 130G and the light emitting device 130B) can be referred to Figure 27 Description of the light emitting device 130.

[0554] An insulator 574 is formed on the transistor 500, and an insulator 581 is formed on the insulator 574. In addition, an opening is provided in the insulator 574 and the insulator 581, and a conductor 596 is embedded in the opening. The insulator 574 and the insulator 581 will be described later. The conductor 596 can be referred to as Figure 27 Description of the conductor 596.

[0555] An insulator 592, an insulator 594, and a conductor 596 are formed on the insulator 581 and the conductor 540. For details about the insulator 592, the insulator 594, and the conductor 596, see Figure 27 Description of insulator 592 and insulator 594.

[0556] <<Structural Example of Transistor 500>> Figure 30A is a schematic cross-sectional view of a transistor 500 that may be included in the display device DSP1B in the channel length direction. Figure 30B : is a schematic cross-sectional view of the transistor 500 in the channel width direction. Figure 30A and Figure 30B , a structure in which the transistor 500 is provided on an insulator 512 instead of a substrate 310 is shown.

[0557] like Figure 30A and Figure 30BAs shown, for example, transistor 500 includes metal oxide 531a, metal oxide 531b, conductor 505, conductor 542a, conductor 542b, insulator 580, conductor 560, insulator 514, insulator 516, insulator 520, insulator 522, insulator 524, insulator 550, insulator 554, insulator 574, insulator 580, and insulator 581. Note that transistor 500 may not include all of the above components. For example, transistor 500 may not include insulator 520.

[0558] The conductor 505 (conductor 505a and conductor 505b) and the insulator 516 are arranged above the substrate (not shown). In particular, the conductor 505 is preferably provided in a manner embedded in the insulator 516. Specifically, the conductor 505a is preferably provided in a manner in contact with the bottom surface and side walls of the opening provided in the insulator 516. In addition, the conductor 505b is preferably provided in a manner embedded in the recess formed in the conductor 505a. Figure 30A and Figure 30B In the transistor 500 shown in the figure, the height of the top surface of the conductor 505 b is substantially equal to the height of the top surface of the conductor 505 a and the height of the top surface of the insulator 516 .

[0559] In addition, the metal oxide 531 and the conductor 560 are arranged in a region overlapping with the conductor 505. In addition, the metal oxide 531b is arranged on the metal oxide 531a. In addition, the conductor 542a and the conductor 542b are arranged separately from each other on the metal oxide 531b. In addition, the insulator 580 is arranged on the conductor 542a and the conductor 542b. In particular, the insulator 580 has an opening formed in the region between the conductor 542a and the conductor 542b. In addition, the conductor 560 is arranged in the opening. In addition, the insulator 550 is arranged between the metal oxide 531b, the conductor 542a, the conductor 542b, and the insulator 580 and the conductor 560. Here, as Figure 30A and Figure 30B As shown, the top surface of conductor 560 is preferably substantially aligned with the top surfaces of insulators 550 and 580. Note that below, conductors 505a and 505b may be collectively referred to as conductor 505. Metal oxides 531a and 531b may be collectively referred to as metal oxide 531. Conductors 542a and 542b may be collectively referred to as conductor 542.

[0560] In addition, if Figure 30AAs shown, region 543a is sometimes formed as a low-resistance region at or near the interface between metal oxide 531b and conductor 542a. Similarly, region 543b is sometimes formed as a low-resistance region at or near the interface between metal oxide 531b and conductor 542b. In this case, region 543a serves as one of the source and drain regions, while region 543b serves as the other. Furthermore, a channel formation region is formed in the region sandwiched between region 543a and region 543b.

[0561] By providing the conductor 542a (conductor 542b) in contact with the metal oxide 531, the oxygen concentration in the region 543a (region 543b) may be reduced. Furthermore, a metal compound layer containing the metal contained in the conductor 542a (conductor 542b) and the components of the metal oxide 531 may be formed in the region 543a (region 543b). In this case, the carrier concentration in the region 543a (region 543b) increases, and the region 543a (region 543b) becomes a low-resistance region.

[0562] exist Figure 30A and Figure 30B In the transistor 500 shown in FIG. 1 , the side surfaces of the conductor 542 a and the conductor 542 b on the side of the conductor 560 have a substantially vertical shape. Figure 30A and Figure 30B The transistor 500 shown is not limited thereto. The angle formed by the side surfaces and bottom surfaces of the conductors 542a and 542b may be greater than or equal to 10° and less than or equal to 80°, preferably greater than or equal to 30° and less than or equal to 60°. Furthermore, the opposing side surfaces of the conductors 542a and 542b may have multiple faces.

[0563] Note that in the transistor 500, two layers of metal oxide 531a and metal oxide 531b are stacked in and near the channel forming region (hereinafter also referred to as the channel formation region), but the present invention is not limited to this. For example, the metal oxide 531b may have a single-layer structure or a stacked structure of three or more layers. Alternatively, the metal oxide 531a and the metal oxide 531b may both have a stacked structure of two or more layers.

[0564] Here, the conductor 560 is used as the first gate electrode of the transistor (sometimes referred to as the top gate electrode or the front gate electrode), and the conductor 542a and the conductor 542b are used as the source electrode or the drain electrode, respectively. As described above, the conductor 560 is embedded in the opening of the insulator 580 and in the area between the conductor 542a and the conductor 542b. Here, the configuration of the conductor 560, the conductor 542a, and the conductor 542b is selected to be self-aligned with respect to the opening of the insulator 580. In other words, in the transistor 500, the first gate electrode can be configured in a self-aligned manner between the source electrode and the drain electrode. Thus, the conductor 560 can be formed in a manner without providing room for alignment, so that the area occupied by the transistor 500 can be reduced. Thus, a high-definition display device can be achieved. In addition, a display device with a narrow frame can be achieved.

[0565] In addition, the conductor 505 is sometimes used as a second gate electrode (sometimes referred to as a bottom gate electrode or back gate electrode). In this case, the threshold voltage V of the transistor 500 can be controlled by independently changing the potential applied to the conductor 505 without coupling it with the potential applied to the conductor 560. th In particular, by applying a negative potential to the conductor 505, the V of the transistor 500 can be further increased. th Therefore, when a negative potential is applied to the conductor 505 , the drain current when the potential applied to the conductor 560 is 0 V can be reduced compared to when no negative potential is applied to the conductor 505 .

[0566] The conductor 505 is preferably larger than the channel formation region in the metal oxide 531. In particular, Figure 30B As shown, it is preferable that the conductor 505 extends as a wiring to the area outside the end portion intersecting the metal oxide 531 in the channel width direction. In other words, it is preferable that the conductor 505 and the conductor 560 overlap with the insulator outside the side surface of the metal oxide 531 in the channel width direction.

[0567] like Figure 30A As shown, the conductor 560 preferably includes a conductor 560a provided inside the insulator 550 and a conductor 560b embedded inside the conductor 560a. Figure 30A and Figure 30B The conductor 560 is shown as a two-layer stacked structure, but the present invention is not limited thereto. For example, the conductor 560 may also have a single-layer structure or a stacked structure of three or more layers.

[0568] like Figure 30A and Figure 30BAs shown, transistor 500 preferably includes an insulator 512 disposed on a substrate (not shown), an insulator 514 disposed on insulator 512, an insulator 516 disposed on insulator 514, a conductor 505 disposed so as to be embedded in insulator 516, an insulator 520 disposed on insulator 516 and conductor 505, an insulator 522 disposed on insulator 520, and an insulator 524 disposed on insulator 522. A metal oxide 531a is preferably disposed on insulator 524.

[0569] In addition, if Figure 30A and Figure 30B As shown in FIG. 5 , it is preferable to arrange an insulator 554 between the insulator 524, the metal oxide 531a, the metal oxide 531b, the conductor 542a, the conductor 542b, and the insulator 580. Figure 30A and Figure 30B As shown, the insulator 554 is preferably in contact with the side surfaces of the insulator 550 , the top and side surfaces of the conductor 542 a , the top and side surfaces of the conductor 542 b , the metal oxide 531 a , the metal oxide 531 b , and the side and top surfaces of the insulator 524 .

[0570] An insulator 574 and an insulator 581 serving as interlayer films are preferably provided over the transistor 500. The insulator 574 is preferably in contact with the top surfaces of the conductor 560, the insulator 550, and the insulator 580. Furthermore, the top surface of the insulator 580 is preferably flattened.

[0571] Furthermore, it is preferable to provide a conductor 540 (conductor 540a and conductor 540b) that is electrically connected to transistor 500 and serves as a plug. Therefore, conductor 540 is provided so as to contact the inner walls of the openings of insulators 554, 580, 574, and 581. In particular, a structure can be employed in which a first conductor of conductor 540 is provided so as to contact the inner walls, and a second conductor of conductor 540 is provided on the side of the first conductor. Here, the height of the top surface of conductor 540 and the height of the top surface of insulator 581 can be substantially the same.

[0572] Specifically, for example, a first conductor of conductor 540a is provided so as to contact the inner wall of one of the two openings of insulator 581, insulator 574, insulator 580, and insulator 554, and a second conductor of conductor 540a is formed so as to contact the side surface thereof. Conductor 542a is located at a portion of the bottom of the opening, and conductor 540a is in contact with conductor 542a. Similarly, for example, a first conductor of conductor 540b is provided so as to contact the inner wall of the other of the two openings of insulator 581, insulator 574, insulator 580, and insulator 554, and a second conductor of conductor 540b is formed so as to contact the side surface thereof. Conductor 542b is located at a portion of the bottom of the opening, and conductor 540b is in contact with conductor 542b.

[0573] Furthermore, in transistor 500, a first conductor 540 and a second conductor 540 are stacked, but the present invention is not limited thereto. For example, conductor 540 may have a single-layer structure or a stacked structure of three or more layers. When a structure has a stacked structure, ordinal numbers are sometimes assigned to distinguish them according to the order in which they were formed.

[0574] like Figure 30B As shown, in the region of the metal oxide 531b that does not overlap with the conductor 542, that is, the channel formation region of the metal oxide 531, the side surfaces of the metal oxide 531 are covered by the conductor 560. As a result, the electric field of the conductor 560, which serves as the first gate electrode, easily acts on the side surfaces of the metal oxide 531. As a result, the channel formation region of the metal oxide 531 can be electrically surrounded by the electric field of the conductor 560. As a result, the on-state current and frequency characteristics of the transistor 500 can be improved.

[0575] <<Transistor Constituent Materials>> Next, constituent materials that can be used for the transistor 500 will be described.

[0576] [Metal oxide (oxide semiconductor)] In the transistor 500, a metal oxide serving as an oxide semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the metal oxide 531 (metal oxide 531a and metal oxide 531b) including the channel formation region. For example, a metal oxide having a band gap of 2 eV or greater, preferably 2.5 eV or greater, is preferably used as the metal oxide in the channel formation region of the metal oxide 531.

[0577] The metal oxide preferably contains at least indium or zinc. Indium and zinc are particularly preferred. Furthermore, it is preferred to further contain an element M. The element M can be one or more selected from aluminum, gallium, yttrium, tin, copper, vanadium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and antimony. In particular, the element M is preferably one or more selected from aluminum, gallium, yttrium, and tin. Furthermore, the element M more preferably contains one or both of gallium and tin.

[0578] As described above, the metal oxide 531 includes the metal oxide 531a and the metal oxide 531b on the metal oxide 531a. When the metal oxide 531a is provided under the metal oxide 531b, diffusion of impurities from a structure formed under the metal oxide 531a to the metal oxide 531b can be suppressed.

[0579] Furthermore, the metal oxide 531 preferably has a stacked structure of multiple oxide layers having different atomic ratios of metal atoms. For example, when the metal oxide 531 contains at least indium (In) and element M, the atomic ratio of element M among all the constituent elements of the metal oxide 531a is preferably greater than the atomic ratio of element M among all the constituent elements of the metal oxide 531b. Furthermore, the atomic ratio of element M to In in the metal oxide 531a is preferably greater than the atomic ratio of element M to In in the metal oxide 531b.

[0580] The energy of the conduction band bottom of the metal oxide 531a is preferably higher than that of the conduction band bottom of the metal oxide 531b. In other words, the electron affinity of the metal oxide 531a is preferably lower than that of the metal oxide 531b.

[0581] Here, the energy level of the conduction band bottom changes smoothly at the junction of the metal oxide 531a and the metal oxide 531b. In other words, the above situation can also be expressed as the energy level of the conduction band bottom at the junction of the metal oxide 531a and the metal oxide 531b changing continuously or being continuously joined. To this end, it is preferable to reduce the defect state density of the mixed layer formed at the interface between the metal oxide 531a and the metal oxide 531b.

[0582] Specifically, by making the metal oxide 531a and the metal oxide 531b contain a common element (as a main component) in addition to oxygen, a mixed layer with a low defect state density can be formed. For example, when the metal oxide 531b is In-Ga-Zn oxide (indium-gallium-zinc oxide), the metal oxide 531a can be In-Ga-Zn oxide, Ga-Zn oxide, or gallium oxide.

[0583] Specifically, the metal oxide 531a may have an atomic ratio of In:Ga:Zn = 1:3:4, 1:3:2, or 1:1:0.5. Furthermore, the metal oxide 531b may have an atomic ratio of In:Ga:Zn = 1:1:1, 4:2:3, or 3:1:2.

[0584] In this case, the main path for carriers is through metal oxide 531b. By adopting the above structure for metal oxide 531a, the defect state density at the interface between metal oxide 531a and metal oxide 531b can be reduced. Therefore, the effect of interface scattering on carrier conduction is reduced, and transistor 500 can achieve high on-state current and high frequency characteristics.

[0585] Furthermore, by forming the conductor 542 in contact with the metal oxide 531, the oxygen concentration near the conductor 542 in the metal oxide 531 may be reduced. Furthermore, a metal compound layer containing the metal contained in the conductor 542 and a component of the metal oxide 531 may be formed near the conductor 542 in the metal oxide 531. In this case, the carrier concentration in the region near the conductor 542 in the metal oxide 531 increases, and this region becomes a low-resistance region.

[0586] Furthermore, the thickness of the region of the metal oxide 531b that does not overlap with the conductor 542 is sometimes thinner than the thickness of the region that overlaps with the conductor 542. This occurs because a portion of the top surface of the metal oxide 531b is removed when forming the conductors 542a and 542b. When a conductive film, which will become the conductor 542, is deposited on the top surface of the metal oxide 531b, a low-resistance region may form near the interface with the conductive film. By removing the low-resistance region between the conductors 542a and 542b on the top surface of the metal oxide 531b, channel formation in this region can be suppressed.

[0587] [Conductor] As the conductor, for example, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum is preferably used. In addition, as the conductor, for example, an alloy composed of two or more of the above-mentioned metal elements or an alloy composed of two or more of the above-mentioned metal elements is preferably used. As the conductor, for example, tantalum nitride, titanium nitride, tungsten, a nitride comprising titanium and aluminum, a nitride comprising tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide comprising strontium and ruthenium, or an oxide comprising lanthanum and nickel is preferably used. In addition, tantalum nitride, titanium nitride, a nitride comprising titanium and aluminum, a nitride comprising tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide comprising strontium and ruthenium, or an oxide comprising lanthanum and nickel is a conductive material that is not easily oxidized or a material that maintains conductivity even when absorbing oxygen, so it is preferred. Alternatively, as the conductor, a semiconductor having high conductivity, such as polycrystalline silicon containing an impurity element (such as phosphorus), or a silicide (such as nickel silicide) may be used.

[0588] Furthermore, multiple conductors formed from the above materials may be stacked. For example, a laminated structure may be formed by combining a material containing the above metal element with a conductive material containing oxygen. Alternatively, a laminated structure may be formed by combining a material containing the above metal element with a conductive material containing nitrogen. Alternatively, a laminated structure may be formed by combining a material containing the above metal element, a conductive material containing oxygen, and a conductive material containing nitrogen.

[0589] As the conductor 505a serving as the second gate electrode, a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, NO, NO, etc.), and copper atoms is preferably used. Alternatively, a conductive material having a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules) is preferably used.

[0590] By using a conductive material that has the function of inhibiting hydrogen diffusion as the conductor 505a, it is possible to prevent impurities such as hydrogen contained in the conductor 505b from diffusing through the insulator 524 to the metal oxide 531. In addition, by using a conductive material that has the function of inhibiting oxygen diffusion as the conductor 505a, it is possible to prevent the conductor 505b from being oxidized and thus reducing its conductivity. Examples of conductive materials that have the function of inhibiting oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 505a can be a single layer or a stack of these conductive materials. For example, titanium nitride can be used as the conductor 505a.

[0591] As the conductor 505b, a conductive material mainly composed of tungsten, copper, or aluminum is preferably used. For example, tungsten can be used for the conductor 505b.

[0592] As the conductor 542 (conductor 542a and conductor 542b) used as the source electrode or drain electrode, a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium, and lanthanum is preferably used. In addition, as the conductor 542, an alloy containing two or more of the above-mentioned metal elements as components or an alloy combining two or more of the above-mentioned metal elements is preferably used. As the conductor 542, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are preferably used. In addition, tantalum nitride, titanium nitride, nitride containing titanium and aluminum, nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, oxide containing strontium and ruthenium, and oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that maintain conductivity even after absorbing oxygen, so they are preferred.

[0593] As the conductor 560a serving as the first gate electrode, it is preferable to use the above-mentioned conductor having the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (for example, NO, NO, etc.), and copper atoms. Alternatively, it is preferable to use a conductive material having the function of inhibiting the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules).

[0594] By providing the conductor 560a with the function of inhibiting oxygen diffusion, it is possible to prevent a decrease in conductivity caused by oxidation of the conductor 560b due to oxygen contained in the insulator 550. Examples of conductive materials that have the function of inhibiting oxygen diffusion include tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide. By providing the conductor 560a with a conductive material containing oxygen, oxygen released from the conductive material is easily supplied to the channel formation region.

[0595] Conductor 560b is preferably a conductive material primarily composed of tungsten, copper, or aluminum. Since conductor 560 also serves as wiring, it is preferable to use a highly conductive material. For example, a conductive material primarily composed of tungsten, copper, or aluminum can be used. Conductor 560b may also have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the aforementioned conductive materials can be used.

[0596] In addition, as the conductor 560, for example, indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, or indium tin oxide doped with silicon can be used. Furthermore, as this conductor, for example, indium gallium zinc oxide containing nitrogen can also be used. Using these materials can sometimes trap hydrogen contained in the metal oxide forming the channel. Alternatively, hydrogen intruding from an external insulator can sometimes be trapped.

[0597] Note that in Figure 30A and Figure 30B In the embodiment, the conductor 560 has a two-layer structure, but may also have a single-layer structure or a stacked-layer structure of three or more layers.

[0598] The conductors 540a and 540b used as the plugs are preferably made of a conductive material mainly composed of tungsten, copper, or aluminum.

[0599] When a laminated structure is employed as conductor 540, it is preferable to use the aforementioned conductors that have the function of inhibiting the diffusion of impurities such as water and hydrogen as the conductors in contact with conductor 542, insulator 554, insulator 580, insulator 574, and insulator 581. For example, tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, or ruthenium oxide are preferably used. Alternatively, a conductive material that has the function of inhibiting the diffusion of impurities such as water and hydrogen may be used in a single layer or in a laminated structure. By using such a conductive material, oxygen added to insulator 580 can be prevented from being absorbed by conductors 540a and 540b. Furthermore, impurities such as water and hydrogen can be prevented from entering metal oxide 531 from the layer above insulator 581 through conductors 540a and 540b.

[0600] [Insulator] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0601] The insulator 514 is preferably used as a blocking insulating film that prevents impurities such as water and hydrogen from entering the transistor 500 from the substrate side. Therefore, an insulating material that has the function of inhibiting the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, etc.), and copper atoms (such as copper atoms) (preferably, such impurities do not easily permeate) is preferably used as the insulator 514. Alternatively, an insulating material that has the function of inhibiting the diffusion of oxygen (e.g., either or both oxygen atoms and oxygen molecules) (preferably, such oxygen does not easily permeate) is preferably used.

[0602] As an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, a single layer or a stack of insulators containing one or more selected from boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium, and tantalum can be used. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide can be mentioned. In addition, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, an oxide containing aluminum and hafnium (hafnium aluminate) can be mentioned. In addition, as an insulator having the function of inhibiting the permeation of impurities such as water and hydrogen, and oxygen, for example, metal nitrides such as aluminum nitride, aluminum titanium nitride, titanium nitride, silicon oxynitride, and silicon nitride can be mentioned.

[0603] It is particularly preferable to use aluminum oxide or silicon nitride as the insulator 514. This can suppress the diffusion of impurities such as water and hydrogen from the substrate side closer to the insulator 514 to the transistor 500 side. Alternatively, for example, the diffusion of oxygen contained in the insulator 524 or the like to the substrate side closer to the insulator 514 can be suppressed.

[0604] Insulators 520 , 522 , and 524 serve as a second gate insulator.

[0605] Here, oxygen is preferably removed from the second gate insulator in contact with the metal oxide 531 by heating. In this specification, etc., oxygen removed by heating is sometimes referred to as excess oxygen. For example, silicon oxide or silicon oxynitride can be suitably used for the insulator 524 serving as the second gate insulator. Providing an insulator containing oxygen in contact with the metal oxide 531 can reduce oxygen vacancies in the metal oxide 531, thereby improving the reliability of the transistor 500.

[0606] Specifically, an oxide material from which a portion of oxygen is released by heating is preferably used as the insulator 524. An oxide from which oxygen is released by heating means that the amount of oxygen released in terms of oxygen atoms in TDS is 1.0×10 18 atoms / cm 3 above, preferably 1.0×10 19 atoms / cm 3 More than 2.0×10 19 atoms / cm 3 Above, or 3.0×10 20 atoms / cm 3 Furthermore, the surface temperature of the film during the TDS analysis is preferably in the range of 100° C. to 700° C., or 100° C. to 400° C.

[0607] Like the insulator 514 and the like, the insulator 522 is preferably used as a block insulating film for suppressing infiltration of impurities such as water and hydrogen from the substrate side into the transistor 500. For example, the insulator 522 preferably has lower hydrogen permeability than the insulator 524.

[0608] Furthermore, the insulator 522 preferably has a function of inhibiting the diffusion of oxygen (e.g., one or both of oxygen atoms and oxygen molecules) (preventing oxygen from easily permeating). For example, the oxygen permeability of the insulator 522 is preferably lower than that of the insulator 524. By providing the insulator 522 with the function of inhibiting the diffusion of impurities such as oxygen, water, and hydrogen, it is preferable because the diffusion of oxygen contained in the metal oxide 531 to the substrate side can be reduced. Furthermore, the reaction between the conductor 505 and oxygen contained in the insulator 524 and the metal oxide 531 can be suppressed.

[0609] The insulator 522 preferably uses an insulating material containing an oxide of one or both of aluminum and hafnium. Examples of the insulator containing an oxide of one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, and an oxide containing aluminum and hafnium (hafnium aluminate). When the insulator 522 is formed using such a material, the insulator 522 serves as a layer that prevents oxygen from being released from the metal oxide 531 and impurities such as hydrogen from being mixed into the metal oxide 531 from the surrounding area of ​​the transistor 500.

[0610] Alternatively, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above-mentioned insulators. Furthermore, these insulators may be nitrided. Silicon oxide, silicon oxynitride, or silicon nitride may also be stacked on the above-mentioned insulators for use.

[0611] As the insulator 522, for example, an insulator containing a so-called high-k material such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, lead zirconate titanate (PZT), strontium titanate (SrTiO3) or (Ba, Sr)TiO3 (BST) can be used in a single layer or a stacked layer. Alternatively, the insulator 522 can also use an insulator with a high relative dielectric constant such as an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, or a nitride containing silicon and hafnium. As the miniaturization or high integration of transistors progresses, problems such as leakage current caused by the thin filming of the gate insulator sometimes occur. By using a high-k material as an insulator used as a gate insulator, the gate potential of the transistor during operation can be reduced while maintaining the physical thickness.

[0612] Insulator 520 is preferably thermally stable. For example, silicon oxide and silicon oxynitride are preferred because of their thermal stability. Furthermore, by combining a high-k insulator with silicon oxide or silicon oxynitride, a laminated structure of insulator 520 can be formed that is thermally stable and has a high relative dielectric constant. Furthermore, materials that can be used for insulator 524 can also be used for insulator 520.

[0613] Furthermore, one or more of the insulators 520, 522, and 524 may have a stacked structure of two or more layers. In this case, the stacked structure is not limited to being formed of the same material, and may be a stacked structure formed of different materials.

[0614] The dielectric constants of the insulators 512, 516, 580, and 581 used as interlayer films are preferably lower than that of the insulator 514. Using materials with low dielectric constants for the interlayer films can reduce parasitic capacitance generated between wiring lines. Furthermore, the concentrations of impurities such as water and hydrogen in the films of the insulators 516, 580, and 581 are preferably reduced.

[0615] As the insulators 512, 516, 580, and 581, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, or silicon nitride can be used. Furthermore, as the insulators 512, 516, 580, and 581, for example, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, or silicon oxide having pores can be used. Silicon oxide and silicon oxynitride are particularly preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide having pores are preferred because they easily form regions containing oxygen that is released by heating. Furthermore, as the insulators 512, 516, 580, and 581, resins can be used. Furthermore, as materials that can be used for the insulators 512, 516, 580, and 581, the above materials can be appropriately combined.

[0616] As with the insulators 514 and 522, the insulators 554 and 574 preferably have a function of suppressing the diffusion of impurities such as water and hydrogen (for example, one or both of hydrogen atoms and hydrogen molecules). In other words, the insulators 554 and 574 are preferably used as a blocking insulating film that suppresses the impurities from being mixed into the transistor 500. Alternatively, the insulators 554 and 574 preferably have a function of suppressing the diffusion of oxygen (for example, one or both of oxygen atoms and oxygen molecules). For example, the oxygen permeability of the insulators 554 and 574 is preferably lower than that of the insulators 524, 550, and 580. In other words, the insulators 554 and 574 preferably have a function of suppressing oxygen from detaching from the metal oxide 531 and diffusing to the outside of the insulator 554 or above the insulator 580. Therefore, as the insulators 554 and 574, a material that can be used for the insulator 514 or 524 can be used.

[0617] Thus, by surrounding the insulator 524, the metal oxide 531, and the insulator 550 with the insulator 522, the insulator 554, and the insulator 574, impurities such as water and hydrogen can be suppressed from entering the transistor 500 from the outside. In addition, diffusion of oxygen from the inside of the transistor 500 to the outside can be suppressed.

[0618] The insulator 550 serves as a first gate insulator. The insulator 550 is preferably disposed in contact with the top surface of the metal oxide 531b. Silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, fluorine-doped silicon oxide, carbon-doped silicon oxide, carbon- and nitrogen-doped silicon oxide, or silicon oxide containing vacancies can be used as the insulator 550. Silicon oxide and silicon oxynitride are particularly preferred due to their thermal stability.

[0619] As with the insulator 524, the concentration of impurities such as water and hydrogen in the insulator 550 is preferably reduced. The thickness of the insulator 550 is preferably not less than 1 nm and not more than 20 nm.

[0620] Alternatively, an insulator may be provided between the insulator 580, the insulator 554, the conductor 542, the metal oxide 531b, and the insulator 550. For example, aluminum oxide or hafnium oxide is preferably used as the insulator. Providing the insulator can suppress the release of oxygen from the metal oxide 531b. 、 Oxygen is excessively supplied to the metal oxide 531 b and the conductor 542 is oxidized.

[0621] Alternatively, a metal oxide may be provided between the insulator 550 and the conductor 560. The metal oxide preferably suppresses oxygen diffusion from the insulator 550 to the conductor 560. This can suppress oxidation of the conductor 560 due to oxygen in the insulator 550.

[0622] The metal oxide is sometimes used as part of the gate insulator. Therefore, when silicon oxide or silicon oxynitride is used for the insulator 550, a metal oxide that is a high-k material with a high relative dielectric constant is preferably used as the metal oxide. By making the gate insulator have a stacked structure of the insulator 550 and the metal oxide, a stacked structure with thermal stability and a high relative dielectric constant can be formed. Therefore, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0623] Specifically, the oxide may be a metal oxide containing one or more metals selected from hafnium, aluminum, gallium, yttrium, zirconium, tungsten, titanium, tantalum, nickel, germanium, and magnesium. In particular, aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate), which is an insulator containing one or both of aluminum and hafnium oxides, is preferably used as the oxide.

[0624] Alternatively, a barrier insulating film against impurities such as water, hydrogen, and oxygen may be provided between the conductor 540 and the insulator 580, the insulator 574, and the insulator 581. This can prevent impurities such as water and hydrogen from entering the metal oxide 531 from the insulator 580 through the conductors 540a and 540b. Furthermore, absorption of oxygen in the insulator 580 by the conductors 540a and 540b can be prevented.

[0625] Although not shown, a conductor serving as wiring may be arranged in contact with the top surface of each of conductors 540a and 540b. The conductor serving as wiring is preferably a conductive material primarily composed of tungsten, copper, or aluminum. Furthermore, the conductor may have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the aforementioned conductive materials. Alternatively, the conductor may be formed so as to be embedded in an opening in an insulator.

[0626] <<Modification Example of Transistor 500>> Note that the structure of the transistor in the semiconductor device according to one embodiment of the present invention is not limited to Figure 30A and Figure 30B For example, as a transistor of a semiconductor device according to one embodiment of the present invention, a transistor 500 may be used. Figure 31 Transistor 500 is shown. Figure 32 The transistor 500 shown is Figure 30A and Figure 30B The modified example of transistor 500 shown in FIG. Figure 30A and Figure 30BThe transistor 500 shown is different in that it includes an insulator 551 and both the conductor 542a (conductor 542a1 and conductor 542a2) and the conductor 542b (conductor 542b1 and conductor 542b2) have a stacked-layer structure.

[0627] Conductor 542a has a laminated structure consisting of conductor 542a1 and conductor 542a2 on conductor 542a1, while conductor 542b has a laminated structure consisting of conductor 542b1 and conductor 542b2 on conductor 542b1. Conductors 542a1 and 542b1, which are in contact with metal oxide 531b, are preferably made of a conductor that is not easily oxidized, such as a metal nitride. This prevents excessive oxidation of conductors 542a and 542b due to oxygen in metal oxide 531b. Furthermore, conductors 542a2 and 542b2 are preferably made of a conductor having a higher conductivity than the metal layer of conductors 542a1 and 542b1. This allows conductors 542a and 542b to function as highly conductive wiring or electrodes. In this manner, a semiconductor device can be provided in which the conductors 542 a and 542 b serving as wiring or electrodes are provided in contact with the top surface of the metal oxide 531 serving as an active layer.

[0628] Metal nitrides are preferably used as the conductors 542a1 and 542b1. For example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, nitrides containing tantalum are particularly preferably used. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, or oxides containing lanthanum and nickel can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even when absorbing oxygen, and therefore are preferred.

[0629] Furthermore, the electrical conductivity of conductors 542a2 and 542b2 is preferably higher than that of conductors 542a1 and 542b1. For example, the thickness of conductors 542a2 and 542b2 is preferably greater than that of conductors 542a1 and 542b1. Any conductor that can be used for conductor 560b described above can be used as conductors 542a2 and 542b2. This structure can reduce the electrical resistance of conductors 542a2 and 542b2.

[0630] Therefore, for example, tantalum nitride or titanium nitride can be used as the conductor 542a1 and the conductor 542b1, and tungsten can be used as the conductor 542a2 and the conductor 542b2.

[0631] like Figure 31As shown, when viewing the channel length direction of transistor 500 from a cross-section, the distance between conductors 542a1 and 542b1 is preferably smaller than the distance between conductors 542a2 and 542b2. By adopting this structure, the distance between the source and drain can be further reduced, and the channel length can be correspondingly reduced. Consequently, the frequency characteristics of transistor 500 can be improved. Thus, by miniaturizing the semiconductor device, a semiconductor device with increased operating speed can be provided.

[0632] Insulator 551 is preferably an insulator that is not easily oxidized, such as a nitride. Insulator 551 contacts the side surfaces of each of conductors 542a2 and 542b2 and functions to protect conductors 542a2 and 542b2. Since it is exposed to an oxidizing atmosphere, insulator 551 is preferably an inorganic insulator that is not easily oxidized. Furthermore, since it is in contact with conductors 542a2 and 542b2, insulator 551 is preferably an inorganic insulat...

Claims

1. A semiconductor device comprising: a first transistor; a second transistor; A third transistor; a fourth transistor; a fifth transistor; a sixth transistor; The seventh transistor; The eighth transistor; a first capacitor; as well as The second capacitor, wherein one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the second transistor, one of the source and the drain of the seventh transistor, and one of the source and the drain of the eighth transistor, The other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor, One of the source and the drain of the first transistor is electrically connected to the gate of the second transistor, one of the source and the drain of the fourth transistor, and the second terminal of the first capacitor, The gate of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor, one of the source and the drain of the sixth transistor, the gate of the eighth transistor, and the first terminal of the second capacitor, Furthermore, a gate of the seventh transistor is electrically connected to a gate of the sixth transistor.

2. A semiconductor device comprising: a first transistor; a second transistor; A third transistor; a fourth transistor; a fifth transistor; a sixth transistor; The seventh transistor; The eighth transistor; a first capacitor; as well as The second capacitor, wherein one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the second transistor, one of the source and the drain of the seventh transistor, and one of the source and the drain of the eighth transistor, The other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor, One of the source and the drain of the first transistor is electrically connected to the gate of the second transistor, the gate of the second transistor, one of the source and the drain of the fourth transistor, and the second terminal of the first capacitor, The gate of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor, one of the source and the drain of the sixth transistor, the gate of the eighth transistor, and the first terminal of the second capacitor, Furthermore, a gate of the seventh transistor is electrically connected to a gate of the sixth transistor.

3. A semiconductor device comprising: a first transistor; a second transistor; A third transistor; a fourth transistor; a fifth transistor; a sixth transistor; The seventh transistor; The eighth transistor; The ninth transistor; a first capacitor; a second capacitor; as well as The third capacitor, wherein one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the second transistor, one of the source and the drain of the fourth transistor, one of the source and the drain of the eighth transistor, and one of the source and the drain of the ninth transistor, The other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor, One of the source and the drain of the first transistor is electrically connected to one of the source and the drain of the fifth transistor, the second terminal of the first capacitor, and the first terminal of the second capacitor, a gate of the second transistor being electrically connected to the other of the source and the drain of the fourth transistor and the second terminal of the second capacitor, The gate of the fifth transistor is electrically connected to one of the source and the drain of the sixth transistor, one of the source and the drain of the seventh transistor, the gate of the ninth transistor, and the first terminal of the third capacitor, Furthermore, a gate of the ninth transistor is electrically connected to a gate of the seventh transistor.

4. A semiconductor device comprising: a first transistor; a second transistor; A third transistor; a fourth transistor; a fifth transistor; a sixth transistor; The seventh transistor; The eighth transistor; a first capacitor; as well as The second capacitor, wherein one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the seventh transistor and one of the source and the drain of the eighth transistor, The other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, one of the source and the drain of the second transistor, and the first terminal of the first capacitor, One of the source and the drain of the first transistor is electrically connected to the gate of the second transistor, one of the source and the drain of the fourth transistor, and the second terminal of the first capacitor, The gate of the fourth transistor is electrically connected to one of the source and the drain of the fifth transistor, one of the source and the drain of the sixth transistor, the gate of the eighth transistor, and the first terminal of the second capacitor, Furthermore, a gate of the seventh transistor is electrically connected to a gate of the sixth transistor.

5. A semiconductor device comprising: a first transistor; a second transistor; A third transistor; as well as The first capacitor, wherein one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the second transistor, The other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor, Furthermore, one of a source and a drain of the first transistor is electrically connected to a gate of the second transistor and a second terminal of the first capacitor.

6. A semiconductor device comprising: a first transistor; a second transistor; A third transistor; as well as The first capacitor, wherein one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the second transistor, The other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor, And, one of the source and the drain of the first transistor is electrically connected to the gate of the second transistor, the other of the source and the drain of the second transistor, and the second terminal of the first capacitor.

7. A semiconductor device comprising: a first transistor; a second transistor; A third transistor; Buffer circuit; as well as The first capacitor, Wherein, the buffer circuit includes an input terminal and an output terminal, One of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the second transistor, The other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor, The input terminal of the buffer circuit is electrically connected to one of the source and the drain of the first transistor and the second terminal of the first capacitor, Furthermore, the output terminal of the buffer circuit is electrically connected to the gate of the second transistor.

8. A semiconductor device comprising: a first transistor; a second transistor; A third transistor; a fourth transistor; a first capacitor; as well as The second capacitor, wherein one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the second transistor and one of the source and the drain of the fourth transistor, The other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor and the first terminal of the first capacitor, One of a source and a drain of the first transistor is electrically connected to a gate of the fourth transistor, a second terminal of the first capacitor, and a first terminal of the second capacitor, Furthermore, a gate of the second transistor is electrically connected to the other of a source and a drain of the fourth transistor and a second terminal of the second capacitor.

9. A semiconductor device comprising: a first transistor; a second transistor; A third transistor; as well as The first capacitor, wherein one of the source and the drain of the third transistor is electrically connected to one of the source and the drain of the second transistor, The other of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, the gate of the second transistor, and the first terminal of the first capacitor, Also, one of a source and a drain of the first transistor is electrically connected to a second terminal of the first capacitor.

10. A display device, comprising: Driving circuit; as well as Display devices, The driving circuit comprises the semiconductor device according to any one of claims 1 to 9, Furthermore, the driving circuit has a function of transmitting a signal for displaying an image to the display device.

11. The display device according to claim 10, The display device comprises a light emitting device or a liquid crystal display device.

12. An electronic device comprising: The display device according to claim 11; as well as Frame.

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