Integrated circuit test method and system, computer equipment and readable storage medium

Abstract

The invention relates to an integrated circuit testing method and system, computer equipment and a readable storage medium, and the integrated circuit testing method comprises the steps: setting a first testing round and a second testing round, carrying out the normal testing in the first testing round, and carrying out the testing of the integrated circuit on the basis of a testing starting signal through a testing machine in the second testing round. Generating a second group of test excitation, sending the second group of test excitation to the integrated circuit on the corresponding test station for testing, and judging whether a second test result is abnormal or not according to a returned second group of output response signals; and under the condition that no abnormity occurs, the test machine generates a third group of test excitation, sends the third group of test excitation to the integrated circuit for spot test, and judges whether a third test result is abnormal or not according to a returned third group of output response signals so as to judge whether the test system is abnormal or not, so that the test efficiency of the test system is ensured, and the test efficiency of the test system is improved. And abnormal problems in the test process can be found in time.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to an integrated circuit testing method, system, computer device, and readable storage medium. Background Art

[0002] The rapid development of integrated circuit testing technology has made a huge contribution to the widespread application of integrated circuits. In each stage of integrated circuit development, production, and application, repeated inspections and tests are required to ensure the quality of integrated circuits and to ensure that integrated circuits that meet system requirements are produced.

[0003] In traditional technology, during the testing process of integrated circuits, due to problems such as insufficient machine operation sensitivity, abnormal test excitation, or weak performance of the integrated circuit itself, the tested integrated circuit is in a failed state after the test is completed; for example, during the test, the test voltage or test current provided to the tested integrated circuit by some test excitation exceeds the acceptable range of the integrated circuit itself, or some circuits of the integrated circuit are relatively weak due to production design and other reasons, and it is difficult to withstand the normal test voltage or test current, which causes the integrated circuit to fail after the test, and this failure is not reflected in the current test. Once this happens, the failed integrated circuit will be mixed into the normal integrated circuit through testing and enter the market, which will have a significant impact. Summary of the invention

[0004] Based on this, it is necessary to provide an integrated circuit testing method, system, computer device and readable storage medium to address the above technical problems.

[0005] In a first aspect, an embodiment of the present application provides an integrated circuit testing method, which is applied to an integrated circuit testing system, wherein the system includes a tester and a sorter, wherein the sorter is provided with at least one test station, an integrated circuit is provided on the test station, and the sorter is used to send at least one test start signal to the tester, wherein the method includes: In the case where the current round is the first test round, the test machine generates a first set of test stimuli based on the test start signal and sends the first set of test stimuli to the integrated circuit on the corresponding test station for testing, and determines whether the first test result is abnormal according to the returned first set of output response signals; When the current round is the second test round, the test machine generates a second set of test stimuli based on the test start signal and sends them to the integrated circuit on the corresponding test station for testing, and determines whether the second test result is abnormal based on the returned second set of output response signals; if no abnormality occurs, the test machine generates a third set of test stimuli and sends them to the integrated circuit for random testing, and determines whether the third test result is abnormal based on the returned third set of output response signals, so as to determine whether an abnormality occurs in the test system.

[0006] In one embodiment, when the current round is the second test round, when no abnormality occurs, the test machine generates a third set of test stimuli and sends them to the integrated circuit for sampling test, including: The test machine generates a third set of test stimuli based on the test start signal and sends the third set of test stimuli to the integrated circuit for sampling test.

[0007] In one embodiment, when the current round is the second test round, the test start signal includes a first test start signal and a second test start signal, and when no abnormality occurs, the test machine generates a corresponding third set of test stimuli and sends them to the integrated circuit for sampling test, including: In the case where the current round is the second test round, determining whether the test machine receives the first test start signal and the second test start signal within a preset time interval; If yes, then in the absence of an abnormality, the test machine generates a third set of test stimuli based on the test start signal and sends the third set of test stimuli to the integrated circuit for sampling testing.

[0008] In one embodiment, generating a corresponding second set of test stimuli based on the test start signal and sending the second set of test stimuli to the integrated circuit includes: Analyze the test start signal to determine the test item corresponding to the test start signal; According to the test items, a corresponding second set of test stimuli is generated and sent to the integrated circuit.

[0009] In one of the embodiments, the test items corresponding to the third group of test stimuli are included in the test items corresponding to the second group of test stimuli.

[0010] In one embodiment, when judging whether the first test result is abnormal according to the returned first set of output response signals, a first judgment standard is adopted; When judging whether the second test result is abnormal according to the returned second group of output response signals, a second judgment standard is adopted; When judging whether the third test result is abnormal according to the returned third group of output response signals, a third judgment standard is adopted; The first judgment standard is the same as the second judgment standard; The third judgment standard is the same as the first judgment standard and the second judgment standard, or the third judgment standard is different from the first judgment standard and the second judgment standard.

[0011] In one embodiment, the method further comprises: The test machine generates a sorting signal loaded with the sorting result based on the test result and sends it to the sorting machine, and the sorting machine sorts the integrated circuit after receiving the sorting signal; wherein, If the first test result or the second test result is abnormal, the corresponding sorting result is defective; If the first test result is normal or the second test result and the third test result are both normal, the corresponding sorting result is good product; If the second test result is normal and the third test result is abnormal, the corresponding sorting result is a special sample.

[0012] In a second aspect, an embodiment of the present application further provides an integrated circuit testing system, the system comprising a tester, a sorter and a setting module, the sorter being provided with at least one test station, the test station being provided with an integrated circuit, the sorter being used to send at least one test start signal to the tester; The setting module is used to set a first preset number of the first test round and a second preset number of the second test round; The test machine is used for, when the current round is the first test round, generating a first set of test stimuli based on a test start signal and sending the first set of test stimuli to the integrated circuit on the corresponding test station for testing, and judging whether the first test result is abnormal according to the returned first set of output response signals; When the current round is the second test round, the test machine generates a second set of test stimuli based on the test start signal and sends them to the integrated circuit on the corresponding test station for testing, and determines whether the second test result is abnormal based on the returned second set of output response signals; if no abnormality occurs, the test machine generates a third set of test stimuli and sends them to the integrated circuit for sampling testing, and determines whether the third test result is abnormal based on the returned third set of output response signals, so as to determine whether the test system has an abnormality.

[0013] In a third aspect, an embodiment of the present application further provides a computer device, comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the method as described in the first aspect above.

[0014] In a fourth aspect, an embodiment of the present application further provides a computer-readable storage medium, wherein the storage medium stores a computer program, wherein when the computer program is executed by a processor, the method described in the first aspect above is implemented.

[0015] The above-mentioned integrated circuit testing method, system, computer device and readable storage medium, by setting the first test round and the second test round, when the current round is the second test round, the test machine generates a second set of test stimuli based on the test start signal and sends it to the integrated circuit on the corresponding test station for testing, and judges whether the second test result is abnormal according to the returned second set of output response signals; when no abnormality occurs, the test machine generates a third set of test stimuli and sends it to the integrated circuit for sampling test, and judges whether the third test result is abnormal according to the returned third set of output response signals, so as to judge whether the test system is abnormal. The test machine analyzes and judges the output response of the tested integrated circuit, and avoids the situation that the tested integrated circuit is in a failed state after the test due to test environment problems such as insufficient machine operation sensitivity, abnormal test stimuli, or weak performance of the integrated circuit itself.

[0016] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings: Figure 1 is a structural block diagram of an integrated circuit testing system in one embodiment; Figure 2 is a schematic flow chart of an integrated circuit testing method in one embodiment; Figure 3 A schematic diagram of a flow chart of an integrated circuit testing method in a preferred embodiment; Figure 4 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0019] The integrated circuit testing method provided in the embodiment of the present application can be applied to Figure 1 In the integrated circuit test system shown in the figure, the system includes a tester 10 and a sorter 20. The tester 10 and the sorter 20 are connected via a test cable and a sorting signal line.

[0020] The sorting machine 20 is provided with at least one test station 21. In a normal test process, the sorting machine will load the tested integrated circuits to the test stations of the sorting machine one by one and send at least one test start signal to the test machine 10. The test machine 10 includes at least one test socket 11, and the test socket 11 is connected to the test stations 21 in a one-to-one correspondence. The test machine 10 obtains at least one test start signal, generates a test stimulus based on the test start signal, and sends it to the tested integrated circuit on the corresponding test station 21; the test machine 10 receives the output response signal of the test station 21, and the output response signal is generated by the tested integrated circuit based on the test stimulus; and based on the output response signal, sends a corresponding test end signal to the sorting machine to end the test, and analyzes the output response signal to determine whether the tested integrated circuit is abnormal.

[0021] In an exemplary embodiment, Figure 2 As shown, a method for testing an integrated circuit is provided. Figure 1 The test machine end in is used as an example for explanation. The test method of the present application sets in advance a first preset number of the first test round and a second preset number of the second test round, wherein the first test round can be understood as normal testing of the first preset number of integrated circuits, and the second test round can be understood as normal testing and sampling testing of the second preset number of integrated circuits, and the first test round and the second test round are performed alternately in sequence. The integrated circuit testing method of the present application includes the following steps 201 to 203. Among them: Step S201, when the current round is the first test round, the test machine generates a first set of test stimuli based on a test start signal and sends them to the integrated circuit on the corresponding test station for testing, and determines whether the first test result is abnormal based on the returned first set of output response signals.

[0022] Specifically, after the sorting machine is loaded with materials, the sorting machine sends a test start signal to the test socket corresponding to the test machine through the sorting signal line. The test machine generates a first set of test stimuli corresponding to the tested integrated circuit according to the received test start signal, and sends it to the tested integrated circuit on the corresponding test station through the test cable. The tested integrated circuit is tested after receiving the first set of test stimuli, and generates a corresponding first set of output response signals, which are sent to the test machine through the test cable. The test machine analyzes the first set of output response signals, compares the output response with the expected response, and determines whether the tested integrated circuit is abnormal.

[0023] At the same time, after receiving the first group of output response signals, the tester sends a test end signal to the communication port of the sorter through the sorting signal line to end the test of the current integrated circuit under test.

[0024] Step S202, when the current round is the second test round, the test machine generates a second set of test stimuli based on the test start signal and sends them to the integrated circuit on the corresponding test station for testing, and determines whether the second test result is abnormal based on the returned second set of output response signals.

[0025] Step S203, when the second test result is not abnormal, the test machine generates a third set of test stimuli and sends them to the integrated circuit for sampling test, and determines whether the third test result is abnormal based on the returned third set of output response signals to determine whether the test system is abnormal.

[0026] Specifically, if the second test result is abnormal, step S203 is not executed. If the second test result is not abnormal, the integrated circuit is sampled to obtain a third test result, and whether the test system is abnormal is determined based on the third test result.

[0027] In this step, when there is no abnormality in the second test result, that is, the test results corresponding to each test item are normal, and a failed item appears in the third test result of the random test, or the test results corresponding to each test item are not completely consistent with the random test results, it means that there may be a problem with the current test system; if the test results corresponding to each test item are consistent with the random test results, it means that the current test system is normal.

[0028] In this embodiment, a sampling test link is set in the normal test process. When the test system is testing, it repeatedly executes a complete test round including normal test and sampling test, that is, after each round of normal test of each M (M≥1) integrated circuit is completed, the subsequent N (N≥1) integrated circuits with no abnormal test results are sampled one by one. The sampling test refers to the normal test of the tested integrated circuit according to a set of test stimuli to obtain a set of test data, and then a set of test stimuli corresponding to each test item is input again to obtain another set of test data as the sampling test data of the tested integrated circuit. In this embodiment, by setting a certain proportion of sampling test links in the normal test link, it can ensure the normal test efficiency while timely discovering the failure of the tested integrated circuit due to problems such as insufficient machine operation sensitivity, abnormal test stimuli, and weak performance of the integrated circuit itself during the test process, thereby improving the stability of the integrated circuit test and avoiding the problem of chip failure due to test system failure.

[0029] In one of the embodiments, when the current round is the second test round, and when no abnormality occurs, the test machine generates a third set of test stimuli and sends them to the integrated circuit for sampling testing, including: the test machine generates a third set of test stimuli based on the test start signal and sends them to the integrated circuit for sampling testing.

[0030] In one embodiment, when the current round is the second test round, the test start signal includes a first test start signal and a second test start signal, and when no abnormality occurs, the test machine generates a corresponding second group of test stimuli and sends them to the integrated circuit for sampling test, including: when the current round is the second test round, determining whether the test machine receives the first test start signal and the second test start signal within a preset time interval; if so, then when no abnormality occurs, the test machine generates a third group of test stimuli based on the test start signal and sends it to the integrated circuit for sampling test.

[0031] In a preferred embodiment, a method for testing an integrated circuit is provided. Figure 1 The integrated circuit test system shown. When performing the test, the integrated circuit test system repeatedly executes a complete test round including normal test and sampling test, that is, after each round of normal test of each M (M≥1) tested integrated circuits (hereinafter referred to as tested products) is completed, the subsequent N (N≥1) tested products are subjected to normal test and sampling test one by one, such as Figure 3 As shown, specifically including the following: First, the sampling test process is controlled from within the test machine.

[0032] Step 1: During the test of the first M products under test, that is, in the first test round, after each product under test is loaded, the sorter sends a SOT sequence (test start signal) to the tester; after the tester detects the SOT sequence, it performs a normal test on the integrated circuit under test, that is, it sends a set of test stimuli to the integrated circuit under test at the corresponding test station for normal testing of the integrated circuit under test; then, after receiving the test data, the tester sends an EOT sequence (test end signal) to the sorter to end the test process of the current integrated circuit.

[0033] Step 2: After the test of the first M products under test is completed, the second test round begins. For the subsequent several products under test, after each product under test is loaded, the sorting machine sends the SOT sequence to the testing machine; after the testing machine detects the SOT sequence, it first sends a group of test stimuli to the tested integrated circuit of the corresponding test station for normal testing of the tested integrated circuit; then, after receiving the test data of the tested integrated circuit, the testing machine determines whether the test data is abnormal. If it is abnormal, the test is terminated. If there is no abnormality, a group of test stimuli is sent again to the tested integrated circuit of the corresponding test station for random testing of the tested product; and then, after receiving the random test data of the tested product, the EOT sequence is sent to the sorting machine to end the test process of the current product under test; in this way, after random testing of N products under test is performed cumulatively, the current round of testing process is terminated.

[0034] Second, the sampling test process is controlled through the inside of the sorting machine.

[0035] Step 1: During the test of the first M integrated circuits, that is, in the first test round, after each integrated circuit is loaded, the sorter sends a SOT sequence to the tester; so that the tester performs normal testing on the tested integrated circuit after detecting the SOT sequence, that is, sends a set of test stimuli to the tested integrated circuit at the corresponding test station for normal testing of the tested integrated circuit; and then after the test of the tested integrated circuit is completed, the sorter waits for the EOT sequence sent by the tester after receiving the test data, so as to end the current integrated circuit test after receiving the EOT sequence.

[0036] Step 2: After the test of the first M integrated circuits is completed, the second test round is entered. For the subsequent integrated circuits, after each integrated circuit is loaded, the sorter continuously sends two groups of SOT sequences to the tester, and the time interval between the two groups of SOT sequences is less than the preset time range (such as less than 100ms); so that after the tester detects the two groups of SOT sequences with a time interval less than the preset time range, it first sends a group of test stimuli to the tested integrated circuit of the corresponding test station for normal testing of the tested integrated circuit; then, after receiving the test data of the tested integrated circuit, the tester determines whether the test data is abnormal. If it is abnormal, the test is terminated. If there is no abnormality, a group of test stimuli is sent again for sampling test of the tested integrated circuit; and then after the sampling test is completed, the sorter waits for the EOT sequence sent by the tester after receiving the sampling data, so as to terminate the current integrated circuit test after receiving the EOT sequence; in this way, after the sampling test of N integrated circuits is cumulatively performed, the current round of testing process is terminated. In this case, the tester is configured to wait for a preset time after detecting the SOT sequence; if another set of SOT sequences is not detected again within the preset time, it enters normal testing; if another set of SOT sequences is detected again within the preset time, it enters random sampling testing.

[0037] In one embodiment, generating a corresponding second set of test stimuli based on the test start signal and sending them to the integrated circuit includes: parsing the test start signal to determine the test item corresponding to the test start signal; generating a corresponding second set of test stimuli according to the test item and sending them to the integrated circuit.

[0038] Specifically, the test machine analyzes the test start signal to determine the test item corresponding to the test start signal. The test item includes, for example, one or more of the following test items: open-short circuit test, leakage current test, static working current test, dynamic working current test, and functional test, etc. The test machine generates a corresponding second set of test stimuli according to the test item and sends it to the integrated circuit under test.

[0039] In one of the embodiments, the test items corresponding to the third group of test stimuli are included in the test items corresponding to the second group of test stimuli.

[0040] Specifically, in the random test, the test items corresponding to the third group of test stimuli can be exactly the same as the test items corresponding to the second group of test stimuli, or they can be a subset of the test items corresponding to the second group of test stimuli, and only some items are tested, such as open and short circuits, to improve test efficiency.

[0041] In one embodiment, when judging whether the first test result is abnormal based on the first group of returned output response signals, a first judgment standard is adopted; when judging whether the second test result is abnormal based on the second group of returned output response signals, a second judgment standard is adopted; when judging whether the third test result is abnormal based on the third group of returned output response signals, a third judgment standard is adopted; the first judgment standard is the same as the second judgment standard; the third judgment standard is the same as the first judgment standard and the second judgment standard, or the third judgment standard is different from the first judgment standard and the second judgment standard.

[0042] Specifically, the judgment of the first test result, the second test result, and the third test result is obtained by comparing the first group of output response signals, the second group of output response signals, and the third group of output response signals with the first judgment standard, the second judgment standard, and the third judgment standard, respectively, and then analyzing and judging the results. The first judgment standard, the second judgment standard, and the third judgment standard are the expected responses corresponding to the first group of test stimuli, the second group of test stimuli, and the third group of test stimuli, respectively, which can be specific values ​​or value ranges, and then the corresponding test results can be obtained by comparing the output response signals of each group according to the first judgment standard, the second judgment standard, and the third judgment standard.

[0043] Among them, the first judgment standard is exactly the same as the second judgment standard, and the first judgment standard and the second judgment standard can provide a unified standard for judging whether it is a good product; the third judgment standard can be the same as the first judgment standard and the second judgment standard, or it can be different from the first judgment standard and the second judgment standard. The third judgment standard is mainly used to provide a judgment standard for whether it is a special sample that indicates an abnormality in the test system.

[0044] Furthermore, in order to improve the accuracy of alarms for test system abnormalities, the third test results in which the third group of output response signals are within the critical conditions of the third judgment standard may be ignored instead of all being alarmed, thereby avoiding abnormal alarms for the test system.

[0045] In one embodiment, if Figure 3 As shown, the method also includes: the testing machine generates a sorting signal for loading a sorting result based on the test result and sends it to the sorting machine, and the sorting machine sorts the integrated circuit after receiving the sorting signal; wherein, if the first test result or the second test result is abnormal, the corresponding sorting result is a defective product; if the first test result is normal or the second test result and the third test result are both normal, the corresponding sorting result is a good product; if the second test result is normal and the third test result is abnormal, the corresponding sorting result is a special sample.

[0046] The integrated circuit testing method constructed in the above embodiments can be applied to the testing process at different stages in the integrated circuit production process, such as CP (Chip Probing) test and FT (Final Test) test, which is not limited here.

[0047] In one embodiment, an integrated circuit testing system is provided. Figure 1 As shown, the system includes a tester and a sorter, and the tester and the sorter are connected via a sorting signal line. The sorter is provided with at least one test station, on which the tested integrated circuit is installed, and the sorter is used to send at least one test start signal to the tester. The tester is configured to implement the integrated circuit testing method as described in the above embodiments.

[0048] In one of the embodiments, the testing machine also includes a setting module.

[0049] The setting module is used to set a first preset number for a first test round and a second preset number for a second test round.

[0050] Optionally, the setting module can also be used to set a third judgment standard, which is used to judge whether the third test result is abnormal in the second test round. By setting the third judgment standard by the setting module, flexible monitoring of abnormalities of the test system can be achieved.

[0051] The test machine is used for, when the current round is the first test round, the test machine generates a first group of test stimuli based on a test start signal and sends them to the integrated circuit on the corresponding test station for testing, and determines whether the first test result is abnormal based on the returned first group of output response signals; when the current round is the second test round, the test machine generates a second group of test stimuli based on a test start signal and sends them to the integrated circuit on the corresponding test station for testing, and determines whether the second test result is abnormal based on the returned second group of output response signals; when no abnormality occurs, the test machine generates a third group of test stimuli and sends them to the integrated circuit for sampling testing, and determines whether the third test result is abnormal based on the returned third group of output response signals, so as to determine whether the test system has an abnormality.

[0052] After receiving the test data and the sampling data, the testing machine can compare the test data or the sampling data with the expected response, determine whether any test item in the test data or the sampling data has failed, and obtain the test results and the sampling results; then the testing machine generates a sorting signal based on the test results of the product under test and sends it to the sorting machine, so that the sorting machine can sort the product under test according to the sorting signal.

[0053] In addition, for the products with normal test results in the last N tests in each round, the test machine will analyze and process the test results and sampling results of each product in real time or upload them to the data analysis platform, and then compare the test results and sampling results of the same product through the test machine or the data analysis platform to obtain the alarm results. If the test results corresponding to each test item are normal, but there are failure items in the sampling results, or the test results corresponding to each test item are not completely consistent with the sampling results, it means that the current test system may have the aforementioned problems and an alarm message is generated; if the test results corresponding to each test item are consistent with the sampling results, it means that the current test system is normal and no alarm message is generated.

[0054] The test system can directly perform corresponding actions according to the alarm results. For example, when an alarm message is detected, the test system is controlled to stop the test process and generate an alarm prompt through human-computer interaction; if no alarm message is detected, the test system is controlled to continue the current test process.

[0055] In an exemplary embodiment, a computer device is provided. The computer device may be a server, and its internal structure diagram may be as shown in FIG. Figure 4 As shown. The computer device includes a processor, a memory, an input / output interface (Input / Output, referred to as I / O) and a communication interface. Among them, the processor, the memory and the input / output interface are connected through a system bus, and the communication interface is connected to the system bus through the input / output interface. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store test data. The input / output interface of the computer device is used to exchange information between the processor and an external device. The communication interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, an integrated circuit testing method is implemented.

[0056] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0057] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in any of the above integrated circuit testing method embodiments are implemented.

[0058] Those of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in the present application can include at least one of non-volatile and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory or optical memory, etc. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM).

[0059] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0060] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. An integrated circuit testing method, applied to an integrated circuit testing system, the system comprising a tester and a sorter, the sorter being provided with at least one test station, the test station being provided with an integrated circuit, the sorter being used to send at least one test start signal to the tester, characterized in that: The method comprises: In the case where the current round is the first test round, the test machine generates a first set of test stimuli based on the test start signal and sends the first set of test stimuli to the integrated circuit on the corresponding test station for testing, and determines whether the first test result is abnormal according to the returned first set of output response signals; When the current round is the second test round, the test machine generates a second set of test stimuli based on the test start signal and sends them to the integrated circuit on the corresponding test station for testing, and determines whether the second test result is abnormal based on the returned second set of output response signals; if no abnormality occurs, the test machine generates a third set of test stimuli and sends them to the integrated circuit for random testing, and determines whether the third test result is abnormal based on the returned third set of output response signals, so as to determine whether an abnormality occurs in the test system.

2. The method according to claim 1, characterized in that: In the case where the current round is the second test round, in the case where no abnormality occurs, the test machine generates a third set of test stimuli and sends them to the integrated circuit for sampling test, including: The test machine generates a third set of test stimuli based on the test start signal and sends the third set of test stimuli to the integrated circuit for sampling test.

3. The method according to claim 1, characterized in that In the case where the current round is the second test round, the test start signal includes a first test start signal and a second test start signal, and in the case where no abnormality occurs, the test machine generates a corresponding third set of test stimuli and sends them to the integrated circuit for sampling test, including: In the case where the current round is the second test round, determining whether the test machine receives the first test start signal and the second test start signal within a preset time interval; If yes, then in the absence of an abnormality, the test machine generates a third set of test stimuli based on the test start signal and sends the third set of test stimuli to the integrated circuit for sampling testing.

4. The method according to claim 1, characterized in that: The generating a corresponding second set of test stimuli based on the test start signal and sending the second set of test stimuli to the integrated circuit comprises: Analyze the test start signal to determine the test item corresponding to the test start signal; According to the test items, a corresponding second set of test stimuli is generated and sent to the integrated circuit.

5. The method according to claim 4, characterized in that The test items corresponding to the third group of test stimuli are included in the test items corresponding to the second group of test stimuli.

6. The method according to claim 1, characterized in that The method further comprises: When judging whether the first test result is abnormal according to the returned first group of output response signals, a first judgment standard is adopted; When judging whether the second test result is abnormal according to the returned second group of output response signals, a second judgment standard is adopted; When judging whether the third test result is abnormal according to the returned third group of output response signals, a third judgment standard is adopted; The first judgment standard is the same as the second judgment standard; The third judgment standard is the same as the first judgment standard and the second judgment standard, or the third judgment standard is different from the first judgment standard and the second judgment standard.

7. The method according to any one of claims 1 to 6, characterized in that: The method further comprises: The test machine generates a sorting signal loaded with the sorting result based on the test result and sends it to the sorting machine, and the sorting machine sorts the integrated circuit after receiving the sorting signal; wherein, If the first test result or the second test result is abnormal, the corresponding sorting result is defective; If the first test result is normal or the second test result and the third test result are both normal, the corresponding sorting result is good product; If the second test result is normal and the third test result is abnormal, the corresponding sorting result is a special sample.

8. An integrated circuit testing system, characterized in that: The system comprises a tester, a sorter and a setting module, wherein the sorter is provided with at least one test station, an integrated circuit is installed on the test station, and the sorter is used to send at least one test start signal to the tester; The setting module is used to set a first preset number of the first test round and a second preset number of the second test round; The test machine is used for, when the current round is the first test round, generating a first set of test stimuli based on a test start signal and sending the first set of test stimuli to the integrated circuit on the corresponding test station for testing, and judging whether the first test result is abnormal according to the returned first set of output response signals; In the case where the current round is the second test round, the test machine generates a second set of test stimuli based on the test start signal and sends them to the integrated circuit on the corresponding test station for testing, and determines whether the second test result is abnormal according to the returned second set of output response signals; When no abnormality occurs, the test machine generates a third set of test stimuli and sends them to the integrated circuit for sampling test, and determines whether the third test result is abnormal based on the returned third set of output response signals to determine whether the test system has an abnormality.

9. A computer device comprising a memory and a processor, wherein the memory stores a computer program, wherein: When the processor executes the computer program, the steps of the method according to any one of claims 1 to 7 are implemented.

10. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 are implemented.

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