Vehicle MCU management system
By designing a vehicle MCU management system that does not rely on the central processor, using SMU and streamlined subset processor for clock and power management, the existing system's low flexibility and insufficient security in low power mode is solved, and higher flexibility, security and resource efficiency are achieved.
Patent Information
- Application Number
- CN202411900476.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-05-13
AI Technical Summary
The management system of existing automotive MCUs is not very flexible in low-power mode and needs to be improved in safety. The configuration process depends on the central processor, which is prone to system errors due to CPU logic errors or data link problems.
A management system for vehicle MCU is designed, including storage module, core module, register module, clock management module, power management module and interrupt management module. The core module is implemented using SMU, and clock and power management is managed by streamlining the subset processor and comparator. The configuration process does not depend on the central processor.
It improves the flexibility and security of the management system in low-power mode, reduces the logical resource usage of core modules, reduces cost and power consumption, and enhances the reliability and security of the system.
Smart Images
Figure CN119987252A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of vehicle technology, and in particular to a management system of a vehicle MCU. Background Art
[0002] In the modern automobile industry, microcontroller units (MCUs), as one of the cores of automotive electronic control, play an important role in the performance and reliability of vehicles. The requirements for power consumption control and functional safety of automotive MCUs are much higher than those of ordinary MCUs. Among them, power consumption control can reduce the standby power consumption of the entire system and extend the service life, while functional safety is crucial during the driving process of the car. Low power consumption is mainly achieved through clock and power management. At present, automotive MCUs usually design a management system to manage the switching of clocks, power supplies and low power consumption scenarios.
[0003] There are two implementation methods in the related technology: the first is a register-type management module, in which the management module is only responsible for the minimum startup process, and the frequency division operation, clock calibration operation, power supply operation, etc. are performed by the CPU (Central Processing Unit). In this method, the overall configuration process depends on the CPU. When a logical error occurs in the CPU or a problem occurs in the data link from the CPU to the configuration module, it may cause a system error. In addition, due to the fact that the CPU generally turns off the power under low power consumption conditions, the flexibility of this method in low power consumption mode is not high; the second is that a separate backup small core handles the entire configuration process, and the management module works as a slave under its bus. In this method, the backup small core is a complete core with a high logic resource occupancy, high power consumption in low power consumption mode, and security needs to be improved. Summary of the invention
[0004] In order to solve the above technical problems, the present disclosure provides a management system for a vehicle MCU.
[0005] The present disclosure provides a management system for a vehicle MCU, including:
[0006] Storage module, core module, register module, clock management module, power management module and interrupt management module;
[0007] The core module includes a master SMU core, a slave SMU core, a delay device and a comparator, and the SMU adopts a simplified subset processor;
[0008] The input content of the main SMU core includes bus return and / or interrupt input, and the output content includes a first bus operation output; the first bus operation output is used as the output of the core module to be transmitted to the clock management module, the power management module and the interrupt management module for control;
[0009] The input content from the SMU core includes the bus return through the delay device and / or the interrupt input through the delay device, and the output content includes a second bus operation output;
[0010] Wherein, the interrupt input includes an input of an external error signal and / or an input of an external bus through the register module, and the bus return includes data read from the storage module, and / or data read from the clock management module, the power management module and the interrupt management module;
[0011] The comparator is used to detect the first bus operation output through the second bus operation output to determine whether to perform error management;
[0012] The clock management module is used for clock and reset control, clock monitoring and security management;
[0013] The power management module is used for PMU management and power correction operations;
[0014] The interrupt management module is used to configure an interrupt mapping vector to map the interrupt to a corresponding address of the storage module.
[0015] Optionally, the master SMU core and the slave SMU core both adopt the following structure:
[0016] PC pointer, first read unit, decoding unit, general register, second read unit, execution unit, write back unit;
[0017] Wherein, the first reading unit is used to read the instruction according to the PC pointer and the storage module and send it to the decoding unit;
[0018] The decoding unit is used to decode the instruction and send it to the second reading unit;
[0019] The second reading unit is used to read the general register according to the instruction to obtain data to be processed;
[0020] The execution unit is used to perform an execution operation according to the data to be processed;
[0021] The write-back unit is used to write the return value of the execution operation back to the general register and update the PC pointer;
[0022] The SMU uses a two-state state machine, where the state is a read state or an execute state.
[0023] Optionally, the system further comprises:
[0024] The watchdog module is used to monitor the state changes of the SMU. When the duration of the state machine of the SMU in any state is greater than or equal to the preset duration, an alarm signal is triggered to perform a reset operation.
[0025] Optionally, the clock management module is specifically used to:
[0026] Monitor the external clock source, internal clock source and phase-locked loop output through an asynchronous clock to obtain a clock monitoring result;
[0027] When the clock monitoring result is abnormal, the clock monitoring result is reported to the MCU error manager and the interrupt management module.
[0028] Optionally, each PMU is internally integrated with a high voltage and a low voltage detection module, and the power management module is specifically used for:
[0029] When the detection results of the high voltage and low voltage detection modules exceed a preset range, the detection results are reported to the MCU error manager and the interrupt management module.
[0030] Optionally, when an interrupt is triggered, the PC pointer jumps to a corresponding position and runs a program corresponding to the interrupt.
[0031] Optionally, the core module is specifically used for:
[0032] In response to the program running being completed, a WFI instruction is called to switch the master SMU core and the slave SMU core to a low power consumption mode.
[0033] Optionally, the delay device is specifically used for:
[0034] The bus return and / or the interrupt input is delayed by 3 cycles.
[0035] Optionally, the number of general registers is 4.
[0036] Optionally, the execution unit is connected to the clock management module, the power management module and the interrupt management module respectively through a bus.
[0037] Compared with the prior art, the technical solution provided by the embodiments of the present disclosure has the following advantages: the management system includes a storage module, a core module, a register module, a clock management module, a power management module and an interrupt management module to realize the clock and power management of the MCU. Compared with the register-type management module, the configuration process does not rely on the central processing unit, which improves flexibility and security. The SMU adopts a streamlined subset processor. By using a streamlined instruction core, compared with the method of separately backing up small core processing, the logic resource occupancy of the core module is reduced, and the cost and power consumption are reduced. Moreover, based on the SMU adopting a streamlined subset processor, it can support the core module to adopt a main SMU core, a slave SMU core, a delay device and a comparator, and then the outputs of the main SMU core and the slave SMU core are detected and error managed through the comparator, while meeting the cost and power consumption requirements, the reliability of the logic is improved, thereby improving the security of the system. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.
[0039] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0040] Figure 1 A schematic diagram of a vehicle MCU management system provided by an embodiment of the present disclosure;
[0041] Figure 2 A schematic diagram of a core module provided by an embodiment of the present disclosure;
[0042] Figure 3 A schematic diagram of an SMU core provided by an embodiment of the present disclosure;
[0043] Figure 4 A schematic diagram of an interrupt wake-up process provided by an embodiment of the present disclosure. DETAILED DESCRIPTION
[0044] In order to more clearly understand the above-mentioned objectives, features and advantages of the present disclosure, the scheme of the present disclosure will be further described below. It should be noted that the embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict.
[0045] In the following description, many specific details are set forth to facilitate a full understanding of the present disclosure, but the present disclosure may also be implemented in other ways different from those described herein; it is obvious that the embodiments in the specification are only part of the embodiments of the present disclosure, rather than all of the embodiments.
[0046] Figure 1 A schematic diagram of a vehicle MCU management system provided by an embodiment of the present disclosure is shown in FIG. Figure 1 As shown, the management system of the vehicle MCU provided by the embodiment of the present disclosure may include: a storage module, a core module, a register module, a clock management module, a power management module and an interrupt management module.
[0047] The core module is used to manage the MCU for system configuration and low-power settings according to bus returns and / or interrupt inputs, such as configuring the MCU's clock and power supply, including but not limited to frequency division operations, clock calibration operations, power supply operations, etc., and for executing interrupt programs when interrupts are triggered. The core module is implemented using SMU (System Management Unit).
[0048] The clock management module is used for clock and reset control, clock monitoring and security management.
[0049] The power management module is used for PMU (Power Management Unit) management and power calibration operations.
[0050] The interrupt management module is used to configure the interrupt mapping vector to map the interrupt to the corresponding address of the storage module.
[0051] Register module, registers used to trigger interrupts.
[0052] The storage module is used to store program instructions. Optionally, the storage module uses an EEPROM (Electrically Erasable Programmable Read-Only Memory), wherein the EEPROM is configured through a JTAG (Joint Test Action Group) interface, and the SMU executes the program in the EEPROM to implement system configuration operations.
[0053] In this embodiment, Figure 2 As shown, the core module includes a master SMU core, a slave SMU core, a delay device and a comparator.
[0054] The input content of the main SMU core includes bus return and / or interrupt input, and the output content includes the first bus operation output. The first bus operation output is used as the output of the core module to be transmitted to the clock management module, the power management module and the interrupt management module for control.
[0055] The input content from the SMU core includes a bus return through the delay device and / or an interrupt input through the delay device, and the output content includes a second bus operation output.
[0056] Among them, the interrupt input includes the input of the external error signal and / or the input of the external bus through the register module, and the bus return includes the data read from the storage module, and / or the data read from the clock management module, the power management module and the interrupt management module.
[0057] The comparator is used to detect the first bus operation output through the second bus operation output to determine whether to perform error management, thereby improving the reliability of logic and the security of the management system.
[0058] The logic of the master SMU core and the slave SMU core are the same, and the slave SMU core is delayed compared to the master SMU core. Optionally, the delay device is specifically used to delay the bus return and / or interrupt input by 3 cycles to reduce the susceptibility of common mode failure to the clock power supply. Figure 2 As shown, the interface of the main SMU core is directly connected to the outside, the interface of the slave SMU core is not directly connected to the outside, the second bus operation output of the slave SMU core is connected to the comparator to be compared with the first bus operation output of the main SMU core, and when the comparison result of the comparator is abnormal, a system-level reset operation is performed.
[0059] In this embodiment, the SMU adopts a reduced subset processor, for example, the SMU is a reduced subset processor that applies the RISC-V instruction set, and uses a backup power supply and a backup clock during operation.
[0060] An example of an instruction list is as follows:
[0061]
[0062]
[0063] Due to the use of a streamlined subset processor with fewer instructions and a smaller area, the logic resource usage is reduced compared to the method of separate backup small core processing. On this basis, it can support the use of the core modules of the master SMU core, slave SMU core, delay device and comparator as described above, while improving the security of the management system.
[0064] The SMU core is described below.
[0065] In one embodiment of the present disclosure, Figure 3 As shown, the master SMU core and the slave SMU core both adopt the following structure: PC pointer, first read unit, decoding unit, general register, second read unit, execution unit, and write back unit.
[0066] The first reading unit is used to read the instruction according to the PC pointer and the storage module and send it to the decoding unit.
[0067] The decoding unit is used to decode the instruction and send it to the second reading unit.
[0068] The second reading unit is used to read the general register according to the instruction to obtain the data to be processed.
[0069] The execution unit is used to perform execution operations according to the data to be processed. The execution unit is connected to the clock management module, the power management module and the interrupt management module through a bus.
[0070] The write-back unit is used to write the return value of the executed operation back to the general register and update the PC pointer.
[0071] Optionally, the number of general purpose registers is 4.
[0072] Among them, the SMU adopts a two-state state machine to save resources, and the state is a read state or an execution state.
[0073] As an example, when the SMU is processing, it reads the instruction from the corresponding PC pointer, decodes the data after reading it, and sends it to the execution unit. Among them, the general register is read according to the instruction, the instruction is executed after the data is read, and the return value is written back to the general register and the PC pointer is updated after the execution is completed. When the interrupt is triggered, the SMU automatically updates the PC pointer to the specified configuration location and executes the program.
[0074] In one embodiment of the present disclosure, Figure 1 As shown, the management system further includes: a watchdog module. The watchdog module is used to monitor the state change of the SMU, and when the duration of the state machine of the SMU in any state is greater than or equal to a preset duration, an alarm signal is triggered to perform a reset operation.
[0075] As an example, in a non-low power state, the watchdog module monitors the state changes of the SMU and obtains a preset fixed value from the EEPROM. When the SMU state machine is in a reading state, or the time in the execution state is greater than or equal to the fixed value, an alarm signal is triggered and a forced reset of the MCU system is triggered to ensure system safety, further improving the security of the system.
[0076] In this embodiment, the SMU core is connected to a proprietary bus, and all data and address link registers of the bus link are triple-module redundant, and the transmission of data and addresses themselves adopts encryption and decryption design. The SMU core is connected to the clock management module, power management module and interrupt management module through the proprietary bus, and each module has independent configuration registers and execution units.
[0077] In one embodiment of the present disclosure, the clock management module is specifically used to: monitor the external clock source, the internal clock source and the phase-locked loop output through an asynchronous clock to obtain a clock monitoring result; when the clock monitoring result is abnormal, report the clock monitoring result to the MCU error manager and the interrupt management module.
[0078] In this embodiment, the objects managed by the clock management module include external clock sources, internal clock sources, phase-locked loop outputs, clock detection units, gated clocks, and reset control units, wherein the external clock source includes an external crystal oscillator OSC, and the internal clock source includes an internal oscillator IRC (e.g., SIRC, FIRC0, 1). Each basic clock (e.g., external crystal oscillator OSC, internal oscillator IRC, and phase-locked loop output) is monitored by the clock monitoring unit using an asynchronous clock. When the monitoring result is an abnormality, the clock monitoring result is reported to the MCU error manager and the interrupt management module to trigger interrupt control, wherein the MCU error manager belongs to an external interrupt, and the interrupt management module belongs to an internal interrupt. Both external interrupts and internal interrupts are input into the core module via interrupt inputs.
[0079] As an example, see Figure 1 , for the case where the MCU is in low power mode, it corresponds to Figure 1 The interrupt input of the external bus-register corresponds to the above internal interrupt and external interrupt. Figure 1 Interrupt input for external error signal.
[0080] In one embodiment of the present disclosure, each PMU is integrated with a high voltage and low voltage detection module, and the power management module is specifically used to: when the detection results of the high voltage and low voltage detection modules exceed a preset range, report the detection results to the MCU error manager and interrupt management module.
[0081] In this embodiment, the objects managed by the power management module include the main PMU and the backup PMU, wherein the main PMU corresponds to the main power domain, and the backup PMU corresponds to the backup power domain. The main power domain includes the central processing unit, digital peripherals, analog peripherals, FIRC and phase-locked loop, and the backup power domain includes the backup processor, low-power peripherals, independent watchdog and RTC (Real-Time Clock). The power management module manages the PMU and power correction related operations of the entire system. Each PMU is internally integrated with a high-voltage / low-voltage detection module. When the detection exceeds the range, the detection result is reported to the MCU error manager and the interrupt management module, wherein the MCU error manager is an external interrupt, and the interrupt management module is an internal interrupt. Both the external interrupt and the internal interrupt are input to the core module in the form of interrupt input.
[0082] In one embodiment of the present disclosure, the interrupt management module is specifically used to: configure the interrupt mapping vector, map the external / internal interrupt to the corresponding address of the EEPROM, and when the corresponding interrupt is triggered, the PC pointer of the SMU core will automatically jump to the corresponding position. Interrupts include internal interrupts and external interrupts, wherein the external interrupts come from the error report of the MCU system-level error manager and the software configuration of the register (power mode switching), and the internal interrupts come from the error signals of the clock management module and the power management module.
[0083] The following is an explanation of the system startup process.
[0084] The system startup process includes the following steps: waiting for the backup power supply to be ready; power-on reset management module; management module runs the program from address 0 of EEPROM. The program includes: configuring interrupt vector; configuring main PMU; waiting for main PMU to start; configuring phase-locked loop, frequency divider, gated clock; waiting for phase-locked loop to start; configuring frequency divider, gated clock, clock selector, and turning on reset. Complete the startup program and wait for interrupt.
[0085] Among them, after power-on and reset, the management system resets the SMU core and each application unit, and after reset, configures the interrupt management module, power management module and clock management module in sequence according to the program. After the configuration is completed, the management system calls the WFI instruction through the program, and cuts off the internal clock of the SMU to save power, and waits for the next interrupt wake-up to switch the power mode of the management system. For example, the power mode includes a low power mode and a non-low power mode, or the power mode includes more than three power consumption modes, which can be determined according to the register configuration, and no specific restrictions are made here.
[0086] The interrupt wake-up process is described below.
[0087] like Figure 4As shown, when an interrupt is triggered, the interrupt vector table is read, the corresponding interrupt position is jumped to, and the interrupt program is run. After the interrupt wakes up, the management system jumps the PC pointer of the SMU to the corresponding vector position of the interrupt, and runs the interrupt program accordingly. In response to the completion of the program, the WFI instruction is called to switch the main SMU core and the slave SMU core to low power consumption mode. Thus, the power consumption mode of the management system can be switched according to different interrupt triggering situations, thereby reducing the power consumption of the management system.
[0088] According to the technical solution of the embodiment of the present disclosure, the management system includes a storage module, a core module, a register module, a clock management module, a power management module and an interrupt management module to realize the clock and power management of the MCU, wherein the SMU adopts a streamlined subset processor. By using a streamlined instruction core, compared with the method of single backup small core processing, the logic resource occupation of the core module is reduced, the cost and power consumption are reduced, and compared with the register-type management module, the configuration process does not rely on the central processing unit, which improves flexibility and security. Moreover, on the basis of the SMU adopting a streamlined subset processor, it can support the core module to adopt a main SMU core, a slave SMU core, a delayer and a comparator, and then use the bus return and interrupt input as the input of the main SMU core, and the bus return and interrupt input through the delayer as the input of the slave SMU core. The outputs of the main SMU core and the slave SMU core are detected and error managed by the comparator. Thus, the same content is run through the main SMU core and the slave SMU core, and each level of data is compared to determine the appropriate running result, thereby improving the reliability of the logic and improving the security of the system.
[0089] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0090] The above description is only a specific embodiment of the present disclosure, so that those skilled in the art can understand or implement the present disclosure. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present disclosure. Therefore, the present disclosure will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A vehicle MCU management system, characterized in that: include: Storage module, core module, register module, clock management module, power management module and interrupt management module; The core module includes a master SMU core, a slave SMU core, a delay device and a comparator, and the SMU adopts a simplified subset processor; The input content of the main SMU core includes bus return and / or interrupt input, and the output content includes a first bus operation output; the first bus operation output is used as the output of the core module to be transmitted to the clock management module, the power management module and the interrupt management module for control; The input content from the SMU core includes the bus return through the delay device and / or the interrupt input through the delay device, and the output content includes a second bus operation output; Wherein, the interrupt input includes an input of an external error signal and / or an input of an external bus through the register module, and the bus return includes data read from the storage module, and / or data read from the clock management module, the power management module and the interrupt management module; The comparator is used to detect the first bus operation output through the second bus operation output to determine whether to perform error management; The clock management module is used for clock and reset control, clock monitoring and security management; The power management module is used for PMU management and power correction operations; The interrupt management module is used to configure an interrupt mapping vector to map the interrupt to a corresponding address of the storage module.
2. The system according to claim 1, characterized in that The master SMU core and the slave SMU core both adopt the following structure: PC pointer, first read unit, decoding unit, general register, second read unit, execution unit, write back unit; Wherein, the first reading unit is used to read the instruction according to the PC pointer and the storage module and send it to the decoding unit; The decoding unit is used to decode the instruction and send it to the second reading unit; The second reading unit is used to read the general register according to the instruction to obtain data to be processed; The execution unit is used to perform an execution operation according to the data to be processed; The write-back unit is used to write the return value of the execution operation back to the general register and update the PC pointer; The SMU uses a two-state state machine, where the state is a read state or an execute state.
3. The system according to claim 2, characterized in that Also includes: The watchdog module is used to monitor the state changes of the SMU. When the duration of the state machine of the SMU in any state is greater than or equal to the preset duration, an alarm signal is triggered to perform a reset operation.
4. The system according to claim 1, characterized in that The clock management module is specifically used for: Monitor the external clock source, internal clock source and phase-locked loop output through an asynchronous clock to obtain a clock monitoring result; When the clock monitoring result is abnormal, the clock monitoring result is reported to the MCU error manager and the interrupt management module.
5. The system according to claim 1, wherein: Each PMU has a high voltage and low voltage detection module integrated inside. The power management module is specifically used for: When the detection results of the high voltage and low voltage detection modules exceed a preset range, the detection results are reported to the MCU error manager and the interrupt management module.
6. The system according to claim 2, characterized in that When an interrupt is triggered, the PC pointer jumps to the corresponding position and runs the program corresponding to the interrupt.
7. The system according to claim 6, characterized in that The core module is specifically used for: In response to the program running being completed, a WFI instruction is called to switch the master SMU core and the slave SMU core to a low power consumption mode.
8. The system of claim 1, wherein: The time delay device is specifically used for: The bus return and / or the interrupt input is delayed by 3 cycles.
9. The system according to claim 2, characterized in that The number of general registers is 4.
10. The system according to claim 2, characterized in that The execution unit is connected to the clock management module, the power management module and the interrupt management module respectively through a bus.