Linear voltage regulator circuit
By designing a dual-mode power transistor operation mode in the linear regulator circuit, the problem of insufficient load capacity of traditional linear regulators under low voltage conditions is solved, and output stability and circuit reliability are improved over a wider input voltage range.
Patent Information
- Application Number
- CN202411907304.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-23
- Publication Date
- 2025-05-13
AI Technical Summary
When the input voltage of traditional high-voltage linear regulators change from high to low, they may not be able to ensure normal load capacity under low voltage conditions, resulting in abnormal drop in the output voltage and affecting the normal operation of the subsequent circuit.
A dual-mode linear voltage regulator circuit is designed to switch the operating mode of the power transistor according to the different input voltages through the mode control circuit. When the input voltage is high, the power transistor operates as a voltage regulator to adjust the output voltage; when the input voltage is low, the power transistor operates as a load switch to ensure load capacity under low voltage conditions.
Maintaining output stability over a wider input voltage range improves the adaptability and flexibility of the circuit, avoids the output voltage drop, and enhances the reliability of the circuit.
Smart Images
Figure CN119987473A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the technical field of integrated circuits, and in particular to a linear voltage regulator circuit. Background Art
[0002] Low Dropout Regulator (LDO), also known as linear regulator or linear regulator, converts unstable input voltage into adjustable DC output voltage to serve as power supply for other systems. Due to its simple structure, low static power consumption and small output voltage ripple, linear regulators are often used for on-chip power management of mobile consumer electronic device chips.
[0003] Figure 1 FIG. 2 shows a schematic circuit diagram of a conventional linear regulator circuit. Figure 1 As shown, the conventional off-chip capacitor linear regulator 100 includes a power transistor MP, a reference circuit 110 and an error amplifier AMP. The power transistor MP is used to provide an output voltage VCC to a subsequent load according to an input voltage VIN provided by a power supply terminal. The capacitor CL is an off-chip capacitor of the linear regulator 100, which is used to improve the stability of the loop. The resistor voltage divider network composed of resistors R1 and R2 is connected between the output terminal of the output voltage VCC and the ground, and is used to divide the output voltage VCC to obtain a feedback voltage VFB. The error amplifier AMP is used to compare the feedback voltage VFB with the reference voltage VREF provided by the reference circuit 110 to obtain an error signal between the two, and to control the voltage drop of the power transistor MP according to the error signal, so as to achieve the purpose of stabilizing the output voltage VCC.
[0004] In order to reduce circuit power consumption, be compatible with the low operating voltage of the digital core part of MCU chips, and improve system compatibility, the input voltage of existing LDOs needs to vary within a wide range. However, due to the limitations and structural characteristics of high-voltage devices, traditional high-voltage linear regulators may not be able to guarantee normal load capacity under low voltage conditions when the input voltage at the power supply end changes from high to low, which in turn causes an abnormal drop in output voltage, affecting the normal operation of subsequent circuits and reducing circuit performance. Summary of the invention
[0005] In order to solve the above technical problems, the present invention provides a linear voltage regulator circuit, which can ensure the output stability of the circuit under low voltage conditions and improve the adaptability and flexibility of the circuit.
[0006] According to one aspect of the present invention, there is provided a linear regulator circuit, comprising: a power transistor having a current conduction path connected between an input voltage and an output voltage, and a control terminal for receiving a control signal; a feedback control circuit for comparing a feedback voltage of the output voltage with a first reference voltage, and modulating the control signal according to the comparison result so that the power transistor is operated as a voltage regulator; a gate control circuit for setting the control signal to a set value so that the power transistor is operated as a load switch; and a mode control circuit for comparing the input voltage with a set threshold value, and turning on one of the feedback control circuit and the gate control circuit according to the comparison result.
[0007] Optionally, the mode control circuit includes: a voltage detection module, used to generate a first voltage division signal according to the input voltage; and a first comparator, used to compare the first voltage division signal with a second reference voltage representing the set threshold, wherein the mode control circuit is used to turn on the feedback control circuit and turn off the gate control circuit when the first voltage division signal is greater than the second reference voltage, and to turn on the gate control circuit and turn off the feedback control circuit when the first voltage division signal is less than the second reference voltage.
[0008] Optionally, the mode control circuit also includes: a second comparator, used to compare the second voltage division signal of the output voltage with a third reference voltage when the power transistor is operated as a load switch, wherein the mode control circuit is used to turn on the feedback control circuit and turn off the gate control circuit when the second voltage division signal is less than the third reference voltage.
[0009] Optionally, the mode control circuit also includes: a logic unit, used to perform a NAND logic operation on a first comparison signal output by the first comparator and an inverted signal of a second comparison signal output by the second comparator to generate a mode switching signal, wherein the mode switching signal is used to control the opening and closing of the feedback control circuit and the gate control circuit.
[0010] Optionally, it also includes: a bias circuit, used to provide a bias current and a bias voltage to the feedback control circuit.
[0011] Optionally, the bias circuit includes: a current source, a first end of which is connected to an on-chip power supply voltage; a first resistor, a first end of which is connected to a second end of the current source; a first transistor and a second transistor, a first end of the first transistor being connected to a second end of the first resistor, and control ends of the first transistor and the second transistor being connected to a first end of the first resistor; a third transistor and a fourth transistor, a first end of the third transistor being connected to a second end of the first transistor, a first end of the fourth transistor being connected to a second end of the second transistor, control ends of the third transistor and the fourth transistor being connected to a second end of the first resistor, and second ends of the third transistor and the fourth transistor being connected to a reference ground; and a fifth transistor, a first end of the fifth transistor being connected to the on-chip power supply voltage, and a control end and a second end of the fifth transistor being connected to a first end of the second transistor, wherein the control ends of the third transistor and the fourth transistor are used to provide the bias voltage, and the fifth transistor provides the bias current to the feedback control circuit in a mirroring manner.
[0012] Optionally, the feedback control circuit includes: an input stage module, used to compare the feedback voltage with the first reference voltage to obtain an error signal; and a driving stage module, used to generate the control signal according to the error signal to drive the control end of the power transistor.
[0013] Optionally, the input stage module includes: a sixth transistor and a seventh transistor, the first ends of the sixth transistor and the seventh transistor are connected to each other, the control end of the sixth transistor is used to receive the first reference voltage, and the seventh transistor is used to receive the feedback voltage; an eighth transistor and a ninth transistor, the first end and the control end of the eighth transistor and the control end of the ninth transistor are connected to the second end of the sixth transistor, the first end of the ninth transistor is connected to the second end of the seventh transistor, and the second ends of the eighth transistor and the ninth transistor are connected to a reference ground; and a tenth transistor, connected between the on-chip power supply voltage and the first ends of the sixth transistor and the seventh transistor, the tenth transistor obtains the bias current by mirroring, wherein the intermediate node of the seventh transistor and the ninth transistor is used to provide the error signal.
[0014] Optionally, the driving stage module includes: a first high-voltage transistor, a first end of which is connected to the input voltage; a second resistor, a first end of which is connected to the second end of the first high-voltage transistor; a second high-voltage transistor, a first end of which is connected to the second end of the second resistor, and a control end for receiving the error signal; a third resistor, a first end of which is connected to the second end of the second high-voltage transistor; an eleventh transistor, a first end of which is connected to the second end of the third resistor, a control end for receiving the mode switching signal, and a second end connected to a reference ground; a third high-voltage transistor, a first end of which is connected to the control end of the first high-voltage transistor, and a second end of which is connected to the control end of the power transistor; a fourth resistor, whose first end is connected to the control end of the third high-voltage transistor; a fourth high-voltage transistor, whose first end is connected to the second end of the fourth resistor, and whose control end is used to receive the mode switching signal; a twelfth transistor, whose first end is connected to the second end of the fourth high-voltage transistor, whose control end is used to receive the bias voltage, and whose second end is connected to the reference ground; and a fifth resistor, which is connected between the input voltage and the control end of the power transistor; a Zener diode, whose cathode is connected to the first end of the third high-voltage transistor, and whose anode is connected to the gate of the third high-voltage transistor; and a sixth resistor, which is connected between the first end and the control end of the third high-voltage transistor.
[0015] Optionally, the power transistor is a PMOS transistor, and the gate control circuit includes: a seventh resistor, a first end of which is connected to the control end of the power transistor; a fifth high-voltage transistor, a first end of which is connected to the second end of the seventh resistor, and the control end is used to receive the inverted signal of the mode switching signal; and an eighth resistor, a first end of which is connected to the second end of the fifth high-voltage transistor, and a second end of which is connected to the reference ground, wherein, when the fifth high-voltage transistor is turned on, the gate control circuit is used to pull the control signal down to the reference ground so that the power transistor is fully turned on.
[0016] Optionally, the linear regulator circuit also includes: a resistor divider network, including a ninth resistor, a tenth resistor and an eleventh resistor connected in series between the output end of the output voltage and a reference ground, wherein an intermediate node between the ninth resistor and the tenth resistor is used to output the second voltage-divided signal, and an intermediate node between the tenth resistor and the eleventh resistor is used to output the feedback voltage.
[0017] Optionally, the voltage detection module includes: a twelfth resistor, a sixth high-voltage transistor, a thirteenth resistor and a fourteenth resistor connected in series between the input voltage and a reference ground, wherein the control end of the sixth high-voltage transistor is connected to an on-chip power supply voltage, and an intermediate node between the thirteenth resistor and the fourteenth resistor is used to output the first voltage-divided signal.
[0018] The embodiment of the present invention provides a dual-mode linear voltage regulator circuit, the operation mode of the power transistor of which can be changed according to the input voltage, so that when the input voltage is high, the power transistor can be operated as a voltage regulator, which can effectively adjust the output voltage, reduce energy loss, and improve the efficiency of the entire circuit. When the input voltage is low, the power transistor can be operated as a load switch, which can ensure the load capacity of the circuit under low voltage conditions, avoid the decrease of the output voltage, and help improve the output stability and reliability of the circuit. Therefore, the linear voltage regulator circuit of the embodiment of the present invention can operate in a wider input voltage range, improving the adaptability and flexibility of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS
[0019] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings.
[0020] Figure 1 A schematic circuit diagram of a conventional linear regulator circuit is shown.
[0021] Figure 2 FIG. 4 shows a schematic structural diagram of a linear regulator circuit according to an embodiment of the present invention.
[0022] Figure 3 FIG. 4 is a schematic circuit diagram of a bias circuit according to an embodiment of the present invention.
[0023] Figure 4 A schematic circuit diagram of a feedback control circuit, a resistor voltage divider network, and a gate control circuit according to an embodiment of the present invention is shown.
[0024] Figure 5 FIG. 4 is a schematic circuit diagram of a mode control circuit according to an embodiment of the present invention. DETAILED DESCRIPTION
[0025] Reference will now be made in detail to the exemplary embodiments of the present disclosure, examples of which are illustrated in the accompanying drawings.Where possible, the same reference numerals will be used throughout the drawings to refer to the same or like parts.
[0026] In the specification, it should be noted that similar reference numerals that have been used to represent similar parts in other drawings are used for these elements as much as possible. In the following description, when functions and configurations known to those skilled in the art are not related to the basic configuration of the present disclosure, their detailed description will be omitted. The terms described in the specification should be understood as follows.
[0027] The advantages and features of the present disclosure and their implementation methods will be described through the following embodiments described with reference to the accompanying drawings. However, the present disclosure can be implemented in different forms and should not be interpreted as being limited to the embodiments described herein. Rather, these embodiments are provided to make the present disclosure comprehensive and complete, so as to fully convey the scope of the present disclosure to those skilled in the art. In addition, the present disclosure is limited only by the scope of the claims.
[0028] The shapes, sizes, ratios, angles, and quantities disclosed in the drawings used to describe the embodiments of the present disclosure are merely examples, and the present disclosure is therefore not limited to the illustrated details. Similar reference numerals always represent similar elements. In the following description, when it is determined that a detailed description of a related known function or construction will inevitably obscure the focus of the present disclosure, the detailed description will be omitted.
[0029] As those skilled in the art can fully understand, the features of the various embodiments of the present disclosure can be partially or completely combined or combined with each other, and can interoperate and technically drive each other in various ways. The embodiments of the present disclosure can be performed independently of each other, or can be performed together in a mutually dependent relationship.
[0030] In the present application, a power transistor is a transistor that operates in a linear mode to provide a current path, including one selected from a bipolar transistor or a field effect transistor. The input terminal and the output terminal of the power transistor are respectively the high potential end and the low potential end on the current path, and the control terminal is used to receive a drive signal to control the voltage drop of the power transistor. The power transistor can be a PMOS (N-Metal-Oxide-Semiconductor) transistor or an NMOS (N-Metal-Oxide-Semiconductor) transistor. The first terminal, the second terminal and the control terminal of the PMOS transistor are the source, the drain and the gate, respectively, and the first terminal, the second terminal and the control terminal of the NMOS transistor are the drain, the source and the gate, respectively.
[0031] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0032] Figure 2 FIG. 2 shows a schematic structural diagram of a linear regulator circuit 200 according to an embodiment of the present invention. Figure 2The embodiment of the present invention provides a dual-mode high-voltage linear regulator circuit 200, which is configured to support operation in one case (for example, when the input voltage is high) so that the power transistor MP is used as a voltage regulator, thereby stabilizing the voltage at the load, and supports operation in another case (for example, when the input voltage is low) so that the power transistor MP is used as a load switch, so that the linear regulator circuit 200 has a strong load-carrying capacity and avoids undershoot of the output voltage.
[0033] Specifically, the linear regulator circuit 200 includes a power transistor MP, a bias circuit 210 , a feedback control circuit 220 , a mode control circuit 230 , a resistor divider network 240 , and a gate control circuit 250 .
[0034] The power transistor MP has a current conduction path connected between the input voltage VIN and the output voltage VCC, and a control terminal for receiving a control signal GATE, and the control signal GATE is used to control the conduction degree of the power transistor MP, thereby controlling the current flowing through the power transistor MP. For example, the power transistor MP can be implemented by a PMOS transistor, whose drain is coupled to the input voltage VIN, whose source is coupled to the output voltage VCC node, and the gate of the power transistor MP is used to receive the control signal GATE. It should be understood that in other embodiments, the power transistor MP can also use other types of transistors, such as NMOS transistors, NPN Darlington transistors, and NPN bipolar transistors, etc., and the present invention is not limited to this.
[0035] The bias circuit 210 is used to provide a bias current Ib and a bias voltage Vbn to the feedback control circuit 220. The feedback control circuit 220 is configured to sense the voltage at the output voltage VCC node and modulate the control signal GATE so that the power transistor MP delivers current to the output voltage VCC node so as to adjust the output voltage VCC to a level that makes the feedback voltage VFB substantially equal to the first reference voltage VREF1. Specifically, the feedback control circuit 220 uses a resistor divider network 240 coupled to the output voltage VCC node to sense the output voltage VCC at the load. The resistor divider network 240 is formed by, for example, connecting a plurality of resistors in series, and generates the feedback voltage VFB at the tap node of the resistors. For example, the feedback control circuit 220 is used to compare the feedback voltage VFB with the first reference voltage VREF1, and modulate the control signal GATE according to the error between the two, so that the power transistor MP operates as a voltage regulator, thereby adjusting the output voltage VCC.
[0036] In this embodiment, the feedback control circuit 220 includes an input stage module 201 and a driving stage module 202. The input stage module 201 is used to compare the feedback voltage VFB with the first reference voltage VREF1 to obtain an error signal VP. The driving stage module 202 generates the control signal GATE according to the error signal VP to drive the gate voltage of the power transistor MP.
[0037] Furthermore, the linear regulator circuit 200 of the present embodiment is a dual power rail structure, the bias circuit 210 and the input stage module 201 work between the on-chip power supply voltage VDD and the reference ground VSS power rail, and the driver stage module 202 works between the input voltage VIN and the reference ground VSS power rail. Among them, the input voltage VIN can be provided by an external high voltage source, and the on-chip power supply voltage VDD is lower than the input voltage VIN. By adopting the dual power rail structure, the linear regulator circuit 200 of the present embodiment can improve the PSR (Power Supply Rejection) performance of the circuit while improving the efficiency.
[0038] The gate control circuit 250 is connected to the gate of the power transistor MP, and is used to clamp the control signal GATE at a set value, so that the power transistor MP works in a fully turned-on state. At this time, the power transistor MP is equivalent to a load switch, so the equivalent on-resistance of the power transistor MP can be reduced, greatly improving the load capacity of the linear regulator circuit 200. For example, for the power transistor MP of a PMOS transistor, the gate control circuit 250 can pull down the voltage value of the control signal GATE to the reference ground VSS when it is turned on, so that the power transistor MP is fully turned on and operated as a load switch. It should be understood that the present invention is not limited to this.
[0039] The mode control circuit 230 is used to compare the input voltage VIN with a set threshold value, and turn on one of the feedback control circuit 220 and the gate control circuit 250 according to the comparison result. For example, the mode control circuit 230 can compare the input voltage VIN with the set threshold value, and provide a mode switching signal CTRL to the feedback control circuit 220 and the gate control circuit 250 according to the comparison result, and use the mode switching signal CTRL to control the feedback control circuit 220 and the gate control circuit 250 to turn on and off.
[0040] Specifically, the working process of the linear regulator circuit 200 of this embodiment is as follows: when the input voltage VIN is higher than the set threshold, the mode switching signal CTRL is at the first level to turn off the gate control circuit 250 and turn on the feedback control circuit 220, and the output of the LDO is dominated by the feedback control circuit 220. The feedback control circuit 220 controls the conduction degree of the power transistor MP by modulating the control signal GATE to increase the amplitude of the current delivered to the load. When the input voltage VIN is lower than the set threshold, the mode switching signal CTRL is at the second level to turn off the feedback control circuit 220 and turn on the gate control circuit 250, and the control signal GATE is pulled down to the reference ground VSS by the gate control circuit 250, so that the power transistor MP is fully turned on.
[0041] Figure 3 FIG. 2 shows a schematic circuit diagram of a bias circuit according to an embodiment of the present invention. Figure 3 As shown, the bias circuit 210 includes a current source 211, a resistor R1, and transistors M1-M5. Among them, the transistors M1-M4 are, for example, NMOS transistors, and the transistor M5 is, for example, a PMOS transistor. The first end of the current source 211 is connected to the on-chip power supply voltage VDD, the second end of the current source 211 is connected to the first end of the resistor R1, the second end of the resistor R1 is connected to the drain of the transistor M1, the source of the transistor M1 is connected to the drain of the transistor M3, and the source of the transistor M3 is connected to the reference ground VSS. The source of the transistor M5 is connected to the on-chip power supply voltage VDD, the gate and drain of the transistor M5 are short-circuited together, and the drain of the transistor M5 is also connected to the drain of the transistor M2, the gate of the transistor M2 is connected to the gate of the transistor M1 and the first end of the resistor R1, the source of the transistor M2 is connected to the drain of the transistor M4, the gate of the transistor M4 is connected to the gate of the transistor M3 and the second end of the resistor R1, and the source of the transistor M4 is connected to the reference ground VSS. The bias voltage Vbn is generated at the gates of the transistors M3 and M4, the bias current Ib is generated in the branch of the transistors M5 to M4, and the transistor M5 provides the bias current Ib to the feedback control circuit 220 in a mirroring manner.
[0042] Figure 4 FIG. 2 shows a schematic circuit diagram of a feedback control circuit, a resistor voltage divider network, and a gate control circuit according to an embodiment of the present invention. Figure 4As shown, the input stage module 201 includes transistors M6-M10. Among them, transistors M6, M7 and M10 are PMOS transistors, and transistors M8 and M9 are NMOS transistors. Transistors M6 and M7 constitute a differential input pair, the sources of transistors M6 and M7 are connected to each other, the gate of transistor M6 is used to receive the first reference voltage VREF1, and the gate of transistor M7 is used to receive the feedback voltage VFB. Transistors M8 and M9 serve as active loads of the input pair, the drain and gate of transistor M8 and the gate of transistor M9 are connected to the drain of transistor M6, the drain of transistor M9 is connected to the drain of transistor M7, and the sources of transistors M8 and M9 are connected to the reference ground VSS. Transistor M10 serves as a tail current source of the input pair, the source of transistor M10 is connected to the on-chip power supply voltage VDD, and the gate of transistor M10 is connected to the reference ground VSS. Figure 3 The gate of the transistor M5 is connected to obtain the bias current Ib in a mirroring manner, and the drain of the transistor M10 is connected to the source of the transistors M6 and M7. The error signal VP is generated at the middle node of the transistors M7 and M9.
[0043] Furthermore, the transistors M6 - M10 of this embodiment are, for example, 5V low-voltage transistors.
[0044] The driving stage module 202 includes transistors MH1-MH4, transistors M11 and M12, and resistors R2-R5. Among them, transistors MH1 and MH3 are PMOS transistors, and transistors MH2, MH4, M11 and M12 are NMOS transistors. The source of transistor MH1 is connected to the input voltage VIN, the gate of transistor MH1 is connected to the source of transistor MH3, the drain of transistor MH3 is connected to the gate of power transistor MP, the drain of transistor MH1 is connected to the first end of resistor R2, the second end of resistor R2 is connected to the drain of transistor MH2, the gate of transistor MH2 is used to receive the error signal VP, the source of transistor MH2 is connected to the first end of resistor R3, the second end of resistor R3 is connected to the drain of transistor M11, the gate of transistor M11 is used to receive the mode switching signal CTRL, and the source of transistor M11 is connected to the reference ground VSS. The first end of the resistor R4 is connected to the gate of the transistor MH3, the second end of the resistor R4 is connected to the drain of the transistor MH4, the gate of the transistor MH4 is used to receive the mode switching signal CTRL, the source of the transistor MH4 is connected to the drain of the transistor M12, the gate of the transistor M12 is used to receive the bias voltage Vbn, and the source of the transistor M12 is connected to the reference ground VSS. In this embodiment, the resistor R3 is a current limiting resistor, and the resistor R5 is used to set the gate initialization voltage of the power transistor MP, which is connected between the input voltage VIN and the gate of the power transistor MP.
[0045] Furthermore, the driving stage module 202 of this embodiment further includes a Zener diode Z1 and a resistor R6. The cathode of the Zener diode Z1 is connected to the source of the transistor MH3, the anode of the Zener diode Z1 is connected to the gate of the transistor MH3, and the resistor R6 is connected between the source and the gate of the transistor MH3. The Zener diode Z1 and the resistor R6 are used to clamp the gate-source voltage of the transistor MH3 to protect the transistor MH3.
[0046] The gate control circuit 250 includes resistors R7 and R8, a transistor MH5, and an inverter INV1. The first end of the resistor R7 is connected to the gate of the power transistor MP, the second end of the resistor R7 is connected to the drain of the transistor MH5, the source of the transistor MH5 is connected to the first end of the resistor R8, the second end of the resistor R8 is connected to the reference ground VSS, the input of the inverter INV1 is used to receive the mode switching signal CTRL, and the output of the inverter INV1 is connected to the gate of the transistor MH5.
[0047] The resistor divider network 240 includes resistors R9-R11, which are connected in series between the drain of the power transistor MP and the reference ground VSS. The middle node between the resistors R9 and R10 is used to provide a voltage division signal VCC_div of the output voltage VCC, and the middle node between the resistors R10 and R11 is used to provide the feedback voltage VFB.
[0048] Figure 5 FIG. 2 shows a schematic circuit diagram of a mode control circuit according to an embodiment of the present invention. Figure 5 As shown, the mode control circuit 230 includes a voltage detection module 231, comparators CMP1 and CMP2, an inverter INV2, and a logic unit NAND. In this embodiment, the voltage detection module 231 is connected between the input voltage VIN and the reference ground VSS, and the comparators CMP1 and CMP2 work between the on-chip power supply voltage VDD and the reference ground VSS.
[0049] The voltage detection module 231 is used to obtain the voltage division signal VIN_div of the input voltage VIN. Specifically, the voltage detection module 231 includes resistors R12-R14 and a transistor MH6, wherein the transistor MH6 is an NMOS transistor, wherein the first end of the resistor R12 is connected to the input voltage VIN, the second end of the resistor R12 is connected to the drain of the transistor MH6, the gate of the transistor MH6 is connected to the on-chip power supply voltage VDD, the source of the transistor MH6 is connected to the first end of the resistor R13, the second end of the resistor R13 is connected to the first end of the resistor R14, the second end of the resistor R14 is connected to the reference ground VSS, and the middle node between the resistors R13 and R14 is used to output the voltage division signal VIN_div. In this embodiment, the transistor MH6 is used to ensure that when the input voltage VIN is too high, the voltage division signal VIN_div is still in the VDD~VSS voltage domain, thereby ensuring that the comparator CMP1 functions normally.
[0050] The comparator CMP1 is used to compare the voltage division signal VIN_div with the second reference voltage VREF2 representing the set threshold value to obtain a comparison signal V1. For example, the positive input terminal of the comparator CMP1 is used to receive the second reference voltage VREF2, the negative input terminal of the comparator CMP1 is used to receive the voltage division signal VIN_div, and the output terminal is used to provide the comparison signal V1.
[0051] The comparator CMP2 is used to compare the voltage division signal VCC_div with the third reference voltage VREF3 to obtain a comparison signal V2. For example, the positive input terminal of the comparator CMP2 is used to receive the third reference voltage VREF3, the negative input terminal of the comparator CMP2 is used to receive the voltage division signal VCC_div, and the output terminal is used to provide the comparison signal V2.
[0052] The input of the inverter INV2 is connected to the output of the comparator CMP2, and the output of the inverter INV2 is connected to one input of the logic unit NAND. The logic unit NAND is implemented by a NAND gate, for example, and its other input is connected to the output of the comparator CMP1, and is used to perform a NAND logic operation on the comparison signal V1 and the inverted signal of the comparison signal V2 to generate the mode switching signal CTRL.
[0053] Furthermore, the transistors MH1-MH6 of this embodiment are implemented by high-voltage transistors, for example. It should be noted that the low-voltage MOS transistors and high-voltage MOS transistors in this article are generally relative. For example, transistors can be divided into high-voltage transistors or low-voltage transistors according to the Vds (drain-source voltage) withstand voltage capability of the MOS transistor. The withstand voltage capability of the high-voltage transistor is greater than that of the low-voltage transistor.
[0054] Combine the following Figure 4 and Figure 5 The working principle of the linear regulator circuit 200 according to the embodiment of the present invention is described.
[0055] In this embodiment, the mode switching signal CTRL defaults to a high level in the output voltage VCC startup phase, and the comparators CMP1 and CMP2 intervene in the control mode switching signal CTRL only after the output voltage VCC is established and enters the load phase. Therefore, at this time, the transistors M11 and MH4 are turned on, and the transistor MH5 is turned off, so the feedback control circuit 220 works normally, and the pull-down branch where the gate control circuit 250 is located is closed. Then, the output voltage VCC is divided by the voltage-dividing resistors R10 and R11 to obtain the feedback voltage VFB, and the input stage module 201 of the feedback control circuit 220 compares the feedback voltage VFB with the first reference voltage VREF1, and then obtains the error signal VP between the two, and then the control signal GATE is modulated according to the error signal VP through the driving stage module 202, so that the power transistor MP is operated as a voltage regulator, and finally the output voltage VCC is regulated. The equivalent on-resistance of the high-voltage transistor is greatly affected by its gate-source voltage. When the gate-source voltage of the high-voltage transistor is less than 4V, its equivalent on-resistance will increase rapidly as the gate-source voltage decreases, which in turn causes the drain-source voltage of the high-voltage transistor to increase rapidly. Therefore, when the input voltage VIN is lower than the set threshold, if the power transistor MP is not switched to a load switch, the drain-source voltage of the high-voltage transistors MH1 and MH2 in the driver module 202 and the current-limiting resistor R3 will limit the margin of the gate-source voltage of the power transistor MP, which may cause the output voltage VCC to undershoot under normal load conditions. Therefore, the purpose of the embodiment of the present invention is to reduce its equivalent on-resistance by increasing the gate-source voltage of the power transistor MP when the input voltage VIN is low, for example, after the input voltage VIN is less than 4V, and reduce the equivalent drain-source voltage of the power transistor MP when loaded, thereby reducing the undershoot of the output voltage VCC and improving the load capacity of the circuit.
[0056] Specifically, when the input voltage VIN is low, for example, when the voltage division signal VIN_div is less than the second reference voltage VREF2, the output V1 of the comparator CMP1 flips to a high level. Assuming that the output V2 of the comparator CMP2 is a low level at this time, the output CTRL of the logic unit NAND flips to a low level, so the transistors M11 and MH4 in the driver stage module 202 are turned off, and the branch from the transistors MH1 to MH2 is turned off by the transistor M11 to avoid a large current in the circuit under the low input voltage VIN. The current path from the gate of the transistor MH3 to the reference ground VSS is disconnected by the high-voltage transistor MH4, so the transistor MH3 is also turned off, thereby disconnecting the signal path from the output of the driver stage module 202 to the power transistor MP. At this time, the feedback control circuit 220 no longer participates in the modulation of the control signal GATE. At the same time, transistor MH6 is turned on, and the gate of power transistor MP is pulled down to reference ground VSS through gate control circuit 250, thereby making the gate-source voltage of power transistor MP equal to input voltage VIN. Therefore, power transistor MP is fully turned on. At this time, power transistor MP is operated as a load switch, thereby improving the load-carrying capacity of the circuit under low voltage conditions.
[0057] Furthermore, the comparator CMP2 is used to provide current limiting protection for the output voltage VCC when the power transistor MP is operated as a load switch. Assuming the load current is IL, when the power transistor MP is operated as a load switch, the output voltage VCC ,in is the equivalent on-resistance of the power transistor MP. It can be seen from the above formula that when the load current IL is too large, the output voltage VCC may further drop. Therefore, when the voltage division signal VCC_div is less than the third reference voltage VREF3, the output V2 of the comparator CMP2 flips to a high level, and then the output CTRL of the logic unit NAND flips to a high level again, thereby turning on the feedback control circuit 220 and turning off the gate control circuit 250, so that the power transistor MP is operated as a voltage regulator again, avoiding the problem of the output voltage VCC dropping when the load is too heavy, and improving the safety of the circuit.
[0058] In summary, the embodiment of the present invention provides a dual-mode linear voltage regulator circuit, the operation mode of the power transistor of which can vary according to the input voltage, so that when the input voltage is high, the power transistor can be operated as a voltage regulator, which can effectively adjust the output voltage, reduce energy loss, and improve the efficiency of the entire circuit. When the input voltage is low, the power transistor can be operated as a load switch, which can ensure the load capacity of the circuit under low voltage conditions, avoid the decrease of the output voltage, and help improve the output stability and reliability of the circuit. Therefore, the linear voltage regulator circuit of the embodiment of the present invention can operate within a wider input voltage range, improving the adaptability and flexibility of the circuit.
[0059] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the statement "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.
[0060] Finally, it should be noted that: Obviously, the above embodiments are only examples for clearly explaining the present invention, and are not intended to limit the implementation methods. For ordinary technicians in the relevant field, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived from this are still within the scope of protection of the present invention.
Claims
1. A linear regulator circuit, comprising: A power transistor having a current conduction path connected between an input voltage and an output voltage, and a control terminal for receiving a control signal; a feedback control circuit for comparing a feedback voltage of the output voltage with a first reference voltage and modulating the control signal according to a comparison result so that the power transistor is operated as a voltage regulator; a gate control circuit for setting the control signal to a set value so that the power transistor is operated as a load switch; as well as The mode control circuit is used to compare the input voltage with a set threshold value and start one of the feedback control circuit and the gate control circuit according to the comparison result.
2. The linear regulator circuit according to claim 1, wherein: The mode control circuit comprises: a voltage detection module, configured to generate a first voltage division signal according to the input voltage; and a first comparator, configured to compare the first voltage-divided signal with a second reference voltage representing the set threshold, The mode control circuit is used to turn on the feedback control circuit and turn off the gate control circuit when the first voltage division signal is greater than the second reference voltage, and to turn on the gate control circuit and turn off the feedback control circuit when the first voltage division signal is less than the second reference voltage.
3. The linear regulator circuit according to claim 2, wherein: The mode control circuit further includes: a second comparator, for comparing the second voltage-divided signal of the output voltage with a third reference voltage when the power transistor is operated as a load switch, The mode control circuit is used to turn on the feedback control circuit and turn off the gate control circuit when the second voltage-divided signal is less than the third reference voltage.
4. The linear regulator circuit according to claim 3, wherein: The mode control circuit further includes: a logic unit, configured to perform a NAND logic operation on a first comparison signal output by the first comparator and an inverted signal of a second comparison signal output by the second comparator to generate a mode switching signal, The mode switching signal is used to control the on and off of the feedback control circuit and the gate control circuit.
5. The linear regulator circuit according to claim 4, wherein: Also includes: The bias circuit is used to provide a bias current and a bias voltage to the feedback control circuit.
6. The linear regulator circuit according to claim 5, wherein: The bias circuit comprises: A current source, a first end of which is connected to an on-chip power supply voltage; a first resistor, a first end of which is connected to the second end of the current source; a first transistor and a second transistor, wherein a first end of the first transistor is connected to a second end of the first resistor, and control ends of the first transistor and the second transistor are connected to a first end of the first resistor; a third transistor and a fourth transistor, wherein a first end of the third transistor is connected to a second end of the first transistor, a first end of the fourth transistor is connected to a second end of the second transistor, control ends of the third transistor and the fourth transistor are connected to a second end of the first resistor, and second ends of the third transistor and the fourth transistor are connected to a reference ground; and a fifth transistor, wherein a first terminal of the fifth transistor is connected to the on-chip power supply voltage, a control terminal and a second terminal of the fifth transistor are connected to the first terminal of the second transistor, The control terminals of the third transistor and the fourth transistor are used to provide the bias voltage, and the fifth transistor provides the bias current to the feedback control circuit in a mirroring manner.
7. The linear regulator circuit according to claim 5, wherein: The feedback control circuit comprises: an input stage module, configured to compare the feedback voltage with the first reference voltage to obtain an error signal; and The driving stage module is used to generate the control signal according to the error signal to drive the control end of the power transistor.
8. The linear regulator circuit according to claim 7, wherein: The input stage module comprises: a sixth transistor and a seventh transistor, wherein first terminals of the sixth transistor and the seventh transistor are connected to each other, a control terminal of the sixth transistor is used to receive the first reference voltage, and the seventh transistor is used to receive the feedback voltage; an eighth transistor and a ninth transistor, wherein a first terminal and a control terminal of the eighth transistor and a control terminal of the ninth transistor are connected to the second terminal of the sixth transistor, a first terminal of the ninth transistor is connected to the second terminal of the seventh transistor, and second terminals of the eighth transistor and the ninth transistor are connected to a reference ground; and a tenth transistor connected between the on-chip power supply voltage and the first ends of the sixth transistor and the seventh transistor, the tenth transistor obtaining the bias current in a mirroring manner, Wherein, the middle node between the seventh transistor and the ninth transistor is used to provide the error signal.
9. The linear regulator circuit according to claim 7, wherein: The driver-level module comprises: A first high-voltage transistor, a first terminal of which is connected to the input voltage; a second resistor, a first end of which is connected to the second end of the first high-voltage transistor; a second high-voltage transistor, a first end of which is connected to the second end of the second resistor, and a control end of which is used to receive the error signal; a third resistor, a first end of which is connected to the second end of the second high-voltage transistor; an eleventh transistor, a first end of which is connected to the second end of the third resistor, a control end of which is used to receive the mode switching signal, and a second end of which is connected to a reference ground; a third high-voltage transistor, a first end of which is connected to the control end of the first high-voltage transistor, and a second end of which is connected to the control end of the power transistor; a fourth resistor, a first end of which is connected to the control end of the third high-voltage transistor; a fourth high-voltage transistor, a first end of which is connected to the second end of the fourth resistor, and a control end of which is used to receive the mode switching signal; a twelfth transistor, having a first end connected to the second end of the fourth high-voltage transistor, a control end for receiving the bias voltage, and a second end connected to a reference ground; and a fifth resistor connected between the input voltage and the control terminal of the power transistor; a Zener diode, a cathode connected to the first end of the third high-voltage transistor, and an anode connected to the gate of the third high-voltage transistor; and A sixth resistor is connected between the first terminal and the control terminal of the third high-voltage transistor.
10. The linear regulator circuit according to claim 4, wherein: The power transistor is a PMOS transistor, and the gate control circuit includes: a seventh resistor, a first end of which is connected to the control end of the power transistor; a fifth high-voltage transistor, a first end of which is connected to the second end of the seventh resistor, and a control end of which is used to receive an inverted signal of the mode switching signal; and an eighth resistor, a first end of which is connected to the second end of the fifth high-voltage transistor, and a second end of which is connected to the reference ground, Wherein, when the fifth high-voltage transistor is turned on, the gate control circuit is used to pull the control signal down to the reference ground so that the power transistor is fully turned on.
11. The linear regulator circuit according to claim 4, wherein: Also includes: a resistor voltage divider network, comprising a ninth resistor, a tenth resistor and an eleventh resistor connected in series between an output terminal of the output voltage and a reference ground, The middle node between the ninth resistor and the tenth resistor is used to output the second voltage-divided signal, and the middle node between the tenth resistor and the eleventh resistor is used to output the feedback voltage.
12. The linear regulator circuit according to claim 4, wherein: The voltage detection module comprises: a twelfth resistor, a sixth high-voltage transistor, a thirteenth resistor and a fourteenth resistor connected in series between the input voltage and the reference ground, The control terminal of the sixth high-voltage transistor is connected to the on-chip power supply voltage, and the middle node between the thirteenth resistor and the fourteenth resistor is used to output the first voltage-divided signal.