Code generation method and system based on RAG and framework type COT

Abstract

The invention provides a code generation method and system based on RAG and frame-type COT, a signal processing algorithm to be converted is input into a frame-type COT large model, an algorithm frame is built according to an operation process of the frame-type COT large model, and the signal processing algorithm to be converted is embodied in a matlab or C language form; generating a basic code according to the algorithm framework; according to user requirements, focusing on a preset part of the basic code through a retrieval enhancement generation method, matching professional terms, and optimizing the preset part; the optimized codes are output, and the codes are FPGA executable codes. Specifically, in the process of developing HDL potential by utilizing LLM enhancement, codes with low time delay and high resource utilization rate are obtained by applying a framework type thought chain prompt technology and retrieval enhancement generation, and the execution efficiency of the FPGA in a hardware circuit is improved from the perspective of time and space.

Description

Technical Field

[0001] The present invention belongs to the technical field of wireless communications, and in particular relates to a code generation method and system based on RAG and frame-type COT. Background Art

[0002] The emergence of software radio systems (SDR) has brought great changes to the field of wireless communications. It has flexibility and adaptability that hardware radio systems cannot achieve, and is an important aspect of wireless network research. In recent years, field programmable gate arrays (FPGAs) have become a commonly used SDR platform because their dynamics, high performance, and reconfigurability can well meet the needs of SDR. Unlike traditional SDRs, FPGAs need to interact more directly with hardware through hardware description languages ​​(HDL) such as Verilog.

[0003] At present, some scholars have verified that large language models (LLMs) have the potential to accelerate HDL development, such as generating 8-bit adder code, code detection and repair, and assisting users in learning HDL, etc. to generate simple HDL code for small computing tasks. Since many signal processing algorithms used in SDR are relatively complex and consume a lot of resources, although the current LLM can generate basic HDL code for signal processing algorithms, the underlying logic of these codes lacks in-depth knowledge of professional fields, resulting in insufficient scalability of the code, occupying a large amount of logic resources, and inefficient time resources. Therefore, the existing LLM can no longer meet the requirements of FPGA to achieve its high efficiency and low power consumption. Summary of the invention

[0004] Based on this, an embodiment of the present invention provides a code generation method and system based on RAG and framework COT, aiming to solve the problems of low FPGA time efficiency and hardware utilization in the process of developing Verilog language for FPGA-based SDR in the prior art.

[0005] A first aspect of an embodiment of the present invention provides a code generation method based on RAG and framework COT, the method comprising: Input the signal processing algorithm to be converted into the framework COT large model, and build an algorithm framework according to the operation flow of the framework COT large model, wherein the signal processing algorithm to be converted is embodied in the form of matlab or C language; Generate basic code according to the algorithm framework; According to user needs, by searching and enhancing the generation method, focusing on the preset part of the generated basic code, and matching professional terms, the preset part is optimized; Output optimized code, wherein the basic code and the optimized code are both FPGA executable codes.

[0006] Furthermore, according to the operation flow of the framework COT large model, the steps of building the algorithm framework include: The signal processing algorithm to be converted is subjected to mathematical operations and algorithm analysis in five dimensions to obtain evaluation results, where the five dimensions include complexity, robustness, scalability, scenario requirements, and implementation cost; Align the evaluation results with the module functions that need to be implemented by the FPGA, and allocate corresponding hardware resources; Divide the signal processing algorithms to be converted into levels according to data dependencies and scenario requirements; The core steps in the signal processing algorithm to be converted are determined and decomposed into a series of intermediate reasoning steps.

[0007] Furthermore, the complexity is obtained by measuring the time complexity and space complexity of the algorithm; The robustness is obtained by judging the anti-interference capability or dynamic channel tracking capability of the signal processing algorithm to be converted; The scalability is obtained by using various parameters applicable to the signal processing algorithm to be converted, wherein the parameters at least include the number of antennas, the number of users, and the bandwidth; The application scenarios of the signal processing algorithm to be converted include at least satellite communication, Internet of Things and 5G communication; The implementation cost is obtained by weighing performance improvement and resource consumption, and considering hardware cost and time performance.

[0008] Furthermore, in the step of dividing the signal processing algorithm to be converted into levels according to data dependency and scenario requirements, from the perspective of data dependency, if the signal processing algorithm to be converted is decomposed into multiple sequential stages, and intermediate results need to be transferred between multiple sequential stages, pipeline operation is selected; if the elements or tasks in the data blocks in the signal processing algorithm to be converted have no dependency, parallel operation is selected; From the perspective of scenario requirements, if hardware resources are limited and time-division multiplexing of hardware units is required, or if periodic delays are acceptable, pipeline operation is selected; if hardware resources are sufficient and low latency or real-time performance is required, parallel operation is selected; When a single strategy cannot meet the needs, pipeline operations and parallel operations are combined.

[0009] Furthermore, data dependencies take precedence over scenario requirements.

[0010] Furthermore, the core steps in the signal processing algorithm to be converted are determined, and the core steps are decomposed into a series of intermediate reasoning steps. The operations with the greatest impact on performance are located by mathematical formulas, the data dependency graph of the algorithm is drawn, the critical path is identified, and the time complexity and hardware resource requirements of each step are calculated to determine the core steps in the signal processing algorithm to be converted.

[0011] A second aspect of an embodiment of the present invention provides a code generation system based on RAG and framework COT, which is used to implement the code generation method based on RAG and framework COT described in the first aspect, and the system includes: An input module is used to input the signal processing algorithm to be converted into the framework COT large model, and build an algorithm framework according to the operation process of the framework COT large model, wherein the signal processing algorithm to be converted is embodied in the form of matlab or C language; A generation module, used to generate basic code according to the algorithm framework; An optimization module, for optimizing the preset part by searching and enhancing the generation method according to user needs, focusing on the preset part of the generated basic code, matching professional terms, and optimizing the preset part; The output module is used to output the optimized code, wherein the basic code and the optimized code are both FPGA executable codes.

[0012] A third aspect of an embodiment of the present invention provides a computer-readable storage medium having a computer program stored thereon. When the program is executed by a processor, the code generation method based on RAG and framework COT provided in the first aspect is implemented.

[0013] A fourth aspect of an embodiment of the present invention provides an electronic device, comprising a memory, a processor, and a computer program stored in the memory and running on the processor, wherein when the processor executes the program, the code generation method based on RAG and framework-based COT provided in the first aspect is implemented.

[0014] The beneficial effects of a code generation method and system based on RAG and framework COT provided by the present invention are as follows: By inputting the signal processing algorithm to be converted into the framework COT large model, and building the algorithm framework according to the operation flow of the framework COT large model, the signal processing algorithm to be converted is embodied in the form of matlab or C language; generating basic code according to the algorithm framework; focusing on the preset part of the generated basic code according to user needs through the search enhancement generation method, and matching professional terms to optimize the preset part; outputting the optimized code, wherein the basic code and the optimized code are both FPGA executable code. Specifically, in the process of using LLM to enhance the development of HDL potential, by applying the framework idea chain prompting technology and search enhancement generation, a code with low latency and high resource utilization is obtained, which improves the execution efficiency of FPGA in hardware circuits from the perspective of time and space. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a flow chart of the framework COT large model; Figure 2 A flowchart of a code generation method based on RAG and framework COT provided in the first embodiment of the present invention; Figure 3 It is a structural diagram of the basic module of FFT; Figure 4 Schematic diagram of FFT structure optimized for "ping-pong operation"; Figure 5 A structural block diagram of a code generation system based on RAG and framework COT provided in Embodiment 3 of the present invention; Figure 6 The figure is a structural block diagram of an electronic device. DETAILED DESCRIPTION

[0016] In order to facilitate the understanding of the present invention, the present invention will be described more fully below with reference to the relevant drawings. Several embodiments of the present invention are given in the drawings. However, the present invention can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present invention more thorough and comprehensive.

[0017] It should be noted that when an element is referred to as being "fixed to" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. The terms "vertical", "horizontal", "left", "right" and similar expressions used herein are for illustrative purposes only.

[0018] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present invention belongs. The terms used herein in the specification of the present invention are only for the purpose of describing specific embodiments and are not intended to limit the present invention. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0019] Embodiment 1 According to an embodiment of the present invention, a code generation method embodiment based on RAG and framework COT is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0020] In the first embodiment of the present invention, a code generation method based on RAG and framework COT is provided, which can be used in electronic devices, such as computers. For a signal algorithm in the field of wireless communication, it often has the characteristics of directionality, high complexity, and large amount of data. Directionality: Many computing tasks can be divided into multiple subtasks with parallel and priority relationships. Subtasks can only be parallelized if they do not violate the underlying priority relationship. For example, the execution of subtask A depends on the completion of subtask B, then the output of B will determine the input of A. High complexity: Signal processing algorithms involve a variety of mathematical operations, and most algorithms also introduce complex numbers and decimals, which put forward high requirements on the accuracy of calculation results, showing the high complexity of the algorithm. Large amount of data: The processing object of the signal processing algorithm is usually a large-scale signal, and with the increase of order, time or dimension, the input parameters and the amount of calculation will increase exponentially. If there is a real-time processing requirement, a large amount of data needs to be processed continuously, thereby increasing the computational burden of the algorithm.

[0021] Since the signal processing algorithm has the characteristics of being directional, highly complex, and having a large amount of data, the present invention proposes to introduce a framework-type chain of ideas prompting technology to provide professional knowledge for generating basic codes for the large model. The flow chart of the framework-type COT large model is as follows: Figure 1 shown.

[0022] For more details, see Figure 2 , Figure 2 A flowchart of an implementation of a code generation method based on RAG and framework COT provided in the first embodiment of the present invention is shown, which specifically includes steps S01 to S04.

[0023] Step S01, input the signal processing algorithm to be converted into the framework COT large model, and build an algorithm framework according to the operation flow of the framework COT large model, wherein the signal processing algorithm to be converted is embodied in the form of matlab or C language.

[0024] It should be noted that the signal processing algorithm to be converted is evaluated in two aspects. On the one hand, the mathematical operations involved in the algorithm are analyzed. On the other hand, the algorithm is analyzed from five dimensions to obtain the evaluation results. Among them, the mathematical operations include step operation characteristics, approximate method errors, and specifically, FFT (Fast Fourier Transform). Transform, Fast Fourier Transform), uses a large number of butterfly operations. Multiple multiplication operations of butterfly operations will affect the computational efficiency of FFT. MIMO detection algorithm uses series approximation, which is more sensitive to approximation errors at high signal-to-noise ratios. The five dimensions include complexity, robustness, scalability, scenario requirements, and implementation costs. Specifically, the complexity is obtained by measuring the algorithm's time complexity (such as the number of floating-point operations) and space complexity (memory usage). Specifically, the main operations of the algorithm are determined, such as Fourier transform (such as FFT), matrix operations (such as matrix multiplication, inversion, decomposition), and iterative operations (such as gradient descent and Newton's method). The time complexity and space complexity of the algorithm are calculated based on the time complexity and space complexity of the main operations. Taking the complexity of PCA (principal component analysis) as an example, the main operation is the covariance matrix calculation. With eigendecomposition , for time complexity, the dominant term is ,like , it is simplified to , for space complexity, storing the covariance matrix requires , the data matrix is ; The robustness is obtained by judging the anti-interference ability or dynamic channel tracking ability of the signal processing algorithm to be converted. Specifically, the changes of indicators such as bit error rate and signal-to-noise ratio gain are detected in the interference scene, and the size of Doppler frequency shift and the length of channel coherence time are considered in the dynamic scene to evaluate its dynamic channel tracking ability; The scalability is obtained by using various parameters applicable to the signal processing algorithm to be converted, wherein the parameters may include the number of antennas, the number of users, and the bandwidth, etc. Specifically, the parameters are changed to test the change of the algorithm performance and determine the boundary of its scalability; The application scenarios of the signal processing algorithm to be converted may include satellite communication, Internet of Things, and 5G communication. Specifically, the application scenarios of 5G and Internet of Things have different requirements. 5G may focus more on high speed and low latency, while Internet of Things may focus more on low power consumption and large-scale connection. The implementation cost is obtained by weighing performance improvement and resource consumption, taking into account hardware cost and time performance. Specifically, a trade-off curve is used to find the optimal solution that improves performance without increasing cost or energy consumption. Align the evaluation results with the module functions that need to be implemented by the FPGA (Field-Programmable Gate Array), and allocate corresponding hardware resources. For example, in order to avoid consuming resources by calculating the rotation factors in real time, consider using a lookup table (LUT) to pre-store the results in the FFT; in the Viterbi decoder, consider using BRAM to store path metrics to avoid frequent access to external memory. Through the alignment operation, the framework COT (Chain-of-Thought) model can obtain the main functions of the algorithm as a whole, meet the algorithm performance requirements in general, set a large framework for the interaction between the FPGA and the hardware, and accumulate experience for the next step of dividing the algorithm level; The signal processing algorithm to be converted is divided into levels according to data dependency and scenario requirements. From the perspective of data dependency, if the signal processing algorithm to be converted is decomposed into multiple sequential stages, and intermediate results need to be transferred between multiple sequential stages, indicating that the data has dependency, then pipeline operation is selected; if the elements or tasks in the data block of the signal processing algorithm to be converted have no dependency, then parallel operation is selected; From the perspective of scenario requirements, if hardware resources are limited and time-division multiplexing of hardware units is required, or if periodic delays are acceptable, pipeline operation is selected; if hardware resources are sufficient and low latency or real-time performance is required, parallel operation is selected; When a single strategy cannot meet the needs, pipeline operations and parallel operations are combined to combine the advantages of both. For example, the MIMO-OFDM system adopts subtask parallelization + stage pipeline mode, and the matrix multiplication accelerator adopts parallel unit internal pipeline mode. Among them, data dependency has higher priority than scenario requirements, and subtasks can be parallelized according to scenario requirements only when they do not violate the underlying priority relationship. This step can obtain the main process and timing requirements of the algorithm implementation. According to user needs and hardware resources, the framework COT large model can flexibly generate code with parallel or pipeline characteristics; Determine the core steps in the signal processing algorithm to be converted, and decompose the core steps into a series of intermediate reasoning steps. Specifically, locate the operations that have the greatest impact on performance (such as bit error rate, capacity) through mathematical formulas, draw the data dependency graph of the algorithm, identify the critical path (the path that has the greatest impact on delay), calculate the time complexity and hardware resource requirements of each step, etc., to determine the core steps in the signal processing algorithm to be converted. The framework-based chain of ideas prompting technology decomposes the core steps into a series of intermediate reasoning steps, guiding the framework-based COT large model to standardize the core steps to improve the flexibility of the code. By formulating a framework for the signal processing algorithm from the whole to the module and then to the details, the framework-based COT large model can produce basic code that reduces storage overhead and has the ability to expand the scale of the algorithm. On the premise of ensuring the accuracy of the code, it can achieve reasonable resource allocation and improve time efficiency, which can meet the basic needs of users.

[0025] Step S02: Generate basic code according to the algorithm framework.

[0026] It is understandable that since the algorithm framework has been built, basic code executable by FPGA can be generated according to this framework.

[0027] Step S03, according to user needs, by searching the enhanced generation method, focusing on the preset part of the generated basic code, and matching professional terms, the preset part is optimized.

[0028] For example, in scenarios that require high throughput, low latency, and continuous data processing, ping-pong operations can be introduced to improve code performance through double buffering and synchronization mechanisms; in scenarios that require direct control of hardware behavior (such as high-speed interface design), primitives can be used to directly correspond to hardware resources, reducing the logic level and thus reducing latency. RAG (Retrieval-Augmented Generation) not only provides users with more accurate and professional code, but also avoids the over-optimization of the code by synthesis tools due to the fantasy of large models. While ensuring the functional integrity of the code, it further improves the execution efficiency of FPGA in hardware circuits. The optimized code output by RAG can be modified again according to user needs. After multiple adjustments of the framework-based COT large model, the final output code can be obtained.

[0029] Step S04, outputting the optimized code, wherein the basic code and the optimized code are both FPGA executable codes.

[0030] In summary, the code generation method based on RAG and framework COT in the above embodiment of the present invention, the method inputs the signal processing algorithm to be converted into the framework COT large model, and builds an algorithm framework according to the operation flow of the framework COT large model, wherein the signal processing algorithm to be converted is embodied in the form of matlab or C language; generates basic code according to the algorithm framework; according to user needs, focuses on the preset part of the generated basic code through the retrieval enhancement generation method, and optimizes the preset part by matching professional terms; outputs the optimized code, wherein the basic code and the optimized code are both FPGA executable code. Specifically, in the process of using LLM to enhance the development of HDL potential, by applying the framework-type idea chain prompting technology and retrieval enhancement generation, a code with low latency and high resource utilization is obtained, which improves the execution efficiency of FPGA in hardware circuits from the perspective of time and space.

[0031] Embodiment 2 In order to better understand the technical means of a code generation method based on RAG and framed COT in Embodiment 1 of the present invention, a specific example of designing FPGA executable code for 64-point FFT is given in Embodiment 2 of the present invention. Specifically, the basic idea of ​​FFT is to use the periodicity, symmetry, specificity of the rotation factor and the interchangeability of the period N to successively decompose the DFT operation of a sequence of N points into DFT operations of shorter sequences, merge similar items, and greatly reduce the amount of calculation.

[0032] First, using the framework COT, we evaluate that FFT has the characteristics of high time complexity and strong scalability. Figure 3 As shown in the figure, it is a structural diagram of the basic module of FFT. To implement FFT in FPGA, the following modules are required: Butterfly Unit (BPU): including multipliers and adders, responsible for performing complex multiplication and addition operations. Each BPU processes two input samples and generates two output samples; Dual-port RAM: used to store intermediate results and input / output data; Twist factor unit: responsible for dynamically generating or pre-storing twist factor values; Address transfer module: dynamically generates the correct RAM address according to the current level and operation stage of FFT; Data reordering module: in the final stage of FFT, it is usually necessary to reverse the output data; Timing management unit: used to generate and manage system clocks to ensure that each module works synchronously; Input / output interface: used to communicate with external systems, receive input data and output FFT calculation results.

[0033] The design schemes for FFT implementation include sequential processing, cascade processing, parallel processing and array processing. Considering that the 64-point FFT has a large number of operation points, a parallel processing scheme is adopted. The 64-point FFT needs to be divided into 6 levels of operation, so the 64-point FFT calculation is divided into 6 stages, each stage uses pipeline registers, and each stage has 32 butterfly operations. 32 BPUs can be designed to work in parallel, and each stage completes all butterfly operations at the same time.

[0034] In the process of implementing FFT, each butterfly operation requires complex multiplication and addition of the input data. The rotation factor is a key parameter in complex multiplication. The symmetry and periodicity of the rotation factor can greatly reduce the amount of calculation. Therefore, the calculation method of the normalized rotation factor can directly affect the efficiency of FFT implementation. For example, the following is the canonical rotation factor Step by step process of converting to a 32-bit binary sequence (with 16-bit imaginary part and 16-bit real part).

[0035] Step 1: Use Euler's formula to express , ; Step 2: Calculation The value of ; Step 3: Use 16-bit fixed-point numbers to enlarge times, The real part is quantized and rounded, , The imaginary part is quantized and rounded. ; Step 4: and Convert to binary representation, i.e. "0111111101100010" and "1111001101110100" respectively, concatenate the binary representation into a 32-bit binary sequence, using the higher / lower 16 bits as the imaginary / real part.

[0036] By applying the framework COT, LLM improves the execution efficiency of FPGA in implementing FFT from the overall link of the algorithm to the key steps. Under the decomposition strategy of FFT, the index of the original input sequence is arranged in natural order, and the single-point index after recursive binary division is arranged in reverse order of binary bits to form an inverted bit order. The input sequence index value of 64-point FFT is 0, 1, 2, 3, ..., 62, 63, and the output sequence index value is 0, 32, 16, 48, ..., 31, 63. When the output index value is 1, the corresponding index value of the input sequence should be 4. In order to correctly calculate and merge the results, the data must be reordered. It is required to improve the time efficiency of data reordering. Therefore, the need to maintain high time efficiency and resource utilization in the data reordering module can be met with the help of retrieval enhancement generation. Retrieval enhancement generation matches the specific term "ping-pong operation" through the demand. The specific operation is to store the output data in RAM3 at the first clock, RAM4 at the second clock, RAM3 at the third clock, RAM4 at the fourth clock, and so on. The 64-point FFT uses a "ping-pong operation" to store data in RAM3 and RAM4. The output sequence index values ​​in RAM3 are 0, 16, ..., 31, and the output sequence index values ​​in RAM4 are 32, 48, ..., 63. Figure 4 The figure shows the schematic diagram of the FFT structure after the "ping-pong operation" optimization. By searching and enhancing the generation of matching professional terms, LLM solves the problem of data continuity in FFT and improves time efficiency without consuming a large number of registers.

[0037] Embodiment 3 See also Figure 5 , Figure 5 1 is a structural block diagram of a code generation system based on RAG and framework COT provided in Embodiment 3 of the present invention. The code generation system 200 based on RAG and framework COT is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0038] Specifically, the code generation system 200 based on RAG and framework COT includes: an input module 21, a generation module 22, an optimization module 23 and an output module 24, wherein: An input module 21 is used to input the signal processing algorithm to be converted into the framework COT large model, and build an algorithm framework according to the operation process of the framework COT large model, wherein the signal processing algorithm to be converted is embodied in the form of matlab or C language; A generating module 22, used for generating basic codes according to the algorithm framework; The optimization module 23 is used to optimize the preset part by searching the enhanced generation method according to user needs, focusing on the preset part of the generated basic code, matching professional terms, and optimizing the preset part; The output module 24 is used to output the optimized code, wherein the basic code and the optimized code are both FPGA executable codes.

[0039] Furthermore, in some other embodiments of the present invention, the input module 21 includes: An evaluation unit, used for performing mathematical operations and five-dimensional algorithm analysis on the signal processing algorithm to be converted to obtain an evaluation result, wherein the five dimensions include complexity, robustness, scalability, scenario requirements, and implementation cost. Specifically, the complexity is obtained by measuring the time complexity and space complexity of the algorithm; The robustness is obtained by judging the anti-interference capability or dynamic channel tracking capability of the signal processing algorithm to be converted; The scalability is obtained by using various parameters applicable to the signal processing algorithm to be converted, wherein the parameters at least include the number of antennas, the number of users, and the bandwidth; The application scenarios of the signal processing algorithm to be converted include at least satellite communication, Internet of Things and 5G communication; The implementation cost is obtained by weighing performance improvement and resource consumption, taking into account hardware cost and time performance; An alignment unit, used to align the evaluation result with the module function that needs to be implemented by the FPGA, and allocate corresponding hardware resources; A hierarchical division unit is used to divide the hierarchies of the signal processing algorithm to be converted according to data dependency and scenario requirements. From the perspective of data dependency, if the signal processing algorithm to be converted is decomposed into multiple sequential stages and intermediate results need to be transferred between multiple sequential stages, pipeline operation is selected; if the elements or tasks in the data blocks of the signal processing algorithm to be converted have no dependency, parallel operation is selected; From the perspective of scenario requirements, if hardware resources are limited and time-division multiplexing of hardware units is required, or if periodic delays are acceptable, pipeline operation is selected; if hardware resources are sufficient and low latency or real-time performance is required, parallel operation is selected; When a single strategy cannot meet the needs, pipeline operations and parallel operations are combined; In addition, data dependencies take precedence over scenario requirements; A determination unit is used to determine the core steps in the signal processing algorithm to be converted, and decompose the core steps into a series of intermediate reasoning steps, wherein the core steps in the signal processing algorithm to be converted are determined by locating the operations that have the greatest impact on performance through mathematical formulas, drawing the data dependency graph of the algorithm, identifying the critical path, and calculating the time complexity and hardware resource requirements of each step.

[0040] Embodiment 4 Embodiment 4 of the present invention provides an electronic device, see Figure 6 , which is a structural block diagram of an electronic device, includes a memory 20, a processor 10, and a computer program 30 stored in the memory and executable on the processor. When the processor 10 executes the computer program 30, the code generation method based on RAG and framework COT as described above is implemented.

[0041] In some embodiments, the processor 10 may be a central processing unit (CPU), a controller, a microcontroller, a microprocessor or other data processing chip, used to run program codes or process data stored in the memory 20, such as executing access restriction programs.

[0042] Among them, the memory 20 includes at least one type of readable storage medium, and the readable storage medium includes a flash memory, a hard disk, a multimedia card, a card-type memory (for example, an SD or DX memory, etc.), a magnetic memory, a magnetic disk, an optical disk, etc. In some embodiments, the memory 20 can be an internal storage unit of an electronic device, such as a hard disk of the electronic device. In other embodiments, the memory 20 can also be an external storage device of an electronic device, such as a plug-in hard disk equipped on the electronic device, a smart memory card (Smart Media Card, SMC), a secure digital (Secure Digital, SD) card, a flash card (FlashCard), etc. Further, the memory 20 can also include both an internal storage unit of the electronic device and an external storage device. The memory 20 can not only be used to store application software and various types of data of the electronic device, but also can be used to temporarily store data that has been output or is to be output.

[0043] The embodiment of the present invention further provides a computer-readable storage medium on which a computer program is stored. When the program is executed by a processor, the code generation method based on RAG and framework COT as described above is implemented.

[0044] Those skilled in the art will appreciate that the logic and / or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable instructions for implementing logical functions, and may be specifically implemented in any computer-readable medium for use by an instruction execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch instructions from an instruction execution system, device or apparatus and execute instructions), or in conjunction with such instruction execution systems, devices or apparatuses. For purposes of this specification, "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use by an instruction execution system, device or apparatus, or in conjunction with such instruction execution systems, devices or apparatuses.

[0045] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0046] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or a combination thereof: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0047] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0048] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present invention. It should be pointed out that, for a person of ordinary skill in the art, several modifications and improvements can be made without departing from the concept of the present invention, and these all belong to the protection scope of the present invention. Therefore, the protection scope of the present invention patent shall be subject to the attached claims.

Claims

1. A code generation method based on RAG and framework COT, characterized in that: The method comprises: Input the signal processing algorithm to be converted into the framework COT large model, and build an algorithm framework according to the operation flow of the framework COT large model, wherein the signal processing algorithm to be converted is embodied in the form of matlab or C language; Generate basic code according to the algorithm framework; According to user needs, by searching and enhancing the generation method, focusing on the preset part of the generated basic code, and matching professional terms, the preset part is optimized; Output optimized code, wherein the basic code and the optimized code are both FPGA executable codes.

2. The code generation method based on RAG and framework COT according to claim 1 is characterized in that: According to the operation process of the framework COT large model, the steps of building the algorithm framework include: The signal processing algorithm to be converted is subjected to mathematical operations and algorithm analysis in five dimensions to obtain evaluation results, where the five dimensions include complexity, robustness, scalability, scenario requirements, and implementation cost; Align the evaluation results with the module functions that need to be implemented by the FPGA, and allocate corresponding hardware resources; Divide the signal processing algorithms to be converted into levels according to data dependencies and scenario requirements; The core steps in the signal processing algorithm to be converted are determined and decomposed into a series of intermediate reasoning steps.

3. The code generation method based on RAG and framework COT according to claim 2 is characterized in that: The complexity is obtained by measuring the time complexity and space complexity of the algorithm; The robustness is obtained by judging the anti-interference capability or dynamic channel tracking capability of the signal processing algorithm to be converted; The scalability is obtained by using various parameters applicable to the signal processing algorithm to be converted, wherein the parameters at least include the number of antennas, the number of users, and the bandwidth; The application scenarios of the signal processing algorithm to be converted include at least satellite communication, Internet of Things and 5G communication; The implementation cost is obtained by weighing performance improvement and resource consumption, and considering hardware cost and time performance.

4. The code generation method based on RAG and framework COT according to claim 3 is characterized in that: In the step of dividing the signal processing algorithm to be converted into levels according to data dependency and scenario requirements, from the perspective of data dependency, if the signal processing algorithm to be converted is decomposed into multiple sequential stages, and intermediate results need to be transferred between the multiple sequential stages, then pipeline operation is selected; if the elements or tasks in the data blocks in the signal processing algorithm to be converted have no dependency, then parallel operation is selected; From the perspective of scenario requirements, if hardware resources are limited and hardware units need to be time-division multiplexed, or if periodic delays are acceptable, pipeline operation is selected; If the hardware resources are sufficient and low latency or real-time performance is required, choose parallel operation; When a single strategy cannot meet the needs, pipeline operations and parallel operations are combined.

5. The code generation method based on RAG and framework COT according to claim 4 is characterized in that: Data dependencies take precedence over scenario requirements.

6. The code generation method based on RAG and framework COT according to claim 5, characterized in that: The method of determining the core steps in the signal processing algorithm to be converted and decomposing the core steps into a series of intermediate reasoning steps locates the operations that have the greatest impact on performance through mathematical formulas, draws the data dependency graph of the algorithm, identifies the critical path, and calculates the time complexity and hardware resource requirements of each step to determine the core steps in the signal processing algorithm to be converted.

7. A code generation system based on RAG and framework COT, characterized in that: For implementing the code generation method based on RAG and framework COT according to any one of claims 1 to 6, the system comprises: An input module is used to input the signal processing algorithm to be converted into the framework COT large model, and build an algorithm framework according to the operation process of the framework COT large model, wherein the signal processing algorithm to be converted is embodied in the form of matlab or C language; A generation module, used to generate basic code according to the algorithm framework; An optimization module, for optimizing the preset part by searching and enhancing the generation method according to user needs, focusing on the preset part of the generated basic code, matching professional terms, and optimizing the preset part; The output module is used to output the optimized code, wherein the basic code and the optimized code are both FPGA executable codes.

8. A computer-readable storage medium, characterized in that: include: The readable storage medium stores one or more programs, which, when executed by a processor, implement the code generation method based on RAG and framework COT as described in any one of claims 1 to 6.

9. An electronic device, characterized in that: The electronic device comprises a memory and a processor, wherein: The memory is used to store computer programs; When the processor is used to execute the computer program stored in the memory, it implements the code generation method based on RAG and framework COT as described in any one of claims 1 to 6.

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