Shifting register, gate driving circuit and display device

Abstract

The embodiment of the invention provides a shift register, a gate driving circuit and a display device. The shift register comprises an input module, a first reset module, a holding module, a noise amplification module, a reset control module, a first output module and a second output module, the input module comprises a first transistor, the first reset module comprises a second transistor, the reset control module comprises an eighth transistor, at least one of the three transistors comprises a suppression grid, and the suppression grid is connected with the first output module. The suppression grid is coupled with a preset voltage signal, the preset voltage signal is used for disconnecting the first pole and the second pole of the corresponding transistor under the condition that the signal of the first node is an effective level signal, and the preset voltage signal is provided by one of the first power supply end, the third power supply end and the second node. The first node can be prevented from electric leakage through the transistor, the effective level signal of the first node is stabilized, and the output of the first output end is stabilized.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to a shift register, a gate driving circuit and a display device. Background Art

[0002] In the related art, the shift register of the gate driving circuit uses a thin film transistor with high mobility oxide. Experiments have shown that the shift register using the high mobility oxide has an output failure problem. Summary of the invention

[0003] Embodiments of the present disclosure provide a packaging cover plate and a method for preparing the same, a display panel, and a display device to solve or alleviate one or more technical problems in the prior art.

[0004] As a first aspect of an embodiment of the present disclosure, an embodiment of the present disclosure provides a shift register, including:

[0005] An input module, coupled to the input signal terminal and the first node respectively, and configured to provide a signal from the input signal terminal to the first node under the control of an effective level signal provided by the input signal terminal;

[0006] A first reset module is coupled to the reset signal terminal, the first node and the first power supply terminal respectively, and is configured to provide a signal of the first power supply terminal to the first node under the control of an effective level signal provided by the reset signal terminal;

[0007] A holding module, coupled to the first node, the second node and the first power supply terminal respectively, and configured to provide a signal of the first power supply terminal to the second node under the control of the first node;

[0008] A noise reduction module, coupled to the second power supply terminal and the second node respectively, and configured to provide a signal of the second power supply terminal to the second node under the control of the second power supply terminal;

[0009] A reset control module, coupled to the second node, the first node and the first power supply terminal respectively, and configured to provide a signal of the first power supply terminal to the first node under the control of an effective level signal provided by the second node;

[0010] A first output module is coupled to the first node, the clock signal terminal and the first output terminal respectively, and is configured to provide a signal of the clock signal terminal to the first output terminal under the control of the first node;

[0011] A second output module is coupled to the second node, the first output terminal and the third power supply terminal respectively, and is configured to provide a signal of the third power supply terminal to the first output terminal under the control of the second node;

[0012] The shift register further includes at least one of the following:

[0013] The input module includes a first transistor, the first transistor includes a control gate, a suppression gate, a first electrode and a second electrode, the control gate and the first electrode of the first transistor are both coupled to the input signal terminal, the second electrode of the first transistor is coupled to the first node, the suppression gate of the first transistor is coupled to a preset voltage signal, the preset voltage signal is used to disconnect the first electrode and the second electrode of the first transistor when an invalid level signal is provided at the input signal terminal and the signal of the first node is a valid level signal, and the preset voltage signal is provided by one of the first power supply terminal, the third power supply terminal and the second node;

[0014] The first reset module includes a second transistor, the second transistor includes a control gate, a suppression gate, a first electrode and a second electrode, the control gate of the second transistor is coupled to the reset signal terminal, the first electrode of the second transistor is coupled to the first node, the second electrode of the second transistor is coupled to the first power supply terminal, the suppression gate of the second transistor is coupled to a preset voltage signal, the preset voltage signal is used to disconnect the first electrode and the second electrode of the second transistor when the reset signal terminal provides an invalid level signal and the signal of the first node is a valid level signal, and the preset voltage signal is provided by one of the first power supply terminal, the third power supply terminal and the second node;

[0015] The reset control module includes an eighth transistor, which includes a control gate, a suppression gate, a first electrode, and a second electrode. The control gate of the eighth transistor is coupled to the second node, the first electrode of the eighth transistor is coupled to the first node, the second electrode of the eighth transistor is coupled to the first power supply terminal, and the suppression gate of the eighth transistor is coupled to a preset voltage signal. The preset voltage signal is used to disconnect the first electrode and the second electrode of the eighth transistor when an invalid level signal is provided at the second node and the signal at the first node is a valid level signal. The preset voltage signal is provided by one of the first power supply terminal, the third power supply terminal, and the second node.

[0016] In some embodiments, a full-screen reset module is also included, the full-screen reset module includes a fifteenth transistor, the fifteenth transistor includes a control gate, a suppression gate, a first electrode and a second electrode, the control gate of the fifteenth transistor is coupled to the full-screen reset terminal, the first electrode of the fifteenth transistor is coupled to the first node, the second electrode of the fifteenth transistor is coupled to the first power supply terminal, the suppression gate of the fifteenth transistor is coupled to a preset voltage signal, the fifteenth transistor provides a signal of the first power supply terminal to the first node under the control of a valid level signal provided by the full-screen reset terminal, the preset voltage signal is used to disconnect the first electrode and the second electrode of the fifteenth transistor when an invalid level signal is provided by the full-screen reset terminal and the signal of the first node is a valid level signal, and the preset voltage signal is provided by one of the first power supply terminal, the third power supply terminal and the second node.

[0017] In some embodiments, the transistors in the shift register are all N-type transistors, and the material of the active layer of at least the first transistor, the second transistor or the eighth transistor includes an oxide semiconductor material.

[0018] In some embodiments, a pull-down module is further included, which is coupled to the input signal terminal, the second node and the first power terminal respectively, and is configured to provide a signal from the first power terminal to the second node under the control of the input signal terminal.

[0019] In some embodiments, a second reset module is further included, which is coupled to the reset signal terminal, the first output terminal and the third power supply terminal respectively, and is configured to provide a signal from the third power supply terminal to the first output terminal under the control of the reset signal terminal.

[0020] In some embodiments, the shift register is disposed in a substrate, the substrate comprising a substrate, a first insulating layer and a second insulating layer.

[0021] When the input module includes a first transistor, the suppression gate of the first transistor is located on one side of the substrate, the first insulating layer is located on a side of the suppression gate of the first transistor away from the substrate, the active layer of the first transistor is located on a side of the first insulating layer away from the substrate, the second insulating layer is located on a side of the active layer of the first transistor away from the substrate, the control gate of the first transistor is located on a side of the second insulating layer away from the substrate, the first electrode and the second electrode of the first transistor are located on a side of the active layer of the first transistor away from the substrate, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer;

[0022] When the first reset module includes a second transistor, the suppression gate of the second transistor is located on one side of the substrate, the first insulating layer is located on a side of the suppression gate of the second transistor away from the substrate, the active layer of the second transistor is located on a side of the first insulating layer away from the substrate, the second insulating layer is located on a side of the active layer of the second transistor away from the substrate, the control gate of the second transistor is located on a side of the second insulating layer away from the substrate, the first electrode and the second electrode of the second transistor are located on a side of the active layer of the second transistor away from the substrate, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer;

[0023] When the reset control module includes an eighth transistor, the suppression gate of the eighth transistor is located on one side of the substrate, the first insulating layer is located on the side of the suppression gate of the eighth transistor away from the substrate, the active layer of the eighth transistor is located on the side of the first insulating layer away from the substrate, the second insulating layer is located on the side of the active layer of the eighth transistor away from the substrate, the control gate of the eighth transistor is located on the side of the second insulating layer away from the substrate, the first electrode and the second electrode of the eighth transistor are located on the side of the active layer of the eighth transistor away from the substrate, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

[0024] In some embodiments, a shift register is disposed in a substrate, the substrate includes a substrate, a first insulating layer, and a second insulating layer, the suppression gate of the fifteenth transistor is located on one side of the substrate, the first insulating layer is located on the side of the suppression gate of the fifteenth transistor away from the substrate, the active layer of the fifteenth transistor is located on the side of the first insulating layer away from the substrate, the second insulating layer is located on the side of the active layer of the fifteenth transistor away from the substrate, the control gate of the fifteenth transistor is located on the side of the second insulating layer away from the substrate, the first electrode and the second electrode of the fifteenth transistor are located on the side of the active layer of the fifteenth transistor away from the substrate, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

[0025] In some embodiments, a ratio of a thickness of the first insulating layer to a thickness of the second insulating layer is greater than or equal to 2.

[0026] In some embodiments, the signal at the first power terminal is the same as or different from the signal at the third power terminal.

[0027] In some embodiments, the shift register includes at least one of the following:

[0028] The holding module includes a sixth transistor, a gate of the sixth transistor is coupled to the first node, and a first electrode and a second electrode of the sixth transistor are coupled to the second node and the second power supply terminal respectively;

[0029] The noise reduction module includes a fifth transistor, a gate and a first electrode of the fifth transistor are coupled to the second power supply terminal, and a second electrode of the fifth transistor is coupled to the second node;

[0030] The first output module includes a third transistor and a first capacitor, the gate of the third transistor is coupled to the first node, the first electrode and the second electrode of the third transistor are respectively coupled to the clock signal terminal and the first output terminal, and the two electrodes of the first capacitor are respectively coupled to the first node and the first output terminal;

[0031] The second output module includes a thirteenth transistor, a gate of the thirteenth transistor is coupled to the second node, and a first electrode and a second electrode of the thirteenth transistor are respectively coupled to the first output terminal and the third power supply terminal.

[0032] As a second aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a gate driving circuit, including the shift register of any embodiment of the present disclosure.

[0033] As a third aspect of the embodiments of the present disclosure, the embodiments of the present disclosure provide a display device, characterized in that it includes the shift register or gate drive circuit of any embodiment of the present disclosure.

[0034] According to the technical solution of the embodiment of the present disclosure, when the signal at the first node is a valid level signal, the preset voltage signal can suppress the threshold voltage offset of the corresponding transistor, so that the corresponding transistor is in an off state, thereby avoiding leakage of the first node through the transistor, stabilizing the valid level signal of the first node, and stabilizing the output of the first output terminal.

[0035] The above summary is for illustrative purposes only and is not intended to be limiting in any way. In addition to the illustrative aspects, embodiments and features described above, further aspects, embodiments and features of the present disclosure will be readily apparent by reference to the accompanying drawings and the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In the accompanying drawings, unless otherwise specified, the same reference numerals throughout the multiple drawings represent the same or similar parts or elements. These drawings are not necessarily drawn to scale. It should be understood that these drawings only depict some embodiments according to the present disclosure and should not be regarded as limiting the scope of the present disclosure.

[0037] Figure 1 is a schematic diagram of a shift register;

[0038] Figure 2 is a timing diagram of a shift register;

[0039] Figure 3 is a schematic diagram of another shift register;

[0040] Figure 4 is a schematic diagram of a shift register in an embodiment of the present disclosure;

[0041] Figure 5 is a schematic diagram of a shift register in another embodiment of the present disclosure;

[0042] Figure 6 is a schematic diagram of a shift register in another embodiment of the present disclosure;

[0043] Figure 7 is a schematic diagram of a shift register in another embodiment of the present disclosure;

[0044] Figure 8 is a cross-sectional schematic diagram of a substrate in a display device according to an embodiment of the present disclosure;

[0045] Fig. 9 is a timing diagram of a shift register according to an embodiment of the present disclosure;

[0046] Fig.10 FIG. 4 is a schematic diagram of a shift register in another embodiment. DETAILED DESCRIPTION

[0047] In the following, only some exemplary embodiments are briefly described. As those skilled in the art will appreciate, the described embodiments may be modified in various ways without departing from the spirit or scope of the present disclosure. Therefore, the drawings and descriptions are considered to be exemplary and non-restrictive in nature.

[0048] The transistors used in all embodiments of the present invention can be thin film transistors or field effect transistors or other devices with the same characteristics. According to the role in the circuit, the transistors used in the embodiments of the present invention are mainly switching transistors. Since the source and drain of the switching transistor used here are symmetrical, the source and drain are interchangeable. In the embodiment of the present invention, the source (source electrode) is called the first electrode, the drain (drain electrode) is called the second electrode, or the drain can be called the first electrode and the source is called the second electrode. According to the form in the accompanying drawings, the middle end of the transistor is specified as the gate (also called the gate electrode), the signal input end is the source, and the signal output end is the drain. The switching transistor used in the embodiment of the present invention can be a P-type switching transistor or an N-type transistor. The P-type switching transistor is turned on when the gate is at a low level and is turned off when the gate is at a high level; the N-type transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. In addition, multiple signals in various embodiments of the present invention correspond to a first level and a second level. The first level and the second level only represent two different level state quantities of the signal, and do not represent that the first level or the second level in the full text has a specific value. In the embodiment of the present invention, the first level is taken as an example to be described as a valid level.

[0049] The coupling may include: direct physical contact between the two ends or indirect connection between the two ends (eg, connection between the two ends via a signal line). The embodiment of the present invention does not limit the coupling method between the two ends.

[0050] Figure 1 A schematic diagram of a shift register. Figure 2 This is a timing diagram of a shift register. Figure 1As shown, the shift register uses high-mobility oxide thin film transistors (TFTs), for example, the first transistor M1, the second transistor M2, the eighth transistor M8, and the fifteenth transistor M15 all use high-mobility oxide N-type TFTs. The threshold voltage Vth of the high-mobility oxide TFT is negatively biased, that is, Vth<0. One of the first transistor M1, the second transistor M2, the eighth transistor M8, and the fifteenth transistor M15 is coupled to the first node PU. When the first node PU is at a high level, Vgs≈0 of the first transistor M1, the second transistor M2, the eighth transistor M8, and the fifteenth transistor M15, resulting in these transistors being in an on state, and the other electrodes of these transistors are all connected to a low level, which results in a path being formed between the high level of the first node PU and the low level of the other electrode, resulting in leakage of the first node PU. As shown Figure 2 As shown, due to the leakage of the first node PU, the voltage of the first node PU is unstable during the gate signal output stage, which further causes the gate signal output to be unstable, affecting the gate signal output of the shift register.

[0051] Figure 3 is a schematic diagram of another shift register. Figure 3 As shown, the first transistor M1, the second transistor M2, the eighth transistor M8, and the fifteenth transistor M15 in the shift register can be dual-gate thin film transistors. The bottom gates of the first transistor M1, the second transistor M2, the eighth transistor M8, and the fifteenth transistor M15 are all coupled to the preset power line VDDN. The preset power line VDDN provides a preset voltage signal Vddn to the bottom gates of these transistors to suppress the negative bias of Vth and realize the positive bias of Vth of these transistors, so that when the first node PU is at a high level, these transistors are in the off state to prevent the first node PU from leaking.

[0052] The preset voltage signal Vddn is not a signal required by the gate driving circuit, so the preset voltage signal Vddn needs to be increased, and then the number of IC output pins needs to be increased to connect the preset power line VDDN. This approach not only increases the demand for IC output pins, but also increases the preset power line VDDN, which is not conducive to narrow frame design.

[0053] In order to solve the problems in the related art, an embodiment of the present disclosure provides a shift register.

[0054] Figure 4 is a schematic diagram of a shift register in an embodiment of the present disclosure, Figure 5 FIG. 1 is a schematic diagram of a shift register in another embodiment of the present disclosure. Figure 4 and Figure 5As shown, the shift register includes an input module 11 , a first reset module 12 , a holding module 13 , a noise reduction module 14 , a reset control module 15 , a first output module 16 and a second output module 17 .

[0055] The input module 11 is coupled to the input signal terminal INPUT and the first node PU respectively, and is configured to provide the signal of the input signal terminal INPUT to the first node PU under the control of the effective level signal provided by the input signal terminal INPUT.

[0056] The first reset module 12 is coupled to the reset signal terminal RST, the first node PU and the first power terminal VSS1 respectively, and is configured to provide a signal of the first power terminal VSS1 to the first node PU under the control of an effective level signal provided by the reset signal terminal RST.

[0057] The holding module 13 is coupled to the first node PU, the second node PD and the first power terminal VSS1 respectively, and is configured to provide a signal of the first power terminal VSS1 to the second node PD under the control of the first node PU.

[0058] The noise reduction module 14 is coupled to the second power supply terminal VDD and the second node PD respectively, and is configured to provide a signal of the second power supply terminal VDD to the second node PD under the control of the second power supply terminal VDD.

[0059] The reset control module 15 is coupled to the second node PD, the first node PU and the first power supply terminal VSS1 respectively, and is configured to provide a signal of the first power supply terminal VSS1 to the first node PU under the control of the effective level signal provided by the second node PD.

[0060] The first output module 16 is coupled to the first node PU, the clock signal terminal CLK and the first output terminal OUT1 respectively, and is configured to provide the signal of the clock signal terminal CLK to the first output terminal OUT1 under the control of the first node PU.

[0061] The second output module 17 is coupled to the second node PD, the first output terminal OUT1 and the third power supply terminal VSS2 respectively, and is configured to provide a signal of the third power supply terminal VSS2 to the first output terminal OUT1 under the control of the second node PD.

[0062] In one embodiment, Figure 5As shown, the input module 11 includes a first transistor M1. The first transistor M1 includes a control gate, a suppression gate, a first electrode and a second electrode. The control gate and the first electrode of the first transistor M1 are coupled to the input signal terminal INPUT, the second electrode of the first transistor M1 is coupled to the first node PU, and the suppression gate of the first transistor M1 is coupled to a preset voltage signal. The preset voltage signal is used to disconnect the first electrode and the second electrode of the first transistor M1 when the input signal terminal INPUT provides an invalid level signal and the signal of the first node PU is a valid level signal. The preset voltage signal is provided by one of the first power supply terminal VSS1, the third power supply terminal VSS2 and the second node PD. That is to say, the suppression gate of the first transistor M1 can be coupled to one of the first power supply terminal VSS1, the third power supply terminal VSS2 and the second node PD.

[0063] Exemplarily, the preset voltage signal can suppress the threshold voltage shift of the first transistor when the input signal terminal INPUT provides an invalid level signal and the signal of the first node PU is a valid level signal, so that the first electrode and the second electrode of the first transistor M1 are disconnected when the input signal terminal INPUT provides an invalid level signal and the signal of the first node PU is a valid level signal.

[0064] When the input signal terminal INPUT provides a valid level signal to the control gate of the first transistor M1, the first and second electrodes of the first transistor M1 are turned on, and the signal of the input signal terminal INPUT is provided to the first node PU; when the input signal terminal INPUT provides an invalid level signal to the control gate of the first transistor M1, it is expected that the first and second electrodes of the first transistor M1 are disconnected. However, in actual applications, when the input signal terminal INPUT provides an invalid level signal to the control gate of the first transistor M1, there may be a leakage problem between the first and second electrodes of the first transistor M1, resulting in a path between the first node PU and the first electrode of the first transistor M1, resulting in leakage of the first node PU.

[0065] In the shift register of the disclosed embodiment, when the input signal terminal INPUT provides an invalid level signal and the signal of the first node PU is a valid level signal, the signal of the first electrode of the first transistor M1 is a signal opposite to the signal of the first node PU. At this time, the preset voltage signal can suppress the threshold voltage shift of the first transistor, so that the first electrode and the second electrode of the first transistor M1 are disconnected under the action of the preset voltage signal received by the suppression gate, thereby avoiding the formation of a path between the first node PU and the first electrode of the first transistor M1, thereby avoiding leakage of the first node PU, stabilizing the valid level signal of the first node PU, and stabilizing the output of the first output terminal OUT1.

[0066] In one embodiment, Figure 5As shown, the first reset module 12 includes a second transistor M2. The second transistor M2 includes a control gate, a suppression gate, a first electrode and a second electrode. The control gate of the second transistor M2 is coupled to the reset signal terminal RST, the first electrode of the second transistor M2 is coupled to the first node PU, the second electrode of the second transistor M2 is coupled to the first power supply terminal VSS1, and the suppression gate of the second transistor M2 is coupled to a preset voltage signal. The preset voltage signal is used to disconnect the first electrode and the second electrode of the second transistor M2 when the reset signal terminal RST provides an invalid level signal and the signal of the first node PU is a valid level signal. The preset voltage signal is provided by one of the first power supply terminal VSS1, the third power supply terminal VSS2 and the second node PD. In other words, the suppression gate of the second transistor M2 can be coupled to one of the first power supply terminal VSS1, the third power supply terminal VSS2 and the second node PD.

[0067] Exemplarily, the preset voltage signal can suppress the threshold voltage shift of the second transistor when the reset signal terminal RST provides an invalid level signal and the signal of the first node PU is a valid level signal, so that the first electrode and the second electrode of the second transistor M2 are disconnected when the reset signal terminal RST provides an invalid level signal and the signal of the first node PU is a valid level signal.

[0068] When the reset signal terminal RST provides a valid level signal to the control gate of the second transistor M2, the first and second electrodes of the second transistor M2 are turned on, and the signal of the first power supply terminal VSS1 is provided to the first node PU; when the reset signal terminal RST provides an invalid level signal to the control gate of the second transistor M2, it is expected that the first and second electrodes of the second transistor M2 are disconnected. However, in actual applications, when the reset signal terminal RST provides an invalid level signal to the control gate of the second transistor M2, there may be a leakage problem between the first and second electrodes of the second transistor M2, resulting in a path between the first node PU and the second electrode of the second transistor M2, resulting in leakage of the first node PU.

[0069] In the shift register of the disclosed embodiment, when the reset signal terminal RST provides an invalid level signal and the signal of the first node PU is a valid level signal, the signal of the second electrode of the second transistor M2 is a signal opposite to the signal of the first node PU. At this time, the preset voltage signal can suppress the threshold voltage offset of the first transistor, so that the first electrode and the second electrode of the second transistor M2 are disconnected under the action of the preset voltage signal received by the suppression gate, thereby avoiding the formation of a path between the first node PU and the second electrode of the second transistor M2, thereby avoiding leakage of the first node PU, stabilizing the valid level signal of the first node PU, and stabilizing the output of the first output terminal OUT1.

[0070] In one embodiment, Figure 5As shown, the reset control module 15 includes an eighth transistor M8. The eighth transistor M8 includes a control gate, a suppression gate, a first electrode and a second electrode. The control gate of the eighth transistor M8 is coupled to the second node PD, the first electrode of the eighth transistor M8 is coupled to the first node PU, the second electrode of the eighth transistor M8 is coupled to the first power supply terminal VSS1, and the suppression gate of the eighth transistor M8 is coupled to a preset voltage signal. The preset voltage signal is used to disconnect the first electrode and the second electrode of the eighth transistor M8 when the second node PD provides an invalid level signal and the signal of the first node PU is a valid level signal. The preset voltage signal is provided by one of the first power supply terminal VSS1, the third power supply terminal VSS2 and the second node PD. In other words, the suppression gate of the eighth transistor can be coupled to one of the first power supply terminal VSS1, the third power supply terminal VSS2 and the second node PD.

[0071] Exemplarily, the preset voltage signal can suppress the threshold voltage shift of the eighth transistor M8 when the second node PD provides an invalid level signal and the signal of the first node PU is a valid level signal, so that the first electrode and the second electrode of the eighth transistor M8 are disconnected when the second node PD provides an invalid level signal and the signal of the first node PU is a valid level signal.

[0072] When the second node PD provides a valid level signal to the control gate of the eighth transistor M8, the first and second electrodes of the eighth transistor M8 are turned on, and the signal of the first power supply terminal VSS1 is provided to the first node PU; when the second node PD provides an invalid level signal to the control gate of the eighth transistor M8, it is expected that the first and second electrodes of the eighth transistor M8 are disconnected. However, in actual applications, when the second node PD provides an invalid level signal to the control gate of the eighth transistor M8, there may be a leakage problem between the first and second electrodes of the eighth transistor M8, resulting in a path between the first node PU and the second electrode of the eighth transistor M8, resulting in leakage of the first node PU.

[0073] In the shift register of the embodiment of the present disclosure, when the second node PD provides an invalid level signal and the signal of the first node PU is a valid level signal, the second electrode of the eighth transistor M8 is coupled to the first power supply terminal VSS1, and the signal of the second electrode of the eighth transistor M8 is a signal opposite to the signal of the first node PU. At this time, the preset voltage signal can suppress the threshold voltage offset of the eighth transistor, so that the first electrode and the second electrode of the eighth transistor M8 are disconnected under the action of the preset voltage signal received by the suppression gate, avoiding the formation of a path between the first node PU and the second electrode of the eighth transistor M8, thereby avoiding leakage of the first node PU, stabilizing the valid level signal of the first node PU, and stabilizing the output of the first output terminal OUT1.

[0074] Exemplarily, the preset voltage signal is an invalid level signal of the corresponding transistor. For example, for the first transistor M1, the preset voltage signal may be an invalid level signal of the first transistor M1; for the second transistor M2, the preset voltage signal is an invalid level signal of the second transistor M2; for the eighth transistor M8, the preset voltage signal is an invalid level signal of the eighth transistor M8. In one embodiment, the first transistor M1, the second transistor M2 and the eighth transistor M8 may be transistors of the same type, so that the preset voltage signal is an invalid level signal of these three transistors. The specific value of the preset voltage signal can be set as needed, as long as the effect in the embodiment of the present disclosure can be achieved.

[0075] It should be noted that the signal of the first node PU is a valid level signal, which can be understood as the valid level signal of the first node PU is a valid level signal of the first output module 16 and the holding module 13. When the first node PU is a valid level signal, the first node PU can control the holding module 13 to provide the signal of the first power supply terminal VSS1 to the second node PD, and the first node PU can control the first output module 16 to provide the signal of the clock signal terminal CLK to the first output terminal OUT1.

[0076] Therefore, in the shift register of the embodiment of the present disclosure, when the signal at the first node PU is a valid level signal, the preset voltage signal can suppress the threshold voltage offset of the corresponding transistor, so that the corresponding transistor is in the off state, thereby avoiding leakage of the first node PU through the transistor, stabilizing the valid level signal of the first node PU, and stabilizing the output of the first output terminal OUT1.

[0077] Figure 6 FIG. 1 is a schematic diagram of a shift register in another embodiment of the present disclosure. Figure 6 As shown, the shift register may further include a fifteenth transistor M15. The fifteenth transistor M15 includes a control gate, a suppression gate, a first electrode, and a second electrode. The control gate of the fifteenth transistor M15 is coupled to the full-screen reset terminal T_RST, the first electrode of the fifteenth transistor M15 is coupled to the first node PU, the second electrode of the fifteenth transistor M15 is coupled to the first power supply terminal VSS1, and the suppression gate of the fifteenth transistor M15 is coupled to a preset voltage signal. The fifteenth transistor M15 provides a signal of the first power supply terminal VSS1 to the first node PU under the control of the valid level signal provided by the full-screen reset terminal T_RST. The preset voltage is used to disconnect the first electrode and the second electrode of the fifteenth transistor M15 when the full-screen reset terminal T_RST provides an invalid level signal and the signal of the first node PU is a valid level signal. The preset voltage signal is provided by one of the first power supply terminal VSS1, the third power supply terminal VSS2, and the second node PD.

[0078] Exemplarily, the preset voltage signal can suppress the threshold voltage offset of the fifteenth transistor M15 when the full-screen reset terminal T_RST provides an invalid level signal and the signal of the first node PU is a valid level signal, so that the first electrode and the second electrode of the fifteenth transistor M15 are disconnected when the full-screen reset terminal T_RST provides an invalid level signal and the signal of the first node PU is a valid level signal.

[0079] For the fifteenth transistor M15, when the full-screen reset terminal T_RST provides a valid level signal to the control gate of the fifteenth transistor M15, the first and second electrodes of the fifteenth transistor M15 are turned on, and the signal of the first power supply terminal VSS1 is provided to the first node PU; when the full-screen reset terminal T_RST provides an invalid level signal to the control gate of the fifteenth transistor M15, it is expected that the first and second electrodes of the fifteenth transistor M15 are disconnected. However, in actual applications, when the full-screen reset terminal T_RST provides an invalid level signal to the control gate of the fifteenth transistor M15, there may be a leakage problem between the first and second electrodes of the fifteenth transistor M15, resulting in a path between the first node PU and the second electrode of the fifteenth transistor M15, resulting in leakage of the first node PU.

[0080] In the shift register of the disclosed embodiment, when the full screen reset terminal T_RST provides an invalid level signal and the signal of the first node PU is a valid level signal, the second electrode of the fifteenth transistor M15 is coupled to the first power supply terminal VSS1, and the signal of the second electrode of the fifteenth transistor M15 is a signal opposite to the signal of the first node PU. At this time, the preset voltage signal can suppress the threshold voltage offset of the fifteenth transistor M15, so that the first electrode and the second electrode of the fifteenth transistor M15 are disconnected under the action of the preset voltage signal received by the suppression gate, avoiding the formation of a path between the first node PU and the second electrode of the fifteenth transistor M15, thereby avoiding leakage of the first node PU, stabilizing the valid level signal of the first node PU, and stabilizing the output of the first output terminal OUT1.

[0081] It should be noted that the exemplary structures of the input module 11, the first reset module 12, the reset control module 15 and the full-screen reset module 18 are shown in the above embodiment. Those skilled in the art can understand that the input module 11, the first reset module 12, the reset control module 15 and the full-screen reset module 18 are not limited to Figure 5The structure shown can be used as long as its function can be achieved. For example, the input module 11 can also include other components, as long as the first transistor M1 can achieve the technical effect of the present disclosure in the input module 11; the first reset module 12 can also include other components, as long as the second transistor M2 can achieve the technical effect of the present disclosure in the first reset module 12; the reset control module 15 can also include other components, as long as the eighth transistor M8 can achieve the technical effect of the present disclosure in the reset control module 15; the full-screen reset module 18 can also include other components, as long as the fifteenth transistor M15 can achieve the technical effect of the present disclosure in the full-screen reset module 18.

[0082] Exemplarily, the endpoints for providing the preset voltage signal to the first transistor M1, the second transistor M2, the eighth transistor M8, and the fifteenth transistor M15 may be different or the same. For example, the preset voltage signal required by the first transistor M1, the second transistor M2, and the fifteenth transistor M15 may be provided by the first power supply terminal VSS1, and the preset voltage signal required by the eighth transistor M8 may be provided by the second node PD.

[0083] In one embodiment, the transistors in the shift register may all be N-type transistors. The material of the active layer of at least the first transistor M1 includes an oxide semiconductor material; and / or, the material of the active layer of at least the second transistor M2 includes an oxide semiconductor material; and / or, the material of the active layer of at least the eighth transistor M8 includes an oxide semiconductor material; and / or, the material of the active layer of at least the fifteenth transistor M15 includes an oxide semiconductor material. The oxide semiconductor material may include at least one of zinc oxide (ZnO), indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), etc.

[0084] For N-type transistors, the effective level signal of each transistor in the shift register can be a high level signal. The signals of the first power supply terminal VSS1 and the third power supply terminal VSS2 can be low level signals. When the signal at the first node PU is an effective level signal, the signal at the second node PD is a low level signal. In the present disclosure, the effective level signals of each transistor can be the same or different, and the signals of the first power supply terminal VSS1 and the third power supply terminal VSS2 can be the same or different.

[0085] Exemplarily, when all transistors in the shift register are N-type transistors, the preset voltage signal may be a low level signal.

[0086] Oxide semiconductor materials have high mobility. When the active layer of the transistor uses high-mobility oxide semiconductor materials, for N-type TFTs, its threshold voltage Vth is negatively biased, that is, Vth<0. Figure 5As shown, when the first node PU is a valid level signal (i.e., a high level signal), Vgs≈0 of the first transistor M1, the second transistor M2, the eighth transistor M8, and the fifteenth transistor M15, causing the first and second electrodes of these transistors to be in an on state, resulting in leakage of the first node PU.

[0087] In the disclosed embodiment, the first transistor M1, the second transistor M2, the eighth transistor M8, and the fifteenth transistor M15 all include a control gate and a suppression gate, that is, these transistors all use dual-gate transistors, and the level of the control gate can control the transistor to be turned off or on. The suppression gate is coupled to a preset voltage signal, and the preset voltage signal is used to suppress the negative bias of the Vth of the transistor and realize the positive bias of the Vth of the transistor. Thus, under the action of the preset voltage signal, when the signal of the control gate is an invalid level signal, the first pole and the second pole of the transistor can be in the off state to prevent the first node PU from leaking through these transistors.

[0088] In one embodiment, Figure 6 As shown, the shift register may further include a pull-down module 19, which is coupled to the input signal terminal INPUT, the second node PD and the first power terminal VSS1 respectively. The pull-down module 19 is configured to provide a signal of the first power terminal VSS1 to the second node PD under the control of the input signal terminal INPUT.

[0089] Exemplarily, the pull-down module 19 may include a seventh transistor M7. The gate of the seventh transistor M7 is coupled to the input signal terminal INPUT, and the first electrode and the second electrode of the seventh transistor M7 are coupled to the second node PD and the second power supply terminal VDD, respectively. When the input signal terminal INPUT provides a valid level signal, the seventh transistor M7 provides a signal of the first power supply terminal VSS1 to the second node PD under the control of the valid level signal of the input signal terminal INPUT. When the input signal terminal INPUT provides an invalid level signal, the first electrode and the second electrode of the seventh transistor M7 are disconnected.

[0090] like Figure 5 and Figure 6 As shown, the holding module 13 is configured to provide a signal of the first power supply terminal VSS1 to the first node PU under the control of the first node PU. When the transistor in the shift register adopts an N-type TFT, the first node PU can be called a pull-up node, and the second node PD can be called a pull-down node. When the first node PU is pulled up to a valid level signal, it is expected that the first node PU can control the holding module 13 to provide the signal of the first power supply terminal VSS1 to the second node PD, so as to pull down the second node PD. However, since the holding module 13 is controlled by the first node PU, the pull-down node is pulled down to a low level and lags behind the high level of the pull-up node.

[0091] By setting a pull-down module 19, the pull-down module 19 provides the signal of the first power supply terminal VSS1 to the second node PD under the control of the input signal terminal INPUT, so that the pull-down of the second node PD and the pull-up of the first node PU can be synchronized, avoiding the first output module 16 and the second output module 17 from providing signals to the first output terminal OUT1 at the same time, and realizing that one of the first output module 16 and the second output module 17 provides an output signal to the first output terminal OUT1, thereby improving the stability of the shift register.

[0092] After the first node PU is pulled up to a high level, the high level control and holding module 13 of the first node PU provides a signal of the first power supply terminal VSS1 to the second node PD, so that the second node PD maintains a pull-down state, that is, the second node PD maintains a low level state.

[0093] like Figure 6 As shown, the shift register may further include a second reset module 21. The second reset module 21 is coupled to the reset signal terminal RST, the first output terminal OUT1 and the third power supply terminal VSS2 respectively, and is configured to provide a signal of the third power supply terminal VSS2 to the first output terminal OUT1 under the control of the reset signal terminal RST.

[0094] In the reset phase of the shift register, the reset signal terminal RST provides an effective level signal to reset the first node PU, for example, to reset the first node PU to a low level signal. After the first node PU is reset, the noise reduction module 14 provides an effective level signal (for example, a high level signal) to the second node PD under the control of the second power supply terminal VDD to reset the second node PD, for example, to reset the second node PD to a high level signal. Thus, the second output module 17 provides a signal of the third power supply terminal VSS2 to the first output terminal OUT1 under the control of the effective level signal of the second node PD to reset the first output terminal OUT1.

[0095] In the disclosed embodiment, by setting a second reset module 21, when the reset signal terminal RST provides a valid level signal, the valid level signal of the reset signal terminal RST can control the second reset module 21, directly realize the reset of the first output terminal OUT1, ensure the timely reset of the first output terminal OUT1, and avoid the reset delay of the first output terminal OUT1.

[0096] like Figure 6 As shown, the second reset module 21 may include a fourth transistor M4. A gate of the fourth transistor M4 is coupled to the reset signal terminal RST, and a first electrode and a second electrode of the fourth transistor M4 are coupled to the first output terminal OUT1 and the third power supply terminal VSS2 respectively.

[0097] like Figure 6As shown, the holding module 13 may include a sixth transistor M6. The gate of the sixth transistor M6 is coupled to the first node PU, and the first electrode and the second electrode of the sixth transistor M6 are coupled to the second node PD and the second power supply terminal VDD, respectively. When the first node PU is a valid level signal, the sixth transistor M6, under the control of the first node PU, provides a signal of the second power supply terminal VDD to the second node PD to discharge the second node PD; when the first node PU is an invalid level signal, the first electrode of the sixth transistor M6 is disconnected from the second electrode.

[0098] The noise reduction module 14 may include a fifth transistor M5, a gate and a first electrode of the fifth transistor M5 are coupled to the second power supply terminal VDD, and a second electrode of the fifth transistor M5 is coupled to the second node PD. The signal of the second power supply terminal VDD is a valid level signal, and the fifth transistor M5, under the control of the second power supply terminal VDD, provides the signal of the second power supply terminal VDD to the second node PD to charge the second node PD.

[0099] Exemplarily, the size of the sixth transistor M6 can be larger than the size of the fifth transistor M5, so the discharge speed of the second node PD through the sixth transistor M6 is greater than the charging speed of the second node PD through the fifth transistor M5. Therefore, when the first node PUPU is a valid level signal, the second node PD can maintain a pull-down state, that is, the second node PD can maintain a low level signal.

[0100] like Figure 6 As shown, the first output module 16 may include a third transistor M3 and a first capacitor C1. The gate of the third transistor M3 is coupled to the first node PU, and the first and second electrodes of the third transistor M3 are coupled to the clock signal terminal CLK and the first output terminal OUT1, respectively. The two electrodes of the first capacitor C1 are coupled to the first node PU and the first output terminal OUT1, respectively.

[0101] When the first node PU is a valid level signal, the third transistor M3 provides the signal of the clock signal terminal CLK to the first output terminal OUT1 under the control of the first node PU; after the first node PU is reset, the first electrode and the second electrode of the third transistor M3 are disconnected.

[0102] The second output module 17 may include a thirteenth transistor M13. The gate of the thirteenth transistor M13 is coupled to the second node PD, and the first electrode and the second electrode of the thirteenth transistor M13 are coupled to the first output terminal OUT1 and the third power supply terminal VSS2, respectively. When the second node PD is a valid level signal, the thirteenth transistor M13 provides a signal of the third power supply terminal VSS2 to the first output terminal OUT1 under the control of the second node PD; when the second node PD is an invalid level signal, the first electrode and the second electrode of the thirteenth transistor M13 are disconnected.

[0103] Figure 7 FIG. 1 is a schematic diagram of a shift register in another embodiment of the present disclosure. Figure 7 As shown, the shift register may further include an eleventh transistor M11. The gate of the eleventh transistor M11 is coupled to the first node PU, and the first electrode and the second electrode of the eleventh transistor M11 are coupled to the clock signal terminal CLK and the second output terminal OUT2, respectively. When the first node PU is a valid level signal, the eleventh transistor M11 provides the signal of the clock signal terminal CLK to the second output terminal OUT2 under the control of the first node PU; when the first node PU is an invalid level signal, the first electrode and the second electrode of the eleventh transistor M11 are disconnected.

[0104] like Figure 7 As shown, the shift register may further include a twelfth transistor M12. The gate of the twelfth transistor M12 is coupled to the second node PD, and the first electrode and the second electrode of the twelfth transistor M12 are coupled to the second output terminal OUT2 and the first power supply terminal VSS1, respectively. When the second node PD is a valid level signal, the twelfth transistor M12 provides a signal of the second power supply terminal VDD to the second output terminal OUT2 under the control of the second node PD; when the second node PD is an invalid level signal, the first electrode and the second electrode of the twelfth transistor M12 are disconnected.

[0105] In the gate driving circuit of the display device, the first output terminal OUT1 can be connected to the gate line of the display area, and the second output terminal OUT2 can be connected to the reset signal terminal RST of the previous stage shift register to reset the previous stage shift register. When the signals of the first power supply terminal VSS1 and the third power supply terminal VSS2 are the same, the signals output by the second output terminal OUT2 and the first output terminal OUT1 are the same.

[0106] Exemplarily, each transistor in the shift register may be an N-type TFT. The first power supply terminal VSS1 and the third power supply terminal VSS2 are both low-level signals. The signal of the first power supply terminal VSS1 and the signal of the third power supply terminal VSS2 may be the same or different. The signal of the second power supply terminal VDD may be a high-level signal.

[0107] It should be noted that Figure 6 and Figure 7 The exemplary structure of the holding module 13, the noise reduction module 14, the first output module 16, the second output module 17, the pull-down module 19 and the second reset module 21 is shown in FIG. Those skilled in the art will appreciate that these modules are not limited to Figure 6 and Figure 7 The structure shown will suffice as long as it can achieve its function.

[0108] It should be noted that, in the above-mentioned embodiments, the transistors in the shift register are all N-type TFTs, the first power supply terminal VSS1 and the third power supply terminal VSS2 can provide low-level signals, and the second power supply terminal VDD can provide high-level signals. Those skilled in the art can understand that, in other embodiments, the transistors in the shift register can be P-type TFTs, and correspondingly, the first power supply terminal VSS1 and the third power supply terminal VSS2 can provide high-level signals, and the second power supply terminal VDD can provide low-level signals.

[0109] Figure 8 The shift register of the embodiment of the present disclosure is arranged in the substrate, and the substrate includes a substrate 11 , a first insulating layer 13 and a second insulating layer 15 .

[0110] like Figure 8 As shown, the suppression gate 121 of the first transistor M1 is located on one side of the substrate 11; the first insulating layer 13 is located on the side of the suppression gate 121 of the first transistor M1 away from the substrate 11; the active layer 141 of the first transistor M1 is located on the side of the first insulating layer 13 away from the substrate 11; the second insulating layer 15 is located on the side of the active layer 141 of the first transistor M1 away from the substrate 11, and the control gate 161 of the first transistor M1 is located on the side of the second insulating layer 15 away from the substrate 11; the first electrode 181 and the second electrode 182 of the first transistor M1 are located on the side of the active layer 141 of the first transistor M1 away from the substrate 11. The thickness of the first insulating layer 13 is greater than the thickness of the second insulating layer 15.

[0111] Exemplarily, the substrate may further include a third insulating layer 17, the third insulating layer 17 is located on the side of the control gate facing away from the substrate 11, the first electrode 181 and the second electrode 182 of the first transistor M1 are located on the side of the third insulating layer 17 facing away from the substrate 11, and the first electrode and the second electrode are respectively connected to the active layer 141 of the first transistor M1 through vias penetrating the third insulating layer 17 and the second insulating layer 15.

[0112] By setting the thickness of the first insulating layer 13 to be greater than the thickness of the second insulating layer 15, the preset voltage signal of the gate can suppress the negative bias of the Vth of the transistor and achieve the positive bias of the Vth of the transistor without affecting the conduction and shutdown of the transistor, so that the conduction and shutdown of the transistor are controlled by the control gate.

[0113] Exemplarily, the ratio of the thickness of the first insulating layer to the thickness of the second insulating layer may be greater than or equal to 2. The thickness of the first insulating layer may range from 1000 angstroms to 10000 angstroms (including endpoint values), for example, the thickness of the first insulating layer may be 1000 angstroms or 10000 angstroms, or the thickness of the first insulating layer may be any value between 1000 angstroms and 10000 angstroms, for example, 5000 angstroms.

[0114] By setting the ratio of the thickness of the first insulating layer to the thickness of the second insulating layer to be greater than or equal to 2, it can be ensured that the preset voltage signal of the suppression gate can suppress the negative bias of the Vth of the transistor and realize the positive bias of the Vth of the transistor without controlling the on and off of the transistor. It can be understood that the thickness of the film layer located on the substrate is the size of the film layer in the direction perpendicular to the substrate.

[0115] like Figure 8 As shown, the suppression gate 122 of the second transistor M2 is located on one side of the substrate 11; the first insulating layer 13 is located on the side of the suppression gate 122 of the second transistor M2 away from the substrate 11; the active layer 142 of the second transistor M2 is located on the side of the first insulating layer 13 away from the substrate 11; the second insulating layer 15 is located on the side of the active layer 142 of the second transistor M2 away from the substrate 11, and the control gate 162 of the second transistor M2 is located on the side of the second insulating layer 15 away from the substrate 11; the first electrode 183 and the second electrode 184 of the second transistor M2 are located on the side of the active layer 142 of the second transistor M2 away from the substrate 11. The thickness of the first insulating layer 13 is greater than the thickness of the second insulating layer 15.

[0116] Exemplarily, the substrate may further include a third insulating layer 17, the third insulating layer 17 is located on the side of the control gate away from the substrate 11, the first electrode 183 and the second electrode 184 of the second transistor M2 are located on the side of the third insulating layer 17 away from the substrate 11, and the first electrode and the second electrode are respectively connected to the active layer 142 of the second transistor M2 through vias penetrating the third insulating layer 17 and the second insulating layer 15.

[0117] refer to Figure 8 , the suppression gate of the eighth transistor M8 is located on one side of the substrate 11; the first insulating layer 13 is located on the side of the suppression gate of the eighth transistor M8 away from the substrate 11; the active layer of the eighth transistor M8 is located on the side of the first insulating layer 13 away from the substrate 11; the second insulating layer 15 is located on the side of the active layer of the eighth transistor M8 away from the substrate 11, and the control gate of the eighth transistor M8 is located on the side of the second insulating layer 15 away from the substrate 11; the first electrode and the second electrode of the eighth transistor M8 are located on the side of the active layer of the eighth transistor M8 away from the substrate 11. The thickness of the first insulating layer 13 is greater than the thickness of the second insulating layer 15.

[0118] Exemplarily, the substrate may further include a third insulating layer 17, the third insulating layer 17 is located on the side of the control gate facing away from the substrate 11, the first electrode and the second electrode of the eighth transistor M8 are located on the side of the third insulating layer 17 facing away from the substrate 11, and the first electrode and the second electrode are respectively connected to the active layer of the eighth transistor M8 through vias penetrating the third insulating layer 17 and the second insulating layer 15.

[0119] refer to Figure 8 , the suppression gate of the fifteenth transistor M15 is located on one side of the substrate 11; the first insulating layer 13 is located on the side of the suppression gate of the fifteenth transistor M15 away from the substrate 11; the active layer of the fifteenth transistor M15 is located on the side of the first insulating layer 13 away from the substrate 11; the second insulating layer 15 is located on the side of the active layer of the fifteenth transistor M15 away from the substrate 11, and the control gate of the fifteenth transistor M15 is located on the side of the second insulating layer 15 away from the substrate 11; the first electrode and the second electrode of the fifteenth transistor M15 are located on the side of the active layer of the fifteenth transistor M15 away from the substrate 11. The thickness of the first insulating layer 13 is greater than the thickness of the second insulating layer 15.

[0120] Exemplarily, the substrate may further include a third insulating layer 17, the third insulating layer 17 is located on the side of the control gate facing away from the substrate 11, the first pole and the second pole of the fifteenth transistor M15 are located on the side of the third insulating layer 17 facing away from the substrate 11, and the first pole and the second pole are respectively connected to the active layer of the fifteenth transistor M15 through vias penetrating the third insulating layer 17 and the second insulating layer 15.

[0121] Fig. 9 The timing diagram of the shift register according to an embodiment of the present disclosure is shown below in combination with Figure 6 and Fig. 9 The working process of the shift register disclosed in the present invention is described in detail. The first power supply terminal VSS1 and the third power supply terminal VSS2 are low level signals, and the second power supply terminal VDD is a high level signal.

[0122] In the first stage T1, the input signal terminal INPUT is an effective level signal (e.g., a high level signal), the first transistor M1M1 is turned on, and the signal of the input signal terminal INPUT is provided to the first node PUPU, and the first node PUPU is pulled up. The effective level signal of the input signal terminal INPUT controls the seventh transistor M7 to be turned on, and the signal of the first power supply terminal VSS1 is provided to the second node PD, and the second node PD is pulled down.

[0123] In the first stage T1, the fifth transistor M5 is turned on, and the first power supply terminal VSS1 charges the second node PD through the fifth transistor M5; the sixth transistor M6 is turned on, and the second node PD is connected to the first power supply terminal VSS1, and the second node PD is discharged. Since the size of the sixth transistor M6 is larger than the size of the fifth transistor M5, the discharge speed of the second node PD through the sixth transistor M6 is greater than the charging speed of the second node PD through the fifth transistor M5. Therefore, when the first node PU is a valid level signal, the second node PD is coupled to the first power supply terminal VSS1 through the sixth transistor M6, and the pull-down state is maintained, that is, the second node PD can maintain a low level signal.

[0124] Since the clock signal terminal CLK is a low-level signal in the first stage T1, the third transistor M3, under the control of the first node PU, provides the low-level signal of the clock signal terminal CLK to the first output terminal OUT1, that is, the first output terminal OUT1 outputs a low-level signal. Therefore, in the first stage T1, the first output terminal OUT1 has no gate signal output.

[0125] In the second stage T2, the first node PU maintains a high-level signal, the clock signal terminal CLK is a high-level signal, and the two plates of the first capacitor C1 are coupled to the first node PU and the first output terminal OUT1 respectively. Under the control of the first node PU, the third transistor M3 provides a high-level signal to one plate of the first capacitor C1. Under the action of bootstrapping, the first capacitor C1 causes the potential of the first node PU to be rapidly raised to a higher high-level signal. The higher high-level signal of the first node PU controls the third transistor M3 to be fully turned on, and provides the high-level signal of the clock signal terminal CLK to the first output terminal OUT1. Therefore, in the second stage T2, the first output terminal OUT1 outputs a gate signal.

[0126] In the disclosed embodiment, since the suppression gates of the first transistor M1, the second transistor M2, the eighth transistor M8, and the fifteenth transistor M15 are all coupled to the preset voltage signal, the preset voltage signal is used to suppress the negative bias of the Vth of the transistor and realize the positive bias of the Vth of the transistor. Thus, under the action of the preset voltage signal, when the signal of the control gate is an invalid level signal, the first and second electrodes of the transistor can be in the off state, thereby avoiding leakage of the first node PU through these transistors. Therefore, in the second stage T2, the first node PU can stably maintain a high-level signal, so that the first output terminal OUT1 can stably output a high-level signal at the second node PDT2.

[0127] It can be understood that in the gate driving circuit, the reset signal terminal RST is connected to the output terminal of the next stage shift register, that is, when the output terminal of the next stage shift register outputs a high level, the shift register of this stage can be reset.

[0128] The timing diagram may further include a third stage T3. In the third stage T3, the reset signal terminal RST is a low level signal, and the first capacitor C1 can store charge, so the first node PU maintains a high level signal and the second node PD maintains a low level signal.

[0129] In the reset stage, the output terminal of the next-stage shift register outputs a high-level signal, the reset signal terminal RST provides a valid level signal (e.g., a high-level signal), the second transistor M2M2 and the fourth transistor M4M4 in the current-stage shift register are both turned on, the first node PU is connected to the first power supply terminal VSS1 through the second transistor M2, and the first node PU is reset to a low-level signal; the first output terminal OUT1 is coupled to the third power supply terminal VSS2 through the fourth transistor M4, and the first output terminal OUT1 outputs a low-level signal. Under the control of the second power supply terminal VDD, the fifth transistor M5 provides a high-level signal of the second power supply terminal VDD to the second node PD, and the second node PD maintains a high-level signal; under the control of the high-level signal of the second node PD, the eighth transistor M8 provides a signal of the second power supply terminal VDD to the first node PU, so that the first node PU maintains a low-level signal.

[0130] In the stages outside the first stage T1, the second stage T2 and the third stage T3, the fifth transistor M5, under the control of the second power supply terminal VDD, provides a high-level signal of the second power supply terminal VDD to the second node PD, and makes the second node PD maintain a high-level signal; the eighth transistor M8, under the control of the high-level signal of the second node PD, provides a signal of the second power supply terminal VDD to the first node PU, so that the first node PU maintains a low-level signal. In this way, the first node PU can be prevented from having a signal instability in the stages outside the first stage T1, the second stage T2 and the third stage T3, and the noise of the first output terminal OUT1 in the gateless signal output stage is reduced.

[0131] In the gate driving circuit, when one frame of picture is displayed, the full-screen reset terminal T_RST provides a full-screen reset signal to reset each shift register in the gate driving circuit to facilitate the output of the next frame of picture, thereby preventing the current frame of picture from affecting the display of the next frame of picture.

[0132] In the disclosed embodiment, in the stages other than the first stage T1, the second stage T2 and the third stage T3, that is, when there is no gate signal output, the second node PD is a high-level signal, and the high-level signal of the second node PD will not affect the on and off states of the first transistor M1, the second transistor M2, the eighth transistor M8 and the fifteenth transistor M15. In other words, although the high level of the second node PD cannot suppress the negative bias of the Vth of these transistors, in the stage of no gate signal output, even if the Vth of these transistors is negatively biased, it will not affect the normal operation of the shift register.

[0133] By analyzing the working principle of the shift register, it can be known that when the first node PU is in the pull-up state, the signal of the input signal terminal INPUT is a low level signal. In one embodiment, the preset voltage signal can also be provided by the input signal terminal INPUT.

[0134] Exemplarily, the endpoints for providing the preset voltage signal to the first transistor M1, the second transistor M2, the eighth transistor M8, and the fifteenth transistor M15 may be different or the same. For example, the preset voltage signal required by the first transistor M1 may be provided by the input signal terminal INPUT; the preset voltage signal required by the second transistor M2 and the fifteenth transistor M15 may be provided by the first power supply terminal VSS1, and the preset voltage signal required by the eighth transistor M8 may be provided by the second node PD.

[0135] Fig.10 FIG. 1 is a schematic diagram of a shift register in another embodiment. Fig.10 As shown, the shift register uses 18T1C. Fig.10 , the second output terminal is Out_C. The first transistor M1, the second transistor M2, the fifteenth transistor M15, the eighth transistor M8A and the eighth transistor M8B each include a first electrode, a second electrode, a control gate and a suppression gate, and the suppression gates of these transistors are coupled to a preset voltage signal. The preset voltage signal is provided by one of the first power supply terminal VSS1, the third power supply terminal VSS2, the second node PDA and the second node PDB.

[0136] exist Fig.10 In the embodiment, the preset voltage signal required by the first transistor M1 is provided by the input signal terminal INPUT, the preset voltage signals required by the second transistor M2 and the fifteenth transistor M15 can be provided by the first power supply terminal VSS1, the preset voltage signal required by the eighth transistor M8A can be provided by the second node PDA, and the preset voltage signal required by the eighth transistor M8B can be provided by the second node PDB.

[0137] The disclosed embodiment also provides a gate drive circuit, including the shift register in the disclosed embodiment. The gate drive circuit may include multiple shift registers, and the multiple shift registers are cascaded. The input signal terminal INPUT of the first-stage shift register is coupled to the trigger signal terminal STV, the first output terminal OUT1 or the second output terminal OUT2 of the i-th stage shift register is coupled to the reset signal terminal RST of the i-1-th stage shift register, and the first output terminal OUT1 of each stage shift register is connected to the corresponding gate line. Wherein, i is a positive integer greater than or equal to 2.

[0138] The embodiments of the present disclosure further provide a display device, the display device includes the shift register in the embodiments of the present disclosure, or the display device includes the gate driving circuit in the embodiments of the present disclosure.

[0139] The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or the like.

[0140] In the description of this specification, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.

[0141] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0142] In the present disclosure, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present disclosure can be understood according to specific circumstances.

[0143] In the present disclosure, unless otherwise clearly specified and limited, a first feature being “above” or “below” a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being “above”, “above”, and “above” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being “below”, “below”, and “below” a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0144] The disclosure above provides many different embodiments or examples to implement different structures of the present disclosure. In order to simplify the present disclosure, the components and settings of specific examples are described above. Of course, they are only examples, and the purpose is not to limit the present disclosure. In addition, the present disclosure can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed.

[0145] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of various changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A shift register, characterized in that: include: An input module, coupled to the input signal terminal and the first node respectively, and configured to provide the signal of the input signal terminal to the first node under the control of the effective level signal provided by the input signal terminal; A first reset module is coupled to a reset signal terminal, the first node and a first power supply terminal respectively, and is configured to provide a signal of the first power supply terminal to the first node under the control of a valid level signal provided by the reset signal terminal; a holding module, coupled to the first node, the second node and the first power supply terminal respectively, and configured to provide a signal of the first power supply terminal to the second node under the control of the first node; a noise reduction module, coupled to the second power supply terminal and the second node respectively, and configured to provide a signal of the second power supply terminal to the second node under the control of the second power supply terminal; a reset control module, coupled to the second node, the first node and the first power supply terminal respectively, and configured to provide a signal from the first power supply terminal to the first node under the control of a valid level signal provided by the second node; A first output module, coupled to the first node, the clock signal terminal and the first output terminal respectively, and configured to provide the signal of the clock signal terminal to the first output terminal under the control of the first node; A second output module is coupled to the second node, the first output terminal and the third power supply terminal respectively, and is configured to provide a signal of the third power supply terminal to the first output terminal under the control of the second node; Wherein, the shift register further includes at least one of the following: The input module comprises a first transistor, the first transistor comprises a control gate, a suppression gate, a first electrode and a second electrode, the control gate and the first electrode of the first transistor are both coupled to the input signal terminal, the second electrode of the first transistor is coupled to the first node, the suppression gate of the first transistor is coupled to a preset voltage signal, the preset voltage signal is used to disconnect the first electrode and the second electrode of the first transistor when an invalid level signal is provided at the input signal terminal and the signal of the first node is a valid level signal, and the preset voltage signal is provided by one of the first power supply terminal, the third power supply terminal and the second node; The first reset module includes a second transistor, the second transistor includes a control gate, a suppression gate, a first electrode and a second electrode, the control gate of the second transistor is coupled to the reset signal terminal, the first electrode of the second transistor is coupled to the first node, the second electrode of the second transistor is coupled to the first power terminal, the suppression gate of the second transistor is coupled to a preset voltage signal, the preset voltage signal is used to disconnect the first electrode and the second electrode of the second transistor when the reset signal terminal provides an invalid level signal and the signal of the first node is a valid level signal, and the preset voltage signal is provided by one of the first power terminal, the third power terminal and the second node; The reset control module includes an eighth transistor, which includes a control gate, a suppression gate, a first electrode and a second electrode. The control gate of the eighth transistor is coupled to the second node, the first electrode of the eighth transistor is coupled to the first node, the second electrode of the eighth transistor is coupled to the first power supply terminal, and the suppression gate of the eighth transistor is coupled to a preset voltage signal. The preset voltage signal is used to disconnect the first electrode and the second electrode of the eighth transistor when the second node provides an invalid level signal and the signal of the first node is a valid level signal. The preset voltage signal is provided by one of the first power supply terminal, the third power supply terminal and the second node.

2. The shift register according to claim 1, characterized in that: The present invention also includes a full-screen reset module, which includes a fifteenth transistor, and the fifteenth transistor includes a control gate, a suppression gate, a first electrode, and a second electrode. The control gate of the fifteenth transistor is coupled to the full-screen reset terminal, the first electrode of the fifteenth transistor is coupled to the first node, the second electrode of the fifteenth transistor is coupled to the first power supply terminal, and the suppression gate of the fifteenth transistor is coupled to a preset voltage signal. The fifteenth transistor provides the signal of the first power supply terminal to the first node under the control of the valid level signal provided by the full-screen reset terminal. The preset voltage signal is used to disconnect the first electrode and the second electrode of the fifteenth transistor when an invalid level signal is provided at the full-screen reset terminal and the signal of the first node is a valid level signal. The preset voltage signal is provided by one of the first power supply terminal, the third power supply terminal, and the second node.

3. The shift register according to claim 1 or 2, characterized in that: The transistors in the shift register are all N-type transistors, and the material of the active layer of at least the first transistor, the second transistor or the eighth transistor includes an oxide semiconductor material.

4. The shift register according to claim 1, wherein: It also includes a pull-down module, which is coupled to the input signal terminal, the second node and the first power supply terminal respectively, and is configured to provide the signal of the first power supply terminal to the second node under the control of the input signal terminal.

5. The shift register according to claim 1, characterized in that: It also includes a second reset module, which is respectively coupled to the reset signal terminal, the first output terminal and the third power supply terminal, and is configured to provide a signal of the third power supply terminal to the first output terminal under the control of the reset signal terminal.

6. The shift register according to claim 1, characterized in that: The shift register is arranged in a substrate, and the substrate comprises a substrate, a first insulating layer and a second insulating layer. When the input module includes a first transistor, the suppression gate of the first transistor is located at one side of the substrate, the first insulating layer is located at a side of the suppression gate of the first transistor away from the substrate, the active layer of the first transistor is located at a side of the first insulating layer away from the substrate, the second insulating layer is located at a side of the active layer of the first transistor away from the substrate, the control gate of the first transistor is located at a side of the second insulating layer away from the substrate, the first electrode and the second electrode of the first transistor are located at a side of the active layer of the first transistor away from the substrate, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer; When the first reset module includes a second transistor, the suppression gate of the second transistor is located at one side of the substrate, the first insulating layer is located at a side of the suppression gate of the second transistor away from the substrate, the active layer of the second transistor is located at a side of the first insulating layer away from the substrate, the second insulating layer is located at a side of the active layer of the second transistor away from the substrate, the control gate of the second transistor is located at a side of the second insulating layer away from the substrate, the first electrode and the second electrode of the second transistor are located at a side of the active layer of the second transistor away from the substrate, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer; When the reset control module includes an eighth transistor, the suppression gate of the eighth transistor is located on one side of the substrate, the first insulating layer is located on the side of the suppression gate of the eighth transistor away from the substrate, the active layer of the eighth transistor is located on the side of the first insulating layer away from the substrate, the second insulating layer is located on the side of the active layer of the eighth transistor away from the substrate, the control gate of the eighth transistor is located on the side of the second insulating layer away from the substrate, the first electrode and the second electrode of the eighth transistor are located on the side of the active layer of the eighth transistor away from the substrate, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

7. The shift register according to claim 2, characterized in that: The shift register is arranged in a substrate, and the substrate includes a substrate, a first insulating layer and a second insulating layer. The suppression gate of the fifteenth transistor is located on one side of the substrate, the first insulating layer is located on the side of the suppression gate of the fifteenth transistor away from the substrate, the active layer of the fifteenth transistor is located on the side of the first insulating layer away from the substrate, the second insulating layer is located on the side of the active layer of the fifteenth transistor away from the substrate, the control gate of the fifteenth transistor is located on the side of the second insulating layer away from the substrate, the first electrode and the second electrode of the fifteenth transistor are located on the side of the active layer of the fifteenth transistor away from the substrate, and the thickness of the first insulating layer is greater than the thickness of the second insulating layer.

8. The shift register according to claim 6, characterized in that: A ratio of a thickness of the first insulating layer to a thickness of the second insulating layer is greater than or equal to 2.

9. The shift register according to claim 1, characterized in that: The signal of the first power supply end is the same as or different from the signal of the third power supply end.

10. The shift register according to claim 1, characterized in that: The shift register includes at least one of the following: The holding module includes a sixth transistor, a gate of the sixth transistor is coupled to the first node, and a first electrode and a second electrode of the sixth transistor are coupled to the second node and the second power supply terminal respectively; The noise reduction module includes a fifth transistor, a gate and a first electrode of the fifth transistor are coupled to the second power supply terminal, and a second electrode of the fifth transistor is coupled to the second node; The first output module includes a third transistor and a first capacitor, the gate of the third transistor is coupled to the first node, the first electrode and the second electrode of the third transistor are respectively coupled to the clock signal terminal and the first output terminal, and the two electrodes of the first capacitor are respectively coupled to the first node and the first output terminal; The second output module includes a thirteenth transistor, a gate of the thirteenth transistor is coupled to the second node, and a first electrode and a second electrode of the thirteenth transistor are respectively coupled to the first output terminal and the third power supply terminal.

11. A gate driving circuit, characterized in that: The invention comprises the shift register according to any one of claims 1 to 10.

12. A display device, characterized in that: A shift register comprising any one of claims 1 to 10 or a gate drive circuit comprising claim 11.

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