Memory operation method and device and storage medium
By cycling and operating the target address of the chip memory on the PC side, the communication burden and efficiency problems during continuous read and write operations of the chip memory are solved, and more efficient memory operations are achieved.
Patent Information
- Application Number
- CN202411819674.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-12-11
- Publication Date
- 2025-05-13
AI Technical Summary
When the PC side performs multiple consecutive read and write operations on a single address in the chip memory, the process of configuring registers, sending instructions and register read and write operations needs to be repeated, resulting in an increase in communication burden and a decrease in operation efficiency.
When receiving the memory operation instructions, the target address and register information of the memory to be operated are determined, and the memory operation instructions are issued to the CPU of the target chip, and the CPU's running status is paused. Then, the data corresponding to the target address is determined and written to the CPU's internal register, the target operation instructions are issued to the CPU, and the write or read operations are performed. Finally, the processing is cycled until the data operation corresponding to the target address is completed, avoiding repeated configuration and operations.
It reduces frequent interactions between the PC terminal and the chip, reduces communication burden, and improves the operation efficiency of data on the same address.
Smart Images
Figure CN119987859A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of data processing technology, and in particular to a memory operation method, device and storage medium. Background Art
[0002] Before the chip is actually used, debugging the chip can timely discover and repair potential problems of the chip. During the debugging process of the chip, the personal computer (PC) can indirectly operate the memory corresponding to the chip through registers.
[0003] At present, when the PC performs read and write operations on a single address of the chip's corresponding memory, it usually sends instructions to the chip to instruct the chip to perform corresponding read and write operations on the memory through registers. In this way, when the same address needs to be read and written multiple times in a row, it is necessary to repeat the process of configuring registers, sending instructions, and register read and write operations. This repetitive process increases the communication burden between the PC and the chip, and also leads to low efficiency of the entire operation process. Summary of the invention
[0004] In order to solve the above technical problems, the present application provides a memory operation method, device and storage medium, which can reduce the communication burden between the PC and the chip and improve the efficiency of memory operation.
[0005] In the first aspect, the present application provides a memory operation method, comprising: upon receiving a memory operation instruction, determining the target address and register information of the memory to be operated, and issuing a memory operation instruction to the central processing unit CPU of the target chip; the memory operation instruction is used to indicate that the CPU state is a suspended operation state; determining the first data corresponding to the target address, and writing the target address into the first internal register of the CPU according to the register information, and writing the first data into the second internal register of the CPU; issuing a target operation instruction to the CPU; the target operation instruction is used to instruct the CPU to perform a target operation on the target address; the target operation is a write operation, or a read operation; the write operation is used to indicate that the data in the second internal register is written to the target address in the first internal register; the read operation is used to indicate that the data in the second internal register is read as the data corresponding to the target address in the first internal register; when it is determined that the data corresponding to the target address has not been operated on, performing loop processing on the data corresponding to the target address in sequence until the data corresponding to the target address is operated on; the loop processing includes: writing the target data into the second internal register, and performing the target operation on the target data; the target data is any data that has not been operated on.
[0006] In a second aspect, the present application provides a memory operation device, comprising: a communication module, which is used to determine the target address and register information of the memory to be operated when receiving a memory operation instruction, and send the memory to-be-operated instruction to the central processing unit CPU of the target chip; the memory to-be-operated instruction is used to indicate that the state of the CPU is a suspended operation state; a writing module, which is used to determine the first data corresponding to the target address, and write the target address into the first internal register of the CPU according to the register information, and write the first data into the second internal register of the CPU; the communication module is also used to send a target operation instruction to the CPU; the target operation instruction is used to instruct the CPU to perform a target operation on the target address; the target operation is a write operation, or a read operation; the write operation is used to indicate that the data in the second internal register is written to the target address in the first internal register; the read operation is used to indicate that the data in the second internal register is read as the data corresponding to the target address in the first internal register; a processing module, which is used to perform loop processing on the data corresponding to the target address in sequence when it is determined that the data corresponding to the target address has not been operated on, until the data corresponding to the target address is operated on; the loop processing includes: writing the target data into the second internal register, and performing the target operation on the target data; the target data is any data that has not been operated on.
[0007] In a third aspect, the present application provides an electronic device comprising: a processor, a memory, and a computer program stored in the memory and executable on the processor, wherein when the computer program is executed by the processor, the memory operation method of the first aspect is implemented.
[0008] In a fourth aspect, the present application provides a computer-readable storage medium, comprising: a computer program is stored on the computer-readable storage medium, and when the computer program is executed by a processor, the memory operation method of the first aspect is implemented.
[0009] In a fifth aspect, the present application provides a computer program product, comprising: when the computer program product is run on a computer, the computer implements the memory operation method of the first aspect.
[0010] The technical solution provided by the present application has the following advantages over the prior art: First, when the PC receives the memory operation instruction, it determines the target address and register information of the memory to be operated, and sends the memory operation instruction to the CPU of the target chip to indicate that the state of the CPU is a suspended operation state. After that, the PC determines the first data corresponding to the target address, and writes the target address into the first internal register of the CPU according to the register information, and writes the first data into the second internal register of the CPU. Then, the PC sends the target operation instruction to the CPU to instruct the CPU of the target chip to perform the target operation on the target address. Among them, the target operation is a write operation, or a read operation. Finally, when the PC determines that the data corresponding to the target address has not been operated, it performs a loop processing on the data corresponding to the target address in sequence until the data corresponding to the target address is operated. Among them, the loop processing includes: writing the target data into the second internal register, performing the target operation on the target data; the target data is any data that has not been operated. In this way, when operating on data at the same address, operations can be performed in a loop processing manner instead of repeatedly executing the process of configuring registers, sending instructions, and register operations. This avoids frequent interactions between the PC and the chip, reduces the communication burden between the PC and the chip, and improves the operational efficiency of operating data at the same address. BRIEF DESCRIPTION OF THE DRAWINGS
[0011] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.
[0012] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, for ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative labor.
[0013] Figure 1 One of the application scenario schematic diagrams of the memory operation method provided in the embodiment of the present application;
[0014] Figure 2 A second schematic diagram of an application scenario of the memory operation method provided in an embodiment of the present application;
[0015] Figure 3 A schematic diagram of a flow chart of a memory operation method provided in an embodiment of the present application;
[0016] Figure 4 A schematic diagram of the structure of a memory operating device provided in an embodiment of the present application;
[0017] Figure 5A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION
[0018] In order to more clearly understand the above-mentioned purposes, features and advantages of the present application, the scheme of the present application will be further described below. It should be noted that the embodiments of the present application and the features in the embodiments can be combined with each other without conflict.
[0019] In the following description, many specific details are set forth to facilitate a full understanding of the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only part of the embodiments of the present application, rather than all of the embodiments.
[0020] First, some nouns or terms involved in the embodiments of the present application are explained below.
[0021] Open On-Chip Debugger (OpenOCD) is an open source chip debugger that can provide debugging and programming support for a variety of microcontrollers and System on Chip (SoC). Developers can customize the development of flash drivers and configuration files, and then program, debug and verify the chip through the debugging emulator.
[0022] Register: A small, fast storage unit that is usually located inside a chip, controller, or processor. It is used to temporarily store data, instructions, and intermediate calculation results. When the processor executes instructions, registers are used to store operation data, calculation results, or control information.
[0023] Memory: It is a hardware component used to store data and programs for a long time. It can be a memory module, such as Random Access Memory (RAM), Read-Only Memory (ROM), etc.), or an external storage device, such as a hard disk, Flash, etc.
[0024] Reduced Instruction Set Computing (RISC-V) architecture: is an open, reduced instruction set computing (RISC) architecture that defines the rules and protocols for computer processors to execute instructions. It provides a concise and efficient instruction set, and through a modular design allows users to expand the instruction set as needed.
[0025] The following is a detailed description of the memory operation method, device and storage medium provided in the embodiments of the present application through specific embodiments in conjunction with the accompanying drawings.
[0026] Figure 1 A schematic diagram of an application scenario of a memory operation method provided in an embodiment of the present application. Figure 1 As shown, the scenario includes a PC terminal 100 and a target board 200. The target board 200 includes a chip 201 and a memory 204; the chip 201 includes a CPU 202 and a controller 203. The PC terminal 100 can interact with the chip in the target board 200. The PC terminal can include but is not limited to various personal computers, laptops, smart phones, tablet computers, portable wearable devices, etc.
[0027] In some embodiments, Figure 2 As shown, the PC end 100 can interact with the chip in the target board 200 through the debugger 300. Among them, the PC end 100 and the debugger 300 interact through a port, and the debugger 300 and the chip in the target board 200 interact through a cable connection.
[0028] In some embodiments, the debugger 300 may be a Joint Test Action Group (JTAG) debugger, and the chip 201 may include a JTAG register. The PC 100 may change the content of the JTAG register in the chip 201 through the debugger 300 to control the CPU 202 to operate the memory 204.
[0029] It should be noted that the memory operation method provided in the embodiment of the present application can be executed through the above-mentioned PC terminal 100.
[0030] The memory operation method provided in the embodiment of the present application can be executed by the memory operation device, and the memory operation device can be hardware or software. When the memory operation device is hardware, it can be various electronic devices with the operation function of running the memory, including but not limited to mobile phones, computers, computers, tablet computers, etc. When the memory operation device is software, it can be installed in the electronic devices listed above. It can be implemented as multiple software or software modules, or it can be implemented as a single software or software module. It is not specifically limited here.
[0031] Figure 3 A flowchart of a memory operation method provided in an embodiment of the present application is shown in FIG. Figure 3 As shown, the memory operation method may include the following steps.
[0032] S11. When receiving a memory operation instruction, determine the target address and register information of the memory to be operated, and send the memory operation instruction to the central processing unit CPU of the target chip.
[0033] First, it is determined that a memory operation instruction is received.
[0034] Specifically, OpenOCD, as a software debugging tool, can realize Figure 2 The control and management of the debugger 300 in the target chip. Thus, the PC side can control the debugger to access the debug register (such as the JTAG register) by running and operating OpenOCD, thereby operating the memory of the target chip. OpenOCD supports multiple access modes to adapt to different hardware architectures and debugging requirements. Among them, the access mode includes an access mode using the system bus, an access mode using the program cache area, and an access mode using the abstract memory. The PC side can read the configuration and status information of the target chip in the debug register through OpenOCD to determine the access mode. When it is determined that the access mode is an access mode using the program cache area, it is determined that a memory operation instruction is received.
[0035] In some embodiments, the method of determining that a memory operation instruction is received may also be that a relevant person triggers an operation on a PC to send a memory operation instruction for the target chip to the PC. For example, a user may set a script file (a file with a suffix of .cfg) to select the same memory address for multiple consecutive operations to trigger the sending of a memory operation instruction for the target chip to the PC. Multiple consecutive operations on the same memory address refer to multiple consecutive readings of data from the same address or multiple consecutive writings of data to the same address.
[0036] Secondly, the PC determines the target address of the memory to be operated. Specifically, when the relevant personnel issue the memory operation instruction, they will indicate the target address of the memory to be operated.
[0037] Again, the PC determines the register information. The register information includes at least the number, identification, address, and size of the register. Specifically, the target chip has a register for debugging, such as a JTAG register, and the PC can obtain the register information by accessing the debug register.
[0038] Finally, the PC sends a memory pending operation instruction to the central processing unit (CPU) of the target chip. The memory pending operation instruction is used to indicate that the CPU is in a suspended state. Specifically, after the PC sends the memory pending operation instruction to the CPU, it can check the status register in the target chip to determine whether the breakpoint instruction has been automatically inserted and whether the CPU is already in a suspended state; if the breakpoint instruction has not been inserted, the PC inserts the breakpoint instruction; if the CPU is not in a suspended state, the PC sends an error report, or the PC instructs the CPU to stop running through the JTAG register.
[0039] In some embodiments, the register includes a program cache register, and the PC can send memory instructions to be operated to the CPU by writing instructions into the program cache register.
[0040] In some embodiments, when the operation indicated by the memory operation instruction is a write operation, the memory operation method also includes determining the data corresponding to the target address of the memory to be operated, and verifying the data to ensure the correctness of the data, for example, whether the data size matches the memory size, whether the data is correct, etc.
[0041] In some embodiments, the memory operation instruction carries a save instruction for instructing the CPU to save the data of the internal register so as to restore the CPU to an initial state when the memory operation is completed.
[0042] S12, determining the first data corresponding to the target address, and writing the target address into the first internal register of the CPU according to the register information, and writing the first data into the second internal register of the CPU.
[0043] First, the first data corresponding to the target address is determined, wherein the first data corresponding to the target address refers to the first data to be read from the target address, or the first data to be written to the target address.
[0044] Specifically, when the target operation is a read operation, the PC terminal sends a read instruction to the controller of the target chip before determining the first data corresponding to the target address. The read instruction includes the target address, which is used to instruct the controller to read the data to be read in the target address. The first data of the data to be read is determined as the first data corresponding to the target address. When the target operation is a write operation, the PC terminal obtains the data to be written corresponding to the target address before determining the first data corresponding to the target address, and determines the first data in the data to be written as the first data corresponding to the target address.
[0045] Secondly, the target address is written into the first internal register of the CPU according to the information of the register. The first internal register is used to temporarily store the target address of the operated memory. For example, in the RISC-V architecture, the first internal register can be the s0 internal register of the CPU.
[0046] Specifically, the registers in the register information obtained in step S11 include a data register and a command register. The method of writing the target address into the first internal register of the CPU according to the register information may be to write the target address into the data register according to the information of the data register, and to send a first command to the command register according to the information of the command register to instruct the command register to write the target address into the first internal register of the CPU.
[0047] Finally, the first data is written into the second internal register of the CPU according to the information of the register. The second internal register is used to temporarily store the data corresponding to the target address. For example, in the RISC-V architecture, the first internal register may be the s1 internal register of the CPU.
[0048] Specifically, the registers in the register information obtained in step S11 include a data register and a command register. The method of writing the first data into the second internal register of the CPU according to the register information may be to write the first data into the data register according to the information of the data register, and to send a second command to the command register according to the information of the command register to instruct the command register to write the first data into the second internal register of the CPU.
[0049] In some embodiments, when the target operation is a read operation, the data register is a data register of a controller in the target chip. For example, when the memory is a flash memory, the controller in the target chip is a flash controller, and when the target operation is a read operation, the data register is a data register in the flash controller. When the target operation is a write operation, the data register is a corresponding data register of the debugger in the target chip. For example, when the debugger is a JTAG debugger and the target operation is a write operation, the data register is a JTAG data register.
[0050] S13. Send target operation instructions to the CPU.
[0051] Among them, the target operation instruction is used to instruct the CPU to perform a target operation on the target address; the target operation is a write operation, or a read operation; the write operation is used to instruct the data in the second internal register to be written to the target address in the first internal register; the read operation is used to instruct the data in the second internal register to be read as the data corresponding to the target address in the first internal register.
[0052] Specifically, the registers in the register information obtained in step S11 include program cache registers, and the target operation instructions are sent to the CPU by writing instructions into the program cache registers.
[0053] S14, when it is determined that the data corresponding to the target address has not been operated on, executing loop processing on the data corresponding to the target address in sequence until the data corresponding to the target address is operated on.
[0054] The loop processing includes: writing the target data into the second internal register, and performing a target operation on the target data; the target data is any data that has not been operated on.
[0055] Specifically, the register in the register information obtained in step S11 includes an abstract command automatic execution register, and the data corresponding to the target address is executed in a loop in sequence until the data operation corresponding to the target address is completed. The method can be: first, an automatic execution command is sent to the abstract command automatic execution register according to the information of the abstract command automatic execution register to indicate that when a target data is written in the data register, the abstract command automatic execution register automatically executes a loop processing; when it is determined that the data operation corresponding to the target address is completed, a close command is sent to the abstract command automatic execution register to indicate that the data operation corresponding to the target address is completed.
[0056] In some embodiments, after the data operation corresponding to the target address is completed, the memory operation method further includes sending a recovery instruction to the CPU to instruct the CPU to recover to an initial state.
[0057] In the above scheme, first, when the PC side receives the memory operation instruction, it determines the target address and register information of the memory to be operated, and sends the memory operation instruction to the CPU of the target chip to indicate that the CPU state is a suspended operation state. After that, the PC side determines the first data corresponding to the target address, and writes the target address into the first internal register of the CPU according to the register information, and writes the first data into the second internal register of the CPU. Then, the PC side sends the target operation instruction to the CPU to instruct the CPU of the target chip to perform the target operation on the target address. Among them, the target operation is a write operation, or a read operation. Finally, when the PC side determines that the data corresponding to the target address has not been operated, it performs a loop processing on the data corresponding to the target address in sequence until the data corresponding to the target address is operated. Among them, the loop processing includes: writing the target data into the second internal register, performing the target operation on the target data; the target data is any data that has not been operated. In this way, when operating on data at the same address, the operation can be performed in a loop processing manner instead of repeatedly executing the process of configuring registers, sending instructions, and register operations. This avoids frequent interactions between the PC and the chip, reduces the communication burden between the PC and the chip, and improves the operational efficiency of operating data at the same address.
[0058] In some embodiments, the memory operation method also includes: detecting a data or state error when executing the target operation, recording the current operation position, and providing a basis for subsequent error location and problem repair. Afterwards, immediately restore the state of the pre-saved CPU internal registers to ensure that the CPU can return to its initial state to avoid the impact of the error state on subsequent operations. After restoring the CPU initial state, continue to complete the data transmission that was not completed before. If the system still cannot successfully complete the data transmission, report the error information to the host computer display interface of the PC. Among them, the error information may include the error type, the location where the error occurred, the state of the relevant registers, etc.
[0059] The embodiment of the present application can divide the memory operation device into functional modules according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing unit. The above integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.
[0060] like Figure 4 As shown, it is a structural schematic diagram of a memory operating device provided in an embodiment of the present application, which is applied to a security operation center. The memory operating device includes a communication module 51, a writing module 52, and a processing module 53.
[0061] The communication module 51 is used to determine the target address and register information of the memory to be operated upon receiving the memory operation instruction, and send the memory operation instruction to the central processing unit CPU of the target chip; the memory operation instruction is used to indicate that the CPU state is a suspended operation state; the writing module 52 is used to determine the first data corresponding to the target address, and write the target address into the first internal register of the CPU according to the register information, and write the first data into the second internal register of the CPU; the communication module 51 is also used to send the target operation instruction to the CPU; the target operation instruction is used to instruct the CPU to perform the target operation on the target address; the target operation is a write operation, or a read operation; the write operation is used to indicate that the data in the second internal register is written to the target address in the first internal register; the read operation is used to indicate that the data in the second internal register is read as the data corresponding to the target address in the first internal register; the processing module 53 is used to perform loop processing on the data corresponding to the target address in sequence when it is determined that the data corresponding to the target address has not been operated on, until the data corresponding to the target address is operated on; the loop processing includes: writing the target data into the second internal register, and performing the target operation on the target data; the target data is any data that has not been operated on.
[0062] In some embodiments, the communication module 51 is also used to send a read instruction to the controller of the target chip before determining the first data corresponding to the target address when the target operation is a read operation; the read instruction includes the target address, which is used to instruct the controller to read the data to be read in the target address; the write module 52 is specifically used to determine the first data of the data to be read as the first data corresponding to the target address; the communication module 51 is also used to obtain the data to be written corresponding to the target address before determining the first data corresponding to the target address when the target operation is a write operation; the write module 52 is specifically used to determine the first data in the data to be written as the first data corresponding to the target address.
[0063] In some embodiments, the register includes a data register and a command register; the write module 52 is specifically used to: write the target address into the data register according to the information of the register, and send a first command to the command register; the first command is used to instruct the command register to write the target address into the first internal register of the CPU; write the first data into the data register according to the information of the register, and send a second command to the command register; the second command is used to instruct the command register to write the first data into the second internal register of the CPU.
[0064] In some embodiments, when the target operation is a read operation, the data register is a data register of the target chip controller; when the target operation is a write operation, the data register is a corresponding data register of the debugger in the target chip.
[0065] In some embodiments, the register includes an abstract command automatic execution register; the processing module 53 is specifically used to: send an automatic execution command to the abstract command automatic execution register according to the information of the register; the automatic execution command is used to indicate: when a target data is written in the data register, the abstract command automatic execution register automatically executes the loop processing once; when it is determined that the data operation corresponding to the target address is completed, send a close command to the abstract command automatic execution register.
[0066] In some embodiments, the register includes a program cache register; the communication module 51 is specifically used to send the memory to-be-operated instructions and the target operation instructions to the CPU by writing instructions into the program cache register.
[0067] The memory operating device provided in this embodiment can execute the memory operating method provided in the above method embodiment. Its implementation principle and technical effect are similar to those of the above method and will not be repeated here.
[0068] Figure 5 An electronic device according to an exemplary embodiment may include a processor 802, and the processor 802 is used to execute application code to implement the memory operation method in the present application.
[0069] The processor 802 may be a central processing unit (CPU), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits for controlling the execution of the program of the present application.
[0070] like Figure 5 As shown, the electronic device may further include a memory 803. The memory 803 is used to store application program codes for executing the solution of the present application, and the execution is controlled by the processor 802.
[0071] The memory 803 may be a read-only memory (ROM) or other types of static storage devices that can store static information and instructions, a random access memory (RAM) or other types of dynamic storage devices that can store information and instructions, or an electrically erasable programmable read-only memory (EEPROM), or any other medium that can be used to carry or store the desired program code in the form of instructions or data structures and can be accessed by a computer, but is not limited thereto. The memory 803 may exist independently and be connected to the processor 802 via the bus 804. The memory 803 may also be integrated with the processor 802.
[0072] like Figure 5 As shown, the electronic device may further include a communication interface 801, wherein the communication interface 801, the processor 802, and the memory 803 may be coupled to each other, for example, via a bus 804. The communication interface 801 is used to exchange information with other devices, for example, to support information exchange between the electronic device and other devices.
[0073] It should be pointed out that Figure 5 The device structure shown in the figure does not constitute a limitation on the electronic device, except Figure 5 In addition to the components shown, the electronic device may include more or fewer components than shown, or combine certain components, or arrange the components differently. The electronic device provided in this embodiment can execute the memory operation method provided in the above method embodiment, and its implementation principle and technical effect are similar to the above method, which will not be repeated here.
[0074] An embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, each process of the memory operation method in the above method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
[0075] The computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.
[0076] An embodiment of the present application provides a computer program product, which stores a computer program. When the computer program is executed by a processor, each process of the memory operation method in the above method embodiment is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.
[0077] Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present application may adopt the form of a computer program product implemented on one or more computer-usable storage media that include computer-usable program code.
[0078] In the present application, the processor may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may also be any conventional processor, etc.
[0079] In this application, memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. Memory is an example of a computer-readable medium.
[0080] In this application, computer-readable media includes permanent and non-permanent, removable and non-removable storage media. Storage media can implement information storage by any method or technology, and the information can be computer-readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, which can be used to store information that can be accessed by a computing device. According to the definition in this article, computer-readable media does not include temporary computer-readable media (transitory media), such as modulated data and carriers.
[0081] It should be noted that, in this article, relational terms such as "first" and "second" are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.
[0082] The above description is only a specific implementation of the present application, so that those skilled in the art can understand or implement the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein can be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments described herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.
Claims
1. A method for operating a memory, characterized in that: include: When receiving a memory operation instruction, determining the target address and register information of the memory to be operated, and sending the memory operation instruction to the central processing unit (CPU) of the target chip; the memory operation instruction is used to indicate that the state of the CPU is determined to be a suspended operation state; Determine the first data corresponding to the target address, and write the target address into the first internal register of the CPU according to the register information, and write the first data into the second internal register of the CPU; Sending a target operation instruction to the CPU; the target operation instruction is used to instruct the CPU to perform a target operation on the target address; the target operation is a write operation or a read operation; the write operation is used to instruct writing the data in the second internal register to the target address in the first internal register; the read operation is used to instruct reading the data in the second internal register as the data corresponding to the target address in the first internal register; When it is determined that the data corresponding to the target address has not been operated on, performing loop processing on the data corresponding to the target address in sequence until the data corresponding to the target address is operated on; The loop processing includes: writing target data into the second internal register, and performing the target operation on the target data; The target data is any data that has not been completely operated on.
2. The operating method according to claim 1, characterized in that: When the target operation is a read operation, before determining the first data corresponding to the target address, the method further includes: Sending a read instruction to the controller of the target chip; the read instruction includes the target address, which is used to instruct the controller to read the data to be read in the target address; The determining the first data corresponding to the target address includes: Determine the first data of the to-be-read data as the first data corresponding to the target address; When the target operation is a write operation, before determining the first data corresponding to the target address, the method further includes: Obtaining the data to be written corresponding to the target address; The determining the first data corresponding to the target address includes: The first data in the data to be written is determined as the first data corresponding to the target address.
3. The operating method according to claim 1, characterized in that: The register includes a data register and a command register; writing the target address into a first internal register of the CPU and writing the first data into a second internal register of the CPU according to information of the register, comprising: Writing the target address into the data register according to the information of the register, and sending a first command to the command register; the first command is used to instruct the command register to write the target address into a first internal register of the CPU; The first data is written into the data register according to the information of the register, and a second command is sent to the command register; the second command is used to instruct the command register to write the first data into a second internal register of the CPU.
4. The operating method according to claim 3, characterized in that: The register also includes an abstract command automatic execution register, and the sequentially executing loop processing on the data corresponding to the target address until the data operation corresponding to the target address is completed includes: Sending an automatic execution command to the abstract command automatic execution register according to the information of the register; the automatic execution command is used to indicate that when a target data is written into the data register, the abstract command automatic execution register executes the loop processing once; When it is determined that the data operation corresponding to the target address is completed, a close command is sent to the abstract command automatic execution register.
5. The operating method according to claim 3, characterized in that: When the target operation is a read operation, the data register is a data register of the target chip controller; When the target operation is a write operation, the data register is a data register corresponding to the debugger in the target chip.
6. The operating method according to any one of claims 1 to 5, characterized in that: The register includes a program cache register, and the method further includes: By writing instructions into the program cache register, the memory to-be-operated instructions and the target operation instructions are sent to the CPU.
7. A memory operating device, characterized in that: include: The communication module is used to determine the target address and register information of the memory to be operated upon receiving the memory operation instruction, and send the memory operation instruction to the central processing unit CPU of the target chip; the memory operation instruction is used to indicate that the state of the CPU is determined to be a suspended operation state; A writing module, used for determining the first data corresponding to the target address, and writing the target address into the first internal register of the CPU according to the information of the register, and writing the first data into the second internal register of the CPU; The communication module is further used to send a target operation instruction to the CPU; the target operation instruction is used to instruct the CPU to perform a target operation on the target address; the target operation is a write operation or a read operation; the write operation is used to instruct to write the data in the second internal register to the target address in the first internal register; the read operation is used to instruct to read the data in the second internal register as the data corresponding to the target address in the first internal register; A processing module, configured to, when it is determined that the data corresponding to the target address has not been operated on, sequentially perform loop processing on the data corresponding to the target address until the data corresponding to the target address is operated on; The loop processing includes: writing target data into the second internal register, and performing the target operation on the target data; The target data is any data that has not been completely operated on.
8. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and executable on the processor, wherein the computer program, when executed by the processor, implements the memory operating method according to any one of claims 1 to 6.
9. A computer-readable storage medium, characterized in that: include: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the memory operating method according to any one of claims 1 to 6 is implemented.
10. A computer program product, characterized in that When the computer program product is executed on a computer, the computer is enabled to implement the memory operating method according to any one of claims 1 to 6.