Flash data storage method, flash data reading method and flash memory

Abstract

The present application provides a flash memory data storage method, a flash memory data reading method, and a flash memory; the storage method includes inverting the original data, forming a codeword from the original data, the inverted data, redundant data, and parity data, inverting the codeword, and writing the codeword and the inverted codeword into the flash memory; the reading method includes reading the codeword and the inverted codeword from the flash memory, restoring the inverted codeword by inverting it, comparing and adjusting the original codeword data and the restored codeword data bit by bit, extracting the codeword containing the original data and the inverted data, restoring the inverted data by inverting it, comparing and adjusting the original data and the restored data bit by bit to obtain the original data, and after adjusting and supplementing the redundant data, performing error correction decoding on the adjusted data to obtain the target read data; by utilizing the characteristic that the state flip probabilities of flash memory data storage are not equal, multiple copies of the original data and the inverted data are backed up, statistically adjusted, and the probability of correctly reading the data is improved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of memories, and particularly to a flash memory data storage method, a flash memory data reading method, and a flash memory. Background Art

[0002] Flash memory (NAND Flash) is a non-volatile data storage device that does not lose data when powered off. Due to the characteristics of flash memory itself, the data stored in it may have different degrees of error counts due to factors such as environmental temperature, storage time, and wear level. When the error count reaches a certain level and exceeds the error correction ability of the main control chip, the data may be lost. By adding multiple backup data, it is beneficial to increase the probability of correctly obtaining key data information. Currently, most of the multi-backup methods store multiple identical backups in the flash memory. The differences mainly lie in selecting different backup quantities according to different storage space and reading time requirements. By increasing the backup quantity, it is expected to improve the probability of reading correct data. These backup data are all the same, and the probability of error is theoretically the same. Therefore, the improvement of the data reading correct probability is limited. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of protection of the claims.

[0004] An object of the present application is to solve at least to some extent one of the technical problems existing in the related art. Embodiments of the present application provide a flash memory data storage method, a flash memory data reading method, and a flash memory, which can improve the probability of correctly reading data.

[0005] In an embodiment of the first aspect of the present application, a flash memory data storage method includes:

[0006] Obtain the original data to be backed up;

[0007] Invert the original data to obtain inverted data;

[0008] Form a codeword from the original data, the inverted data, redundant data, and check data;

[0009] Invert the codeword to obtain an inverted codeword;

[0010] Determine the number p of codewords and the number q of inverted codewords according to the storage space and reliability requirements of the flash memory;

[0011] Write p copies of the codeword and q copies of the inverted codeword into the flash memory.

[0012] According to certain embodiments of the first aspect of the present application, the forming of the codeword from the original data, the inverted data, redundant data, and check data includes:

[0013] Obtain the size of the original data and the size of the user data area of the codeword;

[0014] Determine the maximum number of the original data and the inverted data according to the size of the original data and the size of the user data area of the codeword;

[0015] Determine the number n of the original data and the number m of the inverted data according to the maximum number;

[0016] Form the user data area of the codeword with n copies of the original data, m copies of the inverted data and redundant data; form the check data area of the codeword with the check data;

[0017] Form the codeword with the user data area and the check data area.

[0018] According to some embodiments of the first aspect of the present application, the position areas where p copies of the codewords and q copies of the inverted codewords are written in the flash memory are the same or have the same storage characteristics.

[0019] According to some embodiments of the first aspect of the present application, the writing of p copies of the codewords and q copies of the inverted codewords into the flash memory includes:

[0020] Write p copies of the codewords and q copies of the inverted codewords into the same block, the same page or the offset within the same page of the flash memory.

[0021] According to some embodiments of the first aspect of the present application, the redundant data consists of data 0.

[0022] Embodiments of the second aspect of the present application, a method for reading flash memory data, the data in the flash memory is backed up according to the flash memory data storage method as described in the embodiments of the first aspect of the present application; the flash memory data reading method includes:

[0023] Obtain the first data storage address of the data to be read;

[0024] Read at least one codeword and at least one inverted codeword from the flash memory according to the first data storage address;

[0025] Invert the inverted codeword to obtain a restored codeword;

[0026] Perform comparison and adjustment on the codeword and the restored codeword bit by bit to obtain a valid codeword;

[0027] Extract the original data and the inverted data from the user data area of the valid codeword;

[0028] Invert the inverted data to obtain restored data;

[0029] Perform a comparison adjustment on the original data and the restored data bit by bit to obtain the first valid data;

[0030] Replace the user data area of the first valid data with the first valid data and redundant data to obtain the second valid data;

[0031] Perform error correction decoding on the second valid data according to the check data in the check data area of the second valid data to obtain the target read data.

[0032] According to some embodiments of the second aspect of the present application, the performing a comparison adjustment on the codeword and the restored codeword bit by bit to obtain a valid codeword includes:

[0033] Count the first quantity of data 0 and the second quantity of data 1 at the same bit position in the user data area of the codeword and the user data area of the restored codeword;

[0034] When the first quantity is greater than the second quantity, determine that the first candidate data at the bit position is data 0;

[0035] When the first quantity is less than the second quantity, determine that the first candidate data at the bit position is data 1;

[0036] Combine the first candidate data of each bit position to obtain a valid codeword.

[0037] According to some embodiments of the second aspect of the present application, the performing a comparison adjustment on the original data and the restored data bit by bit to obtain the first valid data includes:

[0038] Align the original data and the restored data;

[0039] Count the third quantity of data 0 and the fourth quantity of data 1 at the same bit position in the original data and the restored data;

[0040] When the third quantity is greater than the fourth quantity, determine that the second candidate data at the bit position is data 0;

[0041] When the third quantity is less than the fourth quantity, determine that the second candidate data at the bit position is data 1;

[0042] Combine the second candidate data of each bit position to obtain the first valid data.

[0043] An embodiment of the third aspect of the present application is a flash memory that applies the flash memory data storage method described in the embodiment of the first aspect of the present application and the flash memory data reading method described in the embodiment of the second aspect of the present application; the flash memory includes a storage controller and flash memory particles, and the storage controller is connected to the flash memory particles; the storage controller includes a codeword adjustment control module and an error correction control module; the codeword adjustment control module is used to perform related operations on codewords; the error correction control module is used to perform error correction decoding operations.

[0044] According to certain embodiments of the third aspect of the present application, the storage controller further includes a protocol interface control module, a system processor, and a system cache. The codeword adjustment control module and the error correction control module are provided in the flash memory read / write control module, and the protocol interface control module, the system processor, and the system cache are connected to the flash memory read / write control module through an internal bus.

[0045] The above solution has at least the following beneficial effects: The storage method includes inverting the original data, forming a codeword with the original data, the inverted data, the redundant data, and the check data, inverting the codeword, and writing the codeword and the inverted codeword into the flash memory; the reading method includes reading the codeword and the inverted codeword from the flash memory, restoring the inverted codeword by inverting it, performing comparison and adjustment on the original data and the restored data bit by bit, extracting the original data and the inverted data, restoring the inverted data by inverting it, performing comparison and adjustment on the original data and the restored data bit by bit, and performing error correction decoding on the adjusted data to obtain the target read data; by utilizing the characteristic that the probabilities of the flash memory data storage state flips are not equal, multiple copies of the original data and the inverted data are backed up, statistically adjusted, and the probability of correctly reading the data is improved. Description of the Drawings

[0046] The drawings are used to provide a further understanding of the technical solution of the present application, and constitute a part of the specification. Together with the embodiments of the present application, they are used to explain the technical solution of the present application, and do not constitute a limitation to the technical solution of the present application.

[0047] Figure 1 is a step diagram of the flash memory data storage method provided by the embodiment of the present application;

[0048] Figure 2 is a sub-step diagram of step S130;

[0049] Figure 3 is a step diagram of the flash memory data reading method provided by the embodiment of the present application;

[0050] Figure 4 is a sub-step diagram of step S240;

[0051] Figure 5 is a sub-step diagram of step S270;

[0052] Figure 6 It is the structural diagram of a codeword;

[0053] Figure 7 It is the structural diagram of p codewords and q inverted codewords;

[0054] Figure 8 It is the schematic diagram of step S240;

[0055] Figure 9 It is the schematic diagram of step S280;

[0056] Figure 10 It is the structural diagram of the flash memory provided by the embodiment of the present application. Detailed implementation manners

[0057] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0058] It should be noted that although the functional modules are divided in the device schematic diagram and the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in a different order from the module division in the device or the flowchart. Terms such as "first", "second", etc. in the specification, claims or the above-mentioned drawings are used to distinguish similar objects and do not necessarily need to describe a specific order or sequence.

[0059] Due to the characteristics of the flash memory itself, the data stored in it may have different degrees of error numbers due to factors such as environmental temperature, storage time, wear degree, etc. After the error number reaches a certain level and exceeds the error correction ability of the main control chip, the data may be lost. By adding multiple backup data, it is beneficial to increase the probability of correctly obtaining the key data information.

[0060] Flash memory data is stored in binary 0 and 1 states, and data flipping may occur during the storage process, flipping 0 to 1 or flipping 1 to 0. Since the two states of 0 and 1 correspond to two different voltage ranges in the flash memory, the external environmental changes or the elongation of the storage time will affect the internal voltage distribution of the flash memory. Therefore, generally, the probabilities of 0 flipping to 1 and 1 flipping to 0 are not exactly equal.

[0061] The following will further elaborate on the embodiments of the present application with reference to the accompanying drawings.

[0062] To solve the above problems, the embodiments of the present application provide a flash memory data storage method.

[0063] Refer to Figure 1, A flash memory data storage method, comprising the following steps:

[0064] Step S110, obtaining the original data to be backed up;

[0065] Step S120, inverting the original data to obtain inverted data;

[0066] Step S130, forming a codeword from the original data, the inverted data, redundant data, and check data;

[0067] Step S140, inverting the codeword to obtain an inverted codeword;

[0068] Step S150, determining the number p of codewords and the number q of inverted codewords according to the storage space and reliability requirements of the flash memory;

[0069] Step S160, writing p copies of codewords and q copies of inverted codewords into the flash memory.

[0070] For step S110, obtaining the original data to be backed up, denoting the original data as X. The original data includes user data.

[0071] For step S120, inverting the original data X to obtain inverted data Xb. For example, inverting data 0 gives data 1, and inverting data 1 gives data 0. Inverting consecutive data 0011 gives data 1100. The inverted data can be used as a reference together with the original data to increase the security and reliability of the data.

[0072] Refer to Figure 2 , for step S130, forming a codeword from the original data, the inverted data, redundant data, and check data, including the following steps:

[0073] Step S131, obtaining the size of the original data and the size of the user data area of the codeword;

[0074] Step S132, determining the maximum number of the original data and the inverted data according to the size of the original data and the size of the user data area of the codeword;

[0075] Step S133, determining the number n of the original data and the number m of the inverted data according to the maximum number;

[0076] Step S134, forming the user data area of the codeword from n copies of the original data, m copies of the inverted data, and redundant data; forming the check data area of the codeword from the check data;

[0077] Step S135, forming a codeword from the user data area and the check data area.

[0078] The size of the original data refers to the storage space occupied by the data to be stored. The file size can be obtained through file operation functions in programming languages, or the size of the original data can be determined by reading the length of the data buffer.

[0079] The codeword includes a user data area and a parity data area. The size of the user data area refers to the storage space in the codeword for storing the original data, inverted data, and redundant data. This size is usually determined by the design of the storage system. For example, the size of the user data area of a codeword may be fixed at 4KB, or it can be flexibly configured according to the actual application requirements and the characteristics of the storage device.

[0080] If the size of the original data is S_original and the size of the user data area is S_user, then the maximum number K of the original data and the inverted data is the integer obtained by taking the floor of S_user / S_original.

[0081] It can be understood that assuming the size of the original data is S_original and the size of the user data area of the codeword is S_user. Since the user data area needs to store the original data, inverted data, and redundant data, the following relational expression can be obtained: n * S_original + m * S_inverted + S_redundant ≤ S_user, where n is the number of original data, m is the number of inverted data, S_inverted is the size of the inverted data (usually the same as the size of the original data, i.e., S_inverted = S_original), and S_redundant is the size of the redundant data. Without considering the redundant data (i.e., S_redundant = 0), the maximum number of the original data and the inverted data satisfies n * S_original + m * S_original ≤ S_user, that is, (n + m) * S_original ≤ S_user. Therefore, the maximum number K = n + m ≤ S_user / S_original.

[0082] Exemplarily, if the size of the original data is 128 bytes, the size of the user data area of the codeword is 1024 bytes, and the redundant data is not considered, then the maximum number is n + m ≤ 1024 / 128 = 8. This means that at most 8 combinations of the original data and the inverted data can be stored, such as 5 pieces of original data and 3 pieces of inverted data, or 4 pieces of original data and 4 pieces of inverted data, etc., as long as the total number does not exceed 8.

[0083] When determining the number n of the original data and the number m of the inverted data, factors such as the utilization rate of the storage space and the reliability requirements of the data need to be comprehensively considered. Generally speaking, increasing the number n of the original data can improve the redundancy of the data, thereby enhancing the reliability of the data, but it will reduce the utilization rate of the storage space; while increasing the number m of the inverted data can improve the error correction ability to a certain extent, but it will also affect the utilization rate of the storage space. Therefore, the appropriate values of n and m need to be determined according to the specific application scenarios and requirements.

[0084] Assume the maximum number is 8. If a higher reliability requirement for the data is needed, n can be set to 5 and m to 3, that is, store 5 copies of the original data and 3 copies of the inverted data; if a higher requirement for the utilization rate of the storage space is needed, n can be set to 6 and m to 2, that is, store 6 copies of the original data and 2 copies of the inverted data.

[0085] Combine n copies of the original data, m copies of the inverted data, and the redundant data together in a certain order or rule to form the user data area of the codeword. For example, first arrange n copies of the original data in sequence, then arrange m copies of the inverted data in sequence after the original data, and finally add the redundant data after the inverted data to form a complete user data area. The redundant data can be used to improve the error correction ability of the data. For example, it can be redundant bits for parity check, or redundant data generated by other error correction coding algorithms. In this embodiment, the redundant data consists of data 0.

[0086] The check data is additional data used to check and correct the user data, usually generated by an error correction coding algorithm. The check data is separately formed into the check data area of the codeword and stored separately from the user data area. For example, during the error correction coding process, an error correction coding algorithm such as the EEC code can be used to encode the user data to generate the corresponding check data, and then the check data is stored in the check data area.

[0087] ECC error correction is the key mechanism to ensure the correctness of flash memory data. By sacrificing part of the data storage space, the reliability of the data is exchanged. When writing data, use the ECC algorithm to encode and generate the check information, and write the user data area and the ECC check information together into the flash memory.

[0088] Combine the user data area and the check data area of the codeword together in a certain format or structure to form a complete codeword.

[0089] Refer to Figure 6 , generate the codeword H. H includes the error correction codeword user data area composed of n copies of the original data, m copies of the inverted data, and the redundant data, and the error correction codeword check data area composed of the check data backup C. The n copies of the original data are backup data X1, backup data X2,..., backup data Xn, and the m copies of the inverted data are backup data Xb1, backup data Xb2,..., backup data Xbn.

[0090] For step S140, invert the codeword to obtain the inverted codeword.

[0091] For step S150, determine the number p of the codewords and the number q of the inverted codewords according to the storage space and reliability requirements of the flash memory.

[0092] Understand the total available storage space of the current flash device. For example, assume that the total flash storage space is 10 GB, and the area available for storing original and inverted codewords is a part of it, say 5 GB. Calculate how many copies can be stored based on the sizes of the codewords and inverted codewords respectively. For example, if each copy of the codeword is 1 qB and the inverted data is also 1 qB (the inversion operation itself does not change the storage size of the data), then in the 5 GB storage area, at most 5×1024 = 5120 copies of such data can be stored. If it is set that p copies of codewords are stored and q copies of inverted codewords are stored, then p + q ≤ 5120 needs to be satisfied.

[0093] Weigh the ratio of p and q according to the expected data reliability. Generally speaking, higher reliability requires more redundant data. For example, during data storage and reading, in order to be able to recover the original information from other data when some data is damaged, a certain redundancy ratio often needs to be set.

[0094] Exemplarily, to achieve higher reliability, it can be set that there are 3 copies of codewords and 1 copy of inverted codewords (i.e., p = 3, q = 1). In this way, when data needs to be recovered, there are multiple redundant sources available for verification and repair. However, the utilization rate of the storage space is relatively low at this time because a relatively large number of total storage units are used for redundant data. On average, assuming that the storage space occupied by each copy of the codeword is S, the total storage requirement is 3S + 1S = 4S. And if there is a higher requirement for the utilization rate of the storage space, the redundancy ratio can be reduced, such as p = 2, q = 1. At this time, the storage requirement is 3S, and the space utilization rate is higher, but the data reliability is relatively reduced.

[0095] It is necessary to find a balance between storage space and reliability. For example, after comprehensive weighing, it may be set to p = 3, q = 1 or a similar combination, while meeting the basic reliability requirements and minimizing the excessive occupation of storage space.

[0096] Refer to Figure 7 , p copies of codewords are denoted as H1, H2,... Hp; q copies of opposite codewords are denoted as Hb1, Hb2,... Hbq.

[0097] For step S160, write p copies of codewords and q copies of inverted codewords into the flash memory.

[0098] Determine the storage locations. The flash memory has multiple storage units, and each unit has a specific address. It is necessary to pre-plan which address areas the codewords and inverted codewords to be stored will be written into respectively. For example, the first copy of the codeword is written to the address range from 0x00000000 to 0x00000FFF, the second copy is written to 0x00001000 to 0x00001FFF, and so on. The inverted codewords are sequentially assigned to the subsequent address segments.

[0099] Clear the storage unit. Before writing, it is usually necessary to perform an erase operation on the target storage area. Since the writing of flash memory depends on erasure, all bits are 1 after erasure, and then 0 can be written. If data is directly written to an un-erased area, writing failure or incomplete data may occur.

[0100] The microcontroller executes the writing operation through the flash memory controller. The controller sequentially writes the codewords and inverted codewords into the corresponding storage units of the flash memory according to the pre-planned address and data order. For example, the controller first sends a write instruction to the flash memory, specifies the first address and transmits the first data of the codeword, and the flash memory writes the data into the storage unit corresponding to the address after receiving the instruction. And so on until all n codewords and m inverted codewords are written completely.

[0101] It should be noted that the position areas for writing n codewords to be backed up and m inverted codewords in the flash memory are the same or have the same storage characteristics. So that the factors and degrees affecting data flipping of the two types of backup data are as the same as possible. For example, they are stored in the same block, page, and page offset of the flash memory. These same storage areas can be determined by analyzing data according to the flash memory characteristics. That is, write n codewords to be backed up and m inverted codewords into the same block, the same page, or the same page offset in the flash memory.

[0102] Perform a data verification operation after writing is completed. Such as reading back the stored data and comparing it with the expected data to ensure that the written data is correct. For example, after writing is completed, the controller reads out some or all of the data from the flash memory, and then compares it with the codewords and inverted codewords before sending to check for any differences. If differences are found, re-writing or other error correction measures may need to be performed to ensure the accuracy of the data.

[0103] It can be understood that there are specific limitations and characteristics in the flash memory writing operation. For example, the erase / write life of each storage unit is limited, and frequent erase / write operations will cause the performance of the flash memory to decline or even be damaged. Therefore, when performing multiple write operations, the flash memory controller will automatically and reasonably arrange the storage locations and the number of erase / write operations to avoid excessive wear on the same storage unit.

[0104] Another embodiment of the present application provides a method for reading flash memory data. The data in the flash memory is backed up according to the above flash memory data storage method.

[0105] Refer to Figure 3 , the flash memory data reading method includes the following steps:

[0106] Step S210, obtain the first data storage address of the data to be read;

[0107] Step S220: Read at least one codeword and at least one inverted codeword from the flash memory according to the first data storage address;

[0108] Step S230: Invert the inverted codeword to obtain the restored codeword;

[0109] Step S240: Compare and adjust the codeword and the restored codeword bit by bit to obtain the valid codeword;

[0110] Step S250: Extract the original data and the inverted data from the user data area of the valid codeword;

[0111] Step S260: Invert the inverted data to obtain the restored data;

[0112] Step S270: Compare and adjust the original data and the restored data bit by bit to obtain the first valid data;

[0113] Step S280: Replace the user data area of the first valid data with the first valid data and the redundant data to obtain the second valid data;

[0114] Step S290: Perform error correction decoding on the second valid data according to the check data in the check data area of the second valid data to obtain the target read data.

[0115] For step S210, obtain the first data storage address of the data to be read. For example, query the data storage address of the data to be read from the address mapping table maintained by the flash memory as the first data storage address. The address mapping table stores the mapping from the logical address to the physical address. When data needs to be read, first find the corresponding physical address in the mapping table according to the logical address (such as the file offset address in the file system). For example, assume the logical address is 0x00123456, and the physical address corresponding to this logical address recorded in the mapping table is 0x87654321, then start reading data from the physical address 0x87654321.

[0116] For step S220, read at least one codeword and at least one inverted codeword from the flash memory according to the first data storage address. Specifically, use the first data storage address as the starting point and read data from the flash memory in a preset order or rule. For example, assume the first data storage address corresponds to the first unit storing the original data, then the controller will start reading subsequent several units from this address, which may include multiple codewords and inverted codewords.

[0117] For step S230, the inverted codeword is inverted to obtain the restored codeword. Specifically, during the storage phase, the inverted codeword is obtained by flipping each bit of the codeword; now, the inverted codeword is inverted again, that is, each of its bits is flipped again. For example, if the inverted codeword is 10010101, after inversion, 01101010 is obtained, and at this time, the restored codeword should be the same as the corresponding codeword.

[0118] Referring to Figure 4 , for step S240, the codeword and the restored codeword are compared and adjusted bit by bit to obtain the valid codeword, including the following steps:

[0119] Step S241, count the first quantity of data 0 and the second quantity of data 1 at the same bit position in the user data area of the codeword and the user data area of the restored codeword;

[0120] Step S242, when the first quantity is greater than the second quantity, determine that the first candidate data for the bit is data 0;

[0121] Step S243, when the first quantity is less than the second quantity, determine that the first candidate data for the bit is data 1;

[0122] Step S244, combine the first candidate data of each bit to obtain the valid codeword.

[0123] Compare the user data area of the codeword and the user data area of the restored codeword bit by bit to check the differences between them at each bit position. For example, if the user data area of the codeword is 0 at a certain bit, while the user data area of the restored codeword is 1 at the corresponding bit, it indicates that there may be an error at this bit.

[0124] Referring to Figure 8 , read the codeword and the restored codeword, denoted as: rH1, rH2,..., rHp; rHb1, rHb2,..., rHbq. Take the inverted data backup and invert it bit by bit to obtain rHbb1, rHbb2, …, rHbbq. Expand rH1, rH2,..., rHp and rHbb1, rHbb2, …, rHbbq bit by bit for statistical judgment to obtain the first candidate data R. Further, count the quantities of 0 and 1 at the same bit positions of rH1, rH2,..., rHp and rHbb1, rHbb2, …, rHbbq. If 1 is more than 0, then determine that the bit at the same position in R of the first candidate data is 1, otherwise it is 0. Combine the first candidate data of each bit to obtain the valid codeword.

[0125] For step S250, the original data and the inverted data are extracted from the user data area of the valid codeword. The user data area of the valid codeword contains the original data, the inverted data, and the redundant data. The original data is extracted from the user data area according to the structure and size of the user data area, the size and quantity of the original data. The inverted data is extracted from the user data area according to the structure and size of the user data area, the size and quantity of the inverted data.

[0126] The original data and the restored data in the user data area are extracted and denoted as: rX1, rX2, ..., rXn; rXb0, rXb1, ..., rXbm.

[0127] For step S260, the inverted data is inverted to obtain the restored data. The m copies of rXb1, rXb2, ..., rXbm are adjusted by bitwise inversion to obtain rXbb1, rXbb2, …, rXbbm.

[0128] Refer to Figure 5 For step S270, the original data and the restored data are adjusted by comparison bit by bit to obtain the first valid data, including the following steps:

[0129] Step S271, align the original data and the restored data;

[0130] Step S272, count the third quantity of data 0 and the fourth quantity of data 1 at the same bit position of the original data and the restored data;

[0131] Step S273, when the third quantity is greater than the fourth quantity, determine that the second candidate data at the bit position is data 0;

[0132] Step S274, when the third quantity is less than the fourth quantity, determine that the second candidate data at the bit position is data 1;

[0133] Step S275, combine the second candidate data at each bit position to obtain the first valid data.

[0134] Align all the original data and the restored data at the first bit position; then the original data and the restored data correspond one by one at the subsequent bit positions.

[0135] Count the quantities of 0 and 1 at the same bit positions of rX1, rX2, ..., rXn and rXbb1, rXbb2, …, rXbbm. If the quantity of 1 is more than that of 0, then determine that the second candidate data is 1, otherwise it is 0. Combine the second candidate data at each bit position to obtain the first valid data.

[0136] For step S280, replace the user data area of the first valid data with the first valid data and redundant data to obtain the second valid data. Specifically, the user data area includes one copy of the first valid data, and the other positions are filled with redundant data, which consists of data 0. The second valid data is composed of the user data area and the check data area. Refer to Figure 9 , replace the user data area of codeword R with the first valid data and redundant data to obtain codeword T.

[0137] For step S290, perform error correction decoding on the second valid data according to the check data in the check data area of the second valid data to obtain the target read data. Specifically, the check data is ECC check information.

[0138] When reading data, both the valid information and the ECC check information are read from the flash memory. Through ECC decoding and error correction operations, it can be ensured that the correct data can be read within the range of correctable errors.

[0139] Perform error correction decoding on the second valid data. When the decoding is correct, the target read data is obtained; when the decoding is incorrect, obtain the second data storage address of the data to be read, read the second original data and the second inverted data corresponding to the data to be read from the second data storage address, invert the second inverted data to obtain the second restored data, compare and adjust the second original data and the second restored data bit by bit to obtain the second adjusted data, and perform error correction decoding on the second adjusted data to obtain the target read data. Among them, the second data storage address is different from the first data storage address. If the decoding is incorrect, continue to search for other backups until all backups have been tried.

[0140] On the basis of storing the original data, add the stored inverted data. By reading the combination of the original data and the inverted data, the probability of obtaining the correct data is increased.

[0141] An example is illustrated as follows:

[0142] Suppose the original data has only 1 bit, and 2 backups are stored, denoted as X1 and X2; the inverted data are Xb1 and Xb2; write the original data and the differentiated data, a total of 4 copies, into the flash memory. When reading data, denote the original data and the inverted data read from the flash memory as: Y1, Y2, Yb1, Yb2. Then invert Yb1 and Yb2 to obtain Ybb1 and Ybb2, and after sorting, the data read from the flash memory is: Y1, Y2, Ybb1, Ybb2. Count the number of 0s and 1s in Y1, Y2, Ybb1, Ybb2. If 1 is more than 0, then determine that the final data is 1, otherwise it is 0.

[0143] First, assume that the original data is 1, then X1 = X2 = 1, Xb1 = Xb2 = 0.

[0144] For the case where the probability \(P_{0\rightarrow1}\) of 0 flipping to 1 is greater than the probability \(P_{1\rightarrow0}\) of 1 flipping to 0 (i.e., \(P_{0\rightarrow1}>P_{1\rightarrow0}\)). The read data \(Y1\), \(Y2\) correspond to the written data \(X1\), \(X2\), both of which are 1. Since the probability of 1 flipping to 0 is low, assuming no flipping occurs, then \((Y1,Y2)=(1,1)\). The read data \(Yb1\), \(Yb2\) correspond to the written data \(Xb1\), \(Xb2\), both of which are 0. Since the probability of 0 flipping to 1 is high, assuming a flipping rate of 50%, then \((Yb1,Yb2)\) can be \((1,0)\) or \((0,1)\). Here, \((1,0)\) is taken, and after taking the inverse, \(Ybb1\), \(Ybb2\) are \((0,1)\). Finally, \((Y1,Y2,Ybb1,Ybb2)=(1,1,0,1)\), the number of 1s is 3, and the number of 0s is 1. It is determined that the final data is 1.

[0145] For the case where the probability \(P_{0\rightarrow1}\) of 0 flipping to 1 is less than the probability \(P_{1\rightarrow0}\) of 1 flipping to 0 (i.e., \(P_{0\rightarrow1}\) <p1->In the case of . The read data Y1 and Y2 correspond to the written data X1 and X2, both of which are 1. Since the probability of 1 flipping to 0 is high, assuming a flipping rate of 50%, then (Y1, Y2) can be (1, 0) or (0, 1). Here, (1, 0) is taken. The read data Yb1 and Yb2 correspond to the written data Xb1 and Xb2, both of which are 0. Since the probability of 0 flipping to 1 is low, assuming no flipping, then (Yb1, Yb2) = (0, 0). After taking the inverse, Ybb1 and Ybb2 are (1, 1). Finally, (Y1, Y2, Ybb1, Ybb2) = (1, 0, 1, 1), the number of 1s is 3, and the number of 0s is 1. It is determined that the final data is also 1.

[0146] When P0->1 = P1->0, the error probabilities are equal, and the probability of determining the final data as 1 is 50%.

[0147] In the above writing, reading, and determination processes, when the original data is 0, the process is similar. It can be seen that by increasing the backup of the inverted data, the probability of reading the correct data can be improved.

[0148] Another embodiment of the present application provides a flash memory that applies the above flash memory data storage method and flash memory data reading method.

[0149] Refer to Figure 10 , the flash memory includes a storage controller and flash memory particles, and the storage controller is connected to the flash memory particles.

[0150] The storage controller is responsible for coordinating and managing the data interaction between the flash memory particles and the external host. It receives data from the external host and writes the data into the flash memory particles for storage; at the same time, it also reads data from the flash memory particles and then transmits the data back to the external host to ensure the correct storage and reading of the data.

[0151] Data is stored through the flash memory particles. The storage controller reads data from the external host and writes the data into the flash memory particles; the storage controller reads data from the flash memory particles and transmits the data to the external host.

[0152] The storage controller includes a codeword adjustment control module and an error correction control module; the codeword adjustment control module is used to perform related operations on the codeword; the error correction control module is used to perform error correction decoding operations.

[0153] The codeword adjustment control module performs the following related operations on the codeword: filling redundant data inside the codeword, filling multiple copies of the same data inside the codeword, and performing an inversion operation on the codeword.

[0154] The error correction control module is responsible for performing error correction decoding operations to detect and correct errors that may occur during data storage and reading. During data reading, if an error is detected in the data, the error correction control module calculates the position and value of the error according to the error correction coding algorithm and corrects it to ensure the accuracy and integrity of the data.

[0155] The storage controller also includes a protocol interface control module, a system processor, and a system cache. The codeword adjustment control module and the error correction control module are set in the flash memory read / write control module. The protocol interface control module, the system processor, and the system cache are connected to the flash memory read / write control module through an internal bus.

[0156] The protocol interface control module is responsible for the conversion and control of communication protocols with the external host side to ensure that the flash memory system can be compatible and communicate with different types of external host sides. It usually supports multiple storage protocols such as SATA, SAS, NVMe, etc. According to the protocol requirements of the external host side, it converts and processes the commands and data sent by the host side and then passes them to the flash memory read / write control module for corresponding operations. At the same time, it also encapsulates and sends the data and status information returned by the flash memory system in the protocol format of the host side to achieve normal communication with the external host side.

[0157] The system processor is the central processing unit of the storage controller and is responsible for the management and control of the entire flash memory system. It coordinates the work of each module and executes various system-level tasks and operations such as initialization, configuration, and monitoring. For example, at system startup, the system processor initializes each module and sets the working mode and parameters of the storage controller; during data reading and writing, it monitors the data transfer status and coordinates the work of the codeword adjustment control module, the error correction control module, and the protocol interface control module to ensure the correct processing and transfer of data.

[0158] The system cache is used to temporarily store data and information to improve the speed and efficiency of data reading and writing. During data writing, the system cache can temporarily store the data received from the external host side and wait for the storage controller to write the data into the flash memory particles; during data reading, it can cache the data read from the flash memory particles to quickly transfer the data to the external host side. In addition, the system cache can also be used to store some system configuration information, status information, etc., so that the system processor can quickly access and process this information.

[0159] The flash memory read / write control module also includes a bus and register module, a flash memory bus timing module, a data transfer control module, and a cache.

[0160] The bus and register module is responsible for managing the bus communication and register operations inside the flash memory read / write control module. It provides a bus interface for data transfer and communication between various sub-modules, ensuring that data can be transferred quickly and accurately between different sub-modules. At the same time, it also contains some registers for storing various control information, status information, and data information, so that other sub-modules can access and use this information.

[0161] The flash memory bus timing module is responsible for controlling the bus timing of the flash memory chips, ensuring that data can be written or read at the correct time points. It generates corresponding timing signals according to the characteristics and requirements of the flash memory chips to control the data transfer and access. For example, during the data writing process, it will control the writing timing to ensure that the data can be correctly written within the writing window period of the flash memory chips; during the data reading process, it will control the reading timing to ensure that the data can be read at the correct time point.

[0162] The data transfer control module is responsible for controlling the data transfer process between the flash memory read / write control module and the flash memory chips. It divides the data into data blocks of appropriate sizes according to the commands and data from the storage controller, and then writes the data blocks into the flash memory chips one by one through the flash memory bus timing module; during the data reading process, it reads the data blocks from the flash memory chips one by one, then combines the data blocks into complete data, and transfers the data to the storage controller through the bus and register module.

[0163] The cache is used to temporarily store data to improve the speed and efficiency of data reading and writing. During the data writing process, the cache can temporarily store the data received from the storage controller and wait to write the data into the flash memory chips when there is free storage space in the flash memory chips; during the data reading process, it can cache the data read from the flash memory chips to quickly transfer the data to the storage controller. In addition, the cache can also be used to store some intermediate data and information so that the data transfer control module can perform data transfer and processing more efficiently.

[0164] The above has specifically described the preferred embodiments of the present application, but the present application is not limited to the embodiments. Those skilled in the art can make various equivalent deformations or substitutions without departing from the spirit of the present application, and these equivalent deformations or substitutions are all included within the scope defined by the claims of the present application.

Claims

1. A flash memory data storage method, characterized in that: include: Obtain the original data to be backed up; Inverting the original data to obtain inverted data; The original data, the inverted data, the redundant data and the check data constitute a codeword; Inverting the codeword to obtain an inverted codeword; Determine the number of code words p and the number of inverted code words q according to the storage space and reliability requirements of the flash memory; Writing p copies of the codeword and q copies of the inverted codeword into the flash memory; The step of forming a codeword from the original data, the inverted data, the redundant data and the check data includes: Obtaining the size of the original data and the size of the user data area of ​​the codeword; Determine the maximum number of original data and inverted data according to the size of the original data and the size of the user data area of ​​the codeword; Determine the number n of the original data and the number m of the negated data according to the maximum number; The n copies of the original data, the m copies of the inverted data and the redundant data constitute a user data area of ​​the codeword; the check data constitutes a check data area of ​​the codeword; The user data area and the check data area constitute a codeword.

2. The flash memory data storage method according to claim 1, characterized in that: The location areas where the p copies of the codeword and the q copies of the inverted codeword are written in the flash memory are the same or have the same storage characteristics.

3. The flash memory data storage method according to claim 1, characterized in that: Writing the p copies of the codeword and the q copies of the inverted codeword into the flash memory comprises: The p copies of the codeword and the q copies of the inverted codeword are written into the same block, the same page or the same offset within the page of the flash memory.

4. The flash memory data storage method according to claim 1, characterized in that: The redundant data consists of data 0.

5. A flash memory data reading method, characterized in that: The data in the flash memory is backed up according to the flash memory data storage method according to any one of claims 1 to 4; the flash memory data reading method comprises: Obtain a first data storage address of data to be read; Read at least one codeword and at least one inverted codeword from the flash memory according to the first data storage address; Inverting the inverted codeword to obtain a restored codeword; Compare and adjust the code word and the restored code word on the bit position to obtain a valid code word; Extracting the original data and the inverted data from the user data area of ​​the valid codeword; Inverting the inverted data to obtain restored data; Compare and adjust the original data and the restored data on a bit basis to obtain first valid data; Replacing the user data area of ​​the first valid data with the first valid data and redundant data to obtain second valid data; The second valid data is subjected to error correction decoding according to the verification data in the verification data area of ​​the second valid data to obtain target read data.

6. The flash memory data reading method according to claim 5, characterized in that: The step of comparing and adjusting the code word and the restored code word on the bit position to obtain a valid code word includes: Counting a first number of data 0s and a second number of data 1s at the same bit position in the user data area of ​​the codeword and the user data area of ​​the restored codeword; When the first number is greater than the second number, determining that the first candidate data of the bit position is data 0; When the first number is less than the second number, determining that the first candidate data of the bit position is data 1; The first candidate data of each bit is combined to obtain a valid code word.

7. The flash memory data reading method according to claim 5, characterized in that: The step of comparing and adjusting the original data and the restored data on a bit basis to obtain first valid data comprises: aligning the original data and the restored data; Counting a third number of data 0s and a fourth number of data 1s at the same bit position of the original data and the restored data; When the third number is greater than the fourth number, determining that the second candidate data of the bit is data 0; When the third number is less than the fourth number, determining that the second candidate data of the bit is data 1; The second candidate data of each bit is combined to obtain the first valid data.

8. A flash memory, characterized in that: The flash memory application comprises a flash memory data storage method as described in any one of claims 1 to 4 and a flash memory data reading method as described in any one of claims 5 to 7; the flash memory comprises a storage controller and flash memory particles, and the storage controller is connected to the flash memory particles; the storage controller comprises a codeword adjustment control module and an error correction control module; the codeword adjustment control module is used to perform codeword related operations; the error correction control module is used to perform error correction decoding operations.

9. The flash memory according to claim 8, characterized in that: The storage controller also includes a protocol interface control module, a system processor and a system cache. The codeword adjustment control module and the error correction control module are arranged in a flash memory read-write control module. The protocol interface control module, the system processor and the system cache are connected to the flash memory read-write control module via an internal bus.

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