Communication configuration method, device, equipment, system, program product and medium

Abstract

Disclosed are a communication configuration method, apparatus, device, system, program product and medium, which relate to the technical field of communications, the method comprising: a first device obtaining a first delay information report message sent by a second device through a PCIe link; the first delay information report message comprises protocol stack processing delay and system response time of the second equipment; determining the transaction concurrency capability of the first equipment according to the protocol stack processing delay and the system response time of the first equipment and the protocol stack processing delay and the system response time of the second equipment in the first delay information report message; according to the transaction concurrency capability, configuring system resources corresponding to a peripheral component rapid interconnection link in the first equipment; according to the method and the device, the first device can accurately determine the PCIe transaction round-trip delay between the first device and the second device so as to accurately determine the required transaction concurrency capability and match the corresponding system resources, and the system resource configuration is optimized on the basis of ensuring the PCIe link efficiency.

Description

Technical Field

[0001] The present invention relates to the field of communication technology, and in particular to a communication configuration method, device, peripheral component rapid interconnection device, peripheral component rapid interconnection system, computer program product and computer readable medium. Background Art

[0002] At present, with its excellent performance and innovative serial connection mechanism, PCIe (Peripheral Component Interconnect Express, a high-speed serial computer expansion bus standard) technology has become a universal standard for connecting computer hardware devices; it has established itself as a mainstream interface in the field of data transmission with significant advantages such as high performance, low latency and flexibility. The application scope of PCIe technology is extremely wide, covering a variety of devices such as solid-state drives (SSDs), graphics processing units (GPUs), network interface cards (NICs), etc., providing powerful data transmission capabilities for modern computer systems.

[0003] Transaction concurrency (Outstanding) is one of the key mechanisms used in PCIe technology to improve data transmission efficiency and reduce latency. By allowing PCIe devices to continue to send new transactions while waiting for responses, idle time is reduced, and bus utilization is improved, thereby achieving higher throughput and lower latency, meeting the needs of modern computer systems for high-speed data transmission. Figure 1 As shown in the figure, taking PCIe read transactions as an example, after device S continuously initiates n PCIe read transactions (MRd), it receives response messages Cpld from device T one after another. It can be considered that the transaction concurrency capability of device S in the example is n. Usually, in order to fully utilize the bandwidth provided by the PCIe bus physical link and reduce the link idle time, designers expect the transaction concurrency capability n of device S to be large enough to offset the round-trip delay between device S and device T. However, it is difficult to accurately determine the transaction concurrency capability of PCIe devices in related technologies, resulting in the problem of PCIe link resource waste or system resource idleness and waste.

[0004] Therefore, how to accurately determine the transaction concurrency capability of PCIe devices, ensure PCIe link efficiency and optimize system resource configuration is an urgent problem to be solved today. Summary of the invention

[0005] The purpose of the present invention is to provide a communication configuration method, device, peripheral component rapid interconnection device, peripheral component rapid interconnection system, computer program product and computer readable medium to accurately determine the transaction concurrency capability of PCIe devices, ensure PCIe link efficiency and optimize the configuration of system resources.

[0006] In order to solve the above technical problems, the present invention provides a communication configuration method, comprising:

[0007] A first device acquires a first delay information report message sent by a second device through a peripheral component express link; wherein the first device and the second device are both peripheral component express devices, and the first delay information report message includes a protocol stack processing delay and a system response time of the second device;

[0008] determining a transaction concurrency capability of the first device according to a protocol stack processing delay and a system response time of the first device and a protocol stack processing delay and a system response time of the second device in the first delay information report message;

[0009] According to the transaction concurrency capability, system resources corresponding to the peripheral component fast interconnect link in the first device are configured; wherein the system resources include at least one of a buffer size, a number of transaction tag numbers, a lookup table specification, and a number of driver queues.

[0010] On the other hand, the first device obtains a first delay information report message sent by the second device through a peripheral component express link, including:

[0011] The first device sends a second delay information report message to the second device through the peripheral component express interconnect link; wherein the second delay information report message includes a protocol stack processing delay and a system response time of the first device, and the first device serves as a delay information report initiator;

[0012] Receive the first delay information report message returned by the second device.

[0013] On the other hand, the first device sends a second delay information report message to the second device through the PCE link, including:

[0014] After the first device and the second device enter a normal working state, the first device sends the second delay information report message to the second device through the peripheral component express interconnect link.

[0015] On the other hand, after the first device obtains the first delay information report message sent by the second device through the peripheral component express link, the method further includes:

[0016] The first device returns a second delay information report message to the second device through the peripheral component express interconnect link; wherein the second delay information report message includes the protocol stack processing delay and system response time of the first device, and the second device serves as the delay information report initiator.

[0017] On the other hand, the first delay information report message is a data packet in the form of a message transaction layer packet or a data link layer packet of the PCI Express protocol.

[0018] On the other hand, when the first delay information report message adopts a data packet in the form of the message transaction layer packet, the first delay information report message includes: a protocol stack processing delay field, a system response time field and a protocol definition field; wherein the protocol definition field includes at least one of a data packet format field, a data packet type field, a transaction category field, a message transaction layer packet summary field, an error identification field, an attribute field, an additional transaction type field, a length field, a requester identification field, a transaction tag field and a message encoding field.

[0019] On the other hand, the first delay information report message is a 16-byte data packet, and the first delay information report message also includes a reserved bit field.

[0020] On the other hand, bytes 1 to 4 in the first delay information report message include the data packet format field, the data packet type field, the transaction category field, the message transaction layer packet summary field, the error identification field, the attribute field, the additional transaction type field and the length field, bytes 5 to 8 in the first delay information report message include the requester identification field, the transaction tag field and the message encoding field, bytes 9 to 12 in the first delay information report message include the protocol stack processing delay field and the system response time field, and bytes 13 to 16 in the first delay information report message include the reserved bit field.

[0021] On the other hand, the packet format field is 001 in binary; the packet type field is 10100 in binary, the transaction category field is 0, the attribute field is 0, the additional transaction type field is 0, the length field is 0, the transaction tag field is 0, and the message encoding field is 00010100 in binary.

[0022] On the other hand, the first device obtains a first delay information report message sent by the second device through a peripheral component express link, including:

[0023] The first device obtains a first delay information report message sent by the second device through the PCE link at a preset time interval.

[0024] On the other hand, determining the transaction concurrency capability of the first device according to the protocol stack processing delay and the system response time of the first device and the protocol stack processing delay and the system response time of the second device in the first delay information report message includes:

[0025] Determine a transaction round trip delay based on a protocol stack processing delay and a system response time of the first device and a protocol stack processing delay and a system response time of the second device;

[0026] The transaction concurrency capability of the first device is determined according to the transaction round-trip delay and the acquired number of channels, single-channel transmission rate, physical layer coding efficiency and transaction layer packet length of the peripheral component rapid interconnect link.

[0027] On the other hand, determining the transaction round trip delay according to the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device includes:

[0028] The transaction round-trip delay is obtained by calculating the sum of the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device.

[0029] On the other hand, determining the transaction concurrency capability of the first device according to the transaction round-trip delay and the acquired number of channels, single-channel transmission rate, physical layer coding efficiency, and transaction layer packet length of the peripheral component rapid interconnect link includes:

[0030] pass , calculate the transaction concurrency capability of the first device; where R link is the single channel transmission rate, N lane is the number of channels, L t is the round trip delay of the transaction, E enc is the physical layer coding efficiency, S packet is the length of the transaction layer packet, and a is a preset parameter.

[0031] On the other hand, the , calculating the transaction concurrency capability of the first device, including:

[0032] right The calculation result is rounded up to obtain the transaction concurrency capability of the first device.

[0033] On the other hand, the unit of the transaction layer packet data length is bytes, and a is 8.

[0034] The present invention also provides a communication configuration device, applied to a first device, comprising:

[0035] an acquisition module, configured to receive a first delay information report message sent by a second device through a peripheral component interconnect express link; wherein the first device and the second device are both peripheral component interconnect express devices, and the first delay information report message includes a protocol stack processing delay and a system response time of the second device;

[0036] a determination module, configured to determine the transaction concurrency capability of the first device according to the protocol stack processing delay and the system response time of the first device and the protocol stack processing delay and the system response time of the second device in the first delay information report message;

[0037] A configuration module is used to configure the system resources corresponding to the peripheral component rapid interconnection link in the first device according to the transaction concurrency capability; wherein the system resources include at least one of a buffer size, a number of transaction tag numbers, a lookup table specification, and a number of driver queues.

[0038] The present invention also provides a peripheral component rapid interconnection device, comprising:

[0039] Memory for storing computer programs;

[0040] A processor is used to execute the computer program to implement the steps of the communication configuration method as described above.

[0041] The present invention also provides a peripheral component rapid interconnection system, comprising: a first peripheral component rapid interconnection device and a second peripheral component rapid interconnection device;

[0042] The first PICI device and the second PICI device are connected via a PICI bus, and both the first PICI device and the second PICI device are the PICI devices described above.

[0043] The present invention also provides a computer program product, comprising a computer program / instruction, which implements the steps of the communication configuration method as described above when the computer program / instruction is executed by a processor.

[0044] In addition, the present invention also provides a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the communication configuration method described above are implemented.

[0045] A communication configuration method provided by the present invention comprises: a first device obtains a first delay information report message sent by a second device through a peripheral component express link; wherein the first device and the second device are both peripheral component express devices, and the first delay information report message includes a protocol stack processing delay and a system response time of the second device; according to the protocol stack processing delay and the system response time of the first device and the protocol stack processing delay and the system response time of the second device in the first delay information report message, the transaction concurrency capability of the first device is determined; according to the transaction concurrency capability, the system resources corresponding to the peripheral component express link in the first device are configured; wherein the system resources include at least one of a buffer size, a number of transaction tag numbers, a lookup table specification and a number of driver queues.

[0046] It can be seen that the present invention obtains the first delay information report message sent by the second device through the peripheral component rapid interconnection link through the first device, so that the first device can obtain the protocol stack processing delay and system response time of the second device, so that the first device can accurately obtain the round-trip delay of the PCIe transaction between the first device and the second device, and then accurately determine the required transaction concurrency capability and match the corresponding system resources. On the basis of ensuring the efficiency of the PCIe link, the configuration of system resources can be optimized to avoid idleness and waste of system resources. In addition, the present invention also provides a communication configuration device, a peripheral component rapid interconnection device, a peripheral component rapid interconnection system, a computer program product and a computer-readable medium, which also have the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0048] Figure 1 A schematic diagram of a concurrent process of a PCIe read transaction;

[0049] Figure 2 A flow chart of a communication configuration method provided by an embodiment of the present invention;

[0050] Figure 3 A flow chart of another communication configuration method provided by an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of a LIR message format provided by an embodiment of the present invention;

[0052] Figure 5A schematic diagram of an application of an LIR mechanism of another communication configuration method provided by an embodiment of the present invention;

[0053] Figure 6 A structural block diagram of a communication configuration device provided by an embodiment of the present invention;

[0054] Figure 7 A simplified structural diagram of a peripheral component rapid interconnection device provided by an embodiment of the present invention;

[0055] Figure 8 A schematic diagram of the specific structure of a peripheral component rapid interconnection device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0056] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0057] In the related art, the transaction concurrency capability of PCIe devices is n The transaction round trip delay L t The relationship between can be expressed by the following formula:

[0058] ;

[0059] Among them, O n It can represent the number of concurrent Outstanding transactions, that is, the transaction concurrency capability; R link It can represent the single-channel transmission rate of the PCIe physical link; N lane It can represent the number of channels of the PCIe physical link; L t The round-trip delay of a transaction (i.e., transaction round-trip delay) can be expressed in nanoseconds (ns); E enc It can represent the physical layer coding efficiency of PCIe. For example, the physical layer coding efficiency of 8b / 10b coding can be 0.8, and the physical layer coding efficiency of 128b / 130b coding can be approximately 1 (i.e., 100%). packet The length of the transmitted TLP (Transaction Layer Packet) data packet (i.e., the size of the data packet) can be expressed, for example, in bytes.

[0060] According to the above formula, the transaction concurrency required for different round-trip delay times under the typical PCIe bus configuration can be calculated, and the results are shown in Table 1 below. Obviously, with two PCIe devices (such as Figure 1 As the transaction round-trip delay between device S and device T in the network increases, the required transaction concurrency (i.e., the number of concurrent transactions) also increases. This is because a larger transaction round-trip delay means that a data packet takes longer to complete a round trip, so the system needs to maintain more unfinished transactions to maintain the continuity of the data flow.

[0061] Table 1 Transaction concurrency required for typical PCIe bus configurations

[0062]

[0063] Experiments have shown that after the PCIe link training is completed, the parameters of the PCIe link such as the single-channel transmission rate, number of channels, packet length and coding efficiency have been determined; however, the round-trip delay of PCIe transactions may still be affected by the following main factors: 1) Bus transmission delay: The transmission time of the data packet on the PCIe bus, which is related to the PCIe physical rate, number of channels and the length of the transmitted data packet. 2) Protocol stack processing delay: The PCIe protocol stack is divided into application layer, transaction layer, data link layer and physical layer according to its function. Each layer has its specific functions and responsibilities. Different manufacturers design and implement PCIe controllers according to the PCIe protocol hierarchy, resulting in significant differences in the processing delay of each layer. The protocol stack processing delay can cover the PCIe devices at both ends of the link, such as Figure 1 Device S (source device) and device T (target device) in the target device; 3) System response delay of the target device: The bus transmission and DDR (memory) access delay of the target system where the PCIe controller is located together constitute the system response delay of the target device. 4) PCIe system connection topology: The round-trip delay of system components such as switches and retimers between PCIe devices at both ends of the link.

[0064] In summary, transaction round-trip delay is closely related to the device deployment environment; when the same PCIe device is deployed in different PCIe systems, its transaction round-trip delay may vary greatly. In the related technology, there is a lack of an effective means to accurately measure the transaction round-trip delay, so designers usually pre-estimate the transaction round-trip delay based on relatively conservative scenarios during the system design phase in order to ensure the bandwidth and utilization of the PCIe link; the larger the estimated transaction round-trip delay, the higher the transaction concurrency capability that the PCIe device needs to support, and the more system resources (such as buffers, lookup tables, and driver queues, etc.) that need to be reserved for each layer of the PCIe protocol stack and its system. This prediction method has certain limitations: if the estimated transaction round-trip delay is smaller than the actual deployment environment, the PCIe link bandwidth will not be fully utilized, the system optimal performance cannot be achieved, and PCIe link resources will be wasted; if the estimated transaction round-trip delay is larger than the actual deployment environment, it may cause system resources to be idle and wasted, increasing the cost of hardware ownership.

[0065] Therefore, the embodiments of the present invention accurately calculate the round-trip delay of PCIe transactions, so that the PCIe device can accurately determine the required transaction concurrency capability and match the corresponding system resources, thereby achieving optimal configuration of system resources while ensuring the efficiency of the PCIe link.

[0066] For details, please refer to Figure 2 , Figure 2 A flow chart of a communication configuration method provided by an embodiment of the present invention. The method may include:

[0067] Step 101: A first device obtains a first delay information report message sent by a second device via a peripheral component express link; wherein the first device and the second device are both peripheral component express devices, and the first delay information report message includes a protocol stack processing delay and a system response time of the second device.

[0068] It can be understood that in this embodiment, both the first device and the second device can be PCIe devices, and the first device and the second device can be connected through a PCIe link. The first delay information report message in this embodiment can be a delay information report (Latency Information Report, LIR) message sent by the second device to the first device through the PCIe link. By receiving the first delay information report message sent by the second device, the first device can obtain the protocol stack processing delay and system response time of the second device, so that the first device can obtain the accurate transaction round-trip delay between the first device and the second device, so as to accurately determine the transaction concurrency capability.

[0069] Among them, the protocol stack processing delay can be the cumulative processing delay of the PCIe controller integrated in the PCIe device at the physical layer, data link layer, transaction layer and application layer; the system response time can be the sum of the transmission delay and memory access delay of the system bus corresponding to the PCIe device.

[0070] Correspondingly, the specific method for the first device in this embodiment to obtain the first delay information report message sent by the second device through the peripheral component express interconnect link can be set by the designer according to practical scenarios and user needs. For example, in order to enable the PCIe devices at both ends of the PCIe link to accurately determine the transaction concurrency capability of their respective PCIe transactions, a new LIR mechanism can be adopted in this embodiment, that is, a mechanism that allows PCIe devices to exchange delay information (such as protocol stack processing delay and system response time); for example, the first device acts as an LIR initiator, and in this step, the first device sends a second delay information report message to the second device through the peripheral component express interconnect link; and receives the first delay information report message returned by the second device; wherein the second delay information report message includes the protocol stack processing delay and system response time of the first device; the second delay information report message can be a LIR message sent by the first device to the second device through the PCIe link. That is to say, the first device can act as the LIR initiator, first send an LIR message (i.e., the second delay information report message) to the second device to inform the second device of its own protocol stack processing delay and system response time; then, receive the LIR message (i.e., the first delay information report message) returned by the second device to obtain the protocol stack processing delay and system response time of the second device.

[0071] Correspondingly, when the second device acts as the LIR initiator, the first device can directly receive the first delay information report message sent by the second device through the PCIe link; after receiving the first delay information report message, it can also return the second delay information report message to the second device through the PCIe link to inform the second device of its own protocol stack processing delay and system response time.

[0072] For example, if Figure 3 As shown, after completing the link training and link negotiation defined in the specification, the PCIe device (such as the first device or the second device) can enter the normal working state (L0 state); at this time, the physical layer and the data link layer are both in the ready state, and the PCIe device can start normal data transmission. After that, the PCIe device can send an LIR message to the peer device (i.e., the second device or the first device) through the PCIe link, and the LIR message includes the protocol stack processing delay and system response time of the PCIe device; the PCIe device receives the LIR message from the peer device, and the LIR message includes the protocol stack processing delay and system response time of the peer device.

[0073] In other embodiments, the first device may send a second delay information report message to the second device and receive a first delay information report message sent by the second device after entering a normal working state. That is, after the PCIe devices at both ends of the PCIe enter a normal working state (L0 state) after link negotiation, they may send an LIR message to the opposite device to send their own protocol stack processing delay and system response time to the opposite device.

[0074] It should be noted that the specific data type and content of the first delay information report message in this embodiment can be set by the designer according to the usage scenario and user needs. For example, the LIR message (such as the first delay information report message and the second delay information report message) can be a data packet in the form of a Message TLP (Transaction Layer Packet) or DLLP (Data Link Layer Packet) of the PCIe protocol, that is, the above-mentioned first delay information report message and the second delay information report message can be transmitted in the form of Message TLP or DLLP defined in the PCIe specification.

[0075] For example, when the LIR message (such as the first delay information report message) is a data packet in the form of a Message TLP (Message Transaction Layer Packet) of the PCIe protocol, the first delay information report message includes: a protocol stack processing delay field, a system response time field, and a protocol definition field; wherein the protocol stack processing delay field may be a field for storing the protocol stack processing delay, the system response time field may be a field for storing the system response time, and the protocol definition field may be other definition fields of the Message TLP of the PCIe protocol; for example, the protocol definition field may include at least one of a data packet format field, a data packet type field, a transaction category field, a message transaction layer packet summary field, an error identification field, an attribute field, an additional transaction type field, a length field, a requester identification field, a transaction tag field, and a message encoding field; for example, Figure 4 As shown, the protocol definition fields may include a packet format field (Fmt), a packet type field (Type), a transaction category field (TC), a message transaction layer packet summary field (TD), an error identification field (EP), an attribute field (Attr), an additional transaction type field (AT), a length field (Length), a requester identification field (Requester ID), a transaction tag field (Tag), a message coding field (Message Code), and reserved bit fields (R, Rsv, and Reserved).

[0076] like Figure 4As shown, the data packet format field (Fmt) in the LIR message can be set to a pre-set identifier without data payload, such as Figure 4 The binary 001 (i.e. 001b) in the LIR message is used to indicate that the LIR message is a message type request without data payload. The packet type field (Type) in the LIR message can be a preset message request identifier, such as Figure 4 The binary 10100 (i.e. 10100b) in the LIR message is used to indicate that the LIR message is a message request and is routed in the Local-Terminated at Receiver manner as defined in the PCIe specification. The Transaction Class field (TC) in the LIR message can be set to 0, such as Figure 4 The message transaction layer packet summary (TLP Digest) field (TD) in the LIR message can be used to indicate whether the TLP level data check is enabled. The error (Poisoned) identification field (EP) in the LIR message can be used to indicate that the current TLP has been damaged or invalid due to some error conditions. The attribute field (Attr) in the LIR message can be used to define additional characteristics of the TLP, which can be set to 0 in this embodiment, such as Figure 4 The additional transaction type (AT) field (AT) in the LIR message can be used to specify a specific type of message, and in this embodiment, it can be set to 0, such as Figure 4 In this embodiment, the length field (Length) in the LIR message may be set to 0, such as the binary 0000000000. The requester ID field (Requester ID) in the LIR message may be used to indicate the device identifier that initiates the transaction.

[0077] Accordingly, since the message request is a special type of transaction that does not require confirmation or completion response, the transaction tag field (Tag) in the LIR message in this embodiment can be set to 0, such as binary 00000000. The message code field (Message Code) in the LIR message in this embodiment can be a preset LIR message identifier, such as Figure 4The binary 00010100 in the LIR message indicates that the current data packet is an LIR message frame. The UnitedStak Latency field in the LIR message can be used to record the delay of the PCIe protocol stack processing request of the PCIe device (i.e., the protocol stack processing delay), which can be in nanoseconds. The System Response Latency field in the LIR message is used to record the response time of the system where the PCIe device is located to the request (i.e., the system response time), which can be in nanoseconds.

[0078] Correspondingly, such as Figure 4 As shown, the LIR message (such as the first delay information report message) can be a 16-byte data packet in the form of Message TLP using the PCIe protocol. The first byte to the fourth byte in the first delay information report message include a data packet format field, a data packet type field, a transaction category field, a message transaction layer packet summary field, an error identification field, an attribute field, an additional transaction type field, and a length field. The fifth byte to the eighth byte in the first delay information report message include a requester identification field, a transaction tag field, and a message encoding field. The ninth byte to the twelfth byte in the first delay information report message include a protocol stack processing delay field and a system response time field. The thirteenth byte to the sixteenth byte in the first delay information report message include a reserved bit field (Reserved).

[0079] Furthermore, in this embodiment, the first device can obtain the first delay information report message sent by the second device through the peripheral component express link at a preset time interval, so that the PCIe device can dynamically adjust its operation according to the real-time delay information to adapt to different delay conditions. For example, after entering the normal working state (L0 state), the first device can obtain the first delay information report message sent by the second device through the peripheral component express link at a preset time interval to update the transaction concurrency capability of the first device and adjust the system resources of the PCIe link.

[0080] Step 102: Determine the transaction concurrency capability of the first device according to the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device in the first delay information report message.

[0081] It can be understood that in this step, the first device can determine the transaction round-trip delay of the PCIe transaction based on its own protocol stack processing delay and system response time and the protocol stack processing delay and system response time of the second device in the first delay information report message, and accurately determine the transaction concurrency capability of the PCIe link required by the first device.

[0082] Correspondingly, the specific method for the first device to determine the transaction concurrency capability of the first device in this step based on the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device in the first delay information report message can be set by the designer according to practical scenarios and user needs. For example, the first device can determine the transaction round-trip delay based on the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device; and determine the transaction concurrency capability of the first device based on the transaction round-trip delay and the number of channels of the acquired peripheral component fast interconnection link, the single-channel transmission rate, the physical layer coding efficiency, and the transaction layer packet length.

[0083] Among them, the specific acquisition method for the first device in this embodiment to obtain the protocol stack processing delay and system response time of the first device, as well as the number of channels, single-channel transmission rate, physical layer coding efficiency and transaction layer packet length of the PCIe link with the second device can be set by the designer according to the usage scenario and user needs. For example, it can be implemented in the same or similar manner as the link negotiation and delay acquisition method of the PCIe link in the related technology. As long as the PCIe device can obtain its own protocol stack processing delay and system response time, as well as the number of channels, single-channel transmission rate, physical layer coding efficiency and transaction layer packet length of the PCIe link, this embodiment does not impose any restrictions on this.

[0084] Correspondingly, the specific method for determining the transaction round-trip delay based on the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device can be set by the designer. For example, the first device can calculate the sum of the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device to obtain the transaction round-trip delay; that is, the first device can directly add the sum of the protocol stack processing delay and system response time of the first device to the sum of the protocol stack processing delay and system response time of the second device to obtain the transaction round-trip delay; Figure 5 As shown in the figure, the protocol stack processing delay and system response delay of device A (i.e., the first device) are 850ns and 500ns respectively, the protocol stack processing delay and system response delay of device B (i.e., the second device) are 600ns and 750ns respectively, and the round-trip delay L of the PCIe connection between device A and device B is t It can be 850+500+600+750=2700ns. The first device can also calculate the sum of the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device to obtain an accumulated result; calculate the product of the accumulated result and the preset delay calculation parameter to obtain the transaction round-trip delay. This embodiment does not impose any limitation on this.

[0085] Correspondingly, the specific method for determining the transaction concurrency capability of the first device based on the transaction round-trip delay and the number of channels of the peripheral component fast interconnection link, the single-channel transmission rate, the physical layer coding efficiency, and the transaction layer packet length can be set by the designer according to practical scenarios and user needs. For example, the first device can be determined by , calculate the transaction concurrency capability of the first device; where R link is the single channel transmission rate, N lane is the number of channels, L t is the transaction round trip delay, E enc is the physical layer coding efficiency, S packet is the transaction layer packet length; a is a preset parameter, such as when the transaction layer packet length is in bytes, a can be 8. The calculation result is rounded up to obtain the transaction concurrency capability of the first device; the first device may also round off or round down the above calculation result to obtain the transaction concurrency capability of the first device; the first device may also directly use the above calculation result as the transaction concurrency capability of the first device. This embodiment does not impose any limitation on this.

[0086] For example, if Figure 5 As shown, after device A (i.e., the first device) and device B (i.e., the second device) complete the link training and link negotiation of the PCIe link, the final negotiated link configuration may be: physical link rate (i.e., single-channel transmission rate R link ) is 8Gbps; the encoding method is 128b / 130b, that is, the physical layer coding efficiency E enc Can be 1; link width is 4 channels, that is, the number of channels is N lane is 4; the maximum data packet load (Max Payload Size) is 512 bytes, that is, the transaction layer packet length S packet The protocol stack processing delay and system response delay of device A are 850ns and 500ns respectively, and the protocol stack processing delay and system response delay of device B are 600ns and 750ns respectively. The transaction round-trip delay L of the PCIe link between device A and device B can be obtained by calculation. t is 2700ns. , we can calculate the transaction concurrency capacity O n =21, device A and device B can calculate the transaction concurrency capacity O n Matching and optimizing the required system resources can fully utilize the current physical link resources, optimize system resources, and reduce ownership costs.

[0087] It should be noted that, in this embodiment, the second device can also determine the transaction concurrency capability of the PCIe link required by itself to configure its own system resources accordingly. For example, the second device can determine the transaction concurrency capability of the second device based on the protocol stack processing delay and system response time of the second device and the protocol stack processing delay and system response time of the second device in the received second delay information report message. The second device can also receive the transaction concurrency capability of the first device sent by the first device, and use the transaction concurrency capability of the first device as the transaction concurrency capability of the second device; accordingly, after step 102, the first device can send the determined transaction concurrency capability of the first device to the second device. This embodiment does not impose any restrictions on this.

[0088] Step 103: configuring system resources corresponding to the peripheral component fast interconnection link in the first device according to the transaction concurrency capability; wherein the system resources include at least one of a buffer size, a number of transaction tag numbers, a lookup table specification, and a number of driver queues.

[0089] It is understandable that in this step, the first device can configure the resources (i.e., system resources) required by the PCIe system in the first device according to the determined transaction concurrency capability to achieve the optimal configuration of the system resources. The specific types of system resources configured in this step can be set by the designer according to practical scenarios and user needs, such as being implemented in the same or similar manner as the system resource configuration method in the related art, such as system resources can include buffer size, number of Tag (transaction tag) numbers, lookup table specifications, and number of driver queues.

[0090] Correspondingly, the specific manner in which the first device configures the system resources corresponding to the peripheral component fast interconnection link in the first device according to the transaction concurrency capability in this step can be set by the designer. For example, the first device can match the corresponding system resources and perform configuration according to the correspondence between each preset transaction concurrency number and the system resources.

[0091] In this embodiment, the embodiment of the present invention obtains the first delay information report message sent by the second device through the peripheral component rapid interconnection link through the first device, so that the first device can obtain the protocol stack processing delay and system response time of the second device, so that the first device can accurately obtain the PCIe transaction round-trip delay between the first device and the second device, and then accurately determine the required transaction concurrency capability and match the corresponding system resources. On the basis of ensuring the efficiency of the PCIe link, it is possible to optimize the configuration of system resources and avoid idleness and waste of system resources.

[0092] Corresponding to the above method embodiment, an embodiment of the present invention further provides a communication configuration device. The communication configuration device described below and the communication configuration method described above can refer to each other.

[0093] Please refer to Figure 6 , Figure 6 This is a structural block diagram of a communication configuration device provided by an embodiment of the present invention. The device is applied to a first device and may include:

[0094] The acquisition module 10 is used to receive a first delay information report message sent by the second device through a peripheral component express link; wherein the first device and the second device are both peripheral component express devices, and the first delay information report message includes a protocol stack processing delay and a system response time of the second device;

[0095] A determination module 20, configured to determine the transaction concurrency capability of the first device according to the protocol stack processing delay and the system response time of the first device and the protocol stack processing delay and the system response time of the second device in the first delay information report message;

[0096] The configuration module 30 is used to configure the system resources corresponding to the peripheral component fast interconnection link in the first device according to the transaction concurrency capability; wherein the system resources include at least one of the buffer size, the number of transaction tag numbers, the lookup table specification and the number of driver queues.

[0097] In some embodiments, the acquisition module 10 may include:

[0098] A sending submodule, configured to send a second delay information report message to the second device via a peripheral component rapid interconnect link; wherein the second delay information report message includes a protocol stack processing delay and a system response time of the first device, and the first device serves as a delay information report initiator;

[0099] The receiving submodule is used to receive a first delay information report message returned by the second device.

[0100] In some embodiments, the sending submodule may be specifically configured to enable the first device to send a second delay information report message to the second device through a peripheral component express interconnect link after the first device and the second device enter a normal working state.

[0101] In some embodiments, the apparatus may further include:

[0102] The sending module is used to return a second delay information report message to the second device through the peripheral component rapid interconnection link; wherein the second delay information report message includes the protocol stack processing delay and system response time of the first device, and the second device serves as the delay information report initiator.

[0103] In some embodiments, the first delay information report message is a data packet in the form of a message transaction layer packet or a data link layer packet of the PCI Express protocol.

[0104] In some embodiments, when the first delay information report message adopts a data packet in the form of a message transaction layer packet, the first delay information report message includes: a protocol stack processing delay field, a system response time field and a protocol definition field; wherein the protocol definition field includes at least one of a data packet format field, a data packet type field, a transaction category field, a message transaction layer packet summary field, an error identification field, an attribute field, an additional transaction type field, a length field, a requester identification field, a transaction tag field and a message encoding field.

[0105] In some embodiments, the first delay information report message is a 16-byte data packet, and the first delay information report message also includes a reserved bit field.

[0106] In some embodiments, the 1st to 4th bytes in the first delay information report message include a data packet format field, a data packet type field, a transaction category field, a message transaction layer packet summary field, an error identification field, an attribute field, an additional transaction type field and a length field, the 5th to 8th bytes in the first delay information report message include a requester identification field, a transaction tag field and a message encoding field, the 9th to 12th bytes in the first delay information report message include a protocol stack processing delay field and a system response time field, and the 13th to 16th bytes in the first delay information report message include a reserved bit field.

[0107] In some embodiments, the data packet format field is binary 001; the data packet type field is binary 10100, the transaction category field is 0, the attribute field is 0, the additional transaction type field is 0, the length field is 0, the transaction tag field is 0, and the message encoding field is binary 00010100.

[0108] In some embodiments, the acquisition module 10 may be specifically configured for the first device to acquire, at a preset time interval, a first delay information report message sent by the second device through a peripheral component express link.

[0109] In some embodiments, the determination module 20 may include:

[0110] A delay determination submodule, configured to determine a transaction round trip delay based on a protocol stack processing delay and a system response time of the first device and a protocol stack processing delay and a system response time of the second device;

[0111] The concurrency determination submodule is used to determine the transaction concurrency capability of the first device according to the transaction round-trip delay and the acquired number of channels of the peripheral component fast interconnection link, the single-channel transmission rate, the physical layer coding efficiency and the transaction layer packet length.

[0112] In some embodiments, the delay determination submodule may be specifically used to calculate the sum of the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device to obtain the transaction round-trip delay.

[0113] In some embodiments, the concurrency determination submodule may be specifically configured to: , calculate the transaction concurrency capability of the first device; where R link is the single channel transmission rate, N lane is the number of channels, L t is the transaction round trip delay, E enc is the physical layer coding efficiency, S packet is the length of the transaction layer packet, and a is a preset parameter.

[0114] The concurrency determination submodule can be used specifically for The calculation result is rounded up to obtain the transaction concurrency capability of the first device.

[0115] In some embodiments, the unit of the transaction layer packet data length is bytes, and a is 8.

[0116] In the present embodiment, the first device of the embodiment of the present invention obtains the first delay information report message sent by the second device through the peripheral component rapid interconnection link through the acquisition module 10, so that the first device can obtain the protocol stack processing delay and the system response time of the second device, so that the first device can obtain the accurate PCIe transaction round-trip delay between the first device and the second device, and then accurately determine the required transaction concurrency capability and match the corresponding system resources, which can optimize the configuration of system resources on the basis of ensuring the efficiency of the PCIe link and avoid idleness and waste of system resources.

[0117] Corresponding to the above method embodiment, an embodiment of the present invention further provides a peripheral component interconnect express (PCIe) device. The peripheral component interconnect express device described below and the communication configuration method described above can be referred to each other.

[0118] Please refer to Figure 7 , Figure 7 A simplified structural diagram of a peripheral component rapid interconnection device provided by an embodiment of the present invention. The peripheral component rapid interconnection device may include:

[0119] A memory D1, for storing computer programs;

[0120] The processor D2 (such as a PCIe controller) is used to implement the steps of the communication configuration method provided in the above method embodiment when executing a computer program.

[0121] Accordingly, please refer to Figure 8 , Figure 8 A schematic diagram of the specific structure of a peripheral component rapid interconnect device provided by an embodiment of the present invention. The peripheral component rapid interconnect device 310 may have relatively large differences due to different configurations or performances, and may include one or more processors (central processing units, CPU) 322 (for example, one or more processors) and memory 332, one or more storage media 330 (for example, one or more mass storage devices) storing application programs 342 or data 344. Among them, the memory 332 and the storage medium 330 can be temporary storage or permanent storage. The program stored in the storage medium 330 may include one or more modules (not shown in the figure), and each module may include a series of instruction operations in the host. Furthermore, the central processor 322 can be configured to communicate with the storage medium 330 to execute a series of instruction operations in the storage medium 330 on the peripheral component rapid interconnect device 310.

[0122] The PCI Express device 310 may further include one or more power supplies 326, one or more wired or wireless network interfaces 350, one or more input and output interfaces 358, and / or one or more operating systems 341, such as Linux system.

[0123] The peripheral component rapid interconnection device 310 in this embodiment may specifically be a solid state drive, a graphics processing unit or a network interface card.

[0124] The steps in the communication configuration method described above may be implemented by the structure of a peripheral component express interconnect device.

[0125] Corresponding to the above method embodiment, the embodiment of the present invention further provides a peripheral component rapid interconnection system. The peripheral component rapid interconnection system described below and the communication configuration method described above can be referred to each other.

[0126] A peripheral component rapid interconnection system, comprising: a first peripheral component rapid interconnection device and a second peripheral component rapid interconnection device;

[0127] Among them, the first peripheral component rapid interconnection device and the second peripheral component rapid interconnection device are connected through a peripheral component rapid interconnection bus, and the first peripheral component rapid interconnection device and the second peripheral component rapid interconnection device are both peripheral component rapid interconnection devices provided by the above embodiment, such as the first peripheral component rapid interconnection device can be the first device in the above embodiment, and the second peripheral component rapid interconnection device can be the second device in the above embodiment.

[0128] Corresponding to the above method embodiment, the embodiment of the present invention further provides a computer program product. The computer program product described below and the communication configuration method described above can refer to each other.

[0129] A computer program product includes a computer program / instruction, which implements the steps of the communication configuration method provided by the above method embodiment when the computer program / instruction is executed by a processor.

[0130] The various embodiments in the specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other. For the devices, equipment, systems, computer program products, and computer-readable storage media disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the description is relatively simple, and the relevant parts can be referred to the method part description.

[0131] The above is a detailed introduction to a communication configuration method, device, peripheral component rapid interconnection device, peripheral component rapid interconnection system, computer program product and computer readable medium provided by the present invention. Specific examples are used herein to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present invention, the present invention can also be improved and modified in a number of ways, and these improvements and modifications also fall within the scope of protection of the present invention.

Claims

1. A communication configuration method, characterized in that: include: A first device acquires a first delay information report message sent by a second device through a peripheral component express link; wherein the first device and the second device are both peripheral component express devices, and the first delay information report message includes a protocol stack processing delay and a system response time of the second device; determining a transaction concurrency capability of the first device according to a protocol stack processing delay and a system response time of the first device and a protocol stack processing delay and a system response time of the second device in the first delay information report message; According to the transaction concurrency capability, system resources corresponding to the peripheral component fast interconnect link in the first device are configured; wherein the system resources include at least one of a buffer size, a number of transaction tag numbers, a lookup table specification, and a number of driver queues.

2. The communication configuration method according to claim 1, characterized in that: The first device obtains a first delay information report message sent by the second device through a peripheral component express interconnect link, including: The first device sends a second delay information report message to the second device through the peripheral component express interconnect link; wherein the second delay information report message includes a protocol stack processing delay and a system response time of the first device, and the first device serves as a delay information report initiator; Receive the first delay information report message returned by the second device.

3. The communication configuration method according to claim 2, characterized in that: The first device sends a second delay information report message to the second device through the peripheral component express interconnect link, including: After the first device and the second device enter a normal working state, the first device sends the second delay information report message to the second device through the peripheral component express interconnect link.

4. The communication configuration method according to claim 1, characterized in that: After the first device acquires the first delay information report message sent by the second device through the peripheral component express interconnect link, the method further includes: The first device returns a second delay information report message to the second device through the peripheral component express interconnect link; wherein the second delay information report message includes the protocol stack processing delay and system response time of the first device, and the second device serves as the delay information report initiator.

5. The communication configuration method according to claim 1, characterized in that: The first delay information report message is a data packet in the form of a message transaction layer packet or a data link layer packet of the PCI Express protocol.

6. The communication configuration method according to claim 5, characterized in that: When the first delay information report message adopts a data packet in the form of the message transaction layer packet, the first delay information report message includes: a protocol stack processing delay field, a system response time field and a protocol definition field; wherein the protocol definition field includes at least one of a data packet format field, a data packet type field, a transaction category field, a message transaction layer packet summary field, an error identification field, an attribute field, an additional transaction type field, a length field, a requester identification field, a transaction tag field and a message encoding field.

7. The communication configuration method according to claim 6, characterized in that: The first delay information report message is a 16-byte data packet, and the first delay information report message also includes a reserved bit field.

8. The communication configuration method according to claim 7, characterized in that: The first to fourth bytes in the first delay information report message include the data packet format field, the data packet type field, the transaction category field, the message transaction layer packet summary field, the error identification field, the attribute field, the additional transaction type field and the length field, the fifth to eighth bytes in the first delay information report message include the requester identification field, the transaction tag field and the message encoding field, the ninth to twelfth bytes in the first delay information report message include the protocol stack processing delay field and the system response time field, and the thirteenth to sixteenth bytes in the first delay information report message include the reserved bit field.

9. The communication configuration method according to claim 7, characterized in that: The data packet format field is 001 in binary; the data packet type field is 10100 in binary, the transaction category field is 0, the attribute field is 0, the additional transaction type field is 0, the length field is 0, the transaction tag field is 0, and the message encoding field is 00010100 in binary.

10. The communication configuration method according to claim 1, characterized in that: The first device obtains a first delay information report message sent by the second device through a peripheral component express interconnect link, including: The first device obtains a first delay information report message sent by the second device through the PCE link at a preset time interval.

11. The communication configuration method according to any one of claims 1 to 10, characterized in that: The determining, according to the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device in the first delay information report message, the transaction concurrency capability of the first device includes: Determine a transaction round trip delay based on a protocol stack processing delay and a system response time of the first device and a protocol stack processing delay and a system response time of the second device; The transaction concurrency capability of the first device is determined according to the transaction round-trip delay and the acquired number of channels, single-channel transmission rate, physical layer coding efficiency and transaction layer packet length of the peripheral component rapid interconnect link.

12. The communication configuration method according to claim 11, characterized in that: Determining the transaction round-trip delay according to the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device includes: The transaction round-trip delay is obtained by calculating the sum of the protocol stack processing delay and system response time of the first device and the protocol stack processing delay and system response time of the second device.

13. The communication configuration method according to claim 11, characterized in that: Determining the transaction concurrency capability of the first device according to the transaction round-trip delay and the acquired number of channels, single-channel transmission rate, physical layer coding efficiency, and transaction layer packet length of the peripheral component fast interconnect link includes: pass , calculate the transaction concurrency capability of the first device; where R link is the single channel transmission rate, N lane is the number of channels, L t is the round trip delay of the transaction, E enc is the physical layer coding efficiency, S packet is the length of the transaction layer packet, and a is a preset parameter.

14. The communication configuration method according to claim 13, characterized in that: Said through , calculating the transaction concurrency capability of the first device, including: right The calculation result is rounded up to obtain the transaction concurrency capability of the first device.

15. The communication configuration method according to claim 13, characterized in that: The unit of the transaction layer packet data length is byte, and a is 8.

16. A communication configuration device, characterized in that: Applied to a first device, comprising: an acquisition module, configured to receive a first delay information report message sent by a second device through a peripheral component interconnect express link; wherein the first device and the second device are both peripheral component interconnect express devices, and the first delay information report message includes a protocol stack processing delay and a system response time of the second device; a determination module, configured to determine the transaction concurrency capability of the first device according to the protocol stack processing delay and the system response time of the first device and the protocol stack processing delay and the system response time of the second device in the first delay information report message; A configuration module is used to configure the system resources corresponding to the peripheral component rapid interconnection link in the first device according to the transaction concurrency capability; wherein the system resources include at least one of a buffer size, a number of transaction tag numbers, a lookup table specification, and a number of driver queues.

17. A peripheral component rapid interconnect device, characterized in that: include: Memory for storing computer programs; A processor, configured to execute the computer program to implement the steps of the communication configuration method according to any one of claims 1 to 15.

18. A peripheral component rapid interconnection system, characterized in that: include: a first peripheral component rapid interconnect device and a second peripheral component rapid interconnect device; The first PICI device and the second PICI device are connected via a PICI bus, and both the first PICI device and the second PICI device are the PICI devices as claimed in claim 17.

19. A computer program product comprising a computer program / instructions, characterized in that When the computer program / instructions are executed by a processor, the steps of the communication configuration method according to any one of claims 1 to 15 are implemented.

20. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the communication configuration method according to any one of claims 1 to 15 are implemented.

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